2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <dev/mlx4/cq.h>
35 #include <dev/mlx4/qp.h>
36 #include <dev/mlx4/srq.h>
37 #include <dev/mlx4/driver.h>
38 #include <linux/slab.h>
41 #include <rdma/mlx4-abi.h>
43 static void mlx4_ib_cq_comp(struct mlx4_cq *cq)
45 struct ib_cq *ibcq = &to_mibcq(cq)->ibcq;
46 ibcq->comp_handler(ibcq, ibcq->cq_context);
49 static void mlx4_ib_cq_event(struct mlx4_cq *cq, enum mlx4_event type)
51 struct ib_event event;
54 if (type != MLX4_EVENT_TYPE_CQ_ERROR) {
55 pr_warn("Unexpected event type %d "
56 "on CQ %06x\n", type, cq->cqn);
60 ibcq = &to_mibcq(cq)->ibcq;
61 if (ibcq->event_handler) {
62 event.device = ibcq->device;
63 event.event = IB_EVENT_CQ_ERR;
64 event.element.cq = ibcq;
65 ibcq->event_handler(&event, ibcq->cq_context);
69 static void *get_cqe_from_buf(struct mlx4_ib_cq_buf *buf, int n)
71 return mlx4_buf_offset(&buf->buf, n * buf->entry_size);
74 static void *get_cqe(struct mlx4_ib_cq *cq, int n)
76 return get_cqe_from_buf(&cq->buf, n);
79 static void *get_sw_cqe(struct mlx4_ib_cq *cq, int n)
81 struct mlx4_cqe *cqe = get_cqe(cq, n & cq->ibcq.cqe);
82 struct mlx4_cqe *tcqe = ((cq->buf.entry_size == 64) ? (cqe + 1) : cqe);
84 return (!!(tcqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK) ^
85 !!(n & (cq->ibcq.cqe + 1))) ? NULL : cqe;
88 static struct mlx4_cqe *next_cqe_sw(struct mlx4_ib_cq *cq)
90 return get_sw_cqe(cq, cq->mcq.cons_index);
93 int mlx4_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
95 struct mlx4_ib_cq *mcq = to_mcq(cq);
96 struct mlx4_ib_dev *dev = to_mdev(cq->device);
98 return mlx4_cq_modify(dev->dev, &mcq->mcq, cq_count, cq_period);
101 static int mlx4_ib_alloc_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int nent)
105 err = mlx4_buf_alloc(dev->dev, nent * dev->dev->caps.cqe_size,
106 PAGE_SIZE * 2, &buf->buf, GFP_KERNEL);
111 buf->entry_size = dev->dev->caps.cqe_size;
112 err = mlx4_mtt_init(dev->dev, buf->buf.npages, buf->buf.page_shift,
117 err = mlx4_buf_write_mtt(dev->dev, &buf->mtt, &buf->buf, GFP_KERNEL);
124 mlx4_mtt_cleanup(dev->dev, &buf->mtt);
127 mlx4_buf_free(dev->dev, nent * buf->entry_size, &buf->buf);
133 static void mlx4_ib_free_cq_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq_buf *buf, int cqe)
135 mlx4_buf_free(dev->dev, (cqe + 1) * buf->entry_size, &buf->buf);
138 static int mlx4_ib_get_cq_umem(struct mlx4_ib_dev *dev, struct ib_ucontext *context,
139 struct mlx4_ib_cq_buf *buf, struct ib_umem **umem,
140 u64 buf_addr, int cqe)
143 int cqe_size = dev->dev->caps.cqe_size;
145 *umem = ib_umem_get(context, buf_addr, cqe * cqe_size,
146 IB_ACCESS_LOCAL_WRITE, 1);
148 return PTR_ERR(*umem);
150 err = mlx4_mtt_init(dev->dev, ib_umem_page_count(*umem),
151 ilog2((*umem)->page_size), &buf->mtt);
155 err = mlx4_ib_umem_write_mtt(dev, &buf->mtt, *umem);
162 mlx4_mtt_cleanup(dev->dev, &buf->mtt);
165 ib_umem_release(*umem);
170 #define CQ_CREATE_FLAGS_SUPPORTED IB_CQ_FLAGS_TIMESTAMP_COMPLETION
171 struct ib_cq *mlx4_ib_create_cq(struct ib_device *ibdev,
172 const struct ib_cq_init_attr *attr,
173 struct ib_ucontext *context,
174 struct ib_udata *udata)
176 int entries = attr->cqe;
177 int vector = attr->comp_vector;
178 struct mlx4_ib_dev *dev = to_mdev(ibdev);
179 struct mlx4_ib_cq *cq;
180 struct mlx4_uar *uar;
183 if (entries < 1 || entries > dev->dev->caps.max_cqes)
184 return ERR_PTR(-EINVAL);
186 if (attr->flags & ~CQ_CREATE_FLAGS_SUPPORTED)
187 return ERR_PTR(-EINVAL);
189 cq = kmalloc(sizeof *cq, GFP_KERNEL);
191 return ERR_PTR(-ENOMEM);
193 entries = roundup_pow_of_two(entries + 1);
194 cq->ibcq.cqe = entries - 1;
195 mutex_init(&cq->resize_mutex);
196 spin_lock_init(&cq->lock);
197 cq->resize_buf = NULL;
198 cq->resize_umem = NULL;
199 cq->create_flags = attr->flags;
200 INIT_LIST_HEAD(&cq->send_qp_list);
201 INIT_LIST_HEAD(&cq->recv_qp_list);
204 struct mlx4_ib_create_cq ucmd;
206 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) {
211 err = mlx4_ib_get_cq_umem(dev, context, &cq->buf, &cq->umem,
212 ucmd.buf_addr, entries);
216 err = mlx4_ib_db_map_user(to_mucontext(context), ucmd.db_addr,
221 uar = &to_mucontext(context)->uar;
223 err = mlx4_db_alloc(dev->dev, &cq->db, 1, GFP_KERNEL);
227 cq->mcq.set_ci_db = cq->db.db;
228 cq->mcq.arm_db = cq->db.db + 1;
229 *cq->mcq.set_ci_db = 0;
232 err = mlx4_ib_alloc_cq_buf(dev, &cq->buf, entries);
236 uar = &dev->priv_uar;
240 vector = dev->eq_table[vector % ibdev->num_comp_vectors];
242 err = mlx4_cq_alloc(dev->dev, entries, &cq->buf.mtt, uar,
243 cq->db.dma, &cq->mcq, vector, 0,
244 !!(cq->create_flags & IB_CQ_FLAGS_TIMESTAMP_COMPLETION));
248 cq->mcq.comp = mlx4_ib_cq_comp;
249 cq->mcq.event = mlx4_ib_cq_event;
252 if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof (__u32))) {
260 mlx4_cq_free(dev->dev, &cq->mcq);
264 mlx4_ib_db_unmap_user(to_mucontext(context), &cq->db);
267 mlx4_mtt_cleanup(dev->dev, &cq->buf.mtt);
270 ib_umem_release(cq->umem);
272 mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
276 mlx4_db_free(dev->dev, &cq->db);
284 static int mlx4_alloc_resize_buf(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq,
292 cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_KERNEL);
296 err = mlx4_ib_alloc_cq_buf(dev, &cq->resize_buf->buf, entries);
298 kfree(cq->resize_buf);
299 cq->resize_buf = NULL;
303 cq->resize_buf->cqe = entries - 1;
308 static int mlx4_alloc_resize_umem(struct mlx4_ib_dev *dev, struct mlx4_ib_cq *cq,
309 int entries, struct ib_udata *udata)
311 struct mlx4_ib_resize_cq ucmd;
317 if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd))
320 cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_KERNEL);
324 err = mlx4_ib_get_cq_umem(dev, cq->umem->context, &cq->resize_buf->buf,
325 &cq->resize_umem, ucmd.buf_addr, entries);
327 kfree(cq->resize_buf);
328 cq->resize_buf = NULL;
332 cq->resize_buf->cqe = entries - 1;
337 static int mlx4_ib_get_outstanding_cqes(struct mlx4_ib_cq *cq)
341 i = cq->mcq.cons_index;
342 while (get_sw_cqe(cq, i))
345 return i - cq->mcq.cons_index;
348 static void mlx4_ib_cq_resize_copy_cqes(struct mlx4_ib_cq *cq)
350 struct mlx4_cqe *cqe, *new_cqe;
352 int cqe_size = cq->buf.entry_size;
353 int cqe_inc = cqe_size == 64 ? 1 : 0;
355 i = cq->mcq.cons_index;
356 cqe = get_cqe(cq, i & cq->ibcq.cqe);
359 while ((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) != MLX4_CQE_OPCODE_RESIZE) {
360 new_cqe = get_cqe_from_buf(&cq->resize_buf->buf,
361 (i + 1) & cq->resize_buf->cqe);
362 memcpy(new_cqe, get_cqe(cq, i & cq->ibcq.cqe), cqe_size);
365 new_cqe->owner_sr_opcode = (cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK) |
366 (((i + 1) & (cq->resize_buf->cqe + 1)) ? MLX4_CQE_OWNER_MASK : 0);
367 cqe = get_cqe(cq, ++i & cq->ibcq.cqe);
370 ++cq->mcq.cons_index;
373 int mlx4_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
375 struct mlx4_ib_dev *dev = to_mdev(ibcq->device);
376 struct mlx4_ib_cq *cq = to_mcq(ibcq);
381 mutex_lock(&cq->resize_mutex);
382 if (entries < 1 || entries > dev->dev->caps.max_cqes) {
387 entries = roundup_pow_of_two(entries + 1);
388 if (entries == ibcq->cqe + 1) {
393 if (entries > dev->dev->caps.max_cqes + 1) {
399 err = mlx4_alloc_resize_umem(dev, cq, entries, udata);
403 /* Can't be smaller than the number of outstanding CQEs */
404 outst_cqe = mlx4_ib_get_outstanding_cqes(cq);
405 if (entries < outst_cqe + 1) {
410 err = mlx4_alloc_resize_buf(dev, cq, entries);
417 err = mlx4_cq_resize(dev->dev, &cq->mcq, entries, &cq->resize_buf->buf.mtt);
421 mlx4_mtt_cleanup(dev->dev, &mtt);
423 cq->buf = cq->resize_buf->buf;
424 cq->ibcq.cqe = cq->resize_buf->cqe;
425 ib_umem_release(cq->umem);
426 cq->umem = cq->resize_umem;
428 kfree(cq->resize_buf);
429 cq->resize_buf = NULL;
430 cq->resize_umem = NULL;
432 struct mlx4_ib_cq_buf tmp_buf;
435 spin_lock_irq(&cq->lock);
436 if (cq->resize_buf) {
437 mlx4_ib_cq_resize_copy_cqes(cq);
439 tmp_cqe = cq->ibcq.cqe;
440 cq->buf = cq->resize_buf->buf;
441 cq->ibcq.cqe = cq->resize_buf->cqe;
443 kfree(cq->resize_buf);
444 cq->resize_buf = NULL;
446 spin_unlock_irq(&cq->lock);
449 mlx4_ib_free_cq_buf(dev, &tmp_buf, tmp_cqe);
455 mlx4_mtt_cleanup(dev->dev, &cq->resize_buf->buf.mtt);
457 mlx4_ib_free_cq_buf(dev, &cq->resize_buf->buf,
458 cq->resize_buf->cqe);
460 kfree(cq->resize_buf);
461 cq->resize_buf = NULL;
463 if (cq->resize_umem) {
464 ib_umem_release(cq->resize_umem);
465 cq->resize_umem = NULL;
469 mutex_unlock(&cq->resize_mutex);
474 int mlx4_ib_destroy_cq(struct ib_cq *cq)
476 struct mlx4_ib_dev *dev = to_mdev(cq->device);
477 struct mlx4_ib_cq *mcq = to_mcq(cq);
479 mlx4_cq_free(dev->dev, &mcq->mcq);
480 mlx4_mtt_cleanup(dev->dev, &mcq->buf.mtt);
483 mlx4_ib_db_unmap_user(to_mucontext(cq->uobject->context), &mcq->db);
484 ib_umem_release(mcq->umem);
486 mlx4_ib_free_cq_buf(dev, &mcq->buf, cq->cqe);
487 mlx4_db_free(dev->dev, &mcq->db);
495 static void dump_cqe(void *cqe)
499 pr_debug("CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n",
500 be32_to_cpu(buf[0]), be32_to_cpu(buf[1]), be32_to_cpu(buf[2]),
501 be32_to_cpu(buf[3]), be32_to_cpu(buf[4]), be32_to_cpu(buf[5]),
502 be32_to_cpu(buf[6]), be32_to_cpu(buf[7]));
505 static void mlx4_ib_handle_error_cqe(struct mlx4_err_cqe *cqe,
508 if (cqe->syndrome == MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR) {
509 pr_debug("local QP operation err "
510 "(QPN %06x, WQE index %x, vendor syndrome %02x, "
512 be32_to_cpu(cqe->my_qpn), be16_to_cpu(cqe->wqe_index),
513 cqe->vendor_err_syndrome,
514 cqe->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK);
518 switch (cqe->syndrome) {
519 case MLX4_CQE_SYNDROME_LOCAL_LENGTH_ERR:
520 wc->status = IB_WC_LOC_LEN_ERR;
522 case MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR:
523 wc->status = IB_WC_LOC_QP_OP_ERR;
525 case MLX4_CQE_SYNDROME_LOCAL_PROT_ERR:
526 wc->status = IB_WC_LOC_PROT_ERR;
528 case MLX4_CQE_SYNDROME_WR_FLUSH_ERR:
529 wc->status = IB_WC_WR_FLUSH_ERR;
531 case MLX4_CQE_SYNDROME_MW_BIND_ERR:
532 wc->status = IB_WC_MW_BIND_ERR;
534 case MLX4_CQE_SYNDROME_BAD_RESP_ERR:
535 wc->status = IB_WC_BAD_RESP_ERR;
537 case MLX4_CQE_SYNDROME_LOCAL_ACCESS_ERR:
538 wc->status = IB_WC_LOC_ACCESS_ERR;
540 case MLX4_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
541 wc->status = IB_WC_REM_INV_REQ_ERR;
543 case MLX4_CQE_SYNDROME_REMOTE_ACCESS_ERR:
544 wc->status = IB_WC_REM_ACCESS_ERR;
546 case MLX4_CQE_SYNDROME_REMOTE_OP_ERR:
547 wc->status = IB_WC_REM_OP_ERR;
549 case MLX4_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
550 wc->status = IB_WC_RETRY_EXC_ERR;
552 case MLX4_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
553 wc->status = IB_WC_RNR_RETRY_EXC_ERR;
555 case MLX4_CQE_SYNDROME_REMOTE_ABORTED_ERR:
556 wc->status = IB_WC_REM_ABORT_ERR;
559 wc->status = IB_WC_GENERAL_ERR;
563 wc->vendor_err = cqe->vendor_err_syndrome;
566 static int mlx4_ib_ipoib_csum_ok(__be16 status, __be16 checksum)
568 return ((status & cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
569 MLX4_CQE_STATUS_IPV4F |
570 MLX4_CQE_STATUS_IPV4OPT |
571 MLX4_CQE_STATUS_IPV6 |
572 MLX4_CQE_STATUS_IPOK)) ==
573 cpu_to_be16(MLX4_CQE_STATUS_IPV4 |
574 MLX4_CQE_STATUS_IPOK)) &&
575 (status & cpu_to_be16(MLX4_CQE_STATUS_UDP |
576 MLX4_CQE_STATUS_TCP)) &&
577 checksum == cpu_to_be16(0xffff);
580 static void use_tunnel_data(struct mlx4_ib_qp *qp, struct mlx4_ib_cq *cq, struct ib_wc *wc,
581 unsigned tail, struct mlx4_cqe *cqe, int is_eth)
583 struct mlx4_ib_proxy_sqp_hdr *hdr;
585 ib_dma_sync_single_for_cpu(qp->ibqp.device,
586 qp->sqp_proxy_rcv[tail].map,
587 sizeof (struct mlx4_ib_proxy_sqp_hdr),
589 hdr = (struct mlx4_ib_proxy_sqp_hdr *) (qp->sqp_proxy_rcv[tail].addr);
590 wc->pkey_index = be16_to_cpu(hdr->tun.pkey_index);
591 wc->src_qp = be32_to_cpu(hdr->tun.flags_src_qp) & 0xFFFFFF;
592 wc->wc_flags |= (hdr->tun.g_ml_path & 0x80) ? (IB_WC_GRH) : 0;
593 wc->dlid_path_bits = 0;
596 wc->vlan_id = be16_to_cpu(hdr->tun.sl_vid);
597 memcpy(&(wc->smac[0]), (char *)&hdr->tun.mac_31_0, 4);
598 memcpy(&(wc->smac[4]), (char *)&hdr->tun.slid_mac_47_32, 2);
599 wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC);
601 wc->slid = be16_to_cpu(hdr->tun.slid_mac_47_32);
602 wc->sl = (u8) (be16_to_cpu(hdr->tun.sl_vid) >> 12);
606 static void mlx4_ib_qp_sw_comp(struct mlx4_ib_qp *qp, int num_entries,
607 struct ib_wc *wc, int *npolled, int is_send)
609 struct mlx4_ib_wq *wq;
613 wq = is_send ? &qp->sq : &qp->rq;
614 cur = wq->head - wq->tail;
619 for (i = 0; i < cur && *npolled < num_entries; i++) {
620 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
621 wc->status = IB_WC_WR_FLUSH_ERR;
622 wc->vendor_err = MLX4_CQE_SYNDROME_WR_FLUSH_ERR;
630 static void mlx4_ib_poll_sw_comp(struct mlx4_ib_cq *cq, int num_entries,
631 struct ib_wc *wc, int *npolled)
633 struct mlx4_ib_qp *qp;
636 /* Find uncompleted WQEs belonging to that cq and retrun
637 * simulated FLUSH_ERR completions
639 list_for_each_entry(qp, &cq->send_qp_list, cq_send_list) {
640 mlx4_ib_qp_sw_comp(qp, num_entries, wc + *npolled, npolled, 1);
641 if (*npolled >= num_entries)
645 list_for_each_entry(qp, &cq->recv_qp_list, cq_recv_list) {
646 mlx4_ib_qp_sw_comp(qp, num_entries, wc + *npolled, npolled, 0);
647 if (*npolled >= num_entries)
655 static int mlx4_ib_poll_one(struct mlx4_ib_cq *cq,
656 struct mlx4_ib_qp **cur_qp,
659 struct mlx4_cqe *cqe;
661 struct mlx4_ib_wq *wq;
662 struct mlx4_ib_srq *srq;
663 struct mlx4_srq *msrq = NULL;
672 cqe = next_cqe_sw(cq);
676 if (cq->buf.entry_size == 64)
679 ++cq->mcq.cons_index;
682 * Make sure we read CQ entry contents after we've checked the
687 is_send = cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK;
688 is_error = (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
689 MLX4_CQE_OPCODE_ERROR;
691 /* Resize CQ in progress */
692 if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) == MLX4_CQE_OPCODE_RESIZE)) {
693 if (cq->resize_buf) {
694 struct mlx4_ib_dev *dev = to_mdev(cq->ibcq.device);
696 mlx4_ib_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe);
697 cq->buf = cq->resize_buf->buf;
698 cq->ibcq.cqe = cq->resize_buf->cqe;
700 kfree(cq->resize_buf);
701 cq->resize_buf = NULL;
708 (be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) != (*cur_qp)->mqp.qpn) {
710 * We do not have to take the QP table lock here,
711 * because CQs will be locked while QPs are removed
714 mqp = __mlx4_qp_lookup(to_mdev(cq->ibcq.device)->dev,
715 be32_to_cpu(cqe->vlan_my_qpn));
716 *cur_qp = to_mibqp(mqp);
719 wc->qp = &(*cur_qp)->ibqp;
721 if (wc->qp->qp_type == IB_QPT_XRC_TGT) {
723 g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn);
724 srq_num = g_mlpath_rqpn & 0xffffff;
725 /* SRQ is also in the radix tree */
726 msrq = mlx4_srq_lookup(to_mdev(cq->ibcq.device)->dev,
732 if (!(*cur_qp)->sq_signal_bits) {
733 wqe_ctr = be16_to_cpu(cqe->wqe_index);
734 wq->tail += (u16) (wqe_ctr - (u16) wq->tail);
736 wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
738 } else if ((*cur_qp)->ibqp.srq) {
739 srq = to_msrq((*cur_qp)->ibqp.srq);
740 wqe_ctr = be16_to_cpu(cqe->wqe_index);
741 wc->wr_id = srq->wrid[wqe_ctr];
742 mlx4_ib_free_srq_wqe(srq, wqe_ctr);
744 srq = to_mibsrq(msrq);
745 wqe_ctr = be16_to_cpu(cqe->wqe_index);
746 wc->wr_id = srq->wrid[wqe_ctr];
747 mlx4_ib_free_srq_wqe(srq, wqe_ctr);
750 tail = wq->tail & (wq->wqe_cnt - 1);
751 wc->wr_id = wq->wrid[tail];
755 if (unlikely(is_error)) {
756 mlx4_ib_handle_error_cqe((struct mlx4_err_cqe *) cqe, wc);
760 wc->status = IB_WC_SUCCESS;
764 switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
765 case MLX4_OPCODE_RDMA_WRITE_IMM:
766 wc->wc_flags |= IB_WC_WITH_IMM;
767 case MLX4_OPCODE_RDMA_WRITE:
768 wc->opcode = IB_WC_RDMA_WRITE;
770 case MLX4_OPCODE_SEND_IMM:
771 wc->wc_flags |= IB_WC_WITH_IMM;
772 case MLX4_OPCODE_SEND:
773 case MLX4_OPCODE_SEND_INVAL:
774 wc->opcode = IB_WC_SEND;
776 case MLX4_OPCODE_RDMA_READ:
777 wc->opcode = IB_WC_RDMA_READ;
778 wc->byte_len = be32_to_cpu(cqe->byte_cnt);
780 case MLX4_OPCODE_ATOMIC_CS:
781 wc->opcode = IB_WC_COMP_SWAP;
784 case MLX4_OPCODE_ATOMIC_FA:
785 wc->opcode = IB_WC_FETCH_ADD;
788 case MLX4_OPCODE_MASKED_ATOMIC_CS:
789 wc->opcode = IB_WC_MASKED_COMP_SWAP;
792 case MLX4_OPCODE_MASKED_ATOMIC_FA:
793 wc->opcode = IB_WC_MASKED_FETCH_ADD;
796 case MLX4_OPCODE_LSO:
797 wc->opcode = IB_WC_LSO;
799 case MLX4_OPCODE_FMR:
800 wc->opcode = IB_WC_REG_MR;
802 case MLX4_OPCODE_LOCAL_INVAL:
803 wc->opcode = IB_WC_LOCAL_INV;
807 wc->byte_len = be32_to_cpu(cqe->byte_cnt);
809 switch (cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) {
810 case MLX4_RECV_OPCODE_RDMA_WRITE_IMM:
811 wc->opcode = IB_WC_RECV_RDMA_WITH_IMM;
812 wc->wc_flags = IB_WC_WITH_IMM;
813 wc->ex.imm_data = cqe->immed_rss_invalid;
815 case MLX4_RECV_OPCODE_SEND_INVAL:
816 wc->opcode = IB_WC_RECV;
817 wc->wc_flags = IB_WC_WITH_INVALIDATE;
818 wc->ex.invalidate_rkey = be32_to_cpu(cqe->immed_rss_invalid);
820 case MLX4_RECV_OPCODE_SEND:
821 wc->opcode = IB_WC_RECV;
824 case MLX4_RECV_OPCODE_SEND_IMM:
825 wc->opcode = IB_WC_RECV;
826 wc->wc_flags = IB_WC_WITH_IMM;
827 wc->ex.imm_data = cqe->immed_rss_invalid;
831 is_eth = (rdma_port_get_link_layer(wc->qp->device,
833 IB_LINK_LAYER_ETHERNET);
834 if (mlx4_is_mfunc(to_mdev(cq->ibcq.device)->dev)) {
835 if ((*cur_qp)->mlx4_ib_qp_type &
836 (MLX4_IB_QPT_PROXY_SMI_OWNER |
837 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
838 use_tunnel_data(*cur_qp, cq, wc, tail, cqe,
844 wc->slid = be16_to_cpu(cqe->rlid);
845 g_mlpath_rqpn = be32_to_cpu(cqe->g_mlpath_rqpn);
846 wc->src_qp = g_mlpath_rqpn & 0xffffff;
847 wc->dlid_path_bits = (g_mlpath_rqpn >> 24) & 0x7f;
848 wc->wc_flags |= g_mlpath_rqpn & 0x80000000 ? IB_WC_GRH : 0;
849 wc->pkey_index = be32_to_cpu(cqe->immed_rss_invalid) & 0x7f;
850 wc->wc_flags |= mlx4_ib_ipoib_csum_ok(cqe->status,
851 cqe->checksum) ? IB_WC_IP_CSUM_OK : 0;
853 wc->sl = be16_to_cpu(cqe->sl_vid) >> 13;
854 if (be32_to_cpu(cqe->vlan_my_qpn) &
855 MLX4_CQE_CVLAN_PRESENT_MASK) {
856 wc->vlan_id = be16_to_cpu(cqe->sl_vid) &
859 wc->vlan_id = 0xffff;
861 memcpy(wc->smac, cqe->smac, ETH_ALEN);
862 wc->wc_flags |= (IB_WC_WITH_VLAN | IB_WC_WITH_SMAC);
864 wc->sl = be16_to_cpu(cqe->sl_vid) >> 12;
865 wc->vlan_id = 0xffff;
872 int mlx4_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
874 struct mlx4_ib_cq *cq = to_mcq(ibcq);
875 struct mlx4_ib_qp *cur_qp = NULL;
878 struct mlx4_ib_dev *mdev = to_mdev(cq->ibcq.device);
880 spin_lock_irqsave(&cq->lock, flags);
881 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR) {
882 mlx4_ib_poll_sw_comp(cq, num_entries, wc, &npolled);
886 for (npolled = 0; npolled < num_entries; ++npolled) {
887 if (mlx4_ib_poll_one(cq, &cur_qp, wc + npolled))
891 mlx4_cq_set_ci(&cq->mcq);
894 spin_unlock_irqrestore(&cq->lock, flags);
899 int mlx4_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
901 mlx4_cq_arm(&to_mcq(ibcq)->mcq,
902 (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
903 MLX4_CQ_DB_REQ_NOT_SOL : MLX4_CQ_DB_REQ_NOT,
904 to_mdev(ibcq->device)->uar_map,
905 MLX4_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->uar_lock));
910 void __mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq)
914 struct mlx4_cqe *cqe, *dest;
916 int cqe_inc = cq->buf.entry_size == 64 ? 1 : 0;
919 * First we need to find the current producer index, so we
920 * know where to start cleaning from. It doesn't matter if HW
921 * adds new entries after this loop -- the QP we're worried
922 * about is already in RESET, so the new entries won't come
923 * from our QP and therefore don't need to be checked.
925 for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); ++prod_index)
926 if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe)
930 * Now sweep backwards through the CQ, removing CQ entries
931 * that match our QP by copying older entries on top of them.
933 while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) {
934 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
937 if ((be32_to_cpu(cqe->vlan_my_qpn) & MLX4_CQE_QPN_MASK) == qpn) {
938 if (srq && !(cqe->owner_sr_opcode & MLX4_CQE_IS_SEND_MASK))
939 mlx4_ib_free_srq_wqe(srq, be16_to_cpu(cqe->wqe_index));
942 dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe);
945 owner_bit = dest->owner_sr_opcode & MLX4_CQE_OWNER_MASK;
946 memcpy(dest, cqe, sizeof *cqe);
947 dest->owner_sr_opcode = owner_bit |
948 (dest->owner_sr_opcode & ~MLX4_CQE_OWNER_MASK);
953 cq->mcq.cons_index += nfreed;
955 * Make sure update of buffer contents is done before
956 * updating consumer index.
959 mlx4_cq_set_ci(&cq->mcq);
963 void mlx4_ib_cq_clean(struct mlx4_ib_cq *cq, u32 qpn, struct mlx4_ib_srq *srq)
965 spin_lock_irq(&cq->lock);
966 __mlx4_ib_cq_clean(cq, qpn, srq);
967 spin_unlock_irq(&cq->lock);