2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/types.h>
38 #include <dev/mlx4/device.h>
40 #define MLX4_INVALID_LKEY 0x100
42 #define DS_SIZE_ALIGNMENT 16
44 #define SET_BYTE_COUNT(byte_count) cpu_to_be32(byte_count)
45 #define SET_LSO_MSS(mss_hdr_size) cpu_to_be32(mss_hdr_size)
46 #define DS_BYTE_COUNT_MASK cpu_to_be32(0x7fffffff)
48 enum ib_m_qp_attr_mask {
49 IB_M_EXT_CLASS_1 = 1 << 28,
50 IB_M_EXT_CLASS_2 = 1 << 29,
51 IB_M_EXT_CLASS_3 = 1 << 30,
53 IB_M_QP_MOD_VEND_MASK = (IB_M_EXT_CLASS_1 | IB_M_EXT_CLASS_2 |
58 MLX4_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
59 MLX4_QP_OPTPAR_RRE = 1 << 1,
60 MLX4_QP_OPTPAR_RAE = 1 << 2,
61 MLX4_QP_OPTPAR_RWE = 1 << 3,
62 MLX4_QP_OPTPAR_PKEY_INDEX = 1 << 4,
63 MLX4_QP_OPTPAR_Q_KEY = 1 << 5,
64 MLX4_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
65 MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
66 MLX4_QP_OPTPAR_SRA_MAX = 1 << 8,
67 MLX4_QP_OPTPAR_RRA_MAX = 1 << 9,
68 MLX4_QP_OPTPAR_PM_STATE = 1 << 10,
69 MLX4_QP_OPTPAR_RETRY_COUNT = 1 << 12,
70 MLX4_QP_OPTPAR_RNR_RETRY = 1 << 13,
71 MLX4_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
72 MLX4_QP_OPTPAR_SCHED_QUEUE = 1 << 16,
73 MLX4_QP_OPTPAR_COUNTER_INDEX = 1 << 20
77 MLX4_QP_STATE_RST = 0,
78 MLX4_QP_STATE_INIT = 1,
79 MLX4_QP_STATE_RTR = 2,
80 MLX4_QP_STATE_RTS = 3,
81 MLX4_QP_STATE_SQER = 4,
82 MLX4_QP_STATE_SQD = 5,
83 MLX4_QP_STATE_ERR = 6,
84 MLX4_QP_STATE_SQ_DRAINING = 7,
98 MLX4_QP_PM_MIGRATED = 0x3,
99 MLX4_QP_PM_ARMED = 0x0,
100 MLX4_QP_PM_REARM = 0x1
105 MLX4_QP_BIT_SRE = 1 << 15,
106 MLX4_QP_BIT_SWE = 1 << 14,
107 MLX4_QP_BIT_SAE = 1 << 13,
109 MLX4_QP_BIT_RRE = 1 << 15,
110 MLX4_QP_BIT_RWE = 1 << 14,
111 MLX4_QP_BIT_RAE = 1 << 13,
112 MLX4_QP_BIT_RIC = 1 << 4,
113 MLX4_QP_BIT_COLL_SYNC_RQ = 1 << 2,
114 MLX4_QP_BIT_COLL_SYNC_SQ = 1 << 1,
115 MLX4_QP_BIT_COLL_MASTER = 1 << 0
119 MLX4_RSS_HASH_XOR = 0,
120 MLX4_RSS_HASH_TOP = 1,
122 MLX4_RSS_UDP_IPV6 = 1 << 0,
123 MLX4_RSS_UDP_IPV4 = 1 << 1,
124 MLX4_RSS_TCP_IPV6 = 1 << 2,
125 MLX4_RSS_IPV6 = 1 << 3,
126 MLX4_RSS_TCP_IPV4 = 1 << 4,
127 MLX4_RSS_IPV4 = 1 << 5,
129 /* offset of mlx4_rss_context within mlx4_qp_context.pri_path */
130 MLX4_RSS_OFFSET_IN_QPC_PRI_PATH = 0x24,
131 /* offset of being RSS indirection QP within mlx4_qp_context.flags */
132 MLX4_RSS_QPC_FLAG_OFFSET = 13,
135 struct mlx4_rss_context {
145 struct mlx4_qp_path {
148 u8 disable_pkey_check;
157 __be32 tclass_flowlabel;
169 MLX4_FL_ETH_HIDE_CQE_VLAN = 1 << 2,
170 MLX4_FL_ETH_SRC_CHECK_MC_LB = 1 << 1,
171 MLX4_FL_ETH_SRC_CHECK_UC_LB = 1 << 0,
173 enum { /* vlan_control */
174 MLX4_VLAN_CTRL_ETH_SRC_CHECK_IF_COUNTER = 1 << 7,
175 MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED = 1 << 6,
176 MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED = 1 << 2,
177 MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED = 1 << 1,/* 802.1p priorty tag*/
178 MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED = 1 << 0
182 MLX4_FEUP_FORCE_ETH_UP = 1 << 6, /* force Eth UP */
183 MLX4_FSM_FORCE_ETH_SRC_MAC = 1 << 5, /* force Source MAC */
184 MLX4_FVL_FORCE_ETH_VLAN = 1 << 3 /* force Eth vlan */
188 MLX4_FVL_RX_FORCE_ETH_VLAN = 1 << 0 /* enforce Eth rx vlan */
191 struct mlx4_qp_context {
201 struct mlx4_qp_path pri_path;
202 struct mlx4_qp_path alt_path;
205 __be32 next_send_psn;
208 __be32 last_acked_psn;
211 __be32 rnr_nextrecvpsn;
218 __be16 rq_wqe_counter;
219 __be16 sq_wqe_counter;
222 __be32 nummmcpeers_basemkey;
226 __be32 mtt_base_addr_l;
230 struct mlx4_update_qp_context {
232 __be64 primary_addr_path_mask;
233 __be64 secondary_addr_path_mask;
235 struct mlx4_qp_context qp_context;
240 MLX4_UPD_QP_MASK_PM_STATE = 32,
241 MLX4_UPD_QP_MASK_VSD = 33,
245 MLX4_UPD_QP_PATH_MASK_PKEY_INDEX = 0 + 32,
246 MLX4_UPD_QP_PATH_MASK_FSM = 1 + 32,
247 MLX4_UPD_QP_PATH_MASK_MAC_INDEX = 2 + 32,
248 MLX4_UPD_QP_PATH_MASK_FVL = 3 + 32,
249 MLX4_UPD_QP_PATH_MASK_CV = 4 + 32,
250 MLX4_UPD_QP_PATH_MASK_VLAN_INDEX = 5 + 32,
251 MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN = 6 + 32,
252 MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED = 7 + 32,
253 MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P = 8 + 32,
254 MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED = 9 + 32,
255 MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED = 10 + 32,
256 MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P = 11 + 32,
257 MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED = 12 + 32,
258 MLX4_UPD_QP_PATH_MASK_FEUP = 13 + 32,
259 MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE = 14 + 32,
260 MLX4_UPD_QP_PATH_MASK_IF_COUNTER_INDEX = 15 + 32,
261 MLX4_UPD_QP_PATH_MASK_FVL_RX = 16 + 32,
262 MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_UC_LB = 18 + 32,
263 MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_MC_LB = 19 + 32,
267 MLX4_STRIP_VLAN = 1 << 30
271 /* Which firmware version adds support for NEC (NoErrorCompletion) bit */
272 #define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232)
275 MLX4_WQE_CTRL_OWN = 1 << 31,
276 MLX4_WQE_CTRL_NEC = 1 << 29,
277 MLX4_WQE_CTRL_RR = 1 << 6,
278 MLX4_WQE_CTRL_FENCE = 1 << 6,
279 MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2,
280 MLX4_WQE_CTRL_SOLICITED = 1 << 1,
281 MLX4_WQE_CTRL_IP_CSUM = 1 << 4,
282 MLX4_WQE_CTRL_TCP_UDP_CSUM = 1 << 5,
283 MLX4_WQE_CTRL_INS_VLAN = 1 << 6,
284 MLX4_WQE_CTRL_STRONG_ORDER = 1 << 7,
285 MLX4_WQE_CTRL_FORCE_LOOPBACK = 1 << 0,
288 struct mlx4_wqe_ctrl_seg {
294 * High 24 bits are SRC remote buffer; low 8 bits are flags:
295 * [7] SO (strong ordering)
296 * [5] TCP/UDP checksum
298 * [3:2] C (generate completion queue entry)
299 * [1] SE (solicited event)
300 * [0] FL (force loopback)
304 __be16 srcrb_flags16[2];
307 * imm is immediate data for send/RDMA write w/ immediate;
308 * also invalidation key for send with invalidate; input
309 * modifier for WQEs on CCQs.
315 MLX4_WQE_MLX_VL15 = 1 << 17,
316 MLX4_WQE_MLX_SLR = 1 << 16
319 struct mlx4_wqe_mlx_seg {
329 * [15:12] static rate
333 * [0] FL (force loopback)
340 struct mlx4_wqe_datagram_seg {
348 struct mlx4_wqe_lso_seg {
353 enum mlx4_wqe_bind_seg_flags2 {
354 MLX4_WQE_BIND_TYPE_2 = (1<<31),
355 MLX4_WQE_BIND_ZERO_BASED = (1<<30),
358 struct mlx4_wqe_bind_seg {
368 MLX4_WQE_FMR_PERM_LOCAL_READ = 1 << 27,
369 MLX4_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28,
370 MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ = 1 << 29,
371 MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE = 1 << 30,
372 MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC = 1 << 31
375 struct mlx4_wqe_fmr_seg {
386 struct mlx4_wqe_fmr_ext_seg {
392 __be32 wire_ref_tag_base;
393 __be32 mem_ref_tag_base;
396 struct mlx4_wqe_local_inval_seg {
403 struct mlx4_wqe_raddr_seg {
409 struct mlx4_wqe_atomic_seg {
414 struct mlx4_wqe_masked_atomic_seg {
417 __be64 swap_add_mask;
421 struct mlx4_wqe_data_seg {
428 MLX4_INLINE_ALIGN = 64,
429 MLX4_INLINE_SEG = 1 << 31,
432 struct mlx4_wqe_inline_seg {
436 int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
437 enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
438 struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar,
439 int sqd_event, struct mlx4_qp *qp);
441 int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp,
442 struct mlx4_qp_context *context);
444 int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
445 struct mlx4_qp_context *context,
446 struct mlx4_qp *qp, enum mlx4_qp_state *qp_state);
448 static inline struct mlx4_qp *__mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn)
450 return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1));
453 void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp);
455 #endif /* MLX4_QP_H */