sys/dev/mlx5/device.h

   1 /*-
   2  * Copyright (c) 2013-2019, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  */
  25
  26 #ifndef MLX5_DEVICE_H
  27 #define MLX5_DEVICE_H
  28
  29 #include <linux/types.h>
  30 #include <rdma/ib_verbs.h>
  31 #include <dev/mlx5/mlx5_ifc.h>
  32
  33 #define FW_INIT_TIMEOUT_MILI            2000
  34 #define FW_INIT_WAIT_MS                 2
  35 #define FW_PRE_INIT_TIMEOUT_MILI        120000
  36 #define FW_INIT_WARN_MESSAGE_INTERVAL   20000
  37
  38 #if defined(__LITTLE_ENDIAN)
  39 #define MLX5_SET_HOST_ENDIANNESS        0
  40 #elif defined(__BIG_ENDIAN)
  41 #define MLX5_SET_HOST_ENDIANNESS        0x80
  42 #else
  43 #error Host endianness not defined
  44 #endif
  45
  46 /* helper macros */
  47 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
  48 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
  49 #define __mlx5_bit_off(typ, fld) __offsetof(struct mlx5_ifc_##typ##_bits, fld)
  50 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
  51 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
  52 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
  53 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf))
  54 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
  55 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
  56 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
  57 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
  58 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld))
  59 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
  60
  61 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
  62 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
  63 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
  64 #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
  65 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
  66 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
  67 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
  68 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
  69
  70 /* insert a value to a struct */
  71 #define MLX5_SET(typ, p, fld, v) do { \
  72         BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32);             \
  73         BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \
  74         *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
  75         cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
  76                      (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
  77                      << __mlx5_dw_bit_off(typ, fld))); \
  78 } while (0)
  79
  80 #define MLX5_SET_TO_ONES(typ, p, fld) do { \
  81         BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32);             \
  82         BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \
  83         *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
  84         cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
  85                      (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
  86                      << __mlx5_dw_bit_off(typ, fld))); \
  87 } while (0)
  88
  89 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
  90 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
  91 __mlx5_mask(typ, fld))
  92
  93 #define MLX5_GET_PR(typ, p, fld) ({ \
  94         u32 ___t = MLX5_GET(typ, p, fld); \
  95         pr_debug(#fld " = 0x%x\n", ___t); \
  96         ___t; \
  97 })
  98
  99 #define __MLX5_SET64(typ, p, fld, v) do { \
 100         BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
 101         *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
 102 } while (0)
 103
 104 #define MLX5_SET64(typ, p, fld, v) do { \
 105         BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
 106         __MLX5_SET64(typ, p, fld, v); \
 107 } while (0)
 108
 109 #define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \
 110         BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
 111         __MLX5_SET64(typ, p, fld[idx], v); \
 112 } while (0)
 113
 114 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
 115
 116 #define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\
 117 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
 118 __mlx5_mask16(typ, fld))
 119
 120 #define MLX5_SET16(typ, p, fld, v) do { \
 121         u16 _v = v; \
 122         BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16);             \
 123         *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \
 124         cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \
 125                      (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \
 126                      << __mlx5_16_bit_off(typ, fld))); \
 127 } while (0)
 128
 129 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
 130         __mlx5_64_off(typ, fld)))
 131
 132 #define MLX5_GET_BE(type_t, typ, p, fld) ({                               \
 133                 type_t tmp;                                               \
 134                 switch (sizeof(tmp)) {                                    \
 135                 case sizeof(u8):                                          \
 136                         tmp = (__force type_t)MLX5_GET(typ, p, fld);      \
 137                         break;                                            \
 138                 case sizeof(u16):                                         \
 139                         tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
 140                         break;                                            \
 141                 case sizeof(u32):                                         \
 142                         tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
 143                         break;                                            \
 144                 case sizeof(u64):                                         \
 145                         tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
 146                         break;                                            \
 147                         }                                                 \
 148                 tmp;                                                      \
 149                 })
 150
 151 #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8
 152 #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8
 153 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
 154 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
 155                                     MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
 156                                     MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
 157
 158 /* insert a value to a struct */
 159 #define MLX5_VSC_SET(typ, p, fld, v) do { \
 160         BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32);             \
 161         BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \
 162         *((__le32 *)(p) + __mlx5_dw_off(typ, fld)) = \
 163         cpu_to_le32((le32_to_cpu(*((__le32 *)(p) + __mlx5_dw_off(typ, fld))) & \
 164                      (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
 165                      << __mlx5_dw_bit_off(typ, fld))); \
 166 } while (0)
 167
 168 #define MLX5_VSC_GET(typ, p, fld) ((le32_to_cpu(*((__le32 *)(p) +\
 169 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
 170 __mlx5_mask(typ, fld))
 171
 172 #define MLX5_VSC_GET_PR(typ, p, fld) ({ \
 173         u32 ___t = MLX5_VSC_GET(typ, p, fld); \
 174         pr_debug(#fld " = 0x%x\n", ___t); \
 175         ___t; \
 176 })
 177
 178 enum {
 179         MLX5_MAX_COMMANDS               = 32,
 180         MLX5_CMD_DATA_BLOCK_SIZE        = 512,
 181         MLX5_CMD_MBOX_SIZE              = 1024,
 182         MLX5_PCI_CMD_XPORT              = 7,
 183         MLX5_MKEY_BSF_OCTO_SIZE         = 4,
 184         MLX5_MAX_PSVS                   = 4,
 185 };
 186
 187 enum {
 188         MLX5_EXTENDED_UD_AV             = 0x80000000,
 189 };
 190
 191 enum {
 192         MLX5_CQ_FLAGS_OI        = 2,
 193 };
 194
 195 enum {
 196         MLX5_STAT_RATE_OFFSET   = 5,
 197 };
 198
 199 enum {
 200         MLX5_INLINE_SEG = 0x80000000,
 201 };
 202
 203 enum {
 204         MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
 205 };
 206
 207 enum {
 208         MLX5_MIN_PKEY_TABLE_SIZE = 128,
 209         MLX5_MAX_LOG_PKEY_TABLE  = 5,
 210 };
 211
 212 enum {
 213         MLX5_MKEY_INBOX_PG_ACCESS = 1U << 31
 214 };
 215
 216 enum {
 217         MLX5_PERM_LOCAL_READ    = 1 << 2,
 218         MLX5_PERM_LOCAL_WRITE   = 1 << 3,
 219         MLX5_PERM_REMOTE_READ   = 1 << 4,
 220         MLX5_PERM_REMOTE_WRITE  = 1 << 5,
 221         MLX5_PERM_ATOMIC        = 1 << 6,
 222         MLX5_PERM_UMR_EN        = 1 << 7,
 223 };
 224
 225 enum {
 226         MLX5_PCIE_CTRL_SMALL_FENCE      = 1 << 0,
 227         MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
 228         MLX5_PCIE_CTRL_NO_SNOOP         = 1 << 3,
 229         MLX5_PCIE_CTRL_TLP_PROCE_EN     = 1 << 6,
 230         MLX5_PCIE_CTRL_TPH_MASK         = 3 << 4,
 231 };
 232
 233 enum {
 234         MLX5_MKEY_REMOTE_INVAL  = 1 << 24,
 235         MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
 236         MLX5_MKEY_BSF_EN        = 1 << 30,
 237         MLX5_MKEY_LEN64         = 1U << 31,
 238 };
 239
 240 enum {
 241         MLX5_EN_RD      = (u64)1,
 242         MLX5_EN_WR      = (u64)2
 243 };
 244
 245 enum {
 246         MLX5_ADAPTER_PAGE_SHIFT         = 12,
 247         MLX5_ADAPTER_PAGE_SIZE          = 1 << MLX5_ADAPTER_PAGE_SHIFT,
 248 };
 249
 250 enum {
 251         MLX5_BFREGS_PER_UAR             = 4,
 252         MLX5_MAX_UARS                   = 1 << 8,
 253         MLX5_NON_FP_BFREGS_PER_UAR      = 2,
 254         MLX5_FP_BFREGS_PER_UAR          = MLX5_BFREGS_PER_UAR -
 255                                           MLX5_NON_FP_BFREGS_PER_UAR,
 256         MLX5_MAX_BFREGS                 = MLX5_MAX_UARS *
 257                                           MLX5_NON_FP_BFREGS_PER_UAR,
 258         MLX5_UARS_IN_PAGE               = PAGE_SIZE / MLX5_ADAPTER_PAGE_SIZE,
 259         MLX5_NON_FP_BFREGS_IN_PAGE      = MLX5_NON_FP_BFREGS_PER_UAR * MLX5_UARS_IN_PAGE,
 260         MLX5_MIN_DYN_BFREGS             = 512,
 261         MLX5_MAX_DYN_BFREGS             = 1024,
 262 };
 263
 264 enum {
 265         MLX5_MKEY_MASK_LEN              = 1ull << 0,
 266         MLX5_MKEY_MASK_PAGE_SIZE        = 1ull << 1,
 267         MLX5_MKEY_MASK_START_ADDR       = 1ull << 6,
 268         MLX5_MKEY_MASK_PD               = 1ull << 7,
 269         MLX5_MKEY_MASK_EN_RINVAL        = 1ull << 8,
 270         MLX5_MKEY_MASK_EN_SIGERR        = 1ull << 9,
 271         MLX5_MKEY_MASK_BSF_EN           = 1ull << 12,
 272         MLX5_MKEY_MASK_KEY              = 1ull << 13,
 273         MLX5_MKEY_MASK_QPN              = 1ull << 14,
 274         MLX5_MKEY_MASK_LR               = 1ull << 17,
 275         MLX5_MKEY_MASK_LW               = 1ull << 18,
 276         MLX5_MKEY_MASK_RR               = 1ull << 19,
 277         MLX5_MKEY_MASK_RW               = 1ull << 20,
 278         MLX5_MKEY_MASK_A                = 1ull << 21,
 279         MLX5_MKEY_MASK_SMALL_FENCE      = 1ull << 23,
 280         MLX5_MKEY_MASK_FREE             = 1ull << 29,
 281 };
 282
 283 enum {
 284         MLX5_UMR_TRANSLATION_OFFSET_EN  = (1 << 4),
 285
 286         MLX5_UMR_CHECK_NOT_FREE         = (1 << 5),
 287         MLX5_UMR_CHECK_FREE             = (2 << 5),
 288
 289         MLX5_UMR_INLINE                 = (1 << 7),
 290 };
 291
 292 #define MLX5_UMR_MTT_ALIGNMENT 0x40
 293 #define MLX5_UMR_MTT_MASK      (MLX5_UMR_MTT_ALIGNMENT - 1)
 294 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
 295
 296 enum {
 297         MLX5_EVENT_QUEUE_TYPE_QP = 0,
 298         MLX5_EVENT_QUEUE_TYPE_RQ = 1,
 299         MLX5_EVENT_QUEUE_TYPE_SQ = 2,
 300         MLX5_EVENT_QUEUE_TYPE_DCT = 6,
 301 };
 302
 303 enum {
 304         MLX5_PORT_CHANGE_SUBTYPE_DOWN           = 1,
 305         MLX5_PORT_CHANGE_SUBTYPE_ACTIVE         = 4,
 306         MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED    = 5,
 307         MLX5_PORT_CHANGE_SUBTYPE_LID            = 6,
 308         MLX5_PORT_CHANGE_SUBTYPE_PKEY           = 7,
 309         MLX5_PORT_CHANGE_SUBTYPE_GUID           = 8,
 310         MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG   = 9,
 311 };
 312
 313 enum {
 314         MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX = 1,
 315         MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE,
 316         MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE,
 317         MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE,
 318         MLX5_MAX_INLINE_RECEIVE_SIZE            = 64
 319 };
 320
 321 enum {
 322         MLX5_DEV_CAP_FLAG_XRC           = 1LL <<  3,
 323         MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL <<  8,
 324         MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL <<  9,
 325         MLX5_DEV_CAP_FLAG_APM           = 1LL << 17,
 326         MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD  = 1LL << 21,
 327         MLX5_DEV_CAP_FLAG_BLOCK_MCAST   = 1LL << 23,
 328         MLX5_DEV_CAP_FLAG_CQ_MODER      = 1LL << 29,
 329         MLX5_DEV_CAP_FLAG_RESIZE_CQ     = 1LL << 30,
 330         MLX5_DEV_CAP_FLAG_ATOMIC        = 1LL << 33,
 331         MLX5_DEV_CAP_FLAG_ROCE          = 1LL << 34,
 332         MLX5_DEV_CAP_FLAG_DCT           = 1LL << 37,
 333         MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
 334         MLX5_DEV_CAP_FLAG_CMDIF_CSUM    = 3LL << 46,
 335         MLX5_DEV_CAP_FLAG_DRAIN_SIGERR  = 1LL << 48,
 336 };
 337
 338 enum {
 339         MLX5_ROCE_VERSION_1             = 0,
 340         MLX5_ROCE_VERSION_1_5           = 1,
 341         MLX5_ROCE_VERSION_2             = 2,
 342 };
 343
 344 enum {
 345         MLX5_ROCE_VERSION_1_CAP         = 1 << MLX5_ROCE_VERSION_1,
 346         MLX5_ROCE_VERSION_1_5_CAP       = 1 << MLX5_ROCE_VERSION_1_5,
 347         MLX5_ROCE_VERSION_2_CAP         = 1 << MLX5_ROCE_VERSION_2,
 348 };
 349
 350 enum {
 351         MLX5_ROCE_L3_TYPE_IPV4          = 0,
 352         MLX5_ROCE_L3_TYPE_IPV6          = 1,
 353 };
 354
 355 enum {
 356         MLX5_ROCE_L3_TYPE_IPV4_CAP      = 1 << 1,
 357         MLX5_ROCE_L3_TYPE_IPV6_CAP      = 1 << 2,
 358 };
 359
 360 enum {
 361         MLX5_OPCODE_NOP                 = 0x00,
 362         MLX5_OPCODE_SEND_INVAL          = 0x01,
 363         MLX5_OPCODE_RDMA_WRITE          = 0x08,
 364         MLX5_OPCODE_RDMA_WRITE_IMM      = 0x09,
 365         MLX5_OPCODE_SEND                = 0x0a,
 366         MLX5_OPCODE_SEND_IMM            = 0x0b,
 367         MLX5_OPCODE_LSO                 = 0x0e,
 368         MLX5_OPCODE_RDMA_READ           = 0x10,
 369         MLX5_OPCODE_ATOMIC_CS           = 0x11,
 370         MLX5_OPCODE_ATOMIC_FA           = 0x12,
 371         MLX5_OPCODE_ATOMIC_MASKED_CS    = 0x14,
 372         MLX5_OPCODE_ATOMIC_MASKED_FA    = 0x15,
 373         MLX5_OPCODE_BIND_MW             = 0x18,
 374         MLX5_OPCODE_CONFIG_CMD          = 0x1f,
 375         MLX5_OPCODE_DUMP                = 0x23,
 376
 377         MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
 378         MLX5_RECV_OPCODE_SEND           = 0x01,
 379         MLX5_RECV_OPCODE_SEND_IMM       = 0x02,
 380         MLX5_RECV_OPCODE_SEND_INVAL     = 0x03,
 381
 382         MLX5_CQE_OPCODE_ERROR           = 0x1e,
 383         MLX5_CQE_OPCODE_RESIZE          = 0x16,
 384
 385         MLX5_OPCODE_SET_PSV             = 0x20,
 386         MLX5_OPCODE_GET_PSV             = 0x21,
 387         MLX5_OPCODE_CHECK_PSV           = 0x22,
 388         MLX5_OPCODE_RGET_PSV            = 0x26,
 389         MLX5_OPCODE_RCHECK_PSV          = 0x27,
 390
 391         MLX5_OPCODE_UMR                 = 0x25,
 392         MLX5_OPCODE_QOS_REMAP           = 0x2a,
 393
 394         MLX5_OPCODE_SIGNATURE_CANCELED  = (1 << 15),
 395 };
 396
 397 enum {
 398         MLX5_OPCODE_MOD_UMR_UMR = 0x0,
 399         MLX5_OPCODE_MOD_UMR_TLS_TIS_STATIC_PARAMS = 0x1,
 400         MLX5_OPCODE_MOD_UMR_TLS_TIR_STATIC_PARAMS = 0x2,
 401 };
 402
 403 enum {
 404         MLX5_OPCODE_MOD_PSV_PSV = 0x0,
 405         MLX5_OPCODE_MOD_PSV_TLS_TIS_PROGRESS_PARAMS = 0x1,
 406         MLX5_OPCODE_MOD_PSV_TLS_TIR_PROGRESS_PARAMS = 0x2,
 407 };
 408
 409 struct mlx5_wqe_tls_static_params_seg {
 410         u8     ctx[MLX5_ST_SZ_BYTES(tls_static_params)];
 411 };
 412
 413 struct mlx5_wqe_tls_progress_params_seg {
 414         u8     ctx[MLX5_ST_SZ_BYTES(tls_progress_params)];
 415 } __aligned(64);
 416
 417 enum {
 418         MLX5_SET_PORT_RESET_QKEY        = 0,
 419         MLX5_SET_PORT_GUID0             = 16,
 420         MLX5_SET_PORT_NODE_GUID         = 17,
 421         MLX5_SET_PORT_SYS_GUID          = 18,
 422         MLX5_SET_PORT_GID_TABLE         = 19,
 423         MLX5_SET_PORT_PKEY_TABLE        = 20,
 424 };
 425
 426 enum {
 427         MLX5_MAX_PAGE_SHIFT             = 31
 428 };
 429
 430 enum {
 431         MLX5_CAP_OFF_CMDIF_CSUM         = 46,
 432 };
 433
 434 enum {
 435         /*
 436          * Max wqe size for rdma read is 512 bytes, so this
 437          * limits our max_sge_rd as the wqe needs to fit:
 438          * - ctrl segment (16 bytes)
 439          * - rdma segment (16 bytes)
 440          * - scatter elements (16 bytes each)
 441          */
 442         MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
 443 };
 444
 445 struct mlx5_cmd_layout {
 446         u8              type;
 447         u8              rsvd0[3];
 448         __be32          inlen;
 449         __be64          in_ptr;
 450         __be32          in[4];
 451         __be32          out[4];
 452         __be64          out_ptr;
 453         __be32          outlen;
 454         u8              token;
 455         u8              sig;
 456         u8              rsvd1;
 457         u8              status_own;
 458 };
 459
 460 enum mlx5_fatal_assert_bit_offsets {
 461         MLX5_RFR_OFFSET = 31,
 462 };
 463
 464 struct mlx5_health_buffer {
 465         __be32          assert_var[5];
 466         __be32          rsvd0[3];
 467         __be32          assert_exit_ptr;
 468         __be32          assert_callra;
 469         __be32          rsvd1[2];
 470         __be32          fw_ver;
 471         __be32          hw_id;
 472         __be32          rfr;
 473         u8              irisc_index;
 474         u8              synd;
 475         __be16          ext_synd;
 476 };
 477
 478 enum mlx5_initializing_bit_offsets {
 479         MLX5_FW_RESET_SUPPORTED_OFFSET = 30,
 480 };
 481
 482 enum mlx5_cmd_addr_l_sz_offset {
 483         MLX5_NIC_IFC_OFFSET = 8,
 484 };
 485
 486 struct mlx5_init_seg {
 487         __be32                  fw_rev;
 488         __be32                  cmdif_rev_fw_sub;
 489         __be32                  rsvd0[2];
 490         __be32                  cmdq_addr_h;
 491         __be32                  cmdq_addr_l_sz;
 492         __be32                  cmd_dbell;
 493         __be32                  rsvd1[120];
 494         __be32                  initializing;
 495         struct mlx5_health_buffer  health;
 496         __be32                  rsvd2[880];
 497         __be32                  internal_timer_h;
 498         __be32                  internal_timer_l;
 499         __be32                  rsvd3[2];
 500         __be32                  health_counter;
 501         __be32                  rsvd4[1019];
 502         __be64                  ieee1588_clk;
 503         __be32                  ieee1588_clk_type;
 504         __be32                  clr_intx;
 505 };
 506
 507 struct mlx5_eqe_comp {
 508         __be32  reserved[6];
 509         __be32  cqn;
 510 };
 511
 512 struct mlx5_eqe_qp_srq {
 513         __be32  reserved1[5];
 514         u8      type;
 515         u8      reserved2[3];
 516         __be32  qp_srq_n;
 517 };
 518
 519 struct mlx5_eqe_cq_err {
 520         __be32  cqn;
 521         u8      reserved1[7];
 522         u8      syndrome;
 523 };
 524
 525 struct mlx5_eqe_xrq_err {
 526         __be32  reserved1[5];
 527         __be32  type_xrqn;
 528         __be32  reserved2;
 529 };
 530
 531 struct mlx5_eqe_port_state {
 532         u8      reserved0[8];
 533         u8      port;
 534 };
 535
 536 struct mlx5_eqe_gpio {
 537         __be32  reserved0[2];
 538         __be64  gpio_event;
 539 };
 540
 541 struct mlx5_eqe_congestion {
 542         u8      type;
 543         u8      rsvd0;
 544         u8      congestion_level;
 545 };
 546
 547 struct mlx5_eqe_stall_vl {
 548         u8      rsvd0[3];
 549         u8      port_vl;
 550 };
 551
 552 struct mlx5_eqe_cmd {
 553         __be32  vector;
 554         __be32  rsvd[6];
 555 };
 556
 557 struct mlx5_eqe_page_req {
 558         u8              rsvd0[2];
 559         __be16          func_id;
 560         __be32          num_pages;
 561         __be32          rsvd1[5];
 562 };
 563
 564 struct mlx5_eqe_vport_change {
 565         u8              rsvd0[2];
 566         __be16          vport_num;
 567         __be32          rsvd1[6];
 568 };
 569
 570
 571 #define PORT_MODULE_EVENT_MODULE_STATUS_MASK  0xF
 572 #define PORT_MODULE_EVENT_ERROR_TYPE_MASK     0xF
 573
 574 enum {
 575         MLX5_MODULE_STATUS_PLUGGED_ENABLED      = 0x1,
 576         MLX5_MODULE_STATUS_UNPLUGGED            = 0x2,
 577         MLX5_MODULE_STATUS_ERROR                = 0x3,
 578         MLX5_MODULE_STATUS_NUM                  ,
 579 };
 580
 581 enum {
 582         MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED                 = 0x0,
 583         MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE  = 0x1,
 584         MLX5_MODULE_EVENT_ERROR_BUS_STUCK                             = 0x2,
 585         MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT               = 0x3,
 586         MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST              = 0x4,
 587         MLX5_MODULE_EVENT_ERROR_UNSUPPORTED_CABLE                     = 0x5,
 588         MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE                      = 0x6,
 589         MLX5_MODULE_EVENT_ERROR_CABLE_IS_SHORTED                      = 0x7,
 590         MLX5_MODULE_EVENT_ERROR_PMD_TYPE_NOT_ENABLED                  = 0x8,
 591         MLX5_MODULE_EVENT_ERROR_LASTER_TEC_FAILURE                    = 0x9,
 592         MLX5_MODULE_EVENT_ERROR_HIGH_CURRENT                          = 0xa,
 593         MLX5_MODULE_EVENT_ERROR_HIGH_VOLTAGE                          = 0xb,
 594         MLX5_MODULE_EVENT_ERROR_PCIE_SYS_POWER_SLOT_EXCEEDED          = 0xc,
 595         MLX5_MODULE_EVENT_ERROR_HIGH_POWER                            = 0xd,
 596         MLX5_MODULE_EVENT_ERROR_MODULE_STATE_MACHINE_FAULT            = 0xe,
 597         MLX5_MODULE_EVENT_ERROR_NUM                                   ,
 598 };
 599
 600 struct mlx5_eqe_port_module_event {
 601         u8        rsvd0;
 602         u8        module;
 603         u8        rsvd1;
 604         u8        module_status;
 605         u8        rsvd2[2];
 606         u8        error_type;
 607 };
 608
 609 struct mlx5_eqe_general_notification_event {
 610         u32       rq_user_index_delay_drop;
 611         u32       rsvd0[6];
 612 };
 613
 614 struct mlx5_eqe_dct {
 615         __be32  reserved[6];
 616         __be32  dctn;
 617 };
 618
 619 struct mlx5_eqe_temp_warning {
 620         __be64 sensor_warning_msb;
 621         __be64 sensor_warning_lsb;
 622 } __packed;
 623
 624 union ev_data {
 625         __be32                          raw[7];
 626         struct mlx5_eqe_cmd             cmd;
 627         struct mlx5_eqe_comp            comp;
 628         struct mlx5_eqe_qp_srq          qp_srq;
 629         struct mlx5_eqe_cq_err          cq_err;
 630         struct mlx5_eqe_port_state      port;
 631         struct mlx5_eqe_gpio            gpio;
 632         struct mlx5_eqe_congestion      cong;
 633         struct mlx5_eqe_stall_vl        stall_vl;
 634         struct mlx5_eqe_page_req        req_pages;
 635         struct mlx5_eqe_port_module_event port_module_event;
 636         struct mlx5_eqe_vport_change    vport_change;
 637         struct mlx5_eqe_general_notification_event general_notifications;
 638         struct mlx5_eqe_dct             dct;
 639         struct mlx5_eqe_temp_warning    temp_warning;
 640         struct mlx5_eqe_xrq_err         xrq_err;
 641 } __packed;
 642
 643 struct mlx5_eqe {
 644         u8              rsvd0;
 645         u8              type;
 646         u8              rsvd1;
 647         u8              sub_type;
 648         __be32          rsvd2[7];
 649         union ev_data   data;
 650         __be16          rsvd3;
 651         u8              signature;
 652         u8              owner;
 653 } __packed;
 654
 655 struct mlx5_cmd_prot_block {
 656         u8              data[MLX5_CMD_DATA_BLOCK_SIZE];
 657         u8              rsvd0[48];
 658         __be64          next;
 659         __be32          block_num;
 660         u8              rsvd1;
 661         u8              token;
 662         u8              ctrl_sig;
 663         u8              sig;
 664 };
 665
 666 #define MLX5_NUM_CMDS_IN_ADAPTER_PAGE \
 667         (MLX5_ADAPTER_PAGE_SIZE / MLX5_CMD_MBOX_SIZE)
 668 CTASSERT(MLX5_CMD_MBOX_SIZE >= sizeof(struct mlx5_cmd_prot_block));
 669 CTASSERT(MLX5_CMD_MBOX_SIZE <= MLX5_ADAPTER_PAGE_SIZE);
 670
 671 enum {
 672         MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
 673 };
 674
 675 struct mlx5_err_cqe {
 676         u8      rsvd0[32];
 677         __be32  srqn;
 678         u8      rsvd1[18];
 679         u8      vendor_err_synd;
 680         u8      syndrome;
 681         __be32  s_wqe_opcode_qpn;
 682         __be16  wqe_counter;
 683         u8      signature;
 684         u8      op_own;
 685 };
 686
 687 struct mlx5_cqe64 {
 688         u8              tls_outer_l3_tunneled;
 689         u8              rsvd0;
 690         __be16          wqe_id;
 691         u8              lro_tcppsh_abort_dupack;
 692         u8              lro_min_ttl;
 693         __be16          lro_tcp_win;
 694         __be32          lro_ack_seq_num;
 695         __be32          rss_hash_result;
 696         u8              rss_hash_type;
 697         u8              ml_path;
 698         u8              rsvd20[2];
 699         __be16          check_sum;
 700         __be16          slid;
 701         __be32          flags_rqpn;
 702         u8              hds_ip_ext;
 703         u8              l4_hdr_type_etc;
 704         __be16          vlan_info;
 705         __be32          srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
 706         __be32          imm_inval_pkey;
 707         u8              rsvd40[4];
 708         __be32          byte_cnt;
 709         __be64          timestamp;
 710         __be32          sop_drop_qpn;
 711         __be16          wqe_counter;
 712         u8              signature;
 713         u8              op_own;
 714 };
 715
 716 #define MLX5_CQE_TSTMP_PTP      (1ULL << 63)
 717
 718 static inline u8 get_cqe_opcode(struct mlx5_cqe64 *cqe)
 719 {
 720         return (cqe->op_own >> 4);
 721 }
 722
 723 static inline bool get_cqe_lro_timestamp_valid(struct mlx5_cqe64 *cqe)
 724 {
 725         return (cqe->lro_tcppsh_abort_dupack >> 7) & 1;
 726 }
 727
 728 static inline bool get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
 729 {
 730         return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
 731 }
 732
 733 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
 734 {
 735         return (cqe->l4_hdr_type_etc >> 4) & 0x7;
 736 }
 737
 738 static inline u16 get_cqe_vlan(struct mlx5_cqe64 *cqe)
 739 {
 740         return be16_to_cpu(cqe->vlan_info) & 0xfff;
 741 }
 742
 743 static inline void get_cqe_smac(struct mlx5_cqe64 *cqe, u8 *smac)
 744 {
 745         memcpy(smac, &cqe->rss_hash_type , 4);
 746         memcpy(smac + 4, &cqe->slid , 2);
 747 }
 748
 749 static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe)
 750 {
 751         return cqe->l4_hdr_type_etc & 0x1;
 752 }
 753
 754 static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe)
 755 {
 756         return cqe->tls_outer_l3_tunneled & 0x1;
 757 }
 758
 759 static inline u8 get_cqe_tls_offload(struct mlx5_cqe64 *cqe)
 760 {
 761         return (cqe->tls_outer_l3_tunneled >> 3) & 0x3;
 762 }
 763
 764 enum {
 765         CQE_L4_HDR_TYPE_NONE                    = 0x0,
 766         CQE_L4_HDR_TYPE_TCP_NO_ACK              = 0x1,
 767         CQE_L4_HDR_TYPE_UDP                     = 0x2,
 768         CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA         = 0x3,
 769         CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA        = 0x4,
 770 };
 771
 772 enum {
 773         /* source L3 hash types */
 774         CQE_RSS_SRC_HTYPE_IP    = 0x3 << 0,
 775         CQE_RSS_SRC_HTYPE_IPV4  = 0x1 << 0,
 776         CQE_RSS_SRC_HTYPE_IPV6  = 0x2 << 0,
 777
 778         /* destination L3 hash types */
 779         CQE_RSS_DST_HTYPE_IP    = 0x3 << 2,
 780         CQE_RSS_DST_HTYPE_IPV4  = 0x1 << 2,
 781         CQE_RSS_DST_HTYPE_IPV6  = 0x2 << 2,
 782
 783         /* source L4 hash types */
 784         CQE_RSS_SRC_HTYPE_L4    = 0x3 << 4,
 785         CQE_RSS_SRC_HTYPE_TCP   = 0x1 << 4,
 786         CQE_RSS_SRC_HTYPE_UDP   = 0x2 << 4,
 787         CQE_RSS_SRC_HTYPE_IPSEC = 0x3 << 4,
 788
 789         /* destination L4 hash types */
 790         CQE_RSS_DST_HTYPE_L4    = 0x3 << 6,
 791         CQE_RSS_DST_HTYPE_TCP   = 0x1 << 6,
 792         CQE_RSS_DST_HTYPE_UDP   = 0x2 << 6,
 793         CQE_RSS_DST_HTYPE_IPSEC = 0x3 << 6,
 794 };
 795
 796 enum {
 797         MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH        = 0x0,
 798         MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6       = 0x1,
 799         MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4       = 0x2,
 800 };
 801
 802 enum {
 803         CQE_L2_OK       = 1 << 0,
 804         CQE_L3_OK       = 1 << 1,
 805         CQE_L4_OK       = 1 << 2,
 806 };
 807
 808 enum {
 809         CQE_TLS_OFFLOAD_NOT_DECRYPTED           = 0x0,
 810         CQE_TLS_OFFLOAD_DECRYPTED               = 0x1,
 811         CQE_TLS_OFFLOAD_RESYNC                  = 0x2,
 812         CQE_TLS_OFFLOAD_ERROR                   = 0x3,
 813 };
 814
 815 struct mlx5_sig_err_cqe {
 816         u8              rsvd0[16];
 817         __be32          expected_trans_sig;
 818         __be32          actual_trans_sig;
 819         __be32          expected_reftag;
 820         __be32          actual_reftag;
 821         __be16          syndrome;
 822         u8              rsvd22[2];
 823         __be32          mkey;
 824         __be64          err_offset;
 825         u8              rsvd30[8];
 826         __be32          qpn;
 827         u8              rsvd38[2];
 828         u8              signature;
 829         u8              op_own;
 830 };
 831
 832 struct mlx5_wqe_srq_next_seg {
 833         u8                      rsvd0[2];
 834         __be16                  next_wqe_index;
 835         u8                      signature;
 836         u8                      rsvd1[11];
 837 };
 838
 839 union mlx5_ext_cqe {
 840         struct ib_grh   grh;
 841         u8              inl[64];
 842 };
 843
 844 struct mlx5_cqe128 {
 845         union mlx5_ext_cqe      inl_grh;
 846         struct mlx5_cqe64       cqe64;
 847 };
 848
 849 enum {
 850         MLX5_MKEY_STATUS_FREE = 1 << 6,
 851 };
 852
 853 struct mlx5_mkey_seg {
 854         /* This is a two bit field occupying bits 31-30.
 855          * bit 31 is always 0,
 856          * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
 857          */
 858         u8              status;
 859         u8              pcie_control;
 860         u8              flags;
 861         u8              version;
 862         __be32          qpn_mkey7_0;
 863         u8              rsvd1[4];
 864         __be32          flags_pd;
 865         __be64          start_addr;
 866         __be64          len;
 867         __be32          bsfs_octo_size;
 868         u8              rsvd2[16];
 869         __be32          xlt_oct_size;
 870         u8              rsvd3[3];
 871         u8              log2_page_size;
 872         u8              rsvd4[4];
 873 };
 874
 875 #define MLX5_ATTR_EXTENDED_PORT_INFO    cpu_to_be16(0xff90)
 876
 877 enum {
 878         MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO        = 1 <<  0
 879 };
 880
 881 static inline int mlx5_host_is_le(void)
 882 {
 883 #if defined(__LITTLE_ENDIAN)
 884         return 1;
 885 #elif defined(__BIG_ENDIAN)
 886         return 0;
 887 #else
 888 #error Host endianness not defined
 889 #endif
 890 }
 891
 892 #define MLX5_CMD_OP_MAX 0x939
 893
 894 enum {
 895         VPORT_STATE_DOWN                = 0x0,
 896         VPORT_STATE_UP                  = 0x1,
 897         VPORT_STATE_FOLLOW              = 0x2,
 898 };
 899
 900 enum {
 901         MLX5_L3_PROT_TYPE_IPV4          = 0,
 902         MLX5_L3_PROT_TYPE_IPV6          = 1,
 903 };
 904
 905 enum {
 906         MLX5_L4_PROT_TYPE_TCP           = 0,
 907         MLX5_L4_PROT_TYPE_UDP           = 1,
 908 };
 909
 910 enum {
 911         MLX5_HASH_FIELD_SEL_SRC_IP      = 1 << 0,
 912         MLX5_HASH_FIELD_SEL_DST_IP      = 1 << 1,
 913         MLX5_HASH_FIELD_SEL_L4_SPORT    = 1 << 2,
 914         MLX5_HASH_FIELD_SEL_L4_DPORT    = 1 << 3,
 915         MLX5_HASH_FIELD_SEL_IPSEC_SPI   = 1 << 4,
 916 };
 917
 918 enum {
 919         MLX5_MATCH_OUTER_HEADERS        = 1 << 0,
 920         MLX5_MATCH_MISC_PARAMETERS      = 1 << 1,
 921         MLX5_MATCH_INNER_HEADERS        = 1 << 2,
 922
 923 };
 924
 925 enum {
 926         MLX5_FLOW_TABLE_TYPE_NIC_RCV     = 0,
 927         MLX5_FLOW_TABLE_TYPE_EGRESS_ACL  = 2,
 928         MLX5_FLOW_TABLE_TYPE_INGRESS_ACL = 3,
 929         MLX5_FLOW_TABLE_TYPE_ESWITCH     = 4,
 930         MLX5_FLOW_TABLE_TYPE_SNIFFER_RX  = 5,
 931         MLX5_FLOW_TABLE_TYPE_SNIFFER_TX  = 6,
 932         MLX5_FLOW_TABLE_TYPE_NIC_RX_RDMA = 7,
 933 };
 934
 935 enum {
 936         MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_NONE       = 0,
 937         MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_IF_NO_VLAN = 1,
 938         MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_OVERWRITE  = 2
 939 };
 940
 941 enum {
 942         MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_STRIP  = 1 << 0,
 943         MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_STRIP  = 1 << 1,
 944         MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_INSERT = 1 << 2,
 945         MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_INSERT = 1 << 3
 946 };
 947
 948 enum {
 949         MLX5_UC_ADDR_CHANGE = (1 << 0),
 950         MLX5_MC_ADDR_CHANGE = (1 << 1),
 951         MLX5_VLAN_CHANGE    = (1 << 2),
 952         MLX5_PROMISC_CHANGE = (1 << 3),
 953         MLX5_MTU_CHANGE     = (1 << 4),
 954 };
 955
 956 enum mlx5_list_type {
 957         MLX5_NIC_VPORT_LIST_TYPE_UC   = 0x0,
 958         MLX5_NIC_VPORT_LIST_TYPE_MC   = 0x1,
 959         MLX5_NIC_VPORT_LIST_TYPE_VLAN = 0x2,
 960 };
 961
 962 enum {
 963         MLX5_ESW_VPORT_ADMIN_STATE_DOWN  = 0x0,
 964         MLX5_ESW_VPORT_ADMIN_STATE_UP    = 0x1,
 965         MLX5_ESW_VPORT_ADMIN_STATE_AUTO  = 0x2,
 966 };
 967
 968 /* MLX5 DEV CAPs */
 969
 970 /* TODO: EAT.ME */
 971 enum mlx5_cap_mode {
 972         HCA_CAP_OPMOD_GET_MAX   = 0,
 973         HCA_CAP_OPMOD_GET_CUR   = 1,
 974 };
 975
 976 enum mlx5_cap_type {
 977         MLX5_CAP_GENERAL = 0,
 978         MLX5_CAP_ETHERNET_OFFLOADS,
 979         MLX5_CAP_ODP,
 980         MLX5_CAP_ATOMIC,
 981         MLX5_CAP_ROCE,
 982         MLX5_CAP_IPOIB_OFFLOADS,
 983         MLX5_CAP_EOIB_OFFLOADS,
 984         MLX5_CAP_FLOW_TABLE,
 985         MLX5_CAP_ESWITCH_FLOW_TABLE,
 986         MLX5_CAP_ESWITCH,
 987         MLX5_CAP_SNAPSHOT,
 988         MLX5_CAP_VECTOR_CALC,
 989         MLX5_CAP_QOS,
 990         MLX5_CAP_DEBUG,
 991         MLX5_CAP_NVME,
 992         MLX5_CAP_DMC,
 993         MLX5_CAP_DEC,
 994         MLX5_CAP_TLS,
 995         MLX5_CAP_DEV_EVENT = 0x14,
 996         MLX5_CAP_GENERAL_2 = 0x20,
 997         /* NUM OF CAP Types */
 998         MLX5_CAP_NUM
 999 };
1000
1001 enum mlx5_qcam_reg_groups {
1002         MLX5_QCAM_REGS_FIRST_128 = 0x0,
1003 };
1004
1005 enum mlx5_qcam_feature_groups {
1006         MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1007 };
1008
1009 enum mlx5_pcam_reg_groups {
1010         MLX5_PCAM_REGS_5000_TO_507F = 0x0,
1011 };
1012
1013 enum mlx5_pcam_feature_groups {
1014         MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1015 };
1016
1017 enum mlx5_mcam_reg_groups {
1018         MLX5_MCAM_REGS_FIRST_128 = 0x0,
1019 };
1020
1021 enum mlx5_mcam_feature_groups {
1022         MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0,
1023 };
1024
1025 /* GET Dev Caps macros */
1026 #define MLX5_CAP_GEN(mdev, cap) \
1027         MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
1028
1029 #define MLX5_CAP_GEN_64(mdev, cap)                                      \
1030         MLX5_GET64(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
1031
1032 #define MLX5_CAP_GEN_MAX(mdev, cap) \
1033         MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
1034
1035 #define MLX5_CAP_GEN_2(mdev, cap) \
1036         MLX5_GET(cmd_hca_cap_2, mdev->hca_caps_cur[MLX5_CAP_GENERAL_2], cap)
1037
1038 #define MLX5_CAP_ETH(mdev, cap) \
1039         MLX5_GET(per_protocol_networking_offload_caps,\
1040                  mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1041
1042 #define MLX5_CAP_ETH_MAX(mdev, cap) \
1043         MLX5_GET(per_protocol_networking_offload_caps,\
1044                  mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
1045
1046 #define MLX5_CAP_ROCE(mdev, cap) \
1047         MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
1048
1049 #define MLX5_CAP_ROCE_MAX(mdev, cap) \
1050         MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
1051
1052 #define MLX5_CAP_ATOMIC(mdev, cap) \
1053         MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
1054
1055 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
1056         MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
1057
1058 #define MLX5_CAP_FLOWTABLE(mdev, cap) \
1059         MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
1060
1061 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1062         MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
1063
1064 #define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \
1065         MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
1066
1067 #define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \
1068         MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
1069
1070 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1071         MLX5_GET(flow_table_eswitch_cap, \
1072                  mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1073
1074 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
1075         MLX5_GET(flow_table_eswitch_cap, \
1076                  mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1077
1078 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1079         MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1080
1081 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
1082         MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1083
1084 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
1085         MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1086
1087 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \
1088         MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1089
1090 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
1091         MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1092
1093 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \
1094         MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1095
1096 #define MLX5_CAP_ESW(mdev, cap) \
1097         MLX5_GET(e_switch_cap, \
1098                  mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap)
1099
1100 #define MLX5_CAP_ESW_MAX(mdev, cap) \
1101         MLX5_GET(e_switch_cap, \
1102                  mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap)
1103
1104 #define MLX5_CAP_ODP(mdev, cap)\
1105         MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1106
1107 #define MLX5_CAP_ODP_MAX(mdev, cap)\
1108         MLX5_GET(odp_cap, mdev->hca_caps_max[MLX5_CAP_ODP], cap)
1109
1110 #define MLX5_CAP_SNAPSHOT(mdev, cap) \
1111         MLX5_GET(snapshot_cap, \
1112                  mdev->hca_caps_cur[MLX5_CAP_SNAPSHOT], cap)
1113
1114 #define MLX5_CAP_SNAPSHOT_MAX(mdev, cap) \
1115         MLX5_GET(snapshot_cap, \
1116                  mdev->hca_caps_max[MLX5_CAP_SNAPSHOT], cap)
1117
1118 #define MLX5_CAP_EOIB_OFFLOADS(mdev, cap) \
1119         MLX5_GET(per_protocol_networking_offload_caps,\
1120                  mdev->hca_caps_cur[MLX5_CAP_EOIB_OFFLOADS], cap)
1121
1122 #define MLX5_CAP_EOIB_OFFLOADS_MAX(mdev, cap) \
1123         MLX5_GET(per_protocol_networking_offload_caps,\
1124                  mdev->hca_caps_max[MLX5_CAP_EOIB_OFFLOADS], cap)
1125
1126 #define MLX5_CAP_DEBUG(mdev, cap) \
1127         MLX5_GET(debug_cap, \
1128                  mdev->hca_caps_cur[MLX5_CAP_DEBUG], cap)
1129
1130 #define MLX5_CAP_DEBUG_MAX(mdev, cap) \
1131         MLX5_GET(debug_cap, \
1132                  mdev->hca_caps_max[MLX5_CAP_DEBUG], cap)
1133
1134 #define MLX5_CAP_QOS(mdev, cap) \
1135         MLX5_GET(qos_cap,\
1136                  mdev->hca_caps_cur[MLX5_CAP_QOS], cap)
1137
1138 #define MLX5_CAP_QOS_MAX(mdev, cap) \
1139         MLX5_GET(qos_cap,\
1140                  mdev->hca_caps_max[MLX5_CAP_QOS], cap)
1141
1142 #define MLX5_CAP_PCAM_FEATURE(mdev, fld) \
1143         MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
1144
1145 #define MLX5_CAP_PCAM_REG(mdev, reg) \
1146         MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg)
1147
1148 #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
1149         MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
1150
1151 #define MLX5_CAP_MCAM_REG(mdev, reg) \
1152         MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg)
1153
1154 #define MLX5_CAP_QCAM_REG(mdev, fld) \
1155         MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)
1156
1157 #define MLX5_CAP_QCAM_FEATURE(mdev, fld) \
1158         MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld)
1159
1160 #define MLX5_CAP_FPGA(mdev, cap) \
1161         MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1162
1163 #define MLX5_CAP64_FPGA(mdev, cap) \
1164         MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1165
1166 #define MLX5_CAP_TLS(mdev, cap) \
1167         MLX5_GET(tls_capabilities, (mdev)->hca_caps_cur[MLX5_CAP_TLS], cap)
1168
1169 #define MLX5_CAP_DEV_EVENT(mdev, cap)\
1170         MLX5_ADDR_OF(device_event_cap, (mdev)->hca_caps_cur[MLX5_CAP_DEV_EVENT], cap)
1171
1172 enum {
1173         MLX5_CMD_STAT_OK                        = 0x0,
1174         MLX5_CMD_STAT_INT_ERR                   = 0x1,
1175         MLX5_CMD_STAT_BAD_OP_ERR                = 0x2,
1176         MLX5_CMD_STAT_BAD_PARAM_ERR             = 0x3,
1177         MLX5_CMD_STAT_BAD_SYS_STATE_ERR         = 0x4,
1178         MLX5_CMD_STAT_BAD_RES_ERR               = 0x5,
1179         MLX5_CMD_STAT_RES_BUSY                  = 0x6,
1180         MLX5_CMD_STAT_LIM_ERR                   = 0x8,
1181         MLX5_CMD_STAT_BAD_RES_STATE_ERR         = 0x9,
1182         MLX5_CMD_STAT_IX_ERR                    = 0xa,
1183         MLX5_CMD_STAT_NO_RES_ERR                = 0xf,
1184         MLX5_CMD_STAT_BAD_INP_LEN_ERR           = 0x50,
1185         MLX5_CMD_STAT_BAD_OUTP_LEN_ERR          = 0x51,
1186         MLX5_CMD_STAT_BAD_QP_STATE_ERR          = 0x10,
1187         MLX5_CMD_STAT_BAD_PKT_ERR               = 0x30,
1188         MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR    = 0x40,
1189 };
1190
1191 enum {
1192         MLX5_IEEE_802_3_COUNTERS_GROUP        = 0x0,
1193         MLX5_RFC_2863_COUNTERS_GROUP          = 0x1,
1194         MLX5_RFC_2819_COUNTERS_GROUP          = 0x2,
1195         MLX5_RFC_3635_COUNTERS_GROUP          = 0x3,
1196         MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1197         MLX5_ETHERNET_DISCARD_COUNTERS_GROUP  = 0x6,
1198         MLX5_PER_PRIORITY_COUNTERS_GROUP      = 0x10,
1199         MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
1200         MLX5_PHYSICAL_LAYER_COUNTERS_GROUP    = 0x12,
1201         MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16,
1202         MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
1203 };
1204
1205 enum {
1206         MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP       = 0x0,
1207         MLX5_PCIE_LANE_COUNTERS_GROUP         = 0x1,
1208         MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP = 0x2,
1209 };
1210
1211 enum {
1212         MLX5_CAP_PORT_TYPE_IB  = 0x0,
1213         MLX5_CAP_PORT_TYPE_ETH = 0x1,
1214 };
1215
1216 enum {
1217         MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_L2           = 0x0,
1218         MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_VPORT_CONFIG = 0x1,
1219         MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_NOT_REQUIRED = 0x2
1220 };
1221
1222 enum mlx5_inline_modes {
1223         MLX5_INLINE_MODE_NONE,
1224         MLX5_INLINE_MODE_L2,
1225         MLX5_INLINE_MODE_IP,
1226         MLX5_INLINE_MODE_TCP_UDP,
1227 };
1228
1229 enum {
1230         MLX5_QUERY_VPORT_STATE_OUT_STATE_FOLLOW = 0x2,
1231 };
1232
1233 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1234 {
1235         if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1236                 return 0;
1237         return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1238 }
1239
1240 struct mlx5_ifc_mcia_reg_bits {
1241         u8         l[0x1];
1242         u8         reserved_0[0x7];
1243         u8         module[0x8];
1244         u8         reserved_1[0x8];
1245         u8         status[0x8];
1246
1247         u8         i2c_device_address[0x8];
1248         u8         page_number[0x8];
1249         u8         device_address[0x10];
1250
1251         u8         reserved_2[0x10];
1252         u8         size[0x10];
1253
1254         u8         reserved_3[0x20];
1255
1256         u8         dword_0[0x20];
1257         u8         dword_1[0x20];
1258         u8         dword_2[0x20];
1259         u8         dword_3[0x20];
1260         u8         dword_4[0x20];
1261         u8         dword_5[0x20];
1262         u8         dword_6[0x20];
1263         u8         dword_7[0x20];
1264         u8         dword_8[0x20];
1265         u8         dword_9[0x20];
1266         u8         dword_10[0x20];
1267         u8         dword_11[0x20];
1268 };
1269
1270 #define MLX5_CMD_OP_QUERY_EEPROM 0x93c
1271
1272 struct mlx5_mini_cqe8 {
1273         union {
1274                 __be32 rx_hash_result;
1275                 __be16 checksum;
1276                 __be16 rsvd;
1277                 struct {
1278                         __be16 wqe_counter;
1279                         u8  s_wqe_opcode;
1280                         u8  reserved;
1281                 } s_wqe_info;
1282         };
1283         __be32 byte_cnt;
1284 };
1285
1286 enum {
1287         MLX5_NO_INLINE_DATA,
1288         MLX5_INLINE_DATA32_SEG,
1289         MLX5_INLINE_DATA64_SEG,
1290         MLX5_COMPRESSED,
1291 };
1292
1293 enum mlx5_exp_cqe_zip_recv_type {
1294         MLX5_CQE_FORMAT_HASH,
1295         MLX5_CQE_FORMAT_CSUM,
1296 };
1297
1298 #define MLX5E_CQE_FORMAT_MASK 0xc
1299 static inline int mlx5_get_cqe_format(const struct mlx5_cqe64 *cqe)
1300 {
1301         return (cqe->op_own & MLX5E_CQE_FORMAT_MASK) >> 2;
1302 }
1303
1304 enum {
1305         MLX5_GEN_EVENT_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1,
1306         MLX5_GEN_EVENT_SUBTYPE_PCI_POWER_CHANGE_EVENT = 0x5,
1307 };
1308
1309 enum {
1310         MLX5_FRL_LEVEL3 = 0x8,
1311         MLX5_FRL_LEVEL6 = 0x40,
1312 };
1313
1314 /* 8 regular priorities + 1 for multicast */
1315 #define MLX5_NUM_BYPASS_FTS     9
1316
1317 #endif /* MLX5_DEVICE_H */