2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <linux/types.h>
32 #include <rdma/ib_verbs.h>
33 #include <dev/mlx5/mlx5_ifc.h>
35 #define FW_INIT_TIMEOUT_MILI 2000
36 #define FW_INIT_WAIT_MS 2
38 #if defined(__LITTLE_ENDIAN)
39 #define MLX5_SET_HOST_ENDIANNESS 0
40 #elif defined(__BIG_ENDIAN)
41 #define MLX5_SET_HOST_ENDIANNESS 0x80
43 #error Host endianness not defined
47 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
48 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
49 #define __mlx5_bit_off(typ, fld) __offsetof(struct mlx5_ifc_##typ##_bits, fld)
50 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
51 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
52 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
53 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
54 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
55 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
57 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
58 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
59 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
60 #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
61 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
62 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
63 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
64 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
66 /* insert a value to a struct */
67 #define MLX5_SET(typ, p, fld, v) do { \
68 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
69 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \
70 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
71 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
72 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
73 << __mlx5_dw_bit_off(typ, fld))); \
76 #define MLX5_SET_TO_ONES(typ, p, fld) do { \
77 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
78 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \
79 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
80 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
81 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
82 << __mlx5_dw_bit_off(typ, fld))); \
85 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
86 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
87 __mlx5_mask(typ, fld))
89 #define MLX5_GET_PR(typ, p, fld) ({ \
90 u32 ___t = MLX5_GET(typ, p, fld); \
91 pr_debug(#fld " = 0x%x\n", ___t); \
95 #define __MLX5_SET64(typ, p, fld, v) do { \
96 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
97 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
100 #define MLX5_SET64(typ, p, fld, v) do { \
101 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
102 __MLX5_SET64(typ, p, fld, v); \
105 #define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \
106 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
107 __MLX5_SET64(typ, p, fld[idx], v); \
110 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
112 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
113 __mlx5_64_off(typ, fld)))
115 #define MLX5_GET_BE(type_t, typ, p, fld) ({ \
117 switch (sizeof(tmp)) { \
119 tmp = (__force type_t)MLX5_GET(typ, p, fld); \
122 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
125 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
128 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
134 #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8
135 #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8
136 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
137 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
138 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
139 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
141 /* insert a value to a struct */
142 #define MLX5_VSC_SET(typ, p, fld, v) do { \
143 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
144 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \
145 *((__le32 *)(p) + __mlx5_dw_off(typ, fld)) = \
146 cpu_to_le32((le32_to_cpu(*((__le32 *)(p) + __mlx5_dw_off(typ, fld))) & \
147 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
148 << __mlx5_dw_bit_off(typ, fld))); \
151 #define MLX5_VSC_GET(typ, p, fld) ((le32_to_cpu(*((__le32 *)(p) +\
152 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
153 __mlx5_mask(typ, fld))
155 #define MLX5_VSC_GET_PR(typ, p, fld) ({ \
156 u32 ___t = MLX5_VSC_GET(typ, p, fld); \
157 pr_debug(#fld " = 0x%x\n", ___t); \
162 MLX5_MAX_COMMANDS = 32,
163 MLX5_CMD_DATA_BLOCK_SIZE = 512,
164 MLX5_CMD_MBOX_SIZE = 1024,
165 MLX5_PCI_CMD_XPORT = 7,
166 MLX5_MKEY_BSF_OCTO_SIZE = 4,
171 MLX5_EXTENDED_UD_AV = 0x80000000,
175 MLX5_CQ_FLAGS_OI = 2,
179 MLX5_STAT_RATE_OFFSET = 5,
183 MLX5_INLINE_SEG = 0x80000000,
187 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
191 MLX5_MIN_PKEY_TABLE_SIZE = 128,
192 MLX5_MAX_LOG_PKEY_TABLE = 5,
196 MLX5_MKEY_INBOX_PG_ACCESS = 1U << 31
200 MLX5_PERM_LOCAL_READ = 1 << 2,
201 MLX5_PERM_LOCAL_WRITE = 1 << 3,
202 MLX5_PERM_REMOTE_READ = 1 << 4,
203 MLX5_PERM_REMOTE_WRITE = 1 << 5,
204 MLX5_PERM_ATOMIC = 1 << 6,
205 MLX5_PERM_UMR_EN = 1 << 7,
209 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
210 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
211 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
212 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
213 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
217 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
218 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
219 MLX5_MKEY_BSF_EN = 1 << 30,
220 MLX5_MKEY_LEN64 = 1U << 31,
229 MLX5_BF_REGS_PER_PAGE = 4,
230 MLX5_MAX_UAR_PAGES = 1 << 8,
231 MLX5_NON_FP_BF_REGS_PER_PAGE = 2,
232 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
236 MLX5_MKEY_MASK_LEN = 1ull << 0,
237 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
238 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
239 MLX5_MKEY_MASK_PD = 1ull << 7,
240 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
241 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
242 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
243 MLX5_MKEY_MASK_KEY = 1ull << 13,
244 MLX5_MKEY_MASK_QPN = 1ull << 14,
245 MLX5_MKEY_MASK_LR = 1ull << 17,
246 MLX5_MKEY_MASK_LW = 1ull << 18,
247 MLX5_MKEY_MASK_RR = 1ull << 19,
248 MLX5_MKEY_MASK_RW = 1ull << 20,
249 MLX5_MKEY_MASK_A = 1ull << 21,
250 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
251 MLX5_MKEY_MASK_FREE = 1ull << 29,
255 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
257 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
258 MLX5_UMR_CHECK_FREE = (2 << 5),
260 MLX5_UMR_INLINE = (1 << 7),
263 #define MLX5_UMR_MTT_ALIGNMENT 0x40
264 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
265 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
268 MLX5_EVENT_QUEUE_TYPE_QP = 0,
269 MLX5_EVENT_QUEUE_TYPE_RQ = 1,
270 MLX5_EVENT_QUEUE_TYPE_SQ = 2,
274 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
275 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
276 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
277 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
278 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
279 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
280 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
284 MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX = 1,
285 MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE,
286 MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE,
287 MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE,
288 MLX5_MAX_INLINE_RECEIVE_SIZE = 64
292 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
293 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
294 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
295 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
296 MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD = 1LL << 21,
297 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
298 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
299 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
300 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 33,
301 MLX5_DEV_CAP_FLAG_ROCE = 1LL << 34,
302 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
303 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
304 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
305 MLX5_DEV_CAP_FLAG_DRAIN_SIGERR = 1LL << 48,
309 MLX5_ROCE_VERSION_1 = 0,
310 MLX5_ROCE_VERSION_1_5 = 1,
311 MLX5_ROCE_VERSION_2 = 2,
315 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
316 MLX5_ROCE_VERSION_1_5_CAP = 1 << MLX5_ROCE_VERSION_1_5,
317 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
321 MLX5_ROCE_L3_TYPE_IPV4 = 0,
322 MLX5_ROCE_L3_TYPE_IPV6 = 1,
326 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
327 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
331 MLX5_OPCODE_NOP = 0x00,
332 MLX5_OPCODE_SEND_INVAL = 0x01,
333 MLX5_OPCODE_RDMA_WRITE = 0x08,
334 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
335 MLX5_OPCODE_SEND = 0x0a,
336 MLX5_OPCODE_SEND_IMM = 0x0b,
337 MLX5_OPCODE_LSO = 0x0e,
338 MLX5_OPCODE_RDMA_READ = 0x10,
339 MLX5_OPCODE_ATOMIC_CS = 0x11,
340 MLX5_OPCODE_ATOMIC_FA = 0x12,
341 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
342 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
343 MLX5_OPCODE_BIND_MW = 0x18,
344 MLX5_OPCODE_CONFIG_CMD = 0x1f,
346 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
347 MLX5_RECV_OPCODE_SEND = 0x01,
348 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
349 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
351 MLX5_CQE_OPCODE_ERROR = 0x1e,
352 MLX5_CQE_OPCODE_RESIZE = 0x16,
354 MLX5_OPCODE_SET_PSV = 0x20,
355 MLX5_OPCODE_GET_PSV = 0x21,
356 MLX5_OPCODE_CHECK_PSV = 0x22,
357 MLX5_OPCODE_RGET_PSV = 0x26,
358 MLX5_OPCODE_RCHECK_PSV = 0x27,
360 MLX5_OPCODE_UMR = 0x25,
362 MLX5_OPCODE_SIGNATURE_CANCELED = (1 << 15),
366 MLX5_SET_PORT_RESET_QKEY = 0,
367 MLX5_SET_PORT_GUID0 = 16,
368 MLX5_SET_PORT_NODE_GUID = 17,
369 MLX5_SET_PORT_SYS_GUID = 18,
370 MLX5_SET_PORT_GID_TABLE = 19,
371 MLX5_SET_PORT_PKEY_TABLE = 20,
375 MLX5_MAX_PAGE_SHIFT = 31
379 MLX5_ADAPTER_PAGE_SHIFT = 12,
380 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
384 MLX5_CAP_OFF_CMDIF_CSUM = 46,
389 * Max wqe size for rdma read is 512 bytes, so this
390 * limits our max_sge_rd as the wqe needs to fit:
391 * - ctrl segment (16 bytes)
392 * - rdma segment (16 bytes)
393 * - scatter elements (16 bytes each)
395 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
398 struct mlx5_cmd_layout {
413 enum mlx5_fatal_assert_bit_offsets {
414 MLX5_RFR_OFFSET = 31,
417 struct mlx5_health_buffer {
418 __be32 assert_var[5];
420 __be32 assert_exit_ptr;
421 __be32 assert_callra;
431 enum mlx5_initializing_bit_offsets {
432 MLX5_FW_RESET_SUPPORTED_OFFSET = 30,
435 enum mlx5_cmd_addr_l_sz_offset {
436 MLX5_NIC_IFC_OFFSET = 8,
439 struct mlx5_init_seg {
441 __be32 cmdif_rev_fw_sub;
444 __be32 cmdq_addr_l_sz;
448 struct mlx5_health_buffer health;
450 __be32 internal_timer_h;
451 __be32 internal_timer_l;
453 __be32 health_counter;
456 __be32 ieee1588_clk_type;
460 struct mlx5_eqe_comp {
465 struct mlx5_eqe_qp_srq {
470 struct mlx5_eqe_cq_err {
476 struct mlx5_eqe_port_state {
481 struct mlx5_eqe_gpio {
486 struct mlx5_eqe_congestion {
492 struct mlx5_eqe_stall_vl {
497 struct mlx5_eqe_cmd {
502 struct mlx5_eqe_page_req {
509 struct mlx5_eqe_vport_change {
516 #define PORT_MODULE_EVENT_MODULE_STATUS_MASK 0xF
517 #define PORT_MODULE_EVENT_ERROR_TYPE_MASK 0xF
520 MLX5_MODULE_STATUS_PLUGGED_ENABLED = 0x1,
521 MLX5_MODULE_STATUS_UNPLUGGED = 0x2,
522 MLX5_MODULE_STATUS_ERROR = 0x3,
523 MLX5_MODULE_STATUS_PLUGGED_DISABLED = 0x4,
527 MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED = 0x0,
528 MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE = 0x1,
529 MLX5_MODULE_EVENT_ERROR_BUS_STUCK = 0x2,
530 MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT = 0x3,
531 MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST = 0x4,
532 MLX5_MODULE_EVENT_ERROR_UNSUPPORTED_CABLE = 0x5,
533 MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE = 0x6,
534 MLX5_MODULE_EVENT_ERROR_CABLE_IS_SHORTED = 0x7,
537 struct mlx5_eqe_port_module_event {
546 struct mlx5_eqe_general_notification_event {
547 u32 rq_user_index_delay_drop;
553 struct mlx5_eqe_cmd cmd;
554 struct mlx5_eqe_comp comp;
555 struct mlx5_eqe_qp_srq qp_srq;
556 struct mlx5_eqe_cq_err cq_err;
557 struct mlx5_eqe_port_state port;
558 struct mlx5_eqe_gpio gpio;
559 struct mlx5_eqe_congestion cong;
560 struct mlx5_eqe_stall_vl stall_vl;
561 struct mlx5_eqe_page_req req_pages;
562 struct mlx5_eqe_port_module_event port_module_event;
563 struct mlx5_eqe_vport_change vport_change;
564 struct mlx5_eqe_general_notification_event general_notifications;
579 struct mlx5_cmd_prot_block {
580 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
590 #define MLX5_NUM_CMDS_IN_ADAPTER_PAGE \
591 (MLX5_ADAPTER_PAGE_SIZE / MLX5_CMD_MBOX_SIZE)
592 CTASSERT(MLX5_CMD_MBOX_SIZE >= sizeof(struct mlx5_cmd_prot_block));
593 CTASSERT(MLX5_CMD_MBOX_SIZE <= MLX5_ADAPTER_PAGE_SIZE);
596 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
599 struct mlx5_err_cqe {
605 __be32 s_wqe_opcode_qpn;
614 u8 lro_tcppsh_abort_dupack;
617 __be32 lro_ack_seq_num;
618 __be32 rss_hash_result;
628 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
629 __be32 imm_inval_pkey;
639 #define MLX5_CQE_TSTMP_PTP (1ULL << 63)
641 static inline bool get_cqe_lro_timestamp_valid(struct mlx5_cqe64 *cqe)
643 return (cqe->lro_tcppsh_abort_dupack >> 7) & 1;
646 static inline bool get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
648 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
651 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
653 return (cqe->l4_hdr_type_etc >> 4) & 0x7;
656 static inline u16 get_cqe_vlan(struct mlx5_cqe64 *cqe)
658 return be16_to_cpu(cqe->vlan_info) & 0xfff;
661 static inline void get_cqe_smac(struct mlx5_cqe64 *cqe, u8 *smac)
663 memcpy(smac, &cqe->rss_hash_type , 4);
664 memcpy(smac + 4, &cqe->slid , 2);
667 static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe)
669 return cqe->l4_hdr_type_etc & 0x1;
672 static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe)
674 return cqe->tunneled_etc & 0x1;
678 CQE_L4_HDR_TYPE_NONE = 0x0,
679 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
680 CQE_L4_HDR_TYPE_UDP = 0x2,
681 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
682 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
686 /* source L3 hash types */
687 CQE_RSS_SRC_HTYPE_IP = 0x3 << 0,
688 CQE_RSS_SRC_HTYPE_IPV4 = 0x1 << 0,
689 CQE_RSS_SRC_HTYPE_IPV6 = 0x2 << 0,
691 /* destination L3 hash types */
692 CQE_RSS_DST_HTYPE_IP = 0x3 << 2,
693 CQE_RSS_DST_HTYPE_IPV4 = 0x1 << 2,
694 CQE_RSS_DST_HTYPE_IPV6 = 0x2 << 2,
696 /* source L4 hash types */
697 CQE_RSS_SRC_HTYPE_L4 = 0x3 << 4,
698 CQE_RSS_SRC_HTYPE_TCP = 0x1 << 4,
699 CQE_RSS_SRC_HTYPE_UDP = 0x2 << 4,
700 CQE_RSS_SRC_HTYPE_IPSEC = 0x3 << 4,
702 /* destination L4 hash types */
703 CQE_RSS_DST_HTYPE_L4 = 0x3 << 6,
704 CQE_RSS_DST_HTYPE_TCP = 0x1 << 6,
705 CQE_RSS_DST_HTYPE_UDP = 0x2 << 6,
706 CQE_RSS_DST_HTYPE_IPSEC = 0x3 << 6,
710 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
711 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
712 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
721 struct mlx5_sig_err_cqe {
723 __be32 expected_trans_sig;
724 __be32 actual_trans_sig;
725 __be32 expected_reftag;
726 __be32 actual_reftag;
738 struct mlx5_wqe_srq_next_seg {
740 __be16 next_wqe_index;
751 union mlx5_ext_cqe inl_grh;
752 struct mlx5_cqe64 cqe64;
756 MLX5_MKEY_STATUS_FREE = 1 << 6,
759 struct mlx5_mkey_seg {
760 /* This is a two bit field occupying bits 31-30.
761 * bit 31 is always 0,
762 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
773 __be32 bsfs_octo_size;
781 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
784 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
787 static inline int mlx5_host_is_le(void)
789 #if defined(__LITTLE_ENDIAN)
791 #elif defined(__BIG_ENDIAN)
794 #error Host endianness not defined
798 #define MLX5_CMD_OP_MAX 0x939
801 VPORT_STATE_DOWN = 0x0,
802 VPORT_STATE_UP = 0x1,
806 MLX5_L3_PROT_TYPE_IPV4 = 0,
807 MLX5_L3_PROT_TYPE_IPV6 = 1,
811 MLX5_L4_PROT_TYPE_TCP = 0,
812 MLX5_L4_PROT_TYPE_UDP = 1,
816 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
817 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
818 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
819 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
820 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
824 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
825 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
826 MLX5_MATCH_INNER_HEADERS = 1 << 2,
831 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
832 MLX5_FLOW_TABLE_TYPE_EGRESS_ACL = 2,
833 MLX5_FLOW_TABLE_TYPE_INGRESS_ACL = 3,
834 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
835 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 5,
836 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 6,
837 MLX5_FLOW_TABLE_TYPE_NIC_RX_RDMA = 7,
841 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_NONE = 0,
842 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_IF_NO_VLAN = 1,
843 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_OVERWRITE = 2
847 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_STRIP = 1 << 0,
848 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_STRIP = 1 << 1,
849 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_INSERT = 1 << 2,
850 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_INSERT = 1 << 3
854 MLX5_UC_ADDR_CHANGE = (1 << 0),
855 MLX5_MC_ADDR_CHANGE = (1 << 1),
856 MLX5_VLAN_CHANGE = (1 << 2),
857 MLX5_PROMISC_CHANGE = (1 << 3),
858 MLX5_MTU_CHANGE = (1 << 4),
861 enum mlx5_list_type {
862 MLX5_NIC_VPORT_LIST_TYPE_UC = 0x0,
863 MLX5_NIC_VPORT_LIST_TYPE_MC = 0x1,
864 MLX5_NIC_VPORT_LIST_TYPE_VLAN = 0x2,
868 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0,
869 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1,
870 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2,
877 HCA_CAP_OPMOD_GET_MAX = 0,
878 HCA_CAP_OPMOD_GET_CUR = 1,
882 MLX5_CAP_GENERAL = 0,
883 MLX5_CAP_ETHERNET_OFFLOADS,
887 MLX5_CAP_IPOIB_OFFLOADS,
888 MLX5_CAP_EOIB_OFFLOADS,
890 MLX5_CAP_ESWITCH_FLOW_TABLE,
893 MLX5_CAP_VECTOR_CALC,
896 /* NUM OF CAP Types */
900 /* GET Dev Caps macros */
901 #define MLX5_CAP_GEN(mdev, cap) \
902 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
904 #define MLX5_CAP_GEN_MAX(mdev, cap) \
905 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
907 #define MLX5_CAP_ETH(mdev, cap) \
908 MLX5_GET(per_protocol_networking_offload_caps,\
909 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
911 #define MLX5_CAP_ETH_MAX(mdev, cap) \
912 MLX5_GET(per_protocol_networking_offload_caps,\
913 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
915 #define MLX5_CAP_ROCE(mdev, cap) \
916 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
918 #define MLX5_CAP_ROCE_MAX(mdev, cap) \
919 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
921 #define MLX5_CAP_ATOMIC(mdev, cap) \
922 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
924 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
925 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
927 #define MLX5_CAP_FLOWTABLE(mdev, cap) \
928 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
930 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
931 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
933 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
934 MLX5_GET(flow_table_eswitch_cap, \
935 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
937 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
938 MLX5_GET(flow_table_eswitch_cap, \
939 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
941 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
942 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
944 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
945 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
947 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
948 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
950 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \
951 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
953 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
954 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
956 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \
957 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
959 #define MLX5_CAP_ESW(mdev, cap) \
960 MLX5_GET(e_switch_cap, \
961 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap)
963 #define MLX5_CAP_ESW_MAX(mdev, cap) \
964 MLX5_GET(e_switch_cap, \
965 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap)
967 #define MLX5_CAP_ODP(mdev, cap)\
968 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
970 #define MLX5_CAP_ODP_MAX(mdev, cap)\
971 MLX5_GET(odp_cap, mdev->hca_caps_max[MLX5_CAP_ODP], cap)
973 #define MLX5_CAP_SNAPSHOT(mdev, cap) \
974 MLX5_GET(snapshot_cap, \
975 mdev->hca_caps_cur[MLX5_CAP_SNAPSHOT], cap)
977 #define MLX5_CAP_SNAPSHOT_MAX(mdev, cap) \
978 MLX5_GET(snapshot_cap, \
979 mdev->hca_caps_max[MLX5_CAP_SNAPSHOT], cap)
981 #define MLX5_CAP_EOIB_OFFLOADS(mdev, cap) \
982 MLX5_GET(per_protocol_networking_offload_caps,\
983 mdev->hca_caps_cur[MLX5_CAP_EOIB_OFFLOADS], cap)
985 #define MLX5_CAP_EOIB_OFFLOADS_MAX(mdev, cap) \
986 MLX5_GET(per_protocol_networking_offload_caps,\
987 mdev->hca_caps_max[MLX5_CAP_EOIB_OFFLOADS], cap)
989 #define MLX5_CAP_DEBUG(mdev, cap) \
990 MLX5_GET(debug_cap, \
991 mdev->hca_caps_cur[MLX5_CAP_DEBUG], cap)
993 #define MLX5_CAP_DEBUG_MAX(mdev, cap) \
994 MLX5_GET(debug_cap, \
995 mdev->hca_caps_max[MLX5_CAP_DEBUG], cap)
997 #define MLX5_CAP_QOS(mdev, cap) \
999 mdev->hca_caps_cur[MLX5_CAP_QOS], cap)
1001 #define MLX5_CAP_QOS_MAX(mdev, cap) \
1003 mdev->hca_caps_max[MLX5_CAP_QOS], cap)
1006 MLX5_CMD_STAT_OK = 0x0,
1007 MLX5_CMD_STAT_INT_ERR = 0x1,
1008 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1009 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1010 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1011 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1012 MLX5_CMD_STAT_RES_BUSY = 0x6,
1013 MLX5_CMD_STAT_LIM_ERR = 0x8,
1014 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1015 MLX5_CMD_STAT_IX_ERR = 0xa,
1016 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1017 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1018 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1019 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1020 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1021 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1025 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1026 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1027 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1028 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1029 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1030 MLX5_ETHERNET_DISCARD_COUNTERS_GROUP = 0x6,
1031 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1032 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
1033 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12,
1034 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16,
1035 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
1039 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0,
1040 MLX5_PCIE_LANE_COUNTERS_GROUP = 0x1,
1041 MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP = 0x2,
1045 MLX5_NUM_UUARS_PER_PAGE = MLX5_NON_FP_BF_REGS_PER_PAGE,
1046 MLX5_DEF_TOT_UUARS = 8 * MLX5_NUM_UUARS_PER_PAGE,
1050 NUM_DRIVER_UARS = 4,
1051 NUM_LOW_LAT_UUARS = 4,
1055 MLX5_CAP_PORT_TYPE_IB = 0x0,
1056 MLX5_CAP_PORT_TYPE_ETH = 0x1,
1060 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_L2 = 0x0,
1061 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_VPORT_CONFIG = 0x1,
1062 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_NOT_REQUIRED = 0x2
1066 MLX5_QUERY_VPORT_STATE_OUT_STATE_FOLLOW = 0x2,
1069 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1071 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1073 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1076 struct mlx5_ifc_mcia_reg_bits {
1083 u8 i2c_device_address[0x8];
1084 u8 page_number[0x8];
1085 u8 device_address[0x10];
1087 u8 reserved_2[0x10];
1090 u8 reserved_3[0x20];
1106 #define MLX5_CMD_OP_QUERY_EEPROM 0x93c
1108 struct mlx5_mini_cqe8 {
1110 __be32 rx_hash_result;
1123 MLX5_NO_INLINE_DATA,
1124 MLX5_INLINE_DATA32_SEG,
1125 MLX5_INLINE_DATA64_SEG,
1129 enum mlx5_exp_cqe_zip_recv_type {
1130 MLX5_CQE_FORMAT_HASH,
1131 MLX5_CQE_FORMAT_CSUM,
1134 #define MLX5E_CQE_FORMAT_MASK 0xc
1135 static inline int mlx5_get_cqe_format(const struct mlx5_cqe64 *cqe)
1137 return (cqe->op_own & MLX5E_CQE_FORMAT_MASK) >> 2;
1141 MLX5_GEN_EVENT_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1,
1144 /* 8 regular priorities + 1 for multicast */
1145 #define MLX5_NUM_BYPASS_FTS 9
1147 #endif /* MLX5_DEVICE_H */