2 * Copyright (c) 2013-2018, Mellanox Technologies, Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <linux/types.h>
32 #include <rdma/ib_verbs.h>
33 #include <dev/mlx5/mlx5_ifc.h>
35 #define FW_INIT_TIMEOUT_MILI 2000
36 #define FW_INIT_WAIT_MS 2
38 #if defined(__LITTLE_ENDIAN)
39 #define MLX5_SET_HOST_ENDIANNESS 0
40 #elif defined(__BIG_ENDIAN)
41 #define MLX5_SET_HOST_ENDIANNESS 0x80
43 #error Host endianness not defined
47 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
48 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
49 #define __mlx5_bit_off(typ, fld) __offsetof(struct mlx5_ifc_##typ##_bits, fld)
50 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
51 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
52 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
53 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf))
54 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
55 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
56 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
57 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
58 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld))
59 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
61 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
62 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
63 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
64 #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
65 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
66 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
67 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
68 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
70 /* insert a value to a struct */
71 #define MLX5_SET(typ, p, fld, v) do { \
72 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
73 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \
74 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
75 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
76 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
77 << __mlx5_dw_bit_off(typ, fld))); \
80 #define MLX5_SET_TO_ONES(typ, p, fld) do { \
81 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
82 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \
83 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
84 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
85 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
86 << __mlx5_dw_bit_off(typ, fld))); \
89 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
90 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
91 __mlx5_mask(typ, fld))
93 #define MLX5_GET_PR(typ, p, fld) ({ \
94 u32 ___t = MLX5_GET(typ, p, fld); \
95 pr_debug(#fld " = 0x%x\n", ___t); \
99 #define __MLX5_SET64(typ, p, fld, v) do { \
100 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
101 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
104 #define MLX5_SET64(typ, p, fld, v) do { \
105 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
106 __MLX5_SET64(typ, p, fld, v); \
109 #define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \
110 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
111 __MLX5_SET64(typ, p, fld[idx], v); \
114 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
116 #define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\
117 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
118 __mlx5_mask16(typ, fld))
120 #define MLX5_SET16(typ, p, fld, v) do { \
122 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \
123 *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \
124 cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \
125 (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \
126 << __mlx5_16_bit_off(typ, fld))); \
129 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
130 __mlx5_64_off(typ, fld)))
132 #define MLX5_GET_BE(type_t, typ, p, fld) ({ \
134 switch (sizeof(tmp)) { \
136 tmp = (__force type_t)MLX5_GET(typ, p, fld); \
139 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
142 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
145 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
151 #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8
152 #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8
153 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
154 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
155 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
156 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
158 /* insert a value to a struct */
159 #define MLX5_VSC_SET(typ, p, fld, v) do { \
160 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
161 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \
162 *((__le32 *)(p) + __mlx5_dw_off(typ, fld)) = \
163 cpu_to_le32((le32_to_cpu(*((__le32 *)(p) + __mlx5_dw_off(typ, fld))) & \
164 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
165 << __mlx5_dw_bit_off(typ, fld))); \
168 #define MLX5_VSC_GET(typ, p, fld) ((le32_to_cpu(*((__le32 *)(p) +\
169 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
170 __mlx5_mask(typ, fld))
172 #define MLX5_VSC_GET_PR(typ, p, fld) ({ \
173 u32 ___t = MLX5_VSC_GET(typ, p, fld); \
174 pr_debug(#fld " = 0x%x\n", ___t); \
179 MLX5_MAX_COMMANDS = 32,
180 MLX5_CMD_DATA_BLOCK_SIZE = 512,
181 MLX5_CMD_MBOX_SIZE = 1024,
182 MLX5_PCI_CMD_XPORT = 7,
183 MLX5_MKEY_BSF_OCTO_SIZE = 4,
188 MLX5_EXTENDED_UD_AV = 0x80000000,
192 MLX5_CQ_FLAGS_OI = 2,
196 MLX5_STAT_RATE_OFFSET = 5,
200 MLX5_INLINE_SEG = 0x80000000,
204 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
208 MLX5_MIN_PKEY_TABLE_SIZE = 128,
209 MLX5_MAX_LOG_PKEY_TABLE = 5,
213 MLX5_MKEY_INBOX_PG_ACCESS = 1U << 31
217 MLX5_PERM_LOCAL_READ = 1 << 2,
218 MLX5_PERM_LOCAL_WRITE = 1 << 3,
219 MLX5_PERM_REMOTE_READ = 1 << 4,
220 MLX5_PERM_REMOTE_WRITE = 1 << 5,
221 MLX5_PERM_ATOMIC = 1 << 6,
222 MLX5_PERM_UMR_EN = 1 << 7,
226 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
227 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
228 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
229 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
230 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
234 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
235 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
236 MLX5_MKEY_BSF_EN = 1 << 30,
237 MLX5_MKEY_LEN64 = 1U << 31,
246 MLX5_BF_REGS_PER_PAGE = 4,
247 MLX5_MAX_UAR_PAGES = 1 << 8,
248 MLX5_NON_FP_BF_REGS_PER_PAGE = 2,
249 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
253 MLX5_MKEY_MASK_LEN = 1ull << 0,
254 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
255 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
256 MLX5_MKEY_MASK_PD = 1ull << 7,
257 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
258 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
259 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
260 MLX5_MKEY_MASK_KEY = 1ull << 13,
261 MLX5_MKEY_MASK_QPN = 1ull << 14,
262 MLX5_MKEY_MASK_LR = 1ull << 17,
263 MLX5_MKEY_MASK_LW = 1ull << 18,
264 MLX5_MKEY_MASK_RR = 1ull << 19,
265 MLX5_MKEY_MASK_RW = 1ull << 20,
266 MLX5_MKEY_MASK_A = 1ull << 21,
267 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
268 MLX5_MKEY_MASK_FREE = 1ull << 29,
272 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
274 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
275 MLX5_UMR_CHECK_FREE = (2 << 5),
277 MLX5_UMR_INLINE = (1 << 7),
280 #define MLX5_UMR_MTT_ALIGNMENT 0x40
281 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
282 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
285 MLX5_EVENT_QUEUE_TYPE_QP = 0,
286 MLX5_EVENT_QUEUE_TYPE_RQ = 1,
287 MLX5_EVENT_QUEUE_TYPE_SQ = 2,
291 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
292 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
293 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
294 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
295 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
296 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
297 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
301 MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX = 1,
302 MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE,
303 MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE,
304 MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE,
305 MLX5_MAX_INLINE_RECEIVE_SIZE = 64
309 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
310 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
311 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
312 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
313 MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD = 1LL << 21,
314 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
315 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
316 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
317 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 33,
318 MLX5_DEV_CAP_FLAG_ROCE = 1LL << 34,
319 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
320 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
321 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
322 MLX5_DEV_CAP_FLAG_DRAIN_SIGERR = 1LL << 48,
326 MLX5_ROCE_VERSION_1 = 0,
327 MLX5_ROCE_VERSION_1_5 = 1,
328 MLX5_ROCE_VERSION_2 = 2,
332 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
333 MLX5_ROCE_VERSION_1_5_CAP = 1 << MLX5_ROCE_VERSION_1_5,
334 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
338 MLX5_ROCE_L3_TYPE_IPV4 = 0,
339 MLX5_ROCE_L3_TYPE_IPV6 = 1,
343 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
344 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
348 MLX5_OPCODE_NOP = 0x00,
349 MLX5_OPCODE_SEND_INVAL = 0x01,
350 MLX5_OPCODE_RDMA_WRITE = 0x08,
351 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
352 MLX5_OPCODE_SEND = 0x0a,
353 MLX5_OPCODE_SEND_IMM = 0x0b,
354 MLX5_OPCODE_LSO = 0x0e,
355 MLX5_OPCODE_RDMA_READ = 0x10,
356 MLX5_OPCODE_ATOMIC_CS = 0x11,
357 MLX5_OPCODE_ATOMIC_FA = 0x12,
358 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
359 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
360 MLX5_OPCODE_BIND_MW = 0x18,
361 MLX5_OPCODE_CONFIG_CMD = 0x1f,
363 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
364 MLX5_RECV_OPCODE_SEND = 0x01,
365 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
366 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
368 MLX5_CQE_OPCODE_ERROR = 0x1e,
369 MLX5_CQE_OPCODE_RESIZE = 0x16,
371 MLX5_OPCODE_SET_PSV = 0x20,
372 MLX5_OPCODE_GET_PSV = 0x21,
373 MLX5_OPCODE_CHECK_PSV = 0x22,
374 MLX5_OPCODE_RGET_PSV = 0x26,
375 MLX5_OPCODE_RCHECK_PSV = 0x27,
377 MLX5_OPCODE_UMR = 0x25,
379 MLX5_OPCODE_SIGNATURE_CANCELED = (1 << 15),
383 MLX5_SET_PORT_RESET_QKEY = 0,
384 MLX5_SET_PORT_GUID0 = 16,
385 MLX5_SET_PORT_NODE_GUID = 17,
386 MLX5_SET_PORT_SYS_GUID = 18,
387 MLX5_SET_PORT_GID_TABLE = 19,
388 MLX5_SET_PORT_PKEY_TABLE = 20,
392 MLX5_MAX_PAGE_SHIFT = 31
396 MLX5_ADAPTER_PAGE_SHIFT = 12,
397 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
401 MLX5_CAP_OFF_CMDIF_CSUM = 46,
406 * Max wqe size for rdma read is 512 bytes, so this
407 * limits our max_sge_rd as the wqe needs to fit:
408 * - ctrl segment (16 bytes)
409 * - rdma segment (16 bytes)
410 * - scatter elements (16 bytes each)
412 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
415 struct mlx5_cmd_layout {
430 enum mlx5_fatal_assert_bit_offsets {
431 MLX5_RFR_OFFSET = 31,
434 struct mlx5_health_buffer {
435 __be32 assert_var[5];
437 __be32 assert_exit_ptr;
438 __be32 assert_callra;
448 enum mlx5_initializing_bit_offsets {
449 MLX5_FW_RESET_SUPPORTED_OFFSET = 30,
452 enum mlx5_cmd_addr_l_sz_offset {
453 MLX5_NIC_IFC_OFFSET = 8,
456 struct mlx5_init_seg {
458 __be32 cmdif_rev_fw_sub;
461 __be32 cmdq_addr_l_sz;
465 struct mlx5_health_buffer health;
467 __be32 internal_timer_h;
468 __be32 internal_timer_l;
470 __be32 health_counter;
473 __be32 ieee1588_clk_type;
477 struct mlx5_eqe_comp {
482 struct mlx5_eqe_qp_srq {
487 struct mlx5_eqe_cq_err {
493 struct mlx5_eqe_port_state {
498 struct mlx5_eqe_gpio {
503 struct mlx5_eqe_congestion {
509 struct mlx5_eqe_stall_vl {
514 struct mlx5_eqe_cmd {
519 struct mlx5_eqe_page_req {
526 struct mlx5_eqe_vport_change {
533 #define PORT_MODULE_EVENT_MODULE_STATUS_MASK 0xF
534 #define PORT_MODULE_EVENT_ERROR_TYPE_MASK 0xF
537 MLX5_MODULE_STATUS_PLUGGED_ENABLED = 0x1,
538 MLX5_MODULE_STATUS_UNPLUGGED = 0x2,
539 MLX5_MODULE_STATUS_ERROR = 0x3,
540 MLX5_MODULE_STATUS_PLUGGED_DISABLED = 0x4,
544 MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED = 0x0,
545 MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE = 0x1,
546 MLX5_MODULE_EVENT_ERROR_BUS_STUCK = 0x2,
547 MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT = 0x3,
548 MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST = 0x4,
549 MLX5_MODULE_EVENT_ERROR_UNSUPPORTED_CABLE = 0x5,
550 MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE = 0x6,
551 MLX5_MODULE_EVENT_ERROR_CABLE_IS_SHORTED = 0x7,
552 MLX5_MODULE_EVENT_ERROR_PCIE_SYSTEM_POWER_SLOT_EXCEEDED = 0xc,
555 struct mlx5_eqe_port_module_event {
564 struct mlx5_eqe_general_notification_event {
565 u32 rq_user_index_delay_drop;
571 struct mlx5_eqe_cmd cmd;
572 struct mlx5_eqe_comp comp;
573 struct mlx5_eqe_qp_srq qp_srq;
574 struct mlx5_eqe_cq_err cq_err;
575 struct mlx5_eqe_port_state port;
576 struct mlx5_eqe_gpio gpio;
577 struct mlx5_eqe_congestion cong;
578 struct mlx5_eqe_stall_vl stall_vl;
579 struct mlx5_eqe_page_req req_pages;
580 struct mlx5_eqe_port_module_event port_module_event;
581 struct mlx5_eqe_vport_change vport_change;
582 struct mlx5_eqe_general_notification_event general_notifications;
597 struct mlx5_cmd_prot_block {
598 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
608 #define MLX5_NUM_CMDS_IN_ADAPTER_PAGE \
609 (MLX5_ADAPTER_PAGE_SIZE / MLX5_CMD_MBOX_SIZE)
610 CTASSERT(MLX5_CMD_MBOX_SIZE >= sizeof(struct mlx5_cmd_prot_block));
611 CTASSERT(MLX5_CMD_MBOX_SIZE <= MLX5_ADAPTER_PAGE_SIZE);
614 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
617 struct mlx5_err_cqe {
623 __be32 s_wqe_opcode_qpn;
632 u8 lro_tcppsh_abort_dupack;
635 __be32 lro_ack_seq_num;
636 __be32 rss_hash_result;
646 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
647 __be32 imm_inval_pkey;
657 #define MLX5_CQE_TSTMP_PTP (1ULL << 63)
659 static inline bool get_cqe_lro_timestamp_valid(struct mlx5_cqe64 *cqe)
661 return (cqe->lro_tcppsh_abort_dupack >> 7) & 1;
664 static inline bool get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
666 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
669 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
671 return (cqe->l4_hdr_type_etc >> 4) & 0x7;
674 static inline u16 get_cqe_vlan(struct mlx5_cqe64 *cqe)
676 return be16_to_cpu(cqe->vlan_info) & 0xfff;
679 static inline void get_cqe_smac(struct mlx5_cqe64 *cqe, u8 *smac)
681 memcpy(smac, &cqe->rss_hash_type , 4);
682 memcpy(smac + 4, &cqe->slid , 2);
685 static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe)
687 return cqe->l4_hdr_type_etc & 0x1;
690 static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe)
692 return cqe->tunneled_etc & 0x1;
696 CQE_L4_HDR_TYPE_NONE = 0x0,
697 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
698 CQE_L4_HDR_TYPE_UDP = 0x2,
699 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
700 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
704 /* source L3 hash types */
705 CQE_RSS_SRC_HTYPE_IP = 0x3 << 0,
706 CQE_RSS_SRC_HTYPE_IPV4 = 0x1 << 0,
707 CQE_RSS_SRC_HTYPE_IPV6 = 0x2 << 0,
709 /* destination L3 hash types */
710 CQE_RSS_DST_HTYPE_IP = 0x3 << 2,
711 CQE_RSS_DST_HTYPE_IPV4 = 0x1 << 2,
712 CQE_RSS_DST_HTYPE_IPV6 = 0x2 << 2,
714 /* source L4 hash types */
715 CQE_RSS_SRC_HTYPE_L4 = 0x3 << 4,
716 CQE_RSS_SRC_HTYPE_TCP = 0x1 << 4,
717 CQE_RSS_SRC_HTYPE_UDP = 0x2 << 4,
718 CQE_RSS_SRC_HTYPE_IPSEC = 0x3 << 4,
720 /* destination L4 hash types */
721 CQE_RSS_DST_HTYPE_L4 = 0x3 << 6,
722 CQE_RSS_DST_HTYPE_TCP = 0x1 << 6,
723 CQE_RSS_DST_HTYPE_UDP = 0x2 << 6,
724 CQE_RSS_DST_HTYPE_IPSEC = 0x3 << 6,
728 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
729 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
730 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
739 struct mlx5_sig_err_cqe {
741 __be32 expected_trans_sig;
742 __be32 actual_trans_sig;
743 __be32 expected_reftag;
744 __be32 actual_reftag;
756 struct mlx5_wqe_srq_next_seg {
758 __be16 next_wqe_index;
769 union mlx5_ext_cqe inl_grh;
770 struct mlx5_cqe64 cqe64;
774 MLX5_MKEY_STATUS_FREE = 1 << 6,
777 struct mlx5_mkey_seg {
778 /* This is a two bit field occupying bits 31-30.
779 * bit 31 is always 0,
780 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
791 __be32 bsfs_octo_size;
799 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
802 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
805 static inline int mlx5_host_is_le(void)
807 #if defined(__LITTLE_ENDIAN)
809 #elif defined(__BIG_ENDIAN)
812 #error Host endianness not defined
816 #define MLX5_CMD_OP_MAX 0x939
819 VPORT_STATE_DOWN = 0x0,
820 VPORT_STATE_UP = 0x1,
824 MLX5_L3_PROT_TYPE_IPV4 = 0,
825 MLX5_L3_PROT_TYPE_IPV6 = 1,
829 MLX5_L4_PROT_TYPE_TCP = 0,
830 MLX5_L4_PROT_TYPE_UDP = 1,
834 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
835 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
836 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
837 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
838 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
842 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
843 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
844 MLX5_MATCH_INNER_HEADERS = 1 << 2,
849 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
850 MLX5_FLOW_TABLE_TYPE_EGRESS_ACL = 2,
851 MLX5_FLOW_TABLE_TYPE_INGRESS_ACL = 3,
852 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
853 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 5,
854 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 6,
855 MLX5_FLOW_TABLE_TYPE_NIC_RX_RDMA = 7,
859 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_NONE = 0,
860 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_IF_NO_VLAN = 1,
861 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_OVERWRITE = 2
865 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_STRIP = 1 << 0,
866 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_STRIP = 1 << 1,
867 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_INSERT = 1 << 2,
868 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_INSERT = 1 << 3
872 MLX5_UC_ADDR_CHANGE = (1 << 0),
873 MLX5_MC_ADDR_CHANGE = (1 << 1),
874 MLX5_VLAN_CHANGE = (1 << 2),
875 MLX5_PROMISC_CHANGE = (1 << 3),
876 MLX5_MTU_CHANGE = (1 << 4),
879 enum mlx5_list_type {
880 MLX5_NIC_VPORT_LIST_TYPE_UC = 0x0,
881 MLX5_NIC_VPORT_LIST_TYPE_MC = 0x1,
882 MLX5_NIC_VPORT_LIST_TYPE_VLAN = 0x2,
886 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0,
887 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1,
888 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2,
895 HCA_CAP_OPMOD_GET_MAX = 0,
896 HCA_CAP_OPMOD_GET_CUR = 1,
900 MLX5_CAP_GENERAL = 0,
901 MLX5_CAP_ETHERNET_OFFLOADS,
905 MLX5_CAP_IPOIB_OFFLOADS,
906 MLX5_CAP_EOIB_OFFLOADS,
908 MLX5_CAP_ESWITCH_FLOW_TABLE,
911 MLX5_CAP_VECTOR_CALC,
914 /* NUM OF CAP Types */
918 enum mlx5_qcam_reg_groups {
919 MLX5_QCAM_REGS_FIRST_128 = 0x0,
922 enum mlx5_qcam_feature_groups {
923 MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0,
926 /* GET Dev Caps macros */
927 #define MLX5_CAP_GEN(mdev, cap) \
928 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
930 #define MLX5_CAP_GEN_MAX(mdev, cap) \
931 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
933 #define MLX5_CAP_ETH(mdev, cap) \
934 MLX5_GET(per_protocol_networking_offload_caps,\
935 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
937 #define MLX5_CAP_ETH_MAX(mdev, cap) \
938 MLX5_GET(per_protocol_networking_offload_caps,\
939 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
941 #define MLX5_CAP_ROCE(mdev, cap) \
942 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
944 #define MLX5_CAP_ROCE_MAX(mdev, cap) \
945 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
947 #define MLX5_CAP_ATOMIC(mdev, cap) \
948 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
950 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
951 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
953 #define MLX5_CAP_FLOWTABLE(mdev, cap) \
954 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
956 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
957 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
959 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
960 MLX5_GET(flow_table_eswitch_cap, \
961 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
963 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
964 MLX5_GET(flow_table_eswitch_cap, \
965 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
967 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
968 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
970 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
971 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
973 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
974 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
976 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \
977 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
979 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
980 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
982 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \
983 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
985 #define MLX5_CAP_ESW(mdev, cap) \
986 MLX5_GET(e_switch_cap, \
987 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap)
989 #define MLX5_CAP_ESW_MAX(mdev, cap) \
990 MLX5_GET(e_switch_cap, \
991 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap)
993 #define MLX5_CAP_ODP(mdev, cap)\
994 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
996 #define MLX5_CAP_ODP_MAX(mdev, cap)\
997 MLX5_GET(odp_cap, mdev->hca_caps_max[MLX5_CAP_ODP], cap)
999 #define MLX5_CAP_SNAPSHOT(mdev, cap) \
1000 MLX5_GET(snapshot_cap, \
1001 mdev->hca_caps_cur[MLX5_CAP_SNAPSHOT], cap)
1003 #define MLX5_CAP_SNAPSHOT_MAX(mdev, cap) \
1004 MLX5_GET(snapshot_cap, \
1005 mdev->hca_caps_max[MLX5_CAP_SNAPSHOT], cap)
1007 #define MLX5_CAP_EOIB_OFFLOADS(mdev, cap) \
1008 MLX5_GET(per_protocol_networking_offload_caps,\
1009 mdev->hca_caps_cur[MLX5_CAP_EOIB_OFFLOADS], cap)
1011 #define MLX5_CAP_EOIB_OFFLOADS_MAX(mdev, cap) \
1012 MLX5_GET(per_protocol_networking_offload_caps,\
1013 mdev->hca_caps_max[MLX5_CAP_EOIB_OFFLOADS], cap)
1015 #define MLX5_CAP_DEBUG(mdev, cap) \
1016 MLX5_GET(debug_cap, \
1017 mdev->hca_caps_cur[MLX5_CAP_DEBUG], cap)
1019 #define MLX5_CAP_DEBUG_MAX(mdev, cap) \
1020 MLX5_GET(debug_cap, \
1021 mdev->hca_caps_max[MLX5_CAP_DEBUG], cap)
1023 #define MLX5_CAP_QOS(mdev, cap) \
1025 mdev->hca_caps_cur[MLX5_CAP_QOS], cap)
1027 #define MLX5_CAP_QOS_MAX(mdev, cap) \
1029 mdev->hca_caps_max[MLX5_CAP_QOS], cap)
1031 #define MLX5_CAP_QCAM_REG(mdev, fld) \
1032 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)
1034 #define MLX5_CAP_QCAM_FEATURE(mdev, fld) \
1035 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld)
1038 MLX5_CMD_STAT_OK = 0x0,
1039 MLX5_CMD_STAT_INT_ERR = 0x1,
1040 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1041 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1042 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1043 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1044 MLX5_CMD_STAT_RES_BUSY = 0x6,
1045 MLX5_CMD_STAT_LIM_ERR = 0x8,
1046 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1047 MLX5_CMD_STAT_IX_ERR = 0xa,
1048 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1049 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1050 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1051 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1052 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1053 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1057 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1058 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1059 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1060 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1061 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1062 MLX5_ETHERNET_DISCARD_COUNTERS_GROUP = 0x6,
1063 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1064 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
1065 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12,
1066 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16,
1067 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
1071 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0,
1072 MLX5_PCIE_LANE_COUNTERS_GROUP = 0x1,
1073 MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP = 0x2,
1077 MLX5_NUM_UUARS_PER_PAGE = MLX5_NON_FP_BF_REGS_PER_PAGE,
1078 MLX5_DEF_TOT_UUARS = 8 * MLX5_NUM_UUARS_PER_PAGE,
1082 NUM_DRIVER_UARS = 4,
1083 NUM_LOW_LAT_UUARS = 4,
1087 MLX5_CAP_PORT_TYPE_IB = 0x0,
1088 MLX5_CAP_PORT_TYPE_ETH = 0x1,
1092 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_L2 = 0x0,
1093 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_VPORT_CONFIG = 0x1,
1094 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_NOT_REQUIRED = 0x2
1097 enum mlx5_inline_modes {
1098 MLX5_INLINE_MODE_NONE,
1099 MLX5_INLINE_MODE_L2,
1100 MLX5_INLINE_MODE_IP,
1101 MLX5_INLINE_MODE_TCP_UDP,
1105 MLX5_QUERY_VPORT_STATE_OUT_STATE_FOLLOW = 0x2,
1108 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1110 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1112 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1115 struct mlx5_ifc_mcia_reg_bits {
1122 u8 i2c_device_address[0x8];
1123 u8 page_number[0x8];
1124 u8 device_address[0x10];
1126 u8 reserved_2[0x10];
1129 u8 reserved_3[0x20];
1145 #define MLX5_CMD_OP_QUERY_EEPROM 0x93c
1147 struct mlx5_mini_cqe8 {
1149 __be32 rx_hash_result;
1162 MLX5_NO_INLINE_DATA,
1163 MLX5_INLINE_DATA32_SEG,
1164 MLX5_INLINE_DATA64_SEG,
1168 enum mlx5_exp_cqe_zip_recv_type {
1169 MLX5_CQE_FORMAT_HASH,
1170 MLX5_CQE_FORMAT_CSUM,
1173 #define MLX5E_CQE_FORMAT_MASK 0xc
1174 static inline int mlx5_get_cqe_format(const struct mlx5_cqe64 *cqe)
1176 return (cqe->op_own & MLX5E_CQE_FORMAT_MASK) >> 2;
1180 MLX5_GEN_EVENT_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1,
1183 /* 8 regular priorities + 1 for multicast */
1184 #define MLX5_NUM_BYPASS_FTS 9
1186 #endif /* MLX5_DEVICE_H */