2 * Copyright (c) 2013-2019, Mellanox Technologies, Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <linux/types.h>
32 #include <rdma/ib_verbs.h>
33 #include <dev/mlx5/mlx5_ifc.h>
35 #define FW_INIT_TIMEOUT_MILI 2000
36 #define FW_INIT_WAIT_MS 2
37 #define FW_PRE_INIT_TIMEOUT_MILI 120000
38 #define FW_INIT_WARN_MESSAGE_INTERVAL 20000
40 #if defined(__LITTLE_ENDIAN)
41 #define MLX5_SET_HOST_ENDIANNESS 0
42 #elif defined(__BIG_ENDIAN)
43 #define MLX5_SET_HOST_ENDIANNESS 0x80
45 #error Host endianness not defined
49 #define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50 #define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
51 #define __mlx5_bit_off(typ, fld) __offsetof(struct mlx5_ifc_##typ##_bits, fld)
52 #define __mlx5_16_off(typ, fld) (__mlx5_bit_off(typ, fld) / 16)
53 #define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
54 #define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
55 #define __mlx5_16_bit_off(typ, fld) (16 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0xf))
56 #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
57 #define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
58 #define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
59 #define __mlx5_mask16(typ, fld) ((u16)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
60 #define __mlx5_16_mask(typ, fld) (__mlx5_mask16(typ, fld) << __mlx5_16_bit_off(typ, fld))
61 #define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
63 #define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
64 #define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
65 #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
66 #define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
67 #define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
68 #define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
69 #define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
70 #define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
72 /* insert a value to a struct */
73 #define MLX5_SET(typ, p, fld, v) do { \
74 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
75 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \
76 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
77 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
78 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
79 << __mlx5_dw_bit_off(typ, fld))); \
82 #define MLX5_SET_TO_ONES(typ, p, fld) do { \
83 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
84 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \
85 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
86 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
87 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
88 << __mlx5_dw_bit_off(typ, fld))); \
91 #define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
92 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
93 __mlx5_mask(typ, fld))
95 #define MLX5_GET_PR(typ, p, fld) ({ \
96 u32 ___t = MLX5_GET(typ, p, fld); \
97 pr_debug(#fld " = 0x%x\n", ___t); \
101 #define __MLX5_SET64(typ, p, fld, v) do { \
102 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
103 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
106 #define MLX5_SET64(typ, p, fld, v) do { \
107 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
108 __MLX5_SET64(typ, p, fld, v); \
111 #define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \
112 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
113 __MLX5_SET64(typ, p, fld[idx], v); \
116 #define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
118 #define MLX5_GET16(typ, p, fld) ((be16_to_cpu(*((__be16 *)(p) +\
119 __mlx5_16_off(typ, fld))) >> __mlx5_16_bit_off(typ, fld)) & \
120 __mlx5_mask16(typ, fld))
122 #define MLX5_SET16(typ, p, fld, v) do { \
124 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 16); \
125 *((__be16 *)(p) + __mlx5_16_off(typ, fld)) = \
126 cpu_to_be16((be16_to_cpu(*((__be16 *)(p) + __mlx5_16_off(typ, fld))) & \
127 (~__mlx5_16_mask(typ, fld))) | (((_v) & __mlx5_mask16(typ, fld)) \
128 << __mlx5_16_bit_off(typ, fld))); \
131 #define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
132 __mlx5_64_off(typ, fld)))
134 #define MLX5_GET_BE(type_t, typ, p, fld) ({ \
136 switch (sizeof(tmp)) { \
138 tmp = (__force type_t)MLX5_GET(typ, p, fld); \
141 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
144 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
147 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
153 #define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8
154 #define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8
155 #define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
156 #define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
157 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
158 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
160 /* insert a value to a struct */
161 #define MLX5_VSC_SET(typ, p, fld, v) do { \
162 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
163 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \
164 *((__le32 *)(p) + __mlx5_dw_off(typ, fld)) = \
165 cpu_to_le32((le32_to_cpu(*((__le32 *)(p) + __mlx5_dw_off(typ, fld))) & \
166 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
167 << __mlx5_dw_bit_off(typ, fld))); \
170 #define MLX5_VSC_GET(typ, p, fld) ((le32_to_cpu(*((__le32 *)(p) +\
171 __mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
172 __mlx5_mask(typ, fld))
174 #define MLX5_VSC_GET_PR(typ, p, fld) ({ \
175 u32 ___t = MLX5_VSC_GET(typ, p, fld); \
176 pr_debug(#fld " = 0x%x\n", ___t); \
181 MLX5_MAX_COMMANDS = 32,
182 MLX5_CMD_DATA_BLOCK_SIZE = 512,
183 MLX5_CMD_MBOX_SIZE = 1024,
184 MLX5_PCI_CMD_XPORT = 7,
185 MLX5_MKEY_BSF_OCTO_SIZE = 4,
190 MLX5_EXTENDED_UD_AV = 0x80000000,
194 MLX5_CQ_FLAGS_OI = 2,
198 MLX5_STAT_RATE_OFFSET = 5,
202 MLX5_INLINE_SEG = 0x80000000,
206 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
210 MLX5_MIN_PKEY_TABLE_SIZE = 128,
211 MLX5_MAX_LOG_PKEY_TABLE = 5,
215 MLX5_MKEY_INBOX_PG_ACCESS = 1U << 31
219 MLX5_PERM_LOCAL_READ = 1 << 2,
220 MLX5_PERM_LOCAL_WRITE = 1 << 3,
221 MLX5_PERM_REMOTE_READ = 1 << 4,
222 MLX5_PERM_REMOTE_WRITE = 1 << 5,
223 MLX5_PERM_ATOMIC = 1 << 6,
224 MLX5_PERM_UMR_EN = 1 << 7,
228 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
229 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
230 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
231 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
232 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
236 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
237 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
238 MLX5_MKEY_BSF_EN = 1 << 30,
239 MLX5_MKEY_LEN64 = 1U << 31,
248 MLX5_BF_REGS_PER_PAGE = 4,
249 MLX5_MAX_UAR_PAGES = 1 << 8,
250 MLX5_NON_FP_BF_REGS_PER_PAGE = 2,
251 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
255 MLX5_MKEY_MASK_LEN = 1ull << 0,
256 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
257 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
258 MLX5_MKEY_MASK_PD = 1ull << 7,
259 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
260 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
261 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
262 MLX5_MKEY_MASK_KEY = 1ull << 13,
263 MLX5_MKEY_MASK_QPN = 1ull << 14,
264 MLX5_MKEY_MASK_LR = 1ull << 17,
265 MLX5_MKEY_MASK_LW = 1ull << 18,
266 MLX5_MKEY_MASK_RR = 1ull << 19,
267 MLX5_MKEY_MASK_RW = 1ull << 20,
268 MLX5_MKEY_MASK_A = 1ull << 21,
269 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
270 MLX5_MKEY_MASK_FREE = 1ull << 29,
274 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
276 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
277 MLX5_UMR_CHECK_FREE = (2 << 5),
279 MLX5_UMR_INLINE = (1 << 7),
282 #define MLX5_UMR_MTT_ALIGNMENT 0x40
283 #define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
284 #define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
287 MLX5_EVENT_QUEUE_TYPE_QP = 0,
288 MLX5_EVENT_QUEUE_TYPE_RQ = 1,
289 MLX5_EVENT_QUEUE_TYPE_SQ = 2,
293 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
294 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
295 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
296 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
297 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
298 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
299 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
303 MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX = 1,
304 MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE,
305 MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE,
306 MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE,
307 MLX5_MAX_INLINE_RECEIVE_SIZE = 64
311 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
312 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
313 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
314 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
315 MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD = 1LL << 21,
316 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
317 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
318 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
319 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 33,
320 MLX5_DEV_CAP_FLAG_ROCE = 1LL << 34,
321 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
322 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
323 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
324 MLX5_DEV_CAP_FLAG_DRAIN_SIGERR = 1LL << 48,
328 MLX5_ROCE_VERSION_1 = 0,
329 MLX5_ROCE_VERSION_1_5 = 1,
330 MLX5_ROCE_VERSION_2 = 2,
334 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
335 MLX5_ROCE_VERSION_1_5_CAP = 1 << MLX5_ROCE_VERSION_1_5,
336 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
340 MLX5_ROCE_L3_TYPE_IPV4 = 0,
341 MLX5_ROCE_L3_TYPE_IPV6 = 1,
345 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
346 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
350 MLX5_OPCODE_NOP = 0x00,
351 MLX5_OPCODE_SEND_INVAL = 0x01,
352 MLX5_OPCODE_RDMA_WRITE = 0x08,
353 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
354 MLX5_OPCODE_SEND = 0x0a,
355 MLX5_OPCODE_SEND_IMM = 0x0b,
356 MLX5_OPCODE_LSO = 0x0e,
357 MLX5_OPCODE_RDMA_READ = 0x10,
358 MLX5_OPCODE_ATOMIC_CS = 0x11,
359 MLX5_OPCODE_ATOMIC_FA = 0x12,
360 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
361 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
362 MLX5_OPCODE_BIND_MW = 0x18,
363 MLX5_OPCODE_CONFIG_CMD = 0x1f,
364 MLX5_OPCODE_DUMP = 0x23,
366 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
367 MLX5_RECV_OPCODE_SEND = 0x01,
368 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
369 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
371 MLX5_CQE_OPCODE_ERROR = 0x1e,
372 MLX5_CQE_OPCODE_RESIZE = 0x16,
374 MLX5_OPCODE_SET_PSV = 0x20,
375 MLX5_OPCODE_GET_PSV = 0x21,
376 MLX5_OPCODE_CHECK_PSV = 0x22,
377 MLX5_OPCODE_RGET_PSV = 0x26,
378 MLX5_OPCODE_RCHECK_PSV = 0x27,
380 MLX5_OPCODE_UMR = 0x25,
382 MLX5_OPCODE_SIGNATURE_CANCELED = (1 << 15),
386 MLX5_OPCODE_MOD_UMR_UMR = 0x0,
387 MLX5_OPCODE_MOD_UMR_TLS_TIS_STATIC_PARAMS = 0x1,
388 MLX5_OPCODE_MOD_UMR_TLS_TIR_STATIC_PARAMS = 0x2,
392 MLX5_OPCODE_MOD_PSV_PSV = 0x0,
393 MLX5_OPCODE_MOD_PSV_TLS_TIS_PROGRESS_PARAMS = 0x1,
394 MLX5_OPCODE_MOD_PSV_TLS_TIR_PROGRESS_PARAMS = 0x2,
398 MLX5_SET_PORT_RESET_QKEY = 0,
399 MLX5_SET_PORT_GUID0 = 16,
400 MLX5_SET_PORT_NODE_GUID = 17,
401 MLX5_SET_PORT_SYS_GUID = 18,
402 MLX5_SET_PORT_GID_TABLE = 19,
403 MLX5_SET_PORT_PKEY_TABLE = 20,
407 MLX5_MAX_PAGE_SHIFT = 31
411 MLX5_ADAPTER_PAGE_SHIFT = 12,
412 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
416 MLX5_CAP_OFF_CMDIF_CSUM = 46,
421 * Max wqe size for rdma read is 512 bytes, so this
422 * limits our max_sge_rd as the wqe needs to fit:
423 * - ctrl segment (16 bytes)
424 * - rdma segment (16 bytes)
425 * - scatter elements (16 bytes each)
427 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
430 struct mlx5_cmd_layout {
445 enum mlx5_fatal_assert_bit_offsets {
446 MLX5_RFR_OFFSET = 31,
449 struct mlx5_health_buffer {
450 __be32 assert_var[5];
452 __be32 assert_exit_ptr;
453 __be32 assert_callra;
463 enum mlx5_initializing_bit_offsets {
464 MLX5_FW_RESET_SUPPORTED_OFFSET = 30,
467 enum mlx5_cmd_addr_l_sz_offset {
468 MLX5_NIC_IFC_OFFSET = 8,
471 struct mlx5_init_seg {
473 __be32 cmdif_rev_fw_sub;
476 __be32 cmdq_addr_l_sz;
480 struct mlx5_health_buffer health;
482 __be32 internal_timer_h;
483 __be32 internal_timer_l;
485 __be32 health_counter;
488 __be32 ieee1588_clk_type;
492 struct mlx5_eqe_comp {
497 struct mlx5_eqe_qp_srq {
502 struct mlx5_eqe_cq_err {
508 struct mlx5_eqe_port_state {
513 struct mlx5_eqe_gpio {
518 struct mlx5_eqe_congestion {
524 struct mlx5_eqe_stall_vl {
529 struct mlx5_eqe_cmd {
534 struct mlx5_eqe_page_req {
541 struct mlx5_eqe_vport_change {
548 #define PORT_MODULE_EVENT_MODULE_STATUS_MASK 0xF
549 #define PORT_MODULE_EVENT_ERROR_TYPE_MASK 0xF
552 MLX5_MODULE_STATUS_PLUGGED_ENABLED = 0x1,
553 MLX5_MODULE_STATUS_UNPLUGGED = 0x2,
554 MLX5_MODULE_STATUS_ERROR = 0x3,
555 MLX5_MODULE_STATUS_NUM ,
559 MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED = 0x0,
560 MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE = 0x1,
561 MLX5_MODULE_EVENT_ERROR_BUS_STUCK = 0x2,
562 MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT = 0x3,
563 MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST = 0x4,
564 MLX5_MODULE_EVENT_ERROR_UNSUPPORTED_CABLE = 0x5,
565 MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE = 0x6,
566 MLX5_MODULE_EVENT_ERROR_CABLE_IS_SHORTED = 0x7,
567 MLX5_MODULE_EVENT_ERROR_NUM ,
570 struct mlx5_eqe_port_module_event {
579 struct mlx5_eqe_general_notification_event {
580 u32 rq_user_index_delay_drop;
584 struct mlx5_eqe_temp_warning {
585 __be64 sensor_warning_msb;
586 __be64 sensor_warning_lsb;
591 struct mlx5_eqe_cmd cmd;
592 struct mlx5_eqe_comp comp;
593 struct mlx5_eqe_qp_srq qp_srq;
594 struct mlx5_eqe_cq_err cq_err;
595 struct mlx5_eqe_port_state port;
596 struct mlx5_eqe_gpio gpio;
597 struct mlx5_eqe_congestion cong;
598 struct mlx5_eqe_stall_vl stall_vl;
599 struct mlx5_eqe_page_req req_pages;
600 struct mlx5_eqe_port_module_event port_module_event;
601 struct mlx5_eqe_vport_change vport_change;
602 struct mlx5_eqe_general_notification_event general_notifications;
603 struct mlx5_eqe_temp_warning temp_warning;
618 struct mlx5_cmd_prot_block {
619 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
629 #define MLX5_NUM_CMDS_IN_ADAPTER_PAGE \
630 (MLX5_ADAPTER_PAGE_SIZE / MLX5_CMD_MBOX_SIZE)
631 CTASSERT(MLX5_CMD_MBOX_SIZE >= sizeof(struct mlx5_cmd_prot_block));
632 CTASSERT(MLX5_CMD_MBOX_SIZE <= MLX5_ADAPTER_PAGE_SIZE);
635 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
638 struct mlx5_err_cqe {
644 __be32 s_wqe_opcode_qpn;
653 u8 lro_tcppsh_abort_dupack;
656 __be32 lro_ack_seq_num;
657 __be32 rss_hash_result;
667 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
668 __be32 imm_inval_pkey;
678 #define MLX5_CQE_TSTMP_PTP (1ULL << 63)
680 static inline bool get_cqe_lro_timestamp_valid(struct mlx5_cqe64 *cqe)
682 return (cqe->lro_tcppsh_abort_dupack >> 7) & 1;
685 static inline bool get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
687 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
690 static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
692 return (cqe->l4_hdr_type_etc >> 4) & 0x7;
695 static inline u16 get_cqe_vlan(struct mlx5_cqe64 *cqe)
697 return be16_to_cpu(cqe->vlan_info) & 0xfff;
700 static inline void get_cqe_smac(struct mlx5_cqe64 *cqe, u8 *smac)
702 memcpy(smac, &cqe->rss_hash_type , 4);
703 memcpy(smac + 4, &cqe->slid , 2);
706 static inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe)
708 return cqe->l4_hdr_type_etc & 0x1;
711 static inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe)
713 return cqe->tunneled_etc & 0x1;
717 CQE_L4_HDR_TYPE_NONE = 0x0,
718 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
719 CQE_L4_HDR_TYPE_UDP = 0x2,
720 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
721 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
725 /* source L3 hash types */
726 CQE_RSS_SRC_HTYPE_IP = 0x3 << 0,
727 CQE_RSS_SRC_HTYPE_IPV4 = 0x1 << 0,
728 CQE_RSS_SRC_HTYPE_IPV6 = 0x2 << 0,
730 /* destination L3 hash types */
731 CQE_RSS_DST_HTYPE_IP = 0x3 << 2,
732 CQE_RSS_DST_HTYPE_IPV4 = 0x1 << 2,
733 CQE_RSS_DST_HTYPE_IPV6 = 0x2 << 2,
735 /* source L4 hash types */
736 CQE_RSS_SRC_HTYPE_L4 = 0x3 << 4,
737 CQE_RSS_SRC_HTYPE_TCP = 0x1 << 4,
738 CQE_RSS_SRC_HTYPE_UDP = 0x2 << 4,
739 CQE_RSS_SRC_HTYPE_IPSEC = 0x3 << 4,
741 /* destination L4 hash types */
742 CQE_RSS_DST_HTYPE_L4 = 0x3 << 6,
743 CQE_RSS_DST_HTYPE_TCP = 0x1 << 6,
744 CQE_RSS_DST_HTYPE_UDP = 0x2 << 6,
745 CQE_RSS_DST_HTYPE_IPSEC = 0x3 << 6,
749 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
750 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
751 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
760 struct mlx5_sig_err_cqe {
762 __be32 expected_trans_sig;
763 __be32 actual_trans_sig;
764 __be32 expected_reftag;
765 __be32 actual_reftag;
777 struct mlx5_wqe_srq_next_seg {
779 __be16 next_wqe_index;
790 union mlx5_ext_cqe inl_grh;
791 struct mlx5_cqe64 cqe64;
795 MLX5_MKEY_STATUS_FREE = 1 << 6,
798 struct mlx5_mkey_seg {
799 /* This is a two bit field occupying bits 31-30.
800 * bit 31 is always 0,
801 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
812 __be32 bsfs_octo_size;
820 #define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
823 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
826 static inline int mlx5_host_is_le(void)
828 #if defined(__LITTLE_ENDIAN)
830 #elif defined(__BIG_ENDIAN)
833 #error Host endianness not defined
837 #define MLX5_CMD_OP_MAX 0x939
840 VPORT_STATE_DOWN = 0x0,
841 VPORT_STATE_UP = 0x1,
845 MLX5_L3_PROT_TYPE_IPV4 = 0,
846 MLX5_L3_PROT_TYPE_IPV6 = 1,
850 MLX5_L4_PROT_TYPE_TCP = 0,
851 MLX5_L4_PROT_TYPE_UDP = 1,
855 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
856 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
857 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
858 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
859 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
863 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
864 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
865 MLX5_MATCH_INNER_HEADERS = 1 << 2,
870 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
871 MLX5_FLOW_TABLE_TYPE_EGRESS_ACL = 2,
872 MLX5_FLOW_TABLE_TYPE_INGRESS_ACL = 3,
873 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
874 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 5,
875 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 6,
876 MLX5_FLOW_TABLE_TYPE_NIC_RX_RDMA = 7,
880 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_NONE = 0,
881 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_IF_NO_VLAN = 1,
882 MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_OVERWRITE = 2
886 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_STRIP = 1 << 0,
887 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_STRIP = 1 << 1,
888 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_INSERT = 1 << 2,
889 MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_INSERT = 1 << 3
893 MLX5_UC_ADDR_CHANGE = (1 << 0),
894 MLX5_MC_ADDR_CHANGE = (1 << 1),
895 MLX5_VLAN_CHANGE = (1 << 2),
896 MLX5_PROMISC_CHANGE = (1 << 3),
897 MLX5_MTU_CHANGE = (1 << 4),
900 enum mlx5_list_type {
901 MLX5_NIC_VPORT_LIST_TYPE_UC = 0x0,
902 MLX5_NIC_VPORT_LIST_TYPE_MC = 0x1,
903 MLX5_NIC_VPORT_LIST_TYPE_VLAN = 0x2,
907 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0,
908 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1,
909 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2,
916 HCA_CAP_OPMOD_GET_MAX = 0,
917 HCA_CAP_OPMOD_GET_CUR = 1,
921 MLX5_CAP_GENERAL = 0,
922 MLX5_CAP_ETHERNET_OFFLOADS,
926 MLX5_CAP_IPOIB_OFFLOADS,
927 MLX5_CAP_EOIB_OFFLOADS,
929 MLX5_CAP_ESWITCH_FLOW_TABLE,
932 MLX5_CAP_VECTOR_CALC,
939 /* NUM OF CAP Types */
943 enum mlx5_qcam_reg_groups {
944 MLX5_QCAM_REGS_FIRST_128 = 0x0,
947 enum mlx5_qcam_feature_groups {
948 MLX5_QCAM_FEATURE_ENHANCED_FEATURES = 0x0,
951 enum mlx5_pcam_reg_groups {
952 MLX5_PCAM_REGS_5000_TO_507F = 0x0,
955 enum mlx5_pcam_feature_groups {
956 MLX5_PCAM_FEATURE_ENHANCED_FEATURES = 0x0,
959 enum mlx5_mcam_reg_groups {
960 MLX5_MCAM_REGS_FIRST_128 = 0x0,
963 enum mlx5_mcam_feature_groups {
964 MLX5_MCAM_FEATURE_ENHANCED_FEATURES = 0x0,
967 /* GET Dev Caps macros */
968 #define MLX5_CAP_GEN(mdev, cap) \
969 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
971 #define MLX5_CAP_GEN_64(mdev, cap) \
972 MLX5_GET64(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
974 #define MLX5_CAP_GEN_MAX(mdev, cap) \
975 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
977 #define MLX5_CAP_ETH(mdev, cap) \
978 MLX5_GET(per_protocol_networking_offload_caps,\
979 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
981 #define MLX5_CAP_ETH_MAX(mdev, cap) \
982 MLX5_GET(per_protocol_networking_offload_caps,\
983 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
985 #define MLX5_CAP_ROCE(mdev, cap) \
986 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
988 #define MLX5_CAP_ROCE_MAX(mdev, cap) \
989 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
991 #define MLX5_CAP_ATOMIC(mdev, cap) \
992 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
994 #define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
995 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
997 #define MLX5_CAP_FLOWTABLE(mdev, cap) \
998 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
1000 #define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
1001 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
1003 #define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
1004 MLX5_GET(flow_table_eswitch_cap, \
1005 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1007 #define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
1008 MLX5_GET(flow_table_eswitch_cap, \
1009 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
1011 #define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
1012 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
1014 #define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
1015 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1017 #define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
1018 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1020 #define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \
1021 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1023 #define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
1024 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1026 #define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \
1027 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1029 #define MLX5_CAP_ESW(mdev, cap) \
1030 MLX5_GET(e_switch_cap, \
1031 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap)
1033 #define MLX5_CAP_ESW_MAX(mdev, cap) \
1034 MLX5_GET(e_switch_cap, \
1035 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap)
1037 #define MLX5_CAP_ODP(mdev, cap)\
1038 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1040 #define MLX5_CAP_ODP_MAX(mdev, cap)\
1041 MLX5_GET(odp_cap, mdev->hca_caps_max[MLX5_CAP_ODP], cap)
1043 #define MLX5_CAP_SNAPSHOT(mdev, cap) \
1044 MLX5_GET(snapshot_cap, \
1045 mdev->hca_caps_cur[MLX5_CAP_SNAPSHOT], cap)
1047 #define MLX5_CAP_SNAPSHOT_MAX(mdev, cap) \
1048 MLX5_GET(snapshot_cap, \
1049 mdev->hca_caps_max[MLX5_CAP_SNAPSHOT], cap)
1051 #define MLX5_CAP_EOIB_OFFLOADS(mdev, cap) \
1052 MLX5_GET(per_protocol_networking_offload_caps,\
1053 mdev->hca_caps_cur[MLX5_CAP_EOIB_OFFLOADS], cap)
1055 #define MLX5_CAP_EOIB_OFFLOADS_MAX(mdev, cap) \
1056 MLX5_GET(per_protocol_networking_offload_caps,\
1057 mdev->hca_caps_max[MLX5_CAP_EOIB_OFFLOADS], cap)
1059 #define MLX5_CAP_DEBUG(mdev, cap) \
1060 MLX5_GET(debug_cap, \
1061 mdev->hca_caps_cur[MLX5_CAP_DEBUG], cap)
1063 #define MLX5_CAP_DEBUG_MAX(mdev, cap) \
1064 MLX5_GET(debug_cap, \
1065 mdev->hca_caps_max[MLX5_CAP_DEBUG], cap)
1067 #define MLX5_CAP_QOS(mdev, cap) \
1069 mdev->hca_caps_cur[MLX5_CAP_QOS], cap)
1071 #define MLX5_CAP_QOS_MAX(mdev, cap) \
1073 mdev->hca_caps_max[MLX5_CAP_QOS], cap)
1075 #define MLX5_CAP_PCAM_FEATURE(mdev, fld) \
1076 MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
1078 #define MLX5_CAP_PCAM_REG(mdev, reg) \
1079 MLX5_GET(pcam_reg, (mdev)->caps.pcam, port_access_reg_cap_mask.regs_5000_to_507f.reg)
1081 #define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
1082 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
1084 #define MLX5_CAP_MCAM_REG(mdev, reg) \
1085 MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_access_reg_cap_mask.access_regs.reg)
1087 #define MLX5_CAP_QCAM_REG(mdev, fld) \
1088 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)
1090 #define MLX5_CAP_QCAM_FEATURE(mdev, fld) \
1091 MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_feature_cap_mask.feature_cap.fld)
1093 #define MLX5_CAP_FPGA(mdev, cap) \
1094 MLX5_GET(fpga_cap, (mdev)->caps.fpga, cap)
1096 #define MLX5_CAP64_FPGA(mdev, cap) \
1097 MLX5_GET64(fpga_cap, (mdev)->caps.fpga, cap)
1099 #define MLX5_CAP_TLS(mdev, cap) \
1100 MLX5_GET(tls_capabilities, (mdev)->hca_caps_cur[MLX5_CAP_TLS], cap)
1103 MLX5_CMD_STAT_OK = 0x0,
1104 MLX5_CMD_STAT_INT_ERR = 0x1,
1105 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1106 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1107 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1108 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1109 MLX5_CMD_STAT_RES_BUSY = 0x6,
1110 MLX5_CMD_STAT_LIM_ERR = 0x8,
1111 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1112 MLX5_CMD_STAT_IX_ERR = 0xa,
1113 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1114 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1115 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1116 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1117 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1118 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1122 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1123 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1124 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1125 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1126 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1127 MLX5_ETHERNET_DISCARD_COUNTERS_GROUP = 0x6,
1128 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1129 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
1130 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12,
1131 MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP = 0x16,
1132 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
1136 MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0,
1137 MLX5_PCIE_LANE_COUNTERS_GROUP = 0x1,
1138 MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP = 0x2,
1142 MLX5_NUM_UUARS_PER_PAGE = MLX5_NON_FP_BF_REGS_PER_PAGE,
1143 MLX5_DEF_TOT_UUARS = 8 * MLX5_NUM_UUARS_PER_PAGE,
1147 NUM_DRIVER_UARS = 4,
1148 NUM_LOW_LAT_UUARS = 4,
1152 MLX5_CAP_PORT_TYPE_IB = 0x0,
1153 MLX5_CAP_PORT_TYPE_ETH = 0x1,
1157 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_L2 = 0x0,
1158 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_VPORT_CONFIG = 0x1,
1159 MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_NOT_REQUIRED = 0x2
1162 enum mlx5_inline_modes {
1163 MLX5_INLINE_MODE_NONE,
1164 MLX5_INLINE_MODE_L2,
1165 MLX5_INLINE_MODE_IP,
1166 MLX5_INLINE_MODE_TCP_UDP,
1170 MLX5_QUERY_VPORT_STATE_OUT_STATE_FOLLOW = 0x2,
1173 static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1175 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1177 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1180 struct mlx5_ifc_mcia_reg_bits {
1187 u8 i2c_device_address[0x8];
1188 u8 page_number[0x8];
1189 u8 device_address[0x10];
1191 u8 reserved_2[0x10];
1194 u8 reserved_3[0x20];
1210 #define MLX5_CMD_OP_QUERY_EEPROM 0x93c
1212 struct mlx5_mini_cqe8 {
1214 __be32 rx_hash_result;
1227 MLX5_NO_INLINE_DATA,
1228 MLX5_INLINE_DATA32_SEG,
1229 MLX5_INLINE_DATA64_SEG,
1233 enum mlx5_exp_cqe_zip_recv_type {
1234 MLX5_CQE_FORMAT_HASH,
1235 MLX5_CQE_FORMAT_CSUM,
1238 #define MLX5E_CQE_FORMAT_MASK 0xc
1239 static inline int mlx5_get_cqe_format(const struct mlx5_cqe64 *cqe)
1241 return (cqe->op_own & MLX5E_CQE_FORMAT_MASK) >> 2;
1245 MLX5_GEN_EVENT_SUBTYPE_DELAY_DROP_TIMEOUT = 0x1,
1246 MLX5_GEN_EVENT_SUBTYPE_PCI_POWER_CHANGE_EVENT = 0x5,
1250 MLX5_FRL_LEVEL3 = 0x8,
1251 MLX5_FRL_LEVEL6 = 0x40,
1254 /* 8 regular priorities + 1 for multicast */
1255 #define MLX5_NUM_BYPASS_FTS 9
1257 #endif /* MLX5_DEVICE_H */