2 * Copyright (c) 2013-2019, Mellanox Technologies, Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include "opt_ratelimit.h"
33 #include <linux/kernel.h>
34 #include <linux/completion.h>
35 #include <linux/pci.h>
36 #include <linux/cache.h>
37 #include <linux/rbtree.h>
38 #include <linux/if_ether.h>
39 #include <linux/semaphore.h>
40 #include <linux/slab.h>
41 #include <linux/vmalloc.h>
42 #include <linux/radix-tree.h>
43 #include <linux/idr.h>
45 #include <dev/mlx5/device.h>
46 #include <dev/mlx5/doorbell.h>
47 #include <dev/mlx5/srq.h>
49 #define MLX5_QCOUNTER_SETS_NETDEV 64
50 #define MLX5_MAX_NUMBER_OF_VFS 128
53 MLX5_BOARD_ID_LEN = 64,
54 MLX5_MAX_NAME_LEN = 16,
58 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000,
64 CMD_STATUS_SUCCESS = 0,
70 MLX5_SQP_IEEE_1588 = 2,
72 MLX5_SQP_SYNC_UMR = 4,
80 MLX5_EQ_VEC_PAGES = 0,
82 MLX5_EQ_VEC_ASYNC = 2,
83 MLX5_EQ_VEC_COMP_BASE,
87 MLX5_ATOMIC_MODE_OFF = 16,
88 MLX5_ATOMIC_MODE_NONE = 0 << MLX5_ATOMIC_MODE_OFF,
89 MLX5_ATOMIC_MODE_IB_COMP = 1 << MLX5_ATOMIC_MODE_OFF,
90 MLX5_ATOMIC_MODE_CX = 2 << MLX5_ATOMIC_MODE_OFF,
91 MLX5_ATOMIC_MODE_8B = 3 << MLX5_ATOMIC_MODE_OFF,
92 MLX5_ATOMIC_MODE_16B = 4 << MLX5_ATOMIC_MODE_OFF,
93 MLX5_ATOMIC_MODE_32B = 5 << MLX5_ATOMIC_MODE_OFF,
94 MLX5_ATOMIC_MODE_64B = 6 << MLX5_ATOMIC_MODE_OFF,
95 MLX5_ATOMIC_MODE_128B = 7 << MLX5_ATOMIC_MODE_OFF,
96 MLX5_ATOMIC_MODE_256B = 8 << MLX5_ATOMIC_MODE_OFF,
100 MLX5_ATOMIC_MODE_DCT_OFF = 20,
101 MLX5_ATOMIC_MODE_DCT_NONE = 0 << MLX5_ATOMIC_MODE_DCT_OFF,
102 MLX5_ATOMIC_MODE_DCT_IB_COMP = 1 << MLX5_ATOMIC_MODE_DCT_OFF,
103 MLX5_ATOMIC_MODE_DCT_CX = 2 << MLX5_ATOMIC_MODE_DCT_OFF,
104 MLX5_ATOMIC_MODE_DCT_8B = 3 << MLX5_ATOMIC_MODE_DCT_OFF,
105 MLX5_ATOMIC_MODE_DCT_16B = 4 << MLX5_ATOMIC_MODE_DCT_OFF,
106 MLX5_ATOMIC_MODE_DCT_32B = 5 << MLX5_ATOMIC_MODE_DCT_OFF,
107 MLX5_ATOMIC_MODE_DCT_64B = 6 << MLX5_ATOMIC_MODE_DCT_OFF,
108 MLX5_ATOMIC_MODE_DCT_128B = 7 << MLX5_ATOMIC_MODE_DCT_OFF,
109 MLX5_ATOMIC_MODE_DCT_256B = 8 << MLX5_ATOMIC_MODE_DCT_OFF,
113 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
114 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
115 MLX5_ATOMIC_OPS_MASKED_CMP_SWAP = 1 << 2,
116 MLX5_ATOMIC_OPS_MASKED_FETCH_ADD = 1 << 3,
120 MLX5_REG_QPTS = 0x4002,
121 MLX5_REG_QETCR = 0x4005,
122 MLX5_REG_QPDP = 0x4007,
123 MLX5_REG_QTCT = 0x400A,
124 MLX5_REG_QPDPM = 0x4013,
125 MLX5_REG_QHLL = 0x4016,
126 MLX5_REG_QCAM = 0x4019,
127 MLX5_REG_DCBX_PARAM = 0x4020,
128 MLX5_REG_DCBX_APP = 0x4021,
129 MLX5_REG_PCAP = 0x5001,
130 MLX5_REG_FPGA_CAP = 0x4022,
131 MLX5_REG_FPGA_CTRL = 0x4023,
132 MLX5_REG_FPGA_ACCESS_REG = 0x4024,
133 MLX5_REG_FPGA_SHELL_CNTR = 0x4025,
134 MLX5_REG_PMTU = 0x5003,
135 MLX5_REG_PTYS = 0x5004,
136 MLX5_REG_PAOS = 0x5006,
137 MLX5_REG_PFCC = 0x5007,
138 MLX5_REG_PPCNT = 0x5008,
139 MLX5_REG_PMAOS = 0x5012,
140 MLX5_REG_PUDE = 0x5009,
141 MLX5_REG_PPTB = 0x500B,
142 MLX5_REG_PBMC = 0x500C,
143 MLX5_REG_PMPE = 0x5010,
144 MLX5_REG_PELC = 0x500e,
145 MLX5_REG_PVLC = 0x500f,
146 MLX5_REG_PMLP = 0x5002,
147 MLX5_REG_PCAM = 0x507f,
148 MLX5_REG_NODE_DESC = 0x6001,
149 MLX5_REG_HOST_ENDIANNESS = 0x7004,
150 MLX5_REG_MTMP = 0x900a,
151 MLX5_REG_MCIA = 0x9014,
152 MLX5_REG_MFRL = 0x9028,
153 MLX5_REG_MPCNT = 0x9051,
154 MLX5_REG_MCQI = 0x9061,
155 MLX5_REG_MCC = 0x9062,
156 MLX5_REG_MCDA = 0x9063,
157 MLX5_REG_MCAM = 0x907f,
167 MLX5_INTERFACE_PROTOCOL_IB = 0,
168 MLX5_INTERFACE_PROTOCOL_ETH = 1,
169 MLX5_INTERFACE_NUMBER = 2,
172 struct mlx5_field_desc {
177 struct mlx5_rsc_debug {
178 struct mlx5_core_dev *dev;
180 enum dbg_rsc_type type;
182 struct mlx5_field_desc fields[0];
185 enum mlx5_dev_event {
186 MLX5_DEV_EVENT_SYS_ERROR,
187 MLX5_DEV_EVENT_PORT_UP,
188 MLX5_DEV_EVENT_PORT_DOWN,
189 MLX5_DEV_EVENT_PORT_INITIALIZED,
190 MLX5_DEV_EVENT_LID_CHANGE,
191 MLX5_DEV_EVENT_PKEY_CHANGE,
192 MLX5_DEV_EVENT_GUID_CHANGE,
193 MLX5_DEV_EVENT_CLIENT_REREG,
194 MLX5_DEV_EVENT_VPORT_CHANGE,
195 MLX5_DEV_EVENT_ERROR_STATE_DCBX,
196 MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE,
197 MLX5_DEV_EVENT_LOCAL_OPER_CHANGE,
198 MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE,
201 enum mlx5_port_status {
202 MLX5_PORT_UP = 1 << 0,
203 MLX5_PORT_DOWN = 1 << 1,
207 MLX5_VSC_SPACE_SUPPORTED = 0x1,
208 MLX5_VSC_SPACE_OFFSET = 0x4,
209 MLX5_VSC_COUNTER_OFFSET = 0x8,
210 MLX5_VSC_SEMA_OFFSET = 0xC,
211 MLX5_VSC_ADDR_OFFSET = 0x10,
212 MLX5_VSC_DATA_OFFSET = 0x14,
213 MLX5_VSC_MAX_RETRIES = 0x1000,
216 #define MLX5_PROT_MASK(link_mode) (1 << link_mode)
218 struct mlx5_uuar_info {
219 struct mlx5_uar *uars;
221 int num_low_latency_uuars;
222 unsigned long *bitmap;
227 * protect uuar allocation data structs
235 void __iomem *regreg;
237 struct mlx5_uar *uar;
238 unsigned long offset;
240 /* protect blue flame buffer selection when needed
244 /* serialize 64 bit writes when done as two 32 bit accesses
250 struct mlx5_cmd_first {
255 struct mlx5_fw_page {
257 struct rb_node rb_node;
258 struct list_head list;
260 struct mlx5_cmd_first first;
261 struct mlx5_core_dev *dev;
262 bus_dmamap_t dma_map;
265 struct cache_ent *cache;
268 #define MLX5_LOAD_ST_NONE 0
269 #define MLX5_LOAD_ST_SUCCESS 1
270 #define MLX5_LOAD_ST_FAILURE 2
273 #define mlx5_cmd_msg mlx5_fw_page
275 struct mlx5_cmd_debug {
276 struct dentry *dbg_root;
277 struct dentry *dbg_in;
278 struct dentry *dbg_out;
279 struct dentry *dbg_outlen;
280 struct dentry *dbg_status;
281 struct dentry *dbg_run;
290 /* protect block chain allocations
293 struct list_head head;
296 struct cmd_msg_cache {
297 struct cache_ent large;
298 struct cache_ent med;
302 struct mlx5_traffic_counter {
308 MLX5_CMD_MODE_POLLING,
312 struct mlx5_cmd_stats {
317 struct dentry *count;
318 /* protect command average calculations */
323 struct mlx5_fw_page *cmd_page;
324 bus_dma_tag_t dma_tag;
327 #define MLX5_DMA_OWNED(dev) mtx_owned(&(dev)->cmd.dma_mtx)
328 #define MLX5_DMA_LOCK(dev) mtx_lock(&(dev)->cmd.dma_mtx)
329 #define MLX5_DMA_UNLOCK(dev) mtx_unlock(&(dev)->cmd.dma_mtx)
331 #define MLX5_DMA_DONE(dev) cv_broadcast(&(dev)->cmd.dma_cv)
332 #define MLX5_DMA_WAIT(dev) cv_wait(&(dev)->cmd.dma_cv, &(dev)->cmd.dma_mtx)
342 /* protect command queue allocations
344 spinlock_t alloc_lock;
346 /* protect token allocations
348 spinlock_t token_lock;
350 unsigned long bitmask;
351 struct semaphore sem;
352 struct semaphore pages_sem;
353 enum mlx5_cmd_mode mode;
354 struct mlx5_cmd_work_ent * volatile ent_arr[MLX5_MAX_COMMANDS];
355 volatile enum mlx5_cmd_mode ent_mode[MLX5_MAX_COMMANDS];
356 struct mlx5_cmd_debug dbg;
357 struct cmd_msg_cache cache;
358 int checksum_disabled;
359 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
362 struct mlx5_port_caps {
369 bus_dma_tag_t dma_tag;
370 bus_dmamap_t dma_map;
371 struct mlx5_core_dev *dev;
382 struct mlx5_frag_buf {
383 struct mlx5_buf_list *frags;
390 struct mlx5_core_dev *dev;
391 __be32 __iomem *doorbell;
399 struct list_head list;
401 struct mlx5_rsc_debug *dbg;
404 struct mlx5_core_psv {
416 struct mlx5_core_sig_ctx {
417 struct mlx5_core_psv psv_memory;
418 struct mlx5_core_psv psv_wire;
419 #if (__FreeBSD_version >= 1100000)
420 struct ib_sig_err err_item;
422 bool sig_status_checked;
433 struct mlx5_core_mkey {
441 struct mlx5_core_mr {
449 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
450 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
451 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
457 struct mlx5_core_rsc_common {
458 enum mlx5_res_type res;
460 struct completion free;
463 struct mlx5_core_srq {
464 struct mlx5_core_rsc_common common; /* must be first */
468 size_t max_avail_gather;
470 void (*event)(struct mlx5_core_srq *, int);
472 struct completion free;
475 struct mlx5_eq_table {
476 void __iomem *update_ci;
477 void __iomem *update_arm_ci;
478 struct list_head comp_eqs_list;
479 struct mlx5_eq pages_eq;
480 struct mlx5_eq async_eq;
481 struct mlx5_eq cmd_eq;
482 int num_comp_vectors;
490 void __iomem *bf_map;
495 struct mlx5_core_health {
496 struct mlx5_health_buffer __iomem *health;
497 __be32 __iomem *health_counter;
498 struct timer_list timer;
502 struct workqueue_struct *wq_watchdog;
503 struct work_struct work_watchdog;
504 /* wq spinlock to synchronize draining */
506 struct workqueue_struct *wq;
508 struct work_struct work;
509 struct delayed_work recover_work;
510 unsigned int last_reset_req;
511 struct work_struct work_cmd_completion;
512 struct workqueue_struct *wq_cmd;
516 #define MLX5_CQ_LINEAR_ARRAY_SIZE (128 * 1024)
518 #define MLX5_CQ_LINEAR_ARRAY_SIZE 1024
521 struct mlx5_cq_linear_array_entry {
523 struct mlx5_core_cq * volatile cq;
526 struct mlx5_cq_table {
527 /* protect radix tree
530 struct radix_tree_root tree;
531 struct mlx5_cq_linear_array_entry linear_array[MLX5_CQ_LINEAR_ARRAY_SIZE];
534 struct mlx5_qp_table {
535 /* protect radix tree
538 struct radix_tree_root tree;
541 struct mlx5_srq_table {
542 /* protect radix tree
545 struct radix_tree_root tree;
548 struct mlx5_mr_table {
549 /* protect radix tree
552 struct radix_tree_root tree;
556 struct mlx5_rl_entry {
563 struct mlx5_rl_table {
564 struct mutex rl_lock;
568 struct mlx5_rl_entry *rl_entry;
572 struct mlx5_pme_stats {
573 u64 status_counters[MLX5_MODULE_STATUS_NUM];
574 u64 error_counters[MLX5_MODULE_EVENT_ERROR_NUM];
578 char name[MLX5_MAX_NAME_LEN];
579 struct mlx5_eq_table eq_table;
580 struct msix_entry *msix_arr;
581 struct mlx5_uuar_info uuari;
582 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
585 struct io_mapping *bf_mapping;
588 struct workqueue_struct *pg_wq;
589 struct rb_root page_root;
592 s64 pages_per_func[MLX5_MAX_NUMBER_OF_VFS];
593 struct mlx5_core_health health;
595 struct mlx5_srq_table srq_table;
597 /* start: qp staff */
598 struct mlx5_qp_table qp_table;
599 struct dentry *qp_debugfs;
600 struct dentry *eq_debugfs;
601 struct dentry *cq_debugfs;
602 struct dentry *cmdif_debugfs;
605 /* start: cq staff */
606 struct mlx5_cq_table cq_table;
609 /* start: mr staff */
610 struct mlx5_mr_table mr_table;
613 /* start: alloc staff */
616 struct mutex pgdir_mutex;
617 struct list_head pgdir_list;
618 /* end: alloc staff */
619 struct dentry *dbg_root;
621 /* protect mkey key part */
622 spinlock_t mkey_lock;
625 struct list_head dev_list;
626 struct list_head ctx_list;
628 unsigned long pci_dev_data;
630 struct mlx5_rl_table rl_table;
632 struct mlx5_pme_stats pme_stats;
635 enum mlx5_device_state {
636 MLX5_DEVICE_STATE_UP,
637 MLX5_DEVICE_STATE_INTERNAL_ERROR,
640 enum mlx5_interface_state {
641 MLX5_INTERFACE_STATE_UP,
644 enum mlx5_pci_status {
645 MLX5_PCI_STATUS_DISABLED,
646 MLX5_PCI_STATUS_ENABLED,
649 #define MLX5_MAX_RESERVED_GIDS 8
651 struct mlx5_rsvd_gids {
657 struct mlx5_special_contexts {
661 struct mlx5_flow_root_namespace;
662 struct mlx5_core_dev {
663 struct pci_dev *pdev;
665 struct mutex pci_status_mutex;
666 enum mlx5_pci_status pci_status;
667 char board_id[MLX5_BOARD_ID_LEN];
669 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
670 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
671 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
673 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
674 u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
675 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
676 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
678 phys_addr_t iseg_base;
679 struct mlx5_init_seg __iomem *iseg;
680 enum mlx5_device_state state;
681 /* sync interface state */
682 struct mutex intf_state_mutex;
683 unsigned long intf_state;
684 void (*event) (struct mlx5_core_dev *dev,
685 enum mlx5_dev_event event,
686 unsigned long param);
687 struct mlx5_priv priv;
688 struct mlx5_profile *profile;
692 struct mlx5_special_contexts special_contexts;
693 unsigned int module_status[MLX5_MAX_PORTS];
694 struct mlx5_flow_root_namespace *root_ns;
695 struct mlx5_flow_root_namespace *fdb_root_ns;
696 struct mlx5_flow_root_namespace *esw_egress_root_ns;
697 struct mlx5_flow_root_namespace *esw_ingress_root_ns;
698 struct mlx5_flow_root_namespace *sniffer_rx_root_ns;
699 struct mlx5_flow_root_namespace *sniffer_tx_root_ns;
700 u32 num_q_counter_allocated[MLX5_INTERFACE_NUMBER];
701 const struct mlx5_crspace_regmap *dump_rege;
706 struct mtx dump_lock;
708 struct sysctl_ctx_list sysctl_ctx;
714 struct mlx5_rsvd_gids reserved_gids;
720 #define MLX5_MPFS_TABLE_MAX 32
721 long bitmap[BITS_TO_LONGS(MLX5_MPFS_TABLE_MAX)];
723 #ifdef CONFIG_MLX5_FPGA
724 struct mlx5_fpga_device *fpga;
729 MLX5_WOL_DISABLE = 0,
730 MLX5_WOL_SECURED_MAGIC = 1 << 1,
731 MLX5_WOL_MAGIC = 1 << 2,
732 MLX5_WOL_ARP = 1 << 3,
733 MLX5_WOL_BROADCAST = 1 << 4,
734 MLX5_WOL_MULTICAST = 1 << 5,
735 MLX5_WOL_UNICAST = 1 << 6,
736 MLX5_WOL_PHY_ACTIVITY = 1 << 7,
742 struct mlx5_db_pgdir *pgdir;
743 struct mlx5_ib_user_db_page *user_page;
749 struct mlx5_net_counters {
754 struct mlx5_ptys_reg {
760 u16 ib_link_width_cap;
763 u16 ib_link_width_admin;
766 u16 ib_link_width_oper;
768 u32 eth_proto_lp_advertise;
771 struct mlx5_pvlc_reg {
778 struct mlx5_pmtu_reg {
785 struct mlx5_vport_counters {
786 struct mlx5_net_counters received_errors;
787 struct mlx5_net_counters transmit_errors;
788 struct mlx5_net_counters received_ib_unicast;
789 struct mlx5_net_counters transmitted_ib_unicast;
790 struct mlx5_net_counters received_ib_multicast;
791 struct mlx5_net_counters transmitted_ib_multicast;
792 struct mlx5_net_counters received_eth_broadcast;
793 struct mlx5_net_counters transmitted_eth_broadcast;
794 struct mlx5_net_counters received_eth_unicast;
795 struct mlx5_net_counters transmitted_eth_unicast;
796 struct mlx5_net_counters received_eth_multicast;
797 struct mlx5_net_counters transmitted_eth_multicast;
801 MLX5_DB_PER_PAGE = MLX5_ADAPTER_PAGE_SIZE / L1_CACHE_BYTES,
804 struct mlx5_core_dct {
805 struct mlx5_core_rsc_common common; /* must be first */
806 void (*event)(struct mlx5_core_dct *, int);
808 struct completion drained;
809 struct mlx5_rsc_debug *dbg;
814 MLX5_COMP_EQ_SIZE = 1024,
818 MLX5_PTYS_IB = 1 << 0,
819 MLX5_PTYS_EN = 1 << 2,
822 struct mlx5_db_pgdir {
823 struct list_head list;
824 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
825 struct mlx5_fw_page *fw_page;
830 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
832 struct mlx5_cmd_work_ent {
833 struct mlx5_cmd_msg *in;
834 struct mlx5_cmd_msg *out;
838 mlx5_cmd_cbk_t callback;
839 struct delayed_work cb_timeout_work;
842 struct completion done;
843 struct mlx5_cmd *cmd;
844 struct work_struct work;
845 struct mlx5_cmd_layout *lay;
862 enum port_state_policy {
863 MLX5_POLICY_DOWN = 0,
865 MLX5_POLICY_FOLLOW = 2,
866 MLX5_POLICY_INVALID = 0xffffffff
870 mlx5_buf_offset(struct mlx5_buf *buf, int offset)
872 return ((char *)buf->direct.buf + offset);
876 extern struct workqueue_struct *mlx5_core_wq;
878 #define STRUCT_FIELD(header, field) \
879 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
880 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
882 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
884 return pci_get_drvdata(pdev);
887 extern struct dentry *mlx5_debugfs_root;
889 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
891 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
894 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
896 return ioread32be(&dev->iseg->fw_rev) >> 16;
899 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
901 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
904 static inline u16 cmdif_rev_get(struct mlx5_core_dev *dev)
906 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
909 static inline int mlx5_get_gid_table_len(u16 param)
912 printf("M4_CORE_DRV_NAME: WARN: ""gid table length is zero\n");
916 return 8 * (1 << param);
919 static inline void *mlx5_vzalloc(unsigned long size)
923 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
927 static inline void *mlx5_vmalloc(unsigned long size)
931 rtn = kmalloc(size, GFP_KERNEL | __GFP_NOWARN);
937 static inline u32 mlx5_base_mkey(const u32 key)
939 return key & 0xffffff00u;
942 int mlx5_cmd_init(struct mlx5_core_dev *dev);
943 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
944 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
945 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
946 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
947 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
948 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
950 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
951 void *out, int out_size, mlx5_cmd_cbk_t callback,
953 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
954 void *out, int out_size);
955 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
956 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
957 int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
958 int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
959 int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
960 void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
961 void mlx5_health_cleanup(struct mlx5_core_dev *dev);
962 int mlx5_health_init(struct mlx5_core_dev *dev);
963 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
964 void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
965 void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
966 void mlx5_drain_health_recovery(struct mlx5_core_dev *dev);
967 void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
968 void mlx5_trigger_health_watchdog(struct mlx5_core_dev *dev);
970 #define mlx5_buf_alloc_node(dev, size, direct, buf, node) \
971 mlx5_buf_alloc(dev, size, direct, buf)
972 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct,
973 struct mlx5_buf *buf);
974 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
975 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
976 struct mlx5_srq_attr *in);
977 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
978 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
979 struct mlx5_srq_attr *out);
980 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
981 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
982 u16 lwm, int is_srq);
983 void mlx5_init_mr_table(struct mlx5_core_dev *dev);
984 void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev);
985 int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev,
986 struct mlx5_core_mr *mkey,
988 u32 *out, int outlen,
989 mlx5_cmd_cbk_t callback, void *context);
990 int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
991 struct mlx5_core_mr *mr,
993 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey);
994 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mkey,
995 u32 *out, int outlen);
996 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
998 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
999 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
1000 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb,
1001 u16 opmod, u8 port);
1002 void mlx5_fwp_flush(struct mlx5_fw_page *fwp);
1003 void mlx5_fwp_invalidate(struct mlx5_fw_page *fwp);
1004 struct mlx5_fw_page *mlx5_fwp_alloc(struct mlx5_core_dev *dev, gfp_t flags, unsigned num);
1005 void mlx5_fwp_free(struct mlx5_fw_page *fwp);
1006 u64 mlx5_fwp_get_dma(struct mlx5_fw_page *fwp, size_t offset);
1007 void *mlx5_fwp_get_virt(struct mlx5_fw_page *fwp, size_t offset);
1008 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
1009 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
1010 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
1011 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
1012 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
1014 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
1015 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
1016 s64 mlx5_wait_for_reclaim_vfs_pages(struct mlx5_core_dev *dev);
1017 void mlx5_register_debugfs(void);
1018 void mlx5_unregister_debugfs(void);
1019 int mlx5_eq_init(struct mlx5_core_dev *dev);
1020 void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
1021 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
1022 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
1023 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
1024 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
1025 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
1026 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vector, enum mlx5_cmd_mode mode);
1027 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
1028 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
1029 int nent, u64 mask, struct mlx5_uar *uar);
1030 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1031 int mlx5_start_eqs(struct mlx5_core_dev *dev);
1032 int mlx5_stop_eqs(struct mlx5_core_dev *dev);
1033 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn);
1034 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1035 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
1036 int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable,
1039 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
1040 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
1041 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
1042 int size_in, void *data_out, int size_out,
1043 u16 reg_num, int arg, int write);
1045 void mlx5_toggle_port_link(struct mlx5_core_dev *dev);
1047 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1048 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
1049 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
1050 u32 *out, int outlen);
1051 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
1052 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
1053 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
1054 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
1055 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
1056 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
1058 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
1060 const char *mlx5_command_str(int command);
1061 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1062 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1063 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1064 int npsvs, u32 *sig_index);
1065 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1066 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1067 u8 mlx5_is_wol_supported(struct mlx5_core_dev *dev);
1068 int mlx5_set_wol(struct mlx5_core_dev *dev, u8 wol_mode);
1069 int mlx5_set_dropless_mode(struct mlx5_core_dev *dev, u16 timeout);
1070 int mlx5_query_dropless_mode(struct mlx5_core_dev *dev, u16 *timeout);
1071 int mlx5_query_wol(struct mlx5_core_dev *dev, u8 *wol_mode);
1072 int mlx5_core_access_pvlc(struct mlx5_core_dev *dev,
1073 struct mlx5_pvlc_reg *pvlc, int write);
1074 int mlx5_core_access_ptys(struct mlx5_core_dev *dev,
1075 struct mlx5_ptys_reg *ptys, int write);
1076 int mlx5_core_access_pmtu(struct mlx5_core_dev *dev,
1077 struct mlx5_pmtu_reg *pmtu, int write);
1078 int mlx5_vxlan_udp_port_add(struct mlx5_core_dev *dev, u16 port);
1079 int mlx5_vxlan_udp_port_delete(struct mlx5_core_dev *dev, u16 port);
1080 int mlx5_query_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
1081 int priority, int *is_enable);
1082 int mlx5_modify_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
1083 int priority, int enable);
1084 int mlx5_query_port_cong_params(struct mlx5_core_dev *mdev, int protocol,
1085 void *out, int out_size);
1086 int mlx5_modify_port_cong_params(struct mlx5_core_dev *mdev,
1087 void *in, int in_size);
1088 int mlx5_query_port_cong_statistics(struct mlx5_core_dev *mdev, int clear,
1089 void *out, int out_size);
1090 int mlx5_set_diagnostic_params(struct mlx5_core_dev *mdev, void *in,
1092 int mlx5_query_diagnostic_counters(struct mlx5_core_dev *mdev,
1093 u8 num_of_samples, u16 sample_index,
1094 void *out, int out_size);
1095 int mlx5_vsc_find_cap(struct mlx5_core_dev *mdev);
1096 int mlx5_vsc_lock(struct mlx5_core_dev *mdev);
1097 void mlx5_vsc_unlock(struct mlx5_core_dev *mdev);
1098 int mlx5_vsc_set_space(struct mlx5_core_dev *mdev, u16 space);
1099 int mlx5_vsc_wait_on_flag(struct mlx5_core_dev *mdev, u32 expected);
1100 int mlx5_vsc_write(struct mlx5_core_dev *mdev, u32 addr, const u32 *data);
1101 int mlx5_vsc_read(struct mlx5_core_dev *mdev, u32 addr, u32 *data);
1102 int mlx5_vsc_lock_addr_space(struct mlx5_core_dev *mdev, u32 addr);
1103 int mlx5_vsc_unlock_addr_space(struct mlx5_core_dev *mdev, u32 addr);
1104 int mlx5_pci_read_power_status(struct mlx5_core_dev *mdev,
1105 u16 *p_power, u8 *p_status);
1107 static inline u32 mlx5_mkey_to_idx(u32 mkey)
1112 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1114 return mkey_idx << 8;
1117 static inline u8 mlx5_mkey_variant(u32 mkey)
1123 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
1124 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
1128 MAX_MR_CACHE_ENTRIES = 15,
1131 struct mlx5_interface {
1132 void * (*add)(struct mlx5_core_dev *dev);
1133 void (*remove)(struct mlx5_core_dev *dev, void *context);
1134 void (*event)(struct mlx5_core_dev *dev, void *context,
1135 enum mlx5_dev_event event, unsigned long param);
1136 void * (*get_dev)(void *context);
1138 struct list_head list;
1141 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
1142 int mlx5_register_interface(struct mlx5_interface *intf);
1143 void mlx5_unregister_interface(struct mlx5_interface *intf);
1145 unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1146 int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1147 u8 roce_version, u8 roce_l3_type, const u8 *gid,
1148 const u8 *mac, bool vlan, u16 vlan_id);
1150 struct mlx5_profile {
1156 } mr_cache[MAX_MR_CACHE_ENTRIES];
1160 MLX5_PCI_DEV_IS_VF = 1 << 0,
1164 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1167 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
1169 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
1172 int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1173 void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1174 int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst, u16 *index);
1175 void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, u32 rate, u32 burst);
1176 bool mlx5_rl_is_in_range(const struct mlx5_core_dev *dev, u32 rate, u32 burst);
1178 static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1180 return !!(dev->priv.rl_table.max_size);
1184 #endif /* MLX5_DRIVER_H */