2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <linux/kernel.h>
32 #include <linux/completion.h>
33 #include <linux/pci.h>
34 #include <linux/cache.h>
35 #include <linux/rbtree.h>
36 #include <linux/if_ether.h>
37 #include <linux/semaphore.h>
38 #include <linux/slab.h>
39 #include <linux/vmalloc.h>
40 #include <linux/radix-tree.h>
42 #include <dev/mlx5/device.h>
43 #include <dev/mlx5/doorbell.h>
45 #define MLX5_QCOUNTER_SETS_NETDEV 64
46 #define MLX5_MAX_NUMBER_OF_VFS 128
49 MLX5_BOARD_ID_LEN = 64,
50 MLX5_MAX_NAME_LEN = 16,
54 MLX5_CMD_TIMEOUT_MSEC = 8 * 60 * 1000,
55 MLX5_CMD_WQ_MAX_NAME = 32,
61 CMD_STATUS_SUCCESS = 0,
67 MLX5_SQP_IEEE_1588 = 2,
69 MLX5_SQP_SYNC_UMR = 4,
77 MLX5_EQ_VEC_PAGES = 0,
79 MLX5_EQ_VEC_ASYNC = 2,
80 MLX5_EQ_VEC_COMP_BASE,
84 MLX5_MAX_IRQ_NAME = 32
88 MLX5_ATOMIC_MODE_OFF = 16,
89 MLX5_ATOMIC_MODE_NONE = 0 << MLX5_ATOMIC_MODE_OFF,
90 MLX5_ATOMIC_MODE_IB_COMP = 1 << MLX5_ATOMIC_MODE_OFF,
91 MLX5_ATOMIC_MODE_CX = 2 << MLX5_ATOMIC_MODE_OFF,
92 MLX5_ATOMIC_MODE_8B = 3 << MLX5_ATOMIC_MODE_OFF,
93 MLX5_ATOMIC_MODE_16B = 4 << MLX5_ATOMIC_MODE_OFF,
94 MLX5_ATOMIC_MODE_32B = 5 << MLX5_ATOMIC_MODE_OFF,
95 MLX5_ATOMIC_MODE_64B = 6 << MLX5_ATOMIC_MODE_OFF,
96 MLX5_ATOMIC_MODE_128B = 7 << MLX5_ATOMIC_MODE_OFF,
97 MLX5_ATOMIC_MODE_256B = 8 << MLX5_ATOMIC_MODE_OFF,
101 MLX5_ATOMIC_MODE_DCT_OFF = 20,
102 MLX5_ATOMIC_MODE_DCT_NONE = 0 << MLX5_ATOMIC_MODE_DCT_OFF,
103 MLX5_ATOMIC_MODE_DCT_IB_COMP = 1 << MLX5_ATOMIC_MODE_DCT_OFF,
104 MLX5_ATOMIC_MODE_DCT_CX = 2 << MLX5_ATOMIC_MODE_DCT_OFF,
105 MLX5_ATOMIC_MODE_DCT_8B = 3 << MLX5_ATOMIC_MODE_DCT_OFF,
106 MLX5_ATOMIC_MODE_DCT_16B = 4 << MLX5_ATOMIC_MODE_DCT_OFF,
107 MLX5_ATOMIC_MODE_DCT_32B = 5 << MLX5_ATOMIC_MODE_DCT_OFF,
108 MLX5_ATOMIC_MODE_DCT_64B = 6 << MLX5_ATOMIC_MODE_DCT_OFF,
109 MLX5_ATOMIC_MODE_DCT_128B = 7 << MLX5_ATOMIC_MODE_DCT_OFF,
110 MLX5_ATOMIC_MODE_DCT_256B = 8 << MLX5_ATOMIC_MODE_DCT_OFF,
114 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
115 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
116 MLX5_ATOMIC_OPS_MASKED_CMP_SWAP = 1 << 2,
117 MLX5_ATOMIC_OPS_MASKED_FETCH_ADD = 1 << 3,
121 MLX5_REG_QETCR = 0x4005,
122 MLX5_REG_QPDP = 0x4007,
123 MLX5_REG_QTCT = 0x400A,
124 MLX5_REG_QHLL = 0x4016,
125 MLX5_REG_DCBX_PARAM = 0x4020,
126 MLX5_REG_DCBX_APP = 0x4021,
127 MLX5_REG_PCAP = 0x5001,
128 MLX5_REG_PMTU = 0x5003,
129 MLX5_REG_PTYS = 0x5004,
130 MLX5_REG_PAOS = 0x5006,
131 MLX5_REG_PFCC = 0x5007,
132 MLX5_REG_PPCNT = 0x5008,
133 MLX5_REG_PMAOS = 0x5012,
134 MLX5_REG_PUDE = 0x5009,
135 MLX5_REG_PPTB = 0x500B,
136 MLX5_REG_PBMC = 0x500C,
137 MLX5_REG_PMPE = 0x5010,
138 MLX5_REG_PELC = 0x500e,
139 MLX5_REG_PVLC = 0x500f,
140 MLX5_REG_PMLP = 0x5002,
141 MLX5_REG_NODE_DESC = 0x6001,
142 MLX5_REG_HOST_ENDIANNESS = 0x7004,
143 MLX5_REG_MCIA = 0x9014,
144 MLX5_REG_MPCNT = 0x9051,
154 MLX5_INTERFACE_PROTOCOL_IB = 0,
155 MLX5_INTERFACE_PROTOCOL_ETH = 1,
156 MLX5_INTERFACE_NUMBER = 2,
159 struct mlx5_field_desc {
164 struct mlx5_rsc_debug {
165 struct mlx5_core_dev *dev;
167 enum dbg_rsc_type type;
169 struct mlx5_field_desc fields[0];
172 enum mlx5_dev_event {
173 MLX5_DEV_EVENT_SYS_ERROR,
174 MLX5_DEV_EVENT_PORT_UP,
175 MLX5_DEV_EVENT_PORT_DOWN,
176 MLX5_DEV_EVENT_PORT_INITIALIZED,
177 MLX5_DEV_EVENT_LID_CHANGE,
178 MLX5_DEV_EVENT_PKEY_CHANGE,
179 MLX5_DEV_EVENT_GUID_CHANGE,
180 MLX5_DEV_EVENT_CLIENT_REREG,
181 MLX5_DEV_EVENT_VPORT_CHANGE,
182 MLX5_DEV_EVENT_ERROR_STATE_DCBX,
183 MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE,
184 MLX5_DEV_EVENT_LOCAL_OPER_CHANGE,
185 MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE,
188 enum mlx5_port_status {
189 MLX5_PORT_UP = 1 << 0,
190 MLX5_PORT_DOWN = 1 << 1,
193 enum mlx5_link_mode {
194 MLX5_1000BASE_CX_SGMII = 0,
195 MLX5_1000BASE_KX = 1,
196 MLX5_10GBASE_CX4 = 2,
197 MLX5_10GBASE_KX4 = 3,
199 MLX5_20GBASE_KR2 = 5,
200 MLX5_40GBASE_CR4 = 6,
201 MLX5_40GBASE_KR4 = 7,
203 MLX5_10GBASE_CR = 12,
204 MLX5_10GBASE_SR = 13,
205 MLX5_10GBASE_ER = 14,
206 MLX5_40GBASE_SR4 = 15,
207 MLX5_40GBASE_LR4 = 16,
208 MLX5_100GBASE_CR4 = 20,
209 MLX5_100GBASE_SR4 = 21,
210 MLX5_100GBASE_KR4 = 22,
211 MLX5_100GBASE_LR4 = 23,
212 MLX5_100BASE_TX = 24,
213 MLX5_1000BASE_T = 25,
215 MLX5_25GBASE_CR = 27,
216 MLX5_25GBASE_KR = 28,
217 MLX5_25GBASE_SR = 29,
218 MLX5_50GBASE_CR2 = 30,
219 MLX5_50GBASE_KR2 = 31,
220 MLX5_LINK_MODES_NUMBER,
223 #define MLX5_PROT_MASK(link_mode) (1 << link_mode)
225 struct mlx5_uuar_info {
226 struct mlx5_uar *uars;
228 int num_low_latency_uuars;
229 unsigned long *bitmap;
234 * protect uuar allocation data structs
242 void __iomem *regreg;
244 struct mlx5_uar *uar;
245 unsigned long offset;
247 /* protect blue flame buffer selection when needed
251 /* serialize 64 bit writes when done as two 32 bit accesses
257 struct mlx5_cmd_first {
262 struct mlx5_fw_page {
264 struct rb_node rb_node;
265 struct list_head list;
267 struct mlx5_cmd_first first;
268 struct mlx5_core_dev *dev;
269 bus_dmamap_t dma_map;
272 struct cache_ent *cache;
275 #define MLX5_LOAD_ST_NONE 0
276 #define MLX5_LOAD_ST_SUCCESS 1
277 #define MLX5_LOAD_ST_FAILURE 2
280 #define mlx5_cmd_msg mlx5_fw_page
282 struct mlx5_cmd_debug {
283 struct dentry *dbg_root;
284 struct dentry *dbg_in;
285 struct dentry *dbg_out;
286 struct dentry *dbg_outlen;
287 struct dentry *dbg_status;
288 struct dentry *dbg_run;
297 /* protect block chain allocations
300 struct list_head head;
303 struct cmd_msg_cache {
304 struct cache_ent large;
305 struct cache_ent med;
309 struct mlx5_cmd_stats {
314 struct dentry *count;
315 /* protect command average calculations */
320 struct mlx5_fw_page *cmd_page;
321 bus_dma_tag_t dma_tag;
324 #define MLX5_DMA_OWNED(dev) mtx_owned(&(dev)->cmd.dma_mtx)
325 #define MLX5_DMA_LOCK(dev) mtx_lock(&(dev)->cmd.dma_mtx)
326 #define MLX5_DMA_UNLOCK(dev) mtx_unlock(&(dev)->cmd.dma_mtx)
328 #define MLX5_DMA_DONE(dev) cv_broadcast(&(dev)->cmd.dma_cv)
329 #define MLX5_DMA_WAIT(dev) cv_wait(&(dev)->cmd.dma_cv, &(dev)->cmd.dma_mtx)
339 /* protect command queue allocations
341 spinlock_t alloc_lock;
343 /* protect token allocations
345 spinlock_t token_lock;
347 unsigned long bitmask;
348 char wq_name[MLX5_CMD_WQ_MAX_NAME];
349 struct workqueue_struct *wq;
350 struct semaphore sem;
351 struct semaphore pages_sem;
353 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
354 struct mlx5_cmd_debug dbg;
355 struct cmd_msg_cache cache;
356 int checksum_disabled;
357 struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX];
358 int moving_to_polling;
361 struct mlx5_port_caps {
368 bus_dma_tag_t dma_tag;
369 bus_dmamap_t dma_map;
370 struct mlx5_core_dev *dev;
382 struct mlx5_core_dev *dev;
383 __be32 __iomem *doorbell;
391 struct list_head list;
393 struct mlx5_rsc_debug *dbg;
396 struct mlx5_core_psv {
408 struct mlx5_core_sig_ctx {
409 struct mlx5_core_psv psv_memory;
410 struct mlx5_core_psv psv_wire;
411 #if (__FreeBSD_version >= 1100000)
412 struct ib_sig_err err_item;
414 bool sig_status_checked;
419 struct mlx5_core_mr {
427 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
428 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
429 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
435 struct mlx5_core_rsc_common {
436 enum mlx5_res_type res;
438 struct completion free;
441 struct mlx5_core_srq {
442 struct mlx5_core_rsc_common common; /* must be first */
446 int max_avail_gather;
448 void (*event)(struct mlx5_core_srq *, int);
450 struct completion free;
453 struct mlx5_eq_table {
454 void __iomem *update_ci;
455 void __iomem *update_arm_ci;
456 struct list_head comp_eqs_list;
457 struct mlx5_eq pages_eq;
458 struct mlx5_eq async_eq;
459 struct mlx5_eq cmd_eq;
460 int num_comp_vectors;
468 void __iomem *bf_map;
473 struct mlx5_core_health {
474 struct mlx5_health_buffer __iomem *health;
475 __be32 __iomem *health_counter;
476 struct timer_list timer;
477 struct list_head list;
482 #define MLX5_CQ_LINEAR_ARRAY_SIZE 1024
484 struct mlx5_cq_linear_array_entry {
486 struct mlx5_core_cq * volatile cq;
489 struct mlx5_cq_table {
490 /* protect radix tree
493 struct radix_tree_root tree;
494 struct mlx5_cq_linear_array_entry linear_array[MLX5_CQ_LINEAR_ARRAY_SIZE];
497 struct mlx5_qp_table {
498 /* protect radix tree
501 struct radix_tree_root tree;
504 struct mlx5_srq_table {
505 /* protect radix tree
508 struct radix_tree_root tree;
511 struct mlx5_mr_table {
512 /* protect radix tree
515 struct radix_tree_root tree;
518 struct mlx5_irq_info {
519 char name[MLX5_MAX_IRQ_NAME];
523 char name[MLX5_MAX_NAME_LEN];
524 struct mlx5_eq_table eq_table;
525 struct msix_entry *msix_arr;
526 struct mlx5_irq_info *irq_info;
527 struct mlx5_uuar_info uuari;
528 MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock);
530 struct io_mapping *bf_mapping;
533 struct workqueue_struct *pg_wq;
534 struct rb_root page_root;
537 s64 pages_per_func[MLX5_MAX_NUMBER_OF_VFS];
538 struct mlx5_core_health health;
540 struct mlx5_srq_table srq_table;
542 /* start: qp staff */
543 struct mlx5_qp_table qp_table;
544 struct dentry *qp_debugfs;
545 struct dentry *eq_debugfs;
546 struct dentry *cq_debugfs;
547 struct dentry *cmdif_debugfs;
550 /* start: cq staff */
551 struct mlx5_cq_table cq_table;
554 /* start: mr staff */
555 struct mlx5_mr_table mr_table;
558 /* start: alloc staff */
561 struct mutex pgdir_mutex;
562 struct list_head pgdir_list;
563 /* end: alloc staff */
564 struct dentry *dbg_root;
566 /* protect mkey key part */
567 spinlock_t mkey_lock;
570 struct list_head dev_list;
571 struct list_head ctx_list;
573 unsigned long pci_dev_data;
576 enum mlx5_device_state {
577 MLX5_DEVICE_STATE_UP,
578 MLX5_DEVICE_STATE_INTERNAL_ERROR,
581 struct mlx5_special_contexts {
585 struct mlx5_core_dev {
586 struct pci_dev *pdev;
587 char board_id[MLX5_BOARD_ID_LEN];
589 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
590 u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
591 u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
592 struct mlx5_init_seg __iomem *iseg;
593 enum mlx5_device_state state;
594 void (*event) (struct mlx5_core_dev *dev,
595 enum mlx5_dev_event event,
596 unsigned long param);
597 struct mlx5_priv priv;
598 struct mlx5_profile *profile;
601 struct mlx5_special_contexts special_contexts;
602 unsigned int module_status[MLX5_MAX_PORTS];
603 u32 num_q_counter_allocated[MLX5_INTERFACE_NUMBER];
607 MLX5_WOL_DISABLE = 0,
608 MLX5_WOL_SECURED_MAGIC = 1 << 1,
609 MLX5_WOL_MAGIC = 1 << 2,
610 MLX5_WOL_ARP = 1 << 3,
611 MLX5_WOL_BROADCAST = 1 << 4,
612 MLX5_WOL_MULTICAST = 1 << 5,
613 MLX5_WOL_UNICAST = 1 << 6,
614 MLX5_WOL_PHY_ACTIVITY = 1 << 7,
620 struct mlx5_db_pgdir *pgdir;
621 struct mlx5_ib_user_db_page *user_page;
627 struct mlx5_net_counters {
632 struct mlx5_ptys_reg {
638 u16 ib_link_width_cap;
641 u16 ib_link_width_admin;
644 u16 ib_link_width_oper;
646 u32 eth_proto_lp_advertise;
649 struct mlx5_pvlc_reg {
656 struct mlx5_pmtu_reg {
663 struct mlx5_vport_counters {
664 struct mlx5_net_counters received_errors;
665 struct mlx5_net_counters transmit_errors;
666 struct mlx5_net_counters received_ib_unicast;
667 struct mlx5_net_counters transmitted_ib_unicast;
668 struct mlx5_net_counters received_ib_multicast;
669 struct mlx5_net_counters transmitted_ib_multicast;
670 struct mlx5_net_counters received_eth_broadcast;
671 struct mlx5_net_counters transmitted_eth_broadcast;
672 struct mlx5_net_counters received_eth_unicast;
673 struct mlx5_net_counters transmitted_eth_unicast;
674 struct mlx5_net_counters received_eth_multicast;
675 struct mlx5_net_counters transmitted_eth_multicast;
679 MLX5_DB_PER_PAGE = MLX5_ADAPTER_PAGE_SIZE / L1_CACHE_BYTES,
682 struct mlx5_core_dct {
683 struct mlx5_core_rsc_common common; /* must be first */
684 void (*event)(struct mlx5_core_dct *, int);
686 struct completion drained;
687 struct mlx5_rsc_debug *dbg;
692 MLX5_COMP_EQ_SIZE = 1024,
696 MLX5_PTYS_IB = 1 << 0,
697 MLX5_PTYS_EN = 1 << 2,
700 struct mlx5_db_pgdir {
701 struct list_head list;
702 DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE);
703 struct mlx5_fw_page *fw_page;
708 typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
710 struct mlx5_cmd_work_ent {
711 struct mlx5_cmd_msg *in;
712 struct mlx5_cmd_msg *out;
716 mlx5_cmd_cbk_t callback;
719 struct completion done;
720 struct mlx5_cmd *cmd;
721 struct work_struct work;
722 struct mlx5_cmd_layout *lay;
739 mlx5_buf_offset(struct mlx5_buf *buf, int offset)
741 return ((char *)buf->direct.buf + offset);
745 extern struct workqueue_struct *mlx5_core_wq;
747 #define STRUCT_FIELD(header, field) \
748 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
749 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
751 static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
753 return pci_get_drvdata(pdev);
756 extern struct dentry *mlx5_debugfs_root;
758 static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
760 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
763 static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
765 return ioread32be(&dev->iseg->fw_rev) >> 16;
768 static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
770 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
773 static inline u16 cmdif_rev_get(struct mlx5_core_dev *dev)
775 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
778 static inline int mlx5_get_gid_table_len(u16 param)
781 printf("M4_CORE_DRV_NAME: WARN: ""gid table length is zero\n");
785 return 8 * (1 << param);
788 static inline void *mlx5_vzalloc(unsigned long size)
792 rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN);
796 static inline void *mlx5_vmalloc(unsigned long size)
800 rtn = kmalloc(size, GFP_KERNEL | __GFP_NOWARN);
806 void mlx5_enter_error_state(struct mlx5_core_dev *dev);
807 int mlx5_cmd_init(struct mlx5_core_dev *dev);
808 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
809 void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
810 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
811 int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr);
812 int mlx5_cmd_status_to_err_v2(void *ptr);
813 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
814 enum mlx5_cap_mode cap_mode);
815 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
817 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
818 void *out, int out_size, mlx5_cmd_cbk_t callback,
820 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
821 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
822 int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
823 int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari);
824 int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
825 void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar);
826 void mlx5_health_cleanup(void);
827 void __init mlx5_health_init(void);
828 void mlx5_start_health_poll(struct mlx5_core_dev *dev);
829 void mlx5_stop_health_poll(struct mlx5_core_dev *dev);
831 #define mlx5_buf_alloc_node(dev, size, direct, buf, node) \
832 mlx5_buf_alloc(dev, size, direct, buf)
833 int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, int max_direct,
834 struct mlx5_buf *buf);
835 void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf);
836 int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
837 struct mlx5_create_srq_mbox_in *in, int inlen,
839 int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq);
840 int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
841 struct mlx5_query_srq_mbox_out *out);
842 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
843 int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq,
844 u16 lwm, int is_srq);
845 void mlx5_init_mr_table(struct mlx5_core_dev *dev);
846 void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev);
847 int mlx5_core_create_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
848 struct mlx5_create_mkey_mbox_in *in, int inlen,
849 mlx5_cmd_cbk_t callback, void *context,
850 struct mlx5_create_mkey_mbox_out *out);
851 int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr);
852 int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
853 struct mlx5_query_mkey_mbox_out *out, int outlen);
854 int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr,
856 int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
857 int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
858 int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, void *inb, void *outb,
860 void mlx5_fwp_flush(struct mlx5_fw_page *fwp);
861 void mlx5_fwp_invalidate(struct mlx5_fw_page *fwp);
862 struct mlx5_fw_page *mlx5_fwp_alloc(struct mlx5_core_dev *dev, gfp_t flags, unsigned num);
863 void mlx5_fwp_free(struct mlx5_fw_page *fwp);
864 u64 mlx5_fwp_get_dma(struct mlx5_fw_page *fwp, size_t offset);
865 void *mlx5_fwp_get_virt(struct mlx5_fw_page *fwp, size_t offset);
866 void mlx5_pagealloc_init(struct mlx5_core_dev *dev);
867 void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
868 int mlx5_pagealloc_start(struct mlx5_core_dev *dev);
869 void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
870 void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
872 int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
873 int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
874 s64 mlx5_wait_for_reclaim_vfs_pages(struct mlx5_core_dev *dev);
875 void mlx5_register_debugfs(void);
876 void mlx5_unregister_debugfs(void);
877 int mlx5_eq_init(struct mlx5_core_dev *dev);
878 void mlx5_eq_cleanup(struct mlx5_core_dev *dev);
879 void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas);
880 void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn);
881 void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type);
882 void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type);
883 struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn);
884 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u32 vector);
885 void mlx5_trigger_cmd_completions(struct mlx5_core_dev *dev);
886 void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type);
887 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
888 int nent, u64 mask, const char *name, struct mlx5_uar *uar);
889 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
890 int mlx5_start_eqs(struct mlx5_core_dev *dev);
891 int mlx5_stop_eqs(struct mlx5_core_dev *dev);
892 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn);
893 int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
894 int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
895 int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable,
898 int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
899 void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
900 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
901 int size_in, void *data_out, int size_out,
902 u16 reg_num, int arg, int write);
904 void mlx5_toggle_port_link(struct mlx5_core_dev *dev);
905 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);
906 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
907 int ptys_size, int proto_mask);
908 int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev,
909 u32 *proto_cap, int proto_mask);
910 int mlx5_query_port_autoneg(struct mlx5_core_dev *dev, int proto_mask,
911 u8 *an_disable_cap, u8 *an_disable_status);
912 int mlx5_set_port_autoneg(struct mlx5_core_dev *dev, bool disable,
913 u32 eth_proto_admin, int proto_mask);
914 int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
915 u32 *proto_admin, int proto_mask);
916 int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin,
918 int mlx5_set_port_status(struct mlx5_core_dev *dev,
919 enum mlx5_port_status status);
920 int mlx5_query_port_status(struct mlx5_core_dev *dev, u8 *status);
921 int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
922 enum mlx5_port_status *status);
923 int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 port,
924 u32 rx_pause, u32 tx_pause);
925 int mlx5_query_port_pause(struct mlx5_core_dev *dev, u32 port,
926 u32 *rx_pause, u32 *tx_pause);
927 int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx);
928 int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx);
930 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu);
931 int mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu);
932 int mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu);
934 unsigned int mlx5_query_module_status(struct mlx5_core_dev *dev, int module_num);
935 int mlx5_query_module_num(struct mlx5_core_dev *dev, int *module_num);
936 int mlx5_query_eeprom(struct mlx5_core_dev *dev, int i2c_addr, int page_num,
937 int device_addr, int size, int module_num, u32 *data,
940 int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
941 void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq);
942 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
943 struct mlx5_query_eq_mbox_out *out, int outlen);
944 int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev);
945 void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev);
946 int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev);
947 void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev);
948 int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
949 int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
951 void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
953 const char *mlx5_command_str(int command);
954 int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
955 void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
956 int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
957 int npsvs, u32 *sig_index);
958 int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
959 void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
960 u8 mlx5_is_wol_supported(struct mlx5_core_dev *dev);
961 int mlx5_set_wol(struct mlx5_core_dev *dev, u8 wol_mode);
962 int mlx5_query_wol(struct mlx5_core_dev *dev, u8 *wol_mode);
963 int mlx5_core_access_pvlc(struct mlx5_core_dev *dev,
964 struct mlx5_pvlc_reg *pvlc, int write);
965 int mlx5_core_access_ptys(struct mlx5_core_dev *dev,
966 struct mlx5_ptys_reg *ptys, int write);
967 int mlx5_core_access_pmtu(struct mlx5_core_dev *dev,
968 struct mlx5_pmtu_reg *pmtu, int write);
969 int mlx5_vxlan_udp_port_add(struct mlx5_core_dev *dev, u16 port);
970 int mlx5_vxlan_udp_port_delete(struct mlx5_core_dev *dev, u16 port);
971 int mlx5_query_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
972 int priority, int *is_enable);
973 int mlx5_modify_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
974 int priority, int enable);
975 int mlx5_query_port_cong_params(struct mlx5_core_dev *mdev, int protocol,
976 void *out, int out_size);
977 int mlx5_modify_port_cong_params(struct mlx5_core_dev *mdev,
978 void *in, int in_size);
979 int mlx5_query_port_cong_statistics(struct mlx5_core_dev *mdev, int clear,
980 void *out, int out_size);
981 int mlx5_set_diagnostic_params(struct mlx5_core_dev *mdev, void *in,
983 int mlx5_query_diagnostic_counters(struct mlx5_core_dev *mdev,
984 u8 num_of_samples, u16 sample_index,
985 void *out, int out_size);
986 static inline u32 mlx5_mkey_to_idx(u32 mkey)
991 static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
993 return mkey_idx << 8;
996 static inline u8 mlx5_mkey_variant(u32 mkey)
1002 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
1003 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
1007 MAX_MR_CACHE_ENTRIES = 15,
1010 struct mlx5_interface {
1011 void * (*add)(struct mlx5_core_dev *dev);
1012 void (*remove)(struct mlx5_core_dev *dev, void *context);
1013 void (*event)(struct mlx5_core_dev *dev, void *context,
1014 enum mlx5_dev_event event, unsigned long param);
1015 void * (*get_dev)(void *context);
1017 struct list_head list;
1020 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol);
1021 int mlx5_register_interface(struct mlx5_interface *intf);
1022 void mlx5_unregister_interface(struct mlx5_interface *intf);
1024 struct mlx5_profile {
1030 } mr_cache[MAX_MR_CACHE_ENTRIES];
1034 MLX5_PCI_DEV_IS_VF = 1 << 0,
1037 static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev)
1039 return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF);
1042 #define MLX5_EEPROM_MAX_BYTES 32
1043 #define MLX5_EEPROM_IDENTIFIER_BYTE_MASK 0x000000ff
1044 #define MLX5_EEPROM_REVISION_ID_BYTE_MASK 0x0000ff00
1045 #define MLX5_EEPROM_PAGE_3_VALID_BIT_MASK 0x00040000
1046 #endif /* MLX5_DRIVER_H */