sys/dev/mlx5/mlx5_core/mlx5_cmd.c

   1 /*-
   2  * Copyright (c) 2013-2015, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include <linux/module.h>
  29 #include <linux/errno.h>
  30 #include <linux/pci.h>
  31 #include <linux/dma-mapping.h>
  32 #include <linux/slab.h>
  33 #include <linux/delay.h>
  34 #include <linux/random.h>
  35 #include <linux/io-mapping.h>
  36 #include <linux/hardirq.h>
  37 #include <linux/ktime.h>
  38 #include <dev/mlx5/driver.h>
  39
  40 #include "mlx5_core.h"
  41
  42 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size);
  43 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
  44                               struct mlx5_cmd_msg *msg);
  45 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg);
  46
  47 enum {
  48         CMD_IF_REV = 5,
  49 };
  50
  51 enum {
  52         CMD_MODE_POLLING,
  53         CMD_MODE_EVENTS
  54 };
  55
  56 enum {
  57         NUM_LONG_LISTS    = 2,
  58         NUM_MED_LISTS     = 64,
  59         LONG_LIST_SIZE    = (2ULL * 1024 * 1024 * 1024 / PAGE_SIZE) * 8 + 16 +
  60                                 MLX5_CMD_DATA_BLOCK_SIZE,
  61         MED_LIST_SIZE     = 16 + MLX5_CMD_DATA_BLOCK_SIZE,
  62 };
  63
  64 enum {
  65         MLX5_CMD_DELIVERY_STAT_OK                       = 0x0,
  66         MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR               = 0x1,
  67         MLX5_CMD_DELIVERY_STAT_TOK_ERR                  = 0x2,
  68         MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR          = 0x3,
  69         MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR        = 0x4,
  70         MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR         = 0x5,
  71         MLX5_CMD_DELIVERY_STAT_FW_ERR                   = 0x6,
  72         MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR            = 0x7,
  73         MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR           = 0x8,
  74         MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR      = 0x9,
  75         MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR            = 0x10,
  76 };
  77
  78 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
  79                                            struct mlx5_cmd_msg *in,
  80                                            struct mlx5_cmd_msg *out,
  81                                            void *uout, int uout_size,
  82                                            mlx5_cmd_cbk_t cbk,
  83                                            void *context, int page_queue)
  84 {
  85         gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
  86         struct mlx5_cmd_work_ent *ent;
  87
  88         ent = kzalloc(sizeof(*ent), alloc_flags);
  89         if (!ent)
  90                 return ERR_PTR(-ENOMEM);
  91
  92         ent->in         = in;
  93         ent->out        = out;
  94         ent->uout       = uout;
  95         ent->uout_size  = uout_size;
  96         ent->callback   = cbk;
  97         ent->context    = context;
  98         ent->cmd        = cmd;
  99         ent->page_queue = page_queue;
 100
 101         return ent;
 102 }
 103
 104 static u8 alloc_token(struct mlx5_cmd *cmd)
 105 {
 106         u8 token;
 107
 108         spin_lock(&cmd->token_lock);
 109         cmd->token++;
 110         if (cmd->token == 0)
 111                 cmd->token++;
 112         token = cmd->token;
 113         spin_unlock(&cmd->token_lock);
 114
 115         return token;
 116 }
 117
 118 static int alloc_ent(struct mlx5_cmd_work_ent *ent)
 119 {
 120         unsigned long flags;
 121         struct mlx5_cmd *cmd = ent->cmd;
 122         struct mlx5_core_dev *dev =
 123                 container_of(cmd, struct mlx5_core_dev, cmd);
 124         int ret = cmd->max_reg_cmds;
 125
 126         spin_lock_irqsave(&cmd->alloc_lock, flags);
 127         if (!ent->page_queue) {
 128                 ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
 129                 if (ret >= cmd->max_reg_cmds)
 130                         ret = -1;
 131         }
 132
 133         if (dev->state != MLX5_DEVICE_STATE_UP)
 134                 ret = -1;
 135
 136         if (ret != -1) {
 137                 ent->busy = 1;
 138                 ent->idx = ret;
 139                 clear_bit(ent->idx, &cmd->bitmask);
 140                 cmd->ent_arr[ent->idx] = ent;
 141         }
 142         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 143
 144         return ret;
 145 }
 146
 147 static void free_ent(struct mlx5_cmd *cmd, int idx)
 148 {
 149         unsigned long flags;
 150
 151         spin_lock_irqsave(&cmd->alloc_lock, flags);
 152         set_bit(idx, &cmd->bitmask);
 153         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 154 }
 155
 156 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
 157 {
 158         return cmd->cmd_buf + (idx << cmd->log_stride);
 159 }
 160
 161 static u8 xor8_buf(void *buf, int len)
 162 {
 163         u8 *ptr = buf;
 164         u8 sum = 0;
 165         int i;
 166
 167         for (i = 0; i < len; i++)
 168                 sum ^= ptr[i];
 169
 170         return sum;
 171 }
 172
 173 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
 174 {
 175         if (xor8_buf(block->rsvd0, sizeof(*block) - sizeof(block->data) - 1) != 0xff)
 176                 return -EINVAL;
 177
 178         if (xor8_buf(block, sizeof(*block)) != 0xff)
 179                 return -EINVAL;
 180
 181         return 0;
 182 }
 183
 184 static void calc_block_sig(struct mlx5_cmd_prot_block *block, u8 token,
 185                            int csum)
 186 {
 187         block->token = token;
 188         if (csum) {
 189                 block->ctrl_sig = ~xor8_buf(block->rsvd0, sizeof(*block) -
 190                                             sizeof(block->data) - 2);
 191                 block->sig = ~xor8_buf(block, sizeof(*block) - 1);
 192         }
 193 }
 194
 195 static void calc_chain_sig(struct mlx5_cmd_msg *msg, u8 token, int csum)
 196 {
 197         struct mlx5_cmd_mailbox *next = msg->next;
 198
 199         while (next) {
 200                 calc_block_sig(next->buf, token, csum);
 201                 next = next->next;
 202         }
 203 }
 204
 205 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
 206 {
 207         ent->lay->sig = ~xor8_buf(ent->lay, sizeof(*ent->lay));
 208         calc_chain_sig(ent->in, ent->token, csum);
 209         calc_chain_sig(ent->out, ent->token, csum);
 210 }
 211
 212 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
 213 {
 214         struct mlx5_core_dev *dev = container_of(ent->cmd,
 215                                                  struct mlx5_core_dev, cmd);
 216         int poll_end = jiffies +
 217                                 msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
 218         u8 own;
 219
 220         do {
 221                 own = ent->lay->status_own;
 222                 if (!(own & CMD_OWNER_HW) ||
 223                     dev->state != MLX5_DEVICE_STATE_UP) {
 224                         ent->ret = 0;
 225                         return;
 226                 }
 227                 usleep_range(5000, 10000);
 228         } while (time_before(jiffies, poll_end));
 229
 230         ent->ret = -ETIMEDOUT;
 231 }
 232
 233 static void free_cmd(struct mlx5_cmd_work_ent *ent)
 234 {
 235         kfree(ent);
 236 }
 237
 238
 239 static int verify_signature(struct mlx5_cmd_work_ent *ent)
 240 {
 241         struct mlx5_cmd_mailbox *next = ent->out->next;
 242         int err;
 243         u8 sig;
 244
 245         sig = xor8_buf(ent->lay, sizeof(*ent->lay));
 246         if (sig != 0xff)
 247                 return -EINVAL;
 248
 249         while (next) {
 250                 err = verify_block_sig(next->buf);
 251                 if (err)
 252                         return err;
 253
 254                 next = next->next;
 255         }
 256
 257         return 0;
 258 }
 259
 260 static void dump_buf(void *buf, int size, int data_only, int offset)
 261 {
 262         __be32 *p = buf;
 263         int i;
 264
 265         for (i = 0; i < size; i += 16) {
 266                 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
 267                          be32_to_cpu(p[1]), be32_to_cpu(p[2]),
 268                          be32_to_cpu(p[3]));
 269                 p += 4;
 270                 offset += 16;
 271         }
 272         if (!data_only)
 273                 pr_debug("\n");
 274 }
 275
 276 const char *mlx5_command_str(int command)
 277 {
 278         switch (command) {
 279         case MLX5_CMD_OP_QUERY_HCA_CAP:
 280                 return "QUERY_HCA_CAP";
 281
 282         case MLX5_CMD_OP_SET_HCA_CAP:
 283                 return "SET_HCA_CAP";
 284
 285         case MLX5_CMD_OP_QUERY_ADAPTER:
 286                 return "QUERY_ADAPTER";
 287
 288         case MLX5_CMD_OP_INIT_HCA:
 289                 return "INIT_HCA";
 290
 291         case MLX5_CMD_OP_TEARDOWN_HCA:
 292                 return "TEARDOWN_HCA";
 293
 294         case MLX5_CMD_OP_ENABLE_HCA:
 295                 return "MLX5_CMD_OP_ENABLE_HCA";
 296
 297         case MLX5_CMD_OP_DISABLE_HCA:
 298                 return "MLX5_CMD_OP_DISABLE_HCA";
 299
 300         case MLX5_CMD_OP_QUERY_PAGES:
 301                 return "QUERY_PAGES";
 302
 303         case MLX5_CMD_OP_MANAGE_PAGES:
 304                 return "MANAGE_PAGES";
 305
 306         case MLX5_CMD_OP_QUERY_ISSI:
 307                 return "QUERY_ISSI";
 308
 309         case MLX5_CMD_OP_SET_ISSI:
 310                 return "SET_ISSI";
 311
 312         case MLX5_CMD_OP_CREATE_MKEY:
 313                 return "CREATE_MKEY";
 314
 315         case MLX5_CMD_OP_QUERY_MKEY:
 316                 return "QUERY_MKEY";
 317
 318         case MLX5_CMD_OP_DESTROY_MKEY:
 319                 return "DESTROY_MKEY";
 320
 321         case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
 322                 return "QUERY_SPECIAL_CONTEXTS";
 323
 324         case MLX5_CMD_OP_PAGE_FAULT_RESUME:
 325                 return "PAGE_FAULT_RESUME";
 326
 327         case MLX5_CMD_OP_CREATE_EQ:
 328                 return "CREATE_EQ";
 329
 330         case MLX5_CMD_OP_DESTROY_EQ:
 331                 return "DESTROY_EQ";
 332
 333         case MLX5_CMD_OP_QUERY_EQ:
 334                 return "QUERY_EQ";
 335
 336         case MLX5_CMD_OP_GEN_EQE:
 337                 return "GEN_EQE";
 338
 339         case MLX5_CMD_OP_CREATE_CQ:
 340                 return "CREATE_CQ";
 341
 342         case MLX5_CMD_OP_DESTROY_CQ:
 343                 return "DESTROY_CQ";
 344
 345         case MLX5_CMD_OP_QUERY_CQ:
 346                 return "QUERY_CQ";
 347
 348         case MLX5_CMD_OP_MODIFY_CQ:
 349                 return "MODIFY_CQ";
 350
 351         case MLX5_CMD_OP_CREATE_QP:
 352                 return "CREATE_QP";
 353
 354         case MLX5_CMD_OP_DESTROY_QP:
 355                 return "DESTROY_QP";
 356
 357         case MLX5_CMD_OP_RST2INIT_QP:
 358                 return "RST2INIT_QP";
 359
 360         case MLX5_CMD_OP_INIT2RTR_QP:
 361                 return "INIT2RTR_QP";
 362
 363         case MLX5_CMD_OP_RTR2RTS_QP:
 364                 return "RTR2RTS_QP";
 365
 366         case MLX5_CMD_OP_RTS2RTS_QP:
 367                 return "RTS2RTS_QP";
 368
 369         case MLX5_CMD_OP_SQERR2RTS_QP:
 370                 return "SQERR2RTS_QP";
 371
 372         case MLX5_CMD_OP_2ERR_QP:
 373                 return "2ERR_QP";
 374
 375         case MLX5_CMD_OP_2RST_QP:
 376                 return "2RST_QP";
 377
 378         case MLX5_CMD_OP_QUERY_QP:
 379                 return "QUERY_QP";
 380
 381         case MLX5_CMD_OP_SQD_RTS_QP:
 382                 return "SQD_RTS_QP";
 383
 384         case MLX5_CMD_OP_MAD_IFC:
 385                 return "MAD_IFC";
 386
 387         case MLX5_CMD_OP_INIT2INIT_QP:
 388                 return "INIT2INIT_QP";
 389
 390         case MLX5_CMD_OP_CREATE_PSV:
 391                 return "CREATE_PSV";
 392
 393         case MLX5_CMD_OP_DESTROY_PSV:
 394                 return "DESTROY_PSV";
 395
 396         case MLX5_CMD_OP_CREATE_SRQ:
 397                 return "CREATE_SRQ";
 398
 399         case MLX5_CMD_OP_DESTROY_SRQ:
 400                 return "DESTROY_SRQ";
 401
 402         case MLX5_CMD_OP_QUERY_SRQ:
 403                 return "QUERY_SRQ";
 404
 405         case MLX5_CMD_OP_ARM_RQ:
 406                 return "ARM_RQ";
 407
 408         case MLX5_CMD_OP_CREATE_XRC_SRQ:
 409                 return "CREATE_XRC_SRQ";
 410
 411         case MLX5_CMD_OP_DESTROY_XRC_SRQ:
 412                 return "DESTROY_XRC_SRQ";
 413
 414         case MLX5_CMD_OP_QUERY_XRC_SRQ:
 415                 return "QUERY_XRC_SRQ";
 416
 417         case MLX5_CMD_OP_ARM_XRC_SRQ:
 418                 return "ARM_XRC_SRQ";
 419
 420         case MLX5_CMD_OP_CREATE_DCT:
 421                 return "CREATE_DCT";
 422
 423         case MLX5_CMD_OP_SET_DC_CNAK_TRACE:
 424                 return "SET_DC_CNAK_TRACE";
 425
 426         case MLX5_CMD_OP_DESTROY_DCT:
 427                 return "DESTROY_DCT";
 428
 429         case MLX5_CMD_OP_DRAIN_DCT:
 430                 return "DRAIN_DCT";
 431
 432         case MLX5_CMD_OP_QUERY_DCT:
 433                 return "QUERY_DCT";
 434
 435         case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
 436                 return "ARM_DCT_FOR_KEY_VIOLATION";
 437
 438         case MLX5_CMD_OP_QUERY_VPORT_STATE:
 439                 return "QUERY_VPORT_STATE";
 440
 441         case MLX5_CMD_OP_MODIFY_VPORT_STATE:
 442                 return "MODIFY_VPORT_STATE";
 443
 444         case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
 445                 return "QUERY_ESW_VPORT_CONTEXT";
 446
 447         case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
 448                 return "MODIFY_ESW_VPORT_CONTEXT";
 449
 450         case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
 451                 return "QUERY_NIC_VPORT_CONTEXT";
 452
 453         case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
 454                 return "MODIFY_NIC_VPORT_CONTEXT";
 455
 456         case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
 457                 return "QUERY_ROCE_ADDRESS";
 458
 459         case MLX5_CMD_OP_SET_ROCE_ADDRESS:
 460                 return "SET_ROCE_ADDRESS";
 461
 462         case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
 463                 return "QUERY_HCA_VPORT_CONTEXT";
 464
 465         case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
 466                 return "MODIFY_HCA_VPORT_CONTEXT";
 467
 468         case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
 469                 return "QUERY_HCA_VPORT_GID";
 470
 471         case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
 472                 return "QUERY_HCA_VPORT_PKEY";
 473
 474         case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
 475                 return "QUERY_VPORT_COUNTER";
 476
 477         case MLX5_CMD_OP_SET_WOL_ROL:
 478                 return "SET_WOL_ROL";
 479
 480         case MLX5_CMD_OP_QUERY_WOL_ROL:
 481                 return "QUERY_WOL_ROL";
 482
 483         case MLX5_CMD_OP_ALLOC_Q_COUNTER:
 484                 return "ALLOC_Q_COUNTER";
 485
 486         case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
 487                 return "DEALLOC_Q_COUNTER";
 488
 489         case MLX5_CMD_OP_QUERY_Q_COUNTER:
 490                 return "QUERY_Q_COUNTER";
 491
 492         case MLX5_CMD_OP_ALLOC_PD:
 493                 return "ALLOC_PD";
 494
 495         case MLX5_CMD_OP_DEALLOC_PD:
 496                 return "DEALLOC_PD";
 497
 498         case MLX5_CMD_OP_ALLOC_UAR:
 499                 return "ALLOC_UAR";
 500
 501         case MLX5_CMD_OP_DEALLOC_UAR:
 502                 return "DEALLOC_UAR";
 503
 504         case MLX5_CMD_OP_CONFIG_INT_MODERATION:
 505                 return "CONFIG_INT_MODERATION";
 506
 507         case MLX5_CMD_OP_ATTACH_TO_MCG:
 508                 return "ATTACH_TO_MCG";
 509
 510         case MLX5_CMD_OP_DETACH_FROM_MCG:
 511                 return "DETACH_FROM_MCG";
 512
 513         case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
 514                 return "GET_DROPPED_PACKET_LOG";
 515
 516         case MLX5_CMD_OP_QUERY_MAD_DEMUX:
 517                 return "QUERY_MAD_DEMUX";
 518
 519         case MLX5_CMD_OP_SET_MAD_DEMUX:
 520                 return "SET_MAD_DEMUX";
 521
 522         case MLX5_CMD_OP_NOP:
 523                 return "NOP";
 524
 525         case MLX5_CMD_OP_ALLOC_XRCD:
 526                 return "ALLOC_XRCD";
 527
 528         case MLX5_CMD_OP_DEALLOC_XRCD:
 529                 return "DEALLOC_XRCD";
 530
 531         case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
 532                 return "ALLOC_TRANSPORT_DOMAIN";
 533
 534         case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
 535                 return "DEALLOC_TRANSPORT_DOMAIN";
 536
 537         case MLX5_CMD_OP_QUERY_CONG_STATUS:
 538                 return "QUERY_CONG_STATUS";
 539
 540         case MLX5_CMD_OP_MODIFY_CONG_STATUS:
 541                 return "MODIFY_CONG_STATUS";
 542
 543         case MLX5_CMD_OP_QUERY_CONG_PARAMS:
 544                 return "QUERY_CONG_PARAMS";
 545
 546         case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
 547                 return "MODIFY_CONG_PARAMS";
 548
 549         case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
 550                 return "QUERY_CONG_STATISTICS";
 551
 552         case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
 553                 return "ADD_VXLAN_UDP_DPORT";
 554
 555         case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
 556                 return "DELETE_VXLAN_UDP_DPORT";
 557
 558         case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
 559                 return "SET_L2_TABLE_ENTRY";
 560
 561         case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
 562                 return "QUERY_L2_TABLE_ENTRY";
 563
 564         case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
 565                 return "DELETE_L2_TABLE_ENTRY";
 566
 567         case MLX5_CMD_OP_CREATE_RMP:
 568                 return "CREATE_RMP";
 569
 570         case MLX5_CMD_OP_MODIFY_RMP:
 571                 return "MODIFY_RMP";
 572
 573         case MLX5_CMD_OP_DESTROY_RMP:
 574                 return "DESTROY_RMP";
 575
 576         case MLX5_CMD_OP_QUERY_RMP:
 577                 return "QUERY_RMP";
 578
 579         case MLX5_CMD_OP_CREATE_RQT:
 580                 return "CREATE_RQT";
 581
 582         case MLX5_CMD_OP_MODIFY_RQT:
 583                 return "MODIFY_RQT";
 584
 585         case MLX5_CMD_OP_DESTROY_RQT:
 586                 return "DESTROY_RQT";
 587
 588         case MLX5_CMD_OP_QUERY_RQT:
 589                 return "QUERY_RQT";
 590
 591         case MLX5_CMD_OP_ACCESS_REG:
 592                 return "MLX5_CMD_OP_ACCESS_REG";
 593
 594         case MLX5_CMD_OP_CREATE_SQ:
 595                 return "CREATE_SQ";
 596
 597         case MLX5_CMD_OP_MODIFY_SQ:
 598                 return "MODIFY_SQ";
 599
 600         case MLX5_CMD_OP_DESTROY_SQ:
 601                 return "DESTROY_SQ";
 602
 603         case MLX5_CMD_OP_QUERY_SQ:
 604                 return "QUERY_SQ";
 605
 606         case MLX5_CMD_OP_CREATE_RQ:
 607                 return "CREATE_RQ";
 608
 609         case MLX5_CMD_OP_MODIFY_RQ:
 610                 return "MODIFY_RQ";
 611
 612         case MLX5_CMD_OP_DESTROY_RQ:
 613                 return "DESTROY_RQ";
 614
 615         case MLX5_CMD_OP_QUERY_RQ:
 616                 return "QUERY_RQ";
 617
 618         case MLX5_CMD_OP_CREATE_TIR:
 619                 return "CREATE_TIR";
 620
 621         case MLX5_CMD_OP_MODIFY_TIR:
 622                 return "MODIFY_TIR";
 623
 624         case MLX5_CMD_OP_DESTROY_TIR:
 625                 return "DESTROY_TIR";
 626
 627         case MLX5_CMD_OP_QUERY_TIR:
 628                 return "QUERY_TIR";
 629
 630         case MLX5_CMD_OP_CREATE_TIS:
 631                 return "CREATE_TIS";
 632
 633         case MLX5_CMD_OP_MODIFY_TIS:
 634                 return "MODIFY_TIS";
 635
 636         case MLX5_CMD_OP_DESTROY_TIS:
 637                 return "DESTROY_TIS";
 638
 639         case MLX5_CMD_OP_QUERY_TIS:
 640                 return "QUERY_TIS";
 641
 642         case MLX5_CMD_OP_CREATE_FLOW_TABLE:
 643                 return "CREATE_FLOW_TABLE";
 644
 645         case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
 646                 return "DESTROY_FLOW_TABLE";
 647
 648         case MLX5_CMD_OP_QUERY_FLOW_TABLE:
 649                 return "QUERY_FLOW_TABLE";
 650
 651         case MLX5_CMD_OP_CREATE_FLOW_GROUP:
 652                 return "CREATE_FLOW_GROUP";
 653
 654         case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
 655                 return "DESTROY_FLOW_GROUP";
 656
 657         case MLX5_CMD_OP_QUERY_FLOW_GROUP:
 658                 return "QUERY_FLOW_GROUP";
 659
 660         case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
 661                 return "SET_FLOW_TABLE_ENTRY";
 662
 663         case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
 664                 return "QUERY_FLOW_TABLE_ENTRY";
 665
 666         case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
 667                 return "DELETE_FLOW_TABLE_ENTRY";
 668
 669         case MLX5_CMD_OP_SET_DIAGNOSTICS:
 670                 return "MLX5_CMD_OP_SET_DIAGNOSTICS";
 671
 672         case MLX5_CMD_OP_QUERY_DIAGNOSTICS:
 673                 return "MLX5_CMD_OP_QUERY_DIAGNOSTICS";
 674
 675         default: return "unknown command opcode";
 676         }
 677 }
 678
 679 static void dump_command(struct mlx5_core_dev *dev,
 680                          struct mlx5_cmd_work_ent *ent, int input)
 681 {
 682         u16 op = be16_to_cpu(((struct mlx5_inbox_hdr *)(ent->lay->in))->opcode);
 683         struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
 684         struct mlx5_cmd_mailbox *next = msg->next;
 685         int data_only;
 686         u32 offset = 0;
 687         int dump_len;
 688
 689         data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
 690
 691         if (data_only)
 692                 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
 693                                    "dump command data %s(0x%x) %s\n",
 694                                    mlx5_command_str(op), op,
 695                                    input ? "INPUT" : "OUTPUT");
 696         else
 697                 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
 698                               mlx5_command_str(op), op,
 699                               input ? "INPUT" : "OUTPUT");
 700
 701         if (data_only) {
 702                 if (input) {
 703                         dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
 704                         offset += sizeof(ent->lay->in);
 705                 } else {
 706                         dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
 707                         offset += sizeof(ent->lay->out);
 708                 }
 709         } else {
 710                 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
 711                 offset += sizeof(*ent->lay);
 712         }
 713
 714         while (next && offset < msg->len) {
 715                 if (data_only) {
 716                         dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
 717                         dump_buf(next->buf, dump_len, 1, offset);
 718                         offset += MLX5_CMD_DATA_BLOCK_SIZE;
 719                 } else {
 720                         mlx5_core_dbg(dev, "command block:\n");
 721                         dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
 722                         offset += sizeof(struct mlx5_cmd_prot_block);
 723                 }
 724                 next = next->next;
 725         }
 726
 727         if (data_only)
 728                 pr_debug("\n");
 729 }
 730
 731 static int set_internal_err_outbox(struct mlx5_core_dev *dev, u16 opcode,
 732                                    struct mlx5_outbox_hdr *hdr)
 733 {
 734         hdr->status = 0;
 735         hdr->syndrome = 0;
 736
 737         switch (opcode) {
 738         case MLX5_CMD_OP_TEARDOWN_HCA:
 739         case MLX5_CMD_OP_DISABLE_HCA:
 740         case MLX5_CMD_OP_MANAGE_PAGES:
 741         case MLX5_CMD_OP_DESTROY_MKEY:
 742         case MLX5_CMD_OP_DESTROY_EQ:
 743         case MLX5_CMD_OP_DESTROY_CQ:
 744         case MLX5_CMD_OP_DESTROY_QP:
 745         case MLX5_CMD_OP_DESTROY_PSV:
 746         case MLX5_CMD_OP_DESTROY_SRQ:
 747         case MLX5_CMD_OP_DESTROY_XRC_SRQ:
 748         case MLX5_CMD_OP_DESTROY_DCT:
 749         case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
 750         case MLX5_CMD_OP_DEALLOC_PD:
 751         case MLX5_CMD_OP_DEALLOC_UAR:
 752         case MLX5_CMD_OP_DETACH_FROM_MCG:
 753         case MLX5_CMD_OP_DEALLOC_XRCD:
 754         case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
 755         case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
 756         case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
 757         case MLX5_CMD_OP_DESTROY_LAG:
 758         case MLX5_CMD_OP_DESTROY_VPORT_LAG:
 759         case MLX5_CMD_OP_DESTROY_TIR:
 760         case MLX5_CMD_OP_DESTROY_SQ:
 761         case MLX5_CMD_OP_DESTROY_RQ:
 762         case MLX5_CMD_OP_DESTROY_RMP:
 763         case MLX5_CMD_OP_DESTROY_TIS:
 764         case MLX5_CMD_OP_DESTROY_RQT:
 765         case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
 766         case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
 767         case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
 768         case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:
 769         case MLX5_CMD_OP_2ERR_QP:
 770         case MLX5_CMD_OP_2RST_QP:
 771         case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
 772         case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
 773         case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
 774         case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT:
 775         case MLX5_CMD_OP_DEALLOC_ENCAP_HEADER:
 776         case MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT:
 777         case MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT:
 778         case MLX5_CMD_OP_MODIFY_VPORT_STATE:
 779         case MLX5_CMD_OP_MODIFY_SQ:
 780         case MLX5_CMD_OP_MODIFY_RQ:
 781         case MLX5_CMD_OP_MODIFY_TIS:
 782         case MLX5_CMD_OP_MODIFY_LAG:
 783         case MLX5_CMD_OP_MODIFY_TIR:
 784         case MLX5_CMD_OP_MODIFY_RMP:
 785         case MLX5_CMD_OP_MODIFY_RQT:
 786         case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT:
 787         case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
 788         case MLX5_CMD_OP_MODIFY_CONG_STATUS:
 789         case MLX5_CMD_OP_MODIFY_CQ:
 790         case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
 791         case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
 792         case MLX5_CMD_OP_MODIFY_OTHER_HCA_CAP:
 793         case MLX5_CMD_OP_ACCESS_REG:
 794         case MLX5_CMD_OP_DRAIN_DCT:
 795                 return 0;
 796
 797         case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
 798         case MLX5_CMD_OP_ALLOC_ENCAP_HEADER:
 799         case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
 800         case MLX5_CMD_OP_ALLOC_PD:
 801         case MLX5_CMD_OP_ALLOC_Q_COUNTER:
 802         case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
 803         case MLX5_CMD_OP_ALLOC_UAR:
 804         case MLX5_CMD_OP_ALLOC_XRCD:
 805         case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
 806         case MLX5_CMD_OP_ARM_RQ:
 807         case MLX5_CMD_OP_ARM_XRC_SRQ:
 808         case MLX5_CMD_OP_ATTACH_TO_MCG:
 809         case MLX5_CMD_OP_CONFIG_INT_MODERATION:
 810         case MLX5_CMD_OP_CREATE_CQ:
 811         case MLX5_CMD_OP_CREATE_DCT:
 812         case MLX5_CMD_OP_CREATE_EQ:
 813         case MLX5_CMD_OP_CREATE_FLOW_GROUP:
 814         case MLX5_CMD_OP_CREATE_FLOW_TABLE:
 815         case MLX5_CMD_OP_CREATE_LAG:
 816         case MLX5_CMD_OP_CREATE_MKEY:
 817         case MLX5_CMD_OP_CREATE_PSV:
 818         case MLX5_CMD_OP_CREATE_QOS_PARA_VPORT:
 819         case MLX5_CMD_OP_CREATE_QP:
 820         case MLX5_CMD_OP_CREATE_RMP:
 821         case MLX5_CMD_OP_CREATE_RQ:
 822         case MLX5_CMD_OP_CREATE_RQT:
 823         case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:
 824         case MLX5_CMD_OP_CREATE_SQ:
 825         case MLX5_CMD_OP_CREATE_SRQ:
 826         case MLX5_CMD_OP_CREATE_TIR:
 827         case MLX5_CMD_OP_CREATE_TIS:
 828         case MLX5_CMD_OP_CREATE_VPORT_LAG:
 829         case MLX5_CMD_OP_CREATE_XRC_SRQ:
 830         case MLX5_CMD_OP_ENABLE_HCA:
 831         case MLX5_CMD_OP_GEN_EQE:
 832         case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
 833         case MLX5_CMD_OP_INIT2INIT_QP:
 834         case MLX5_CMD_OP_INIT2RTR_QP:
 835         case MLX5_CMD_OP_INIT_HCA:
 836         case MLX5_CMD_OP_MAD_IFC:
 837         case MLX5_CMD_OP_NOP:
 838         case MLX5_CMD_OP_PAGE_FAULT_RESUME:
 839         case MLX5_CMD_OP_QUERY_ADAPTER:
 840         case MLX5_CMD_OP_QUERY_CONG_PARAMS:
 841         case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
 842         case MLX5_CMD_OP_QUERY_CONG_STATUS:
 843         case MLX5_CMD_OP_QUERY_CQ:
 844         case MLX5_CMD_OP_QUERY_DCT:
 845         case MLX5_CMD_OP_QUERY_EQ:
 846         case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
 847         case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
 848         case MLX5_CMD_OP_QUERY_FLOW_GROUP:
 849         case MLX5_CMD_OP_QUERY_FLOW_TABLE:
 850         case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
 851         case MLX5_CMD_OP_QUERY_HCA_CAP:
 852         case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
 853         case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
 854         case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
 855         case MLX5_CMD_OP_QUERY_ISSI:
 856         case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
 857         case MLX5_CMD_OP_QUERY_LAG:
 858         case MLX5_CMD_OP_QUERY_MAD_DEMUX:
 859         case MLX5_CMD_OP_QUERY_MKEY:
 860         case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
 861         case MLX5_CMD_OP_QUERY_OTHER_HCA_CAP:
 862         case MLX5_CMD_OP_QUERY_PAGES:
 863         case MLX5_CMD_OP_QUERY_QP:
 864         case MLX5_CMD_OP_QUERY_Q_COUNTER:
 865         case MLX5_CMD_OP_QUERY_RMP:
 866         case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
 867         case MLX5_CMD_OP_QUERY_RQ:
 868         case MLX5_CMD_OP_QUERY_RQT:
 869         case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT:
 870         case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
 871         case MLX5_CMD_OP_QUERY_SQ:
 872         case MLX5_CMD_OP_QUERY_SRQ:
 873         case MLX5_CMD_OP_QUERY_TIR:
 874         case MLX5_CMD_OP_QUERY_TIS:
 875         case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
 876         case MLX5_CMD_OP_QUERY_VPORT_STATE:
 877         case MLX5_CMD_OP_QUERY_XRC_SRQ:
 878         case MLX5_CMD_OP_RST2INIT_QP:
 879         case MLX5_CMD_OP_RTR2RTS_QP:
 880         case MLX5_CMD_OP_RTS2RTS_QP:
 881         case MLX5_CMD_OP_SET_DC_CNAK_TRACE:
 882         case MLX5_CMD_OP_SET_HCA_CAP:
 883         case MLX5_CMD_OP_SET_ISSI:
 884         case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
 885         case MLX5_CMD_OP_SET_MAD_DEMUX:
 886         case MLX5_CMD_OP_SET_ROCE_ADDRESS:
 887         case MLX5_CMD_OP_SQD_RTS_QP:
 888         case MLX5_CMD_OP_SQERR2RTS_QP:
 889                 hdr->status = MLX5_CMD_STAT_INT_ERR;
 890                 hdr->syndrome = 0xFFFFFFFF;
 891                 return -ECANCELED;
 892         default:
 893                 mlx5_core_err(dev, "Unknown FW command (%d)\n", opcode);
 894                 return -EINVAL;
 895         }
 896 }
 897
 898 static void complete_command(struct mlx5_cmd_work_ent *ent)
 899 {
 900         struct mlx5_cmd *cmd = ent->cmd;
 901         struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev,
 902                                                  cmd);
 903         mlx5_cmd_cbk_t callback;
 904         void *context;
 905
 906         s64 ds;
 907         struct mlx5_cmd_stats *stats;
 908         unsigned long flags;
 909         int err;
 910         struct semaphore *sem;
 911
 912         if (ent->page_queue)
 913                 sem = &cmd->pages_sem;
 914         else
 915                 sem = &cmd->sem;
 916
 917         if (dev->state != MLX5_DEVICE_STATE_UP) {
 918                 struct mlx5_outbox_hdr *out_hdr =
 919                         (struct mlx5_outbox_hdr *)ent->out;
 920                 struct mlx5_inbox_hdr *in_hdr =
 921                         (struct mlx5_inbox_hdr *)(ent->in->first.data);
 922                 u16 opcode = be16_to_cpu(in_hdr->opcode);
 923
 924                 ent->ret = set_internal_err_outbox(dev,
 925                                                    opcode,
 926                                                    out_hdr);
 927         }
 928
 929         if (ent->callback) {
 930                 ds = ent->ts2 - ent->ts1;
 931                 if (ent->op < ARRAY_SIZE(cmd->stats)) {
 932                         stats = &cmd->stats[ent->op];
 933                         spin_lock_irqsave(&stats->lock, flags);
 934                         stats->sum += ds;
 935                         ++stats->n;
 936                         spin_unlock_irqrestore(&stats->lock, flags);
 937                 }
 938
 939                 callback = ent->callback;
 940                 context = ent->context;
 941                 err = ent->ret;
 942                 if (!err)
 943                         err = mlx5_copy_from_msg(ent->uout,
 944                                                  ent->out,
 945                                                  ent->uout_size);
 946
 947                 mlx5_free_cmd_msg(dev, ent->out);
 948                 free_msg(dev, ent->in);
 949
 950                 free_cmd(ent);
 951                 callback(err, context);
 952         } else {
 953                 complete(&ent->done);
 954         }
 955         up(sem);
 956 }
 957
 958 static void cmd_work_handler(struct work_struct *work)
 959 {
 960         struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
 961         struct mlx5_cmd *cmd = ent->cmd;
 962         struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
 963         struct mlx5_cmd_layout *lay;
 964         struct semaphore *sem;
 965
 966         sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
 967         if (cmd->moving_to_polling) {
 968                 mlx5_core_warn(dev, "not expecting command execution, ignoring...\n");
 969                 return;
 970         }
 971
 972         down(sem);
 973
 974         if (alloc_ent(ent) < 0) {
 975                 complete_command(ent);
 976                 return;
 977         }
 978
 979         ent->token = alloc_token(cmd);
 980         lay = get_inst(cmd, ent->idx);
 981         ent->lay = lay;
 982         memset(lay, 0, sizeof(*lay));
 983         memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
 984         ent->op = be32_to_cpu(lay->in[0]) >> 16;
 985         if (ent->in->next)
 986                 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
 987         lay->inlen = cpu_to_be32(ent->in->len);
 988         if (ent->out->next)
 989                 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
 990         lay->outlen = cpu_to_be32(ent->out->len);
 991         lay->type = MLX5_PCI_CMD_XPORT;
 992         lay->token = ent->token;
 993         lay->status_own = CMD_OWNER_HW;
 994         set_signature(ent, !cmd->checksum_disabled);
 995         dump_command(dev, ent, 1);
 996         ent->ts1 = ktime_get_ns();
 997         ent->busy = 0;
 998         /* ring doorbell after the descriptor is valid */
 999         mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
1000         wmb();
1001         iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
1002         mmiowb();
1003         /* if not in polling don't use ent after this point*/
1004         if (cmd->mode == CMD_MODE_POLLING) {
1005                 poll_timeout(ent);
1006                 /* make sure we read the descriptor after ownership is SW */
1007                 rmb();
1008                 mlx5_cmd_comp_handler(dev, 1U << ent->idx);
1009         }
1010 }
1011
1012 static const char *deliv_status_to_str(u8 status)
1013 {
1014         switch (status) {
1015         case MLX5_CMD_DELIVERY_STAT_OK:
1016                 return "no errors";
1017         case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
1018                 return "signature error";
1019         case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
1020                 return "token error";
1021         case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
1022                 return "bad block number";
1023         case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
1024                 return "output pointer not aligned to block size";
1025         case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
1026                 return "input pointer not aligned to block size";
1027         case MLX5_CMD_DELIVERY_STAT_FW_ERR:
1028                 return "firmware internal error";
1029         case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
1030                 return "command input length error";
1031         case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
1032                 return "command ouput length error";
1033         case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
1034                 return "reserved fields not cleared";
1035         case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
1036                 return "bad command descriptor type";
1037         default:
1038                 return "unknown status code";
1039         }
1040 }
1041
1042 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
1043 {
1044         struct mlx5_inbox_hdr *hdr = (struct mlx5_inbox_hdr *)(in->first.data);
1045
1046         return be16_to_cpu(hdr->opcode);
1047 }
1048
1049 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
1050 {
1051         int timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
1052         struct mlx5_cmd *cmd = &dev->cmd;
1053         int err;
1054
1055         if (cmd->mode == CMD_MODE_POLLING) {
1056                 wait_for_completion(&ent->done);
1057                 err = ent->ret;
1058         } else {
1059                 if (!wait_for_completion_timeout(&ent->done, timeout))
1060                         err = -ETIMEDOUT;
1061                 else
1062                         err = 0;
1063         }
1064
1065         if (err == -ETIMEDOUT) {
1066                 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
1067                                mlx5_command_str(msg_to_opcode(ent->in)),
1068                                msg_to_opcode(ent->in));
1069         }
1070         mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
1071                       err, deliv_status_to_str(ent->status), ent->status);
1072
1073         return err;
1074 }
1075
1076 /*  Notes:
1077  *    1. Callback functions may not sleep
1078  *    2. page queue commands do not support asynchrous completion
1079  */
1080 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
1081                            struct mlx5_cmd_msg *out, void *uout, int uout_size,
1082                            mlx5_cmd_cbk_t callback,
1083                            void *context, int page_queue, u8 *status)
1084 {
1085         struct mlx5_cmd *cmd = &dev->cmd;
1086         struct mlx5_cmd_work_ent *ent;
1087         struct mlx5_cmd_stats *stats;
1088         int err = 0;
1089         s64 ds;
1090         u16 op;
1091
1092         if (callback && page_queue)
1093                 return -EINVAL;
1094
1095         ent = alloc_cmd(cmd, in, out, uout, uout_size, callback, context,
1096                         page_queue);
1097         if (IS_ERR(ent))
1098                 return PTR_ERR(ent);
1099
1100         if (!callback)
1101                 init_completion(&ent->done);
1102
1103         INIT_WORK(&ent->work, cmd_work_handler);
1104         if (page_queue) {
1105                 cmd_work_handler(&ent->work);
1106         } else if (!queue_work(cmd->wq, &ent->work)) {
1107                 mlx5_core_warn(dev, "failed to queue work\n");
1108                 err = -ENOMEM;
1109                 goto out_free;
1110         }
1111
1112         if (!callback) {
1113                 err = wait_func(dev, ent);
1114                 if (err == -ETIMEDOUT)
1115                         goto out;
1116
1117                 ds = ent->ts2 - ent->ts1;
1118                 op = be16_to_cpu(((struct mlx5_inbox_hdr *)in->first.data)->opcode);
1119                 if (op < ARRAY_SIZE(cmd->stats)) {
1120                         stats = &cmd->stats[op];
1121                         spin_lock_irq(&stats->lock);
1122                         stats->sum += ds;
1123                         ++stats->n;
1124                         spin_unlock_irq(&stats->lock);
1125                 }
1126                 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
1127                                    "fw exec time for %s is %lld nsec\n",
1128                                    mlx5_command_str(op), (long long)ds);
1129                 *status = ent->status;
1130                 free_cmd(ent);
1131         }
1132
1133         return err;
1134
1135 out_free:
1136         free_cmd(ent);
1137 out:
1138         return err;
1139 }
1140
1141 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size)
1142 {
1143         struct mlx5_cmd_prot_block *block;
1144         struct mlx5_cmd_mailbox *next;
1145         int copy;
1146
1147         if (!to || !from)
1148                 return -ENOMEM;
1149
1150         copy = min_t(int, size, sizeof(to->first.data));
1151         memcpy(to->first.data, from, copy);
1152         size -= copy;
1153         from += copy;
1154
1155         next = to->next;
1156         while (size) {
1157                 if (!next) {
1158                         /* this is a BUG */
1159                         return -ENOMEM;
1160                 }
1161
1162                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1163                 block = next->buf;
1164                 memcpy(block->data, from, copy);
1165                 from += copy;
1166                 size -= copy;
1167                 next = next->next;
1168         }
1169
1170         return 0;
1171 }
1172
1173 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
1174 {
1175         struct mlx5_cmd_prot_block *block;
1176         struct mlx5_cmd_mailbox *next;
1177         int copy;
1178
1179         if (!to || !from)
1180                 return -ENOMEM;
1181
1182         copy = min_t(int, size, sizeof(from->first.data));
1183         memcpy(to, from->first.data, copy);
1184         size -= copy;
1185         to += copy;
1186
1187         next = from->next;
1188         while (size) {
1189                 if (!next) {
1190                         /* this is a BUG */
1191                         return -ENOMEM;
1192                 }
1193
1194                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1195                 block = next->buf;
1196
1197                 memcpy(to, block->data, copy);
1198                 to += copy;
1199                 size -= copy;
1200                 next = next->next;
1201         }
1202
1203         return 0;
1204 }
1205
1206 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
1207                                               gfp_t flags)
1208 {
1209         struct mlx5_cmd_mailbox *mailbox;
1210
1211         mailbox = kmalloc(sizeof(*mailbox), flags);
1212         if (!mailbox)
1213                 return ERR_PTR(-ENOMEM);
1214
1215         mailbox->buf = pci_pool_alloc(dev->cmd.pool, flags,
1216                                       &mailbox->dma);
1217         if (!mailbox->buf) {
1218                 mlx5_core_dbg(dev, "failed allocation\n");
1219                 kfree(mailbox);
1220                 return ERR_PTR(-ENOMEM);
1221         }
1222         memset(mailbox->buf, 0, sizeof(struct mlx5_cmd_prot_block));
1223         mailbox->next = NULL;
1224
1225         return mailbox;
1226 }
1227
1228 static void free_cmd_box(struct mlx5_core_dev *dev,
1229                          struct mlx5_cmd_mailbox *mailbox)
1230 {
1231         pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
1232         kfree(mailbox);
1233 }
1234
1235 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
1236                                                gfp_t flags, int size)
1237 {
1238         struct mlx5_cmd_mailbox *tmp, *head = NULL;
1239         struct mlx5_cmd_prot_block *block;
1240         struct mlx5_cmd_msg *msg;
1241         int blen;
1242         int err;
1243         int n;
1244         int i;
1245
1246         msg = kzalloc(sizeof(*msg), flags);
1247         if (!msg)
1248                 return ERR_PTR(-ENOMEM);
1249
1250         blen = size - min_t(int, sizeof(msg->first.data), size);
1251         n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1) / MLX5_CMD_DATA_BLOCK_SIZE;
1252
1253         for (i = 0; i < n; i++) {
1254                 tmp = alloc_cmd_box(dev, flags);
1255                 if (IS_ERR(tmp)) {
1256                         mlx5_core_warn(dev, "failed allocating block\n");
1257                         err = PTR_ERR(tmp);
1258                         goto err_alloc;
1259                 }
1260
1261                 block = tmp->buf;
1262                 tmp->next = head;
1263                 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
1264                 block->block_num = cpu_to_be32(n - i - 1);
1265                 head = tmp;
1266         }
1267         msg->next = head;
1268         msg->len = size;
1269         return msg;
1270
1271 err_alloc:
1272         while (head) {
1273                 tmp = head->next;
1274                 free_cmd_box(dev, head);
1275                 head = tmp;
1276         }
1277         kfree(msg);
1278
1279         return ERR_PTR(err);
1280 }
1281
1282 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
1283                                   struct mlx5_cmd_msg *msg)
1284 {
1285         struct mlx5_cmd_mailbox *head = msg->next;
1286         struct mlx5_cmd_mailbox *next;
1287
1288         while (head) {
1289                 next = head->next;
1290                 free_cmd_box(dev, head);
1291                 head = next;
1292         }
1293         kfree(msg);
1294 }
1295
1296 static void set_wqname(struct mlx5_core_dev *dev)
1297 {
1298         struct mlx5_cmd *cmd = &dev->cmd;
1299
1300         snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1301                  dev_name(&dev->pdev->dev));
1302 }
1303
1304 static void clean_debug_files(struct mlx5_core_dev *dev)
1305 {
1306 }
1307
1308
1309 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1310 {
1311         struct mlx5_cmd *cmd = &dev->cmd;
1312         int i;
1313
1314         for (i = 0; i < cmd->max_reg_cmds; i++)
1315                 down(&cmd->sem);
1316
1317         down(&cmd->pages_sem);
1318
1319         flush_workqueue(cmd->wq);
1320
1321         cmd->mode = CMD_MODE_EVENTS;
1322
1323         up(&cmd->pages_sem);
1324         for (i = 0; i < cmd->max_reg_cmds; i++)
1325                 up(&cmd->sem);
1326 }
1327
1328 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1329 {
1330         struct mlx5_cmd *cmd = &dev->cmd;
1331
1332         synchronize_irq(dev->priv.eq_table.pages_eq.irqn);
1333         flush_workqueue(dev->priv.pg_wq);
1334         cmd->moving_to_polling = 1;
1335         flush_workqueue(cmd->wq);
1336         cmd->mode = CMD_MODE_POLLING;
1337         cmd->moving_to_polling = 0;
1338 }
1339
1340 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1341 {
1342         unsigned long flags;
1343
1344         if (msg->cache) {
1345                 spin_lock_irqsave(&msg->cache->lock, flags);
1346                 list_add_tail(&msg->list, &msg->cache->head);
1347                 spin_unlock_irqrestore(&msg->cache->lock, flags);
1348         } else {
1349                 mlx5_free_cmd_msg(dev, msg);
1350         }
1351 }
1352
1353 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u32 vector)
1354 {
1355         struct mlx5_cmd *cmd = &dev->cmd;
1356         struct mlx5_cmd_work_ent *ent;
1357         int i;
1358
1359         while (vector != 0) {
1360                 i = ffs(vector) - 1;
1361                 vector &= ~(1U << i);
1362                 ent = cmd->ent_arr[i];
1363                 ent->ts2 = ktime_get_ns();
1364                 memcpy(ent->out->first.data, ent->lay->out,
1365                        sizeof(ent->lay->out));
1366                 dump_command(dev, ent, 0);
1367                 if (!ent->ret) {
1368                         if (!cmd->checksum_disabled)
1369                                 ent->ret = verify_signature(ent);
1370                         else
1371                                 ent->ret = 0;
1372                         ent->status = ent->lay->status_own >> 1;
1373
1374                         mlx5_core_dbg(dev,
1375                                       "FW command ret 0x%x, status %s(0x%x)\n",
1376                                       ent->ret,
1377                                       deliv_status_to_str(ent->status),
1378                                       ent->status);
1379                 }
1380                 free_ent(cmd, ent->idx);
1381                 complete_command(ent);
1382         }
1383 }
1384 EXPORT_SYMBOL(mlx5_cmd_comp_handler);
1385
1386 void mlx5_trigger_cmd_completions(struct mlx5_core_dev *dev)
1387 {
1388         unsigned long vector;
1389         int i = 0;
1390         unsigned long flags;
1391         synchronize_irq(dev->priv.eq_table.cmd_eq.irqn);
1392         spin_lock_irqsave(&dev->cmd.alloc_lock, flags);
1393         vector = ~dev->cmd.bitmask & ((1ul << (1 << dev->cmd.log_sz)) - 1);
1394         spin_unlock_irqrestore(&dev->cmd.alloc_lock, flags);
1395
1396         if (!vector)
1397                 return;
1398
1399         for (i = 0; i < (1 << dev->cmd.log_sz); i++) {
1400                 struct mlx5_cmd_work_ent *ent = dev->cmd.ent_arr[i];
1401
1402                 if (!test_bit(i, &vector))
1403                         continue;
1404
1405                 while (ent->busy)
1406                         usleep_range(1000, 1100);
1407                 free_ent(&dev->cmd, i);
1408                 complete_command(ent);
1409         }
1410 }
1411 EXPORT_SYMBOL(mlx5_trigger_cmd_completions);
1412
1413 static int status_to_err(u8 status)
1414 {
1415         return status ? -1 : 0; /* TBD more meaningful codes */
1416 }
1417
1418 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1419                                       gfp_t gfp)
1420 {
1421         struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1422         struct mlx5_cmd *cmd = &dev->cmd;
1423         struct cache_ent *ent = NULL;
1424
1425         if (in_size > MED_LIST_SIZE && in_size <= LONG_LIST_SIZE)
1426                 ent = &cmd->cache.large;
1427         else if (in_size > 16 && in_size <= MED_LIST_SIZE)
1428                 ent = &cmd->cache.med;
1429
1430         if (ent) {
1431                 spin_lock_irq(&ent->lock);
1432                 if (!list_empty(&ent->head)) {
1433                         msg = list_entry(ent->head.next, struct mlx5_cmd_msg,
1434                                          list);
1435                         /* For cached lists, we must explicitly state what is
1436                          * the real size
1437                          */
1438                         msg->len = in_size;
1439                         list_del(&msg->list);
1440                 }
1441                 spin_unlock_irq(&ent->lock);
1442         }
1443
1444         if (IS_ERR(msg))
1445                 msg = mlx5_alloc_cmd_msg(dev, gfp, in_size);
1446
1447         return msg;
1448 }
1449
1450 static int is_manage_pages(struct mlx5_inbox_hdr *in)
1451 {
1452         return be16_to_cpu(in->opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1453 }
1454
1455 static int cmd_exec_helper(struct mlx5_core_dev *dev,
1456                            void *in, int in_size,
1457                            void *out, int out_size,
1458                            mlx5_cmd_cbk_t callback, void *context)
1459 {
1460         struct mlx5_cmd_msg *inb;
1461         struct mlx5_cmd_msg *outb;
1462         int pages_queue;
1463         gfp_t gfp;
1464         int err;
1465         u8 status = 0;
1466
1467         pages_queue = is_manage_pages(in);
1468         gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1469
1470         inb = alloc_msg(dev, in_size, gfp);
1471         if (IS_ERR(inb)) {
1472                 err = PTR_ERR(inb);
1473                 return err;
1474         }
1475
1476         err = mlx5_copy_to_msg(inb, in, in_size);
1477         if (err) {
1478                 mlx5_core_warn(dev, "err %d\n", err);
1479                 goto out_in;
1480         }
1481
1482         outb = mlx5_alloc_cmd_msg(dev, gfp, out_size);
1483         if (IS_ERR(outb)) {
1484                 err = PTR_ERR(outb);
1485                 goto out_in;
1486         }
1487
1488         err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1489                               pages_queue, &status);
1490         if (err) {
1491                 if (err == -ETIMEDOUT)
1492                         return err;
1493                 goto out_out;
1494         }
1495
1496         mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1497         if (status) {
1498                 err = status_to_err(status);
1499                 goto out_out;
1500         }
1501
1502         if (callback)
1503                 return err;
1504
1505         err = mlx5_copy_from_msg(out, outb, out_size);
1506
1507 out_out:
1508         mlx5_free_cmd_msg(dev, outb);
1509
1510 out_in:
1511         free_msg(dev, inb);
1512         return err;
1513 }
1514
1515 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1516                   int out_size)
1517 {
1518         return cmd_exec_helper(dev, in, in_size, out, out_size, NULL, NULL);
1519 }
1520 EXPORT_SYMBOL(mlx5_cmd_exec);
1521
1522 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
1523                      void *out, int out_size, mlx5_cmd_cbk_t callback,
1524                      void *context)
1525 {
1526         return cmd_exec_helper(dev, in, in_size, out, out_size, callback, context);
1527 }
1528 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1529
1530 static void destroy_msg_cache(struct mlx5_core_dev *dev)
1531 {
1532         struct mlx5_cmd *cmd = &dev->cmd;
1533         struct mlx5_cmd_msg *msg;
1534         struct mlx5_cmd_msg *n;
1535
1536         list_for_each_entry_safe(msg, n, &cmd->cache.large.head, list) {
1537                 list_del(&msg->list);
1538                 mlx5_free_cmd_msg(dev, msg);
1539         }
1540
1541         list_for_each_entry_safe(msg, n, &cmd->cache.med.head, list) {
1542                 list_del(&msg->list);
1543                 mlx5_free_cmd_msg(dev, msg);
1544         }
1545 }
1546
1547 static int create_msg_cache(struct mlx5_core_dev *dev)
1548 {
1549         struct mlx5_cmd *cmd = &dev->cmd;
1550         struct mlx5_cmd_msg *msg;
1551         int err;
1552         int i;
1553
1554         spin_lock_init(&cmd->cache.large.lock);
1555         INIT_LIST_HEAD(&cmd->cache.large.head);
1556         spin_lock_init(&cmd->cache.med.lock);
1557         INIT_LIST_HEAD(&cmd->cache.med.head);
1558
1559         for (i = 0; i < NUM_LONG_LISTS; i++) {
1560                 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, LONG_LIST_SIZE);
1561                 if (IS_ERR(msg)) {
1562                         err = PTR_ERR(msg);
1563                         goto ex_err;
1564                 }
1565                 msg->cache = &cmd->cache.large;
1566                 list_add_tail(&msg->list, &cmd->cache.large.head);
1567         }
1568
1569         for (i = 0; i < NUM_MED_LISTS; i++) {
1570                 msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL, MED_LIST_SIZE);
1571                 if (IS_ERR(msg)) {
1572                         err = PTR_ERR(msg);
1573                         goto ex_err;
1574                 }
1575                 msg->cache = &cmd->cache.med;
1576                 list_add_tail(&msg->list, &cmd->cache.med.head);
1577         }
1578
1579         return 0;
1580
1581 ex_err:
1582         destroy_msg_cache(dev);
1583         return err;
1584 }
1585
1586 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1587 {
1588         struct device *ddev = &dev->pdev->dev;
1589         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE,
1590                                                  &cmd->alloc_dma, GFP_KERNEL);
1591         if (!cmd->cmd_alloc_buf)
1592                 return -ENOMEM;
1593
1594         /* make sure it is aligned to 4K */
1595         if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
1596                 cmd->cmd_buf = cmd->cmd_alloc_buf;
1597                 cmd->dma = cmd->alloc_dma;
1598                 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
1599                 return 0;
1600         }
1601
1602         dma_free_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf, cmd->alloc_dma);
1603         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev, 2 * MLX5_ADAPTER_PAGE_SIZE - 1,
1604                                                  &cmd->alloc_dma, GFP_KERNEL);
1605         if (!cmd->cmd_alloc_buf)
1606                 return -ENOMEM;
1607
1608         cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
1609         cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
1610         cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
1611         return 0;
1612 }
1613
1614 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1615 {
1616         struct device *ddev = &dev->pdev->dev;
1617         dma_free_coherent(ddev, cmd->alloc_size, cmd->cmd_alloc_buf, cmd->alloc_dma);
1618 }
1619
1620 int mlx5_cmd_init(struct mlx5_core_dev *dev)
1621 {
1622         int size = sizeof(struct mlx5_cmd_prot_block);
1623         int align = roundup_pow_of_two(size);
1624         struct mlx5_cmd *cmd = &dev->cmd;
1625         u32 cmd_h, cmd_l;
1626         u16 cmd_if_rev;
1627         int err;
1628         int i;
1629
1630         cmd_if_rev = cmdif_rev_get(dev);
1631         if (cmd_if_rev != CMD_IF_REV) {
1632                 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""Driver cmdif rev(%d) differs from firmware's(%d)\n", CMD_IF_REV, cmd_if_rev);
1633                 return -EINVAL;
1634         }
1635
1636         cmd->pool = pci_pool_create("mlx5_cmd", dev->pdev, size, align, 0);
1637         if (!cmd->pool)
1638                 return -ENOMEM;
1639
1640         err = alloc_cmd_page(dev, cmd);
1641         if (err)
1642                 goto err_free_pool;
1643
1644         cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
1645         cmd->log_sz = cmd_l >> 4 & 0xf;
1646         cmd->log_stride = cmd_l & 0xf;
1647         if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
1648                 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""firmware reports too many outstanding commands %d\n", 1 << cmd->log_sz);
1649                 err = -EINVAL;
1650                 goto err_free_page;
1651         }
1652
1653         if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
1654                 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""command queue size overflow\n");
1655                 err = -EINVAL;
1656                 goto err_free_page;
1657         }
1658
1659         cmd->checksum_disabled = 1;
1660         cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
1661         cmd->bitmask = (1 << cmd->max_reg_cmds) - 1;
1662
1663         cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
1664         if (cmd->cmdif_rev > CMD_IF_REV) {
1665                 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""driver does not support command interface version. driver %d, firmware %d\n", CMD_IF_REV, cmd->cmdif_rev);
1666                 err = -ENOTSUPP;
1667                 goto err_free_page;
1668         }
1669
1670         spin_lock_init(&cmd->alloc_lock);
1671         spin_lock_init(&cmd->token_lock);
1672         for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
1673                 spin_lock_init(&cmd->stats[i].lock);
1674
1675         sema_init(&cmd->sem, cmd->max_reg_cmds);
1676         sema_init(&cmd->pages_sem, 1);
1677
1678         cmd_h = (u32)((u64)(cmd->dma) >> 32);
1679         cmd_l = (u32)(cmd->dma);
1680         if (cmd_l & 0xfff) {
1681                 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""invalid command queue address\n");
1682                 err = -ENOMEM;
1683                 goto err_free_page;
1684         }
1685
1686         iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
1687         iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
1688
1689         /* Make sure firmware sees the complete address before we proceed */
1690         wmb();
1691
1692         mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
1693
1694         cmd->mode = CMD_MODE_POLLING;
1695
1696         err = create_msg_cache(dev);
1697         if (err) {
1698                 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""failed to create command cache\n");
1699                 goto err_free_page;
1700         }
1701
1702         set_wqname(dev);
1703         cmd->wq = create_singlethread_workqueue(cmd->wq_name);
1704         if (!cmd->wq) {
1705                 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""failed to create command workqueue\n");
1706                 err = -ENOMEM;
1707                 goto err_cache;
1708         }
1709
1710         return 0;
1711
1712 err_cache:
1713         destroy_msg_cache(dev);
1714
1715 err_free_page:
1716         free_cmd_page(dev, cmd);
1717
1718 err_free_pool:
1719         pci_pool_destroy(cmd->pool);
1720
1721         return err;
1722 }
1723 EXPORT_SYMBOL(mlx5_cmd_init);
1724
1725 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
1726 {
1727         struct mlx5_cmd *cmd = &dev->cmd;
1728
1729         clean_debug_files(dev);
1730         destroy_workqueue(cmd->wq);
1731         destroy_msg_cache(dev);
1732         free_cmd_page(dev, cmd);
1733         pci_pool_destroy(cmd->pool);
1734 }
1735 EXPORT_SYMBOL(mlx5_cmd_cleanup);
1736
1737 static const char *cmd_status_str(u8 status)
1738 {
1739         switch (status) {
1740         case MLX5_CMD_STAT_OK:
1741                 return "OK";
1742         case MLX5_CMD_STAT_INT_ERR:
1743                 return "internal error";
1744         case MLX5_CMD_STAT_BAD_OP_ERR:
1745                 return "bad operation";
1746         case MLX5_CMD_STAT_BAD_PARAM_ERR:
1747                 return "bad parameter";
1748         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
1749                 return "bad system state";
1750         case MLX5_CMD_STAT_BAD_RES_ERR:
1751                 return "bad resource";
1752         case MLX5_CMD_STAT_RES_BUSY:
1753                 return "resource busy";
1754         case MLX5_CMD_STAT_LIM_ERR:
1755                 return "limits exceeded";
1756         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
1757                 return "bad resource state";
1758         case MLX5_CMD_STAT_IX_ERR:
1759                 return "bad index";
1760         case MLX5_CMD_STAT_NO_RES_ERR:
1761                 return "no resources";
1762         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
1763                 return "bad input length";
1764         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
1765                 return "bad output length";
1766         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
1767                 return "bad QP state";
1768         case MLX5_CMD_STAT_BAD_PKT_ERR:
1769                 return "bad packet (discarded)";
1770         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
1771                 return "bad size too many outstanding CQEs";
1772         default:
1773                 return "unknown status";
1774         }
1775 }
1776
1777 static int cmd_status_to_err_helper(u8 status)
1778 {
1779         switch (status) {
1780         case MLX5_CMD_STAT_OK:                          return 0;
1781         case MLX5_CMD_STAT_INT_ERR:                     return -EIO;
1782         case MLX5_CMD_STAT_BAD_OP_ERR:                  return -EINVAL;
1783         case MLX5_CMD_STAT_BAD_PARAM_ERR:               return -EINVAL;
1784         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:           return -EIO;
1785         case MLX5_CMD_STAT_BAD_RES_ERR:                 return -EINVAL;
1786         case MLX5_CMD_STAT_RES_BUSY:                    return -EBUSY;
1787         case MLX5_CMD_STAT_LIM_ERR:                     return -ENOMEM;
1788         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:           return -EINVAL;
1789         case MLX5_CMD_STAT_IX_ERR:                      return -EINVAL;
1790         case MLX5_CMD_STAT_NO_RES_ERR:                  return -EAGAIN;
1791         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:             return -EIO;
1792         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:            return -EIO;
1793         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:            return -EINVAL;
1794         case MLX5_CMD_STAT_BAD_PKT_ERR:                 return -EINVAL;
1795         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:      return -EINVAL;
1796         default:                                        return -EIO;
1797         }
1798 }
1799
1800 /* this will be available till all the commands use set/get macros */
1801 int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr)
1802 {
1803         if (!hdr->status)
1804                 return 0;
1805
1806         printf("mlx5_core: WARN: ""command failed, status %s(0x%x), syndrome 0x%x\n", cmd_status_str(hdr->status), hdr->status, be32_to_cpu(hdr->syndrome));
1807
1808         return cmd_status_to_err_helper(hdr->status);
1809 }
1810
1811 int mlx5_cmd_status_to_err_v2(void *ptr)
1812 {
1813         u32     syndrome;
1814         u8      status;
1815
1816         status = be32_to_cpu(*(__be32 *)ptr) >> 24;
1817         if (!status)
1818                 return 0;
1819
1820         syndrome = be32_to_cpu(*(__be32 *)(ptr + 4));
1821
1822         printf("mlx5_core: WARN: ""command failed, status %s(0x%x), syndrome 0x%x\n", cmd_status_str(status), status, syndrome);
1823
1824         return cmd_status_to_err_helper(status);
1825 }
1826