2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <linux/interrupt.h>
29 #include <linux/module.h>
30 #include <dev/mlx5/port.h>
31 #include <dev/mlx5/mlx5_ifc.h>
32 #include "mlx5_core.h"
37 #include <net/rss_config.h>
38 #include <netinet/in_rss.h>
42 MLX5_EQE_SIZE = sizeof(struct mlx5_eqe),
43 MLX5_EQE_OWNER_INIT_VAL = 0x1,
47 MLX5_NUM_SPARE_EQE = 0x80,
48 MLX5_NUM_ASYNC_EQE = 0x100,
49 MLX5_NUM_CMD_EQE = 32,
53 MLX5_EQ_DOORBEL_OFFSET = 0x40,
56 #define MLX5_ASYNC_EVENT_MASK ((1ull << MLX5_EVENT_TYPE_PATH_MIG) | \
57 (1ull << MLX5_EVENT_TYPE_COMM_EST) | \
58 (1ull << MLX5_EVENT_TYPE_SQ_DRAINED) | \
59 (1ull << MLX5_EVENT_TYPE_CQ_ERROR) | \
60 (1ull << MLX5_EVENT_TYPE_WQ_CATAS_ERROR) | \
61 (1ull << MLX5_EVENT_TYPE_PATH_MIG_FAILED) | \
62 (1ull << MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
63 (1ull << MLX5_EVENT_TYPE_WQ_ACCESS_ERROR) | \
64 (1ull << MLX5_EVENT_TYPE_PORT_CHANGE) | \
65 (1ull << MLX5_EVENT_TYPE_SRQ_CATAS_ERROR) | \
66 (1ull << MLX5_EVENT_TYPE_SRQ_LAST_WQE) | \
67 (1ull << MLX5_EVENT_TYPE_SRQ_RQ_LIMIT))
80 /*Function prototype*/
81 static void mlx5_port_module_event(struct mlx5_core_dev *dev,
82 struct mlx5_eqe *eqe);
83 static void mlx5_port_general_notification_event(struct mlx5_core_dev *dev,
84 struct mlx5_eqe *eqe);
86 static int mlx5_cmd_destroy_eq(struct mlx5_core_dev *dev, u8 eqn)
88 u32 in[MLX5_ST_SZ_DW(destroy_eq_in)] = {0};
89 u32 out[MLX5_ST_SZ_DW(destroy_eq_out)] = {0};
91 MLX5_SET(destroy_eq_in, in, opcode, MLX5_CMD_OP_DESTROY_EQ);
92 MLX5_SET(destroy_eq_in, in, eq_number, eqn);
94 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
97 static struct mlx5_eqe *get_eqe(struct mlx5_eq *eq, u32 entry)
99 return mlx5_buf_offset(&eq->buf, entry * MLX5_EQE_SIZE);
102 static struct mlx5_eqe *next_eqe_sw(struct mlx5_eq *eq)
104 struct mlx5_eqe *eqe = get_eqe(eq, eq->cons_index & (eq->nent - 1));
106 return ((eqe->owner & 1) ^ !!(eq->cons_index & eq->nent)) ? NULL : eqe;
109 static const char *eqe_type_str(u8 type)
112 case MLX5_EVENT_TYPE_COMP:
113 return "MLX5_EVENT_TYPE_COMP";
114 case MLX5_EVENT_TYPE_PATH_MIG:
115 return "MLX5_EVENT_TYPE_PATH_MIG";
116 case MLX5_EVENT_TYPE_COMM_EST:
117 return "MLX5_EVENT_TYPE_COMM_EST";
118 case MLX5_EVENT_TYPE_SQ_DRAINED:
119 return "MLX5_EVENT_TYPE_SQ_DRAINED";
120 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
121 return "MLX5_EVENT_TYPE_SRQ_LAST_WQE";
122 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
123 return "MLX5_EVENT_TYPE_SRQ_RQ_LIMIT";
124 case MLX5_EVENT_TYPE_CQ_ERROR:
125 return "MLX5_EVENT_TYPE_CQ_ERROR";
126 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
127 return "MLX5_EVENT_TYPE_WQ_CATAS_ERROR";
128 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
129 return "MLX5_EVENT_TYPE_PATH_MIG_FAILED";
130 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
131 return "MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR";
132 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
133 return "MLX5_EVENT_TYPE_WQ_ACCESS_ERROR";
134 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
135 return "MLX5_EVENT_TYPE_SRQ_CATAS_ERROR";
136 case MLX5_EVENT_TYPE_INTERNAL_ERROR:
137 return "MLX5_EVENT_TYPE_INTERNAL_ERROR";
138 case MLX5_EVENT_TYPE_PORT_CHANGE:
139 return "MLX5_EVENT_TYPE_PORT_CHANGE";
140 case MLX5_EVENT_TYPE_GPIO_EVENT:
141 return "MLX5_EVENT_TYPE_GPIO_EVENT";
142 case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT:
143 return "MLX5_EVENT_TYPE_PORT_MODULE_EVENT";
144 case MLX5_EVENT_TYPE_REMOTE_CONFIG:
145 return "MLX5_EVENT_TYPE_REMOTE_CONFIG";
146 case MLX5_EVENT_TYPE_DB_BF_CONGESTION:
147 return "MLX5_EVENT_TYPE_DB_BF_CONGESTION";
148 case MLX5_EVENT_TYPE_STALL_EVENT:
149 return "MLX5_EVENT_TYPE_STALL_EVENT";
150 case MLX5_EVENT_TYPE_CMD:
151 return "MLX5_EVENT_TYPE_CMD";
152 case MLX5_EVENT_TYPE_PAGE_REQUEST:
153 return "MLX5_EVENT_TYPE_PAGE_REQUEST";
154 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE:
155 return "MLX5_EVENT_TYPE_NIC_VPORT_CHANGE";
156 case MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT:
157 return "MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT";
158 case MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT:
159 return "MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT";
161 return "Unrecognized event";
165 static enum mlx5_dev_event port_subtype_event(u8 subtype)
168 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
169 return MLX5_DEV_EVENT_PORT_DOWN;
170 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
171 return MLX5_DEV_EVENT_PORT_UP;
172 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
173 return MLX5_DEV_EVENT_PORT_INITIALIZED;
174 case MLX5_PORT_CHANGE_SUBTYPE_LID:
175 return MLX5_DEV_EVENT_LID_CHANGE;
176 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
177 return MLX5_DEV_EVENT_PKEY_CHANGE;
178 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
179 return MLX5_DEV_EVENT_GUID_CHANGE;
180 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
181 return MLX5_DEV_EVENT_CLIENT_REREG;
186 static enum mlx5_dev_event dcbx_subevent(u8 subtype)
189 case MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX:
190 return MLX5_DEV_EVENT_ERROR_STATE_DCBX;
191 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE:
192 return MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE;
193 case MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE:
194 return MLX5_DEV_EVENT_LOCAL_OPER_CHANGE;
195 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE:
196 return MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE;
201 static void eq_update_ci(struct mlx5_eq *eq, int arm)
203 __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2);
204 u32 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24);
205 __raw_writel((__force u32) cpu_to_be32(val), addr);
206 /* We still want ordering, just not swabbing, so add a barrier */
210 static int mlx5_eq_int(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
212 struct mlx5_eqe *eqe;
219 while ((eqe = next_eqe_sw(eq))) {
221 * Make sure we read EQ entry contents after we've
222 * checked the ownership bit.
226 mlx5_core_dbg(eq->dev, "eqn %d, eqe type %s\n",
227 eq->eqn, eqe_type_str(eqe->type));
229 case MLX5_EVENT_TYPE_COMP:
230 cqn = be32_to_cpu(eqe->data.comp.cqn) & 0xffffff;
231 mlx5_cq_completion(dev, cqn);
234 case MLX5_EVENT_TYPE_PATH_MIG:
235 case MLX5_EVENT_TYPE_COMM_EST:
236 case MLX5_EVENT_TYPE_SQ_DRAINED:
237 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
238 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
239 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
240 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
241 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
242 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
243 mlx5_core_dbg(dev, "event %s(%d) arrived on resource 0x%x\n",
244 eqe_type_str(eqe->type), eqe->type, rsn);
245 mlx5_rsc_event(dev, rsn, eqe->type);
248 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
249 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
250 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
251 mlx5_core_dbg(dev, "SRQ event %s(%d): srqn 0x%x\n",
252 eqe_type_str(eqe->type), eqe->type, rsn);
253 mlx5_srq_event(dev, rsn, eqe->type);
256 case MLX5_EVENT_TYPE_CMD:
257 if (dev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR)
258 mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector));
261 case MLX5_EVENT_TYPE_PORT_CHANGE:
262 port = (eqe->data.port.port >> 4) & 0xf;
263 switch (eqe->sub_type) {
264 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
265 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
266 case MLX5_PORT_CHANGE_SUBTYPE_LID:
267 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
268 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
269 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
270 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
272 dev->event(dev, port_subtype_event(eqe->sub_type),
273 (unsigned long)port);
276 mlx5_core_warn(dev, "Port event with unrecognized subtype: port %d, sub_type %d\n",
277 port, eqe->sub_type);
281 case MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT:
282 port = (eqe->data.port.port >> 4) & 0xf;
283 switch (eqe->sub_type) {
284 case MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX:
285 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE:
286 case MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE:
287 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE:
290 dcbx_subevent(eqe->sub_type),
295 "dcbx event with unrecognized subtype: port %d, sub_type %d\n",
296 port, eqe->sub_type);
300 case MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT:
301 mlx5_port_general_notification_event(dev, eqe);
304 case MLX5_EVENT_TYPE_CQ_ERROR:
305 cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff;
306 mlx5_core_warn(dev, "CQ error on CQN 0x%x, syndrom 0x%x\n",
307 cqn, eqe->data.cq_err.syndrome);
308 mlx5_cq_event(dev, cqn, eqe->type);
311 case MLX5_EVENT_TYPE_PAGE_REQUEST:
313 u16 func_id = be16_to_cpu(eqe->data.req_pages.func_id);
314 s32 npages = be32_to_cpu(eqe->data.req_pages.num_pages);
316 mlx5_core_dbg(dev, "page request for func 0x%x, npages %d\n",
318 mlx5_core_req_pages_handler(dev, func_id, npages);
322 case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT:
323 mlx5_port_module_event(dev, eqe);
326 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE:
328 struct mlx5_eqe_vport_change *vc_eqe =
329 &eqe->data.vport_change;
330 u16 vport_num = be16_to_cpu(vc_eqe->vport_num);
334 MLX5_DEV_EVENT_VPORT_CHANGE,
335 (unsigned long)vport_num);
340 mlx5_core_warn(dev, "Unhandled event 0x%x on EQ 0x%x\n",
349 /* The HCA will think the queue has overflowed if we
350 * don't tell it we've been processing events. We
351 * create our EQs with MLX5_NUM_SPARE_EQE extra
352 * entries, so we must update our consumer index at
355 if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) {
366 static irqreturn_t mlx5_msix_handler(int irq, void *eq_ptr)
368 struct mlx5_eq *eq = eq_ptr;
369 struct mlx5_core_dev *dev = eq->dev;
371 mlx5_eq_int(dev, eq);
373 /* MSI-X vectors always belong to us */
377 static void init_eq_buf(struct mlx5_eq *eq)
379 struct mlx5_eqe *eqe;
382 for (i = 0; i < eq->nent; i++) {
383 eqe = get_eqe(eq, i);
384 eqe->owner = MLX5_EQE_OWNER_INIT_VAL;
388 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
389 int nent, u64 mask, const char *name, struct mlx5_uar *uar)
391 u32 out[MLX5_ST_SZ_DW(create_eq_out)] = {0};
392 struct mlx5_priv *priv = &dev->priv;
399 eq->nent = roundup_pow_of_two(nent + MLX5_NUM_SPARE_EQE);
401 err = mlx5_buf_alloc(dev, eq->nent * MLX5_EQE_SIZE, 2 * PAGE_SIZE,
408 inlen = MLX5_ST_SZ_BYTES(create_eq_in) +
409 MLX5_FLD_SZ_BYTES(create_eq_in, pas[0]) * eq->buf.npages;
410 in = mlx5_vzalloc(inlen);
416 pas = (__be64 *)MLX5_ADDR_OF(create_eq_in, in, pas);
417 mlx5_fill_page_array(&eq->buf, pas);
419 MLX5_SET(create_eq_in, in, opcode, MLX5_CMD_OP_CREATE_EQ);
420 MLX5_SET64(create_eq_in, in, event_bitmask, mask);
422 eqc = MLX5_ADDR_OF(create_eq_in, in, eq_context_entry);
423 MLX5_SET(eqc, eqc, log_eq_size, ilog2(eq->nent));
424 MLX5_SET(eqc, eqc, uar_page, uar->index);
425 MLX5_SET(eqc, eqc, intr, vecidx);
426 MLX5_SET(eqc, eqc, log_page_size,
427 eq->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
429 err = mlx5_cmd_exec(dev, in, inlen, out, sizeof(out));
433 eq->eqn = MLX5_GET(create_eq_out, out, eq_number);
436 eq->doorbell = uar->map + MLX5_EQ_DOORBEL_OFFSET;
437 snprintf(priv->irq_info[vecidx].name, MLX5_MAX_IRQ_NAME, "%s@pci:%s",
438 name, pci_name(dev->pdev));
439 err = request_irq(priv->msix_arr[vecidx].vector, mlx5_msix_handler, 0,
440 priv->irq_info[vecidx].name, eq);
444 if (vecidx >= MLX5_EQ_VEC_COMP_BASE) {
445 u8 bucket = vecidx - MLX5_EQ_VEC_COMP_BASE;
446 err = bind_irq_to_cpu(priv->msix_arr[vecidx].vector,
447 rss_getcpu(bucket % rss_getnumbuckets()));
457 /* EQs are created in ARMED state
465 free_irq(priv->msix_arr[vecidx].vector, eq);
468 mlx5_cmd_destroy_eq(dev, eq->eqn);
474 mlx5_buf_free(dev, &eq->buf);
477 EXPORT_SYMBOL_GPL(mlx5_create_map_eq);
479 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
483 free_irq(dev->priv.msix_arr[eq->irqn].vector, eq);
484 err = mlx5_cmd_destroy_eq(dev, eq->eqn);
486 mlx5_core_warn(dev, "failed to destroy a previously created eq: eqn %d\n",
488 mlx5_buf_free(dev, &eq->buf);
492 EXPORT_SYMBOL_GPL(mlx5_destroy_unmap_eq);
494 int mlx5_eq_init(struct mlx5_core_dev *dev)
498 spin_lock_init(&dev->priv.eq_table.lock);
506 void mlx5_eq_cleanup(struct mlx5_core_dev *dev)
510 int mlx5_start_eqs(struct mlx5_core_dev *dev)
512 struct mlx5_eq_table *table = &dev->priv.eq_table;
513 u64 async_event_mask = MLX5_ASYNC_EVENT_MASK;
516 if (MLX5_CAP_GEN(dev, port_module_event))
517 async_event_mask |= (1ull <<
518 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT);
520 if (MLX5_CAP_GEN(dev, nic_vport_change_event))
521 async_event_mask |= (1ull <<
522 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE);
524 if (MLX5_CAP_GEN(dev, dcbx))
525 async_event_mask |= (1ull <<
526 MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT);
528 err = mlx5_create_map_eq(dev, &table->cmd_eq, MLX5_EQ_VEC_CMD,
529 MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD,
530 "mlx5_cmd_eq", &dev->priv.uuari.uars[0]);
532 mlx5_core_warn(dev, "failed to create cmd EQ %d\n", err);
536 mlx5_cmd_use_events(dev);
538 err = mlx5_create_map_eq(dev, &table->async_eq, MLX5_EQ_VEC_ASYNC,
539 MLX5_NUM_ASYNC_EQE, async_event_mask,
540 "mlx5_async_eq", &dev->priv.uuari.uars[0]);
542 mlx5_core_warn(dev, "failed to create async EQ %d\n", err);
546 err = mlx5_create_map_eq(dev, &table->pages_eq,
548 /* TODO: sriov max_vf + */ 1,
549 1 << MLX5_EVENT_TYPE_PAGE_REQUEST, "mlx5_pages_eq",
550 &dev->priv.uuari.uars[0]);
552 mlx5_core_warn(dev, "failed to create pages EQ %d\n", err);
559 mlx5_destroy_unmap_eq(dev, &table->async_eq);
562 mlx5_cmd_use_polling(dev);
563 mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
567 int mlx5_stop_eqs(struct mlx5_core_dev *dev)
569 struct mlx5_eq_table *table = &dev->priv.eq_table;
572 err = mlx5_destroy_unmap_eq(dev, &table->pages_eq);
576 mlx5_destroy_unmap_eq(dev, &table->async_eq);
577 mlx5_cmd_use_polling(dev);
579 err = mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
581 mlx5_cmd_use_events(dev);
586 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
587 u32 *out, int outlen)
589 u32 in[MLX5_ST_SZ_DW(query_eq_in)] = {0};
591 memset(out, 0, outlen);
592 MLX5_SET(query_eq_in, in, opcode, MLX5_CMD_OP_QUERY_EQ);
593 MLX5_SET(query_eq_in, in, eq_number, eq->eqn);
595 return mlx5_cmd_exec(dev, in, sizeof(in), out, outlen);
597 EXPORT_SYMBOL_GPL(mlx5_core_eq_query);
599 static const char *mlx5_port_module_event_error_type_to_string(u8 error_type)
601 switch (error_type) {
602 case MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED:
603 return "Power Budget Exceeded";
604 case MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE:
605 return "Long Range for non MLNX cable/module";
606 case MLX5_MODULE_EVENT_ERROR_BUS_STUCK:
607 return "Bus stuck(I2C or data shorted)";
608 case MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT:
609 return "No EEPROM/retry timeout";
610 case MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST:
611 return "Enforce part number list";
612 case MLX5_MODULE_EVENT_ERROR_UNSUPPORTED_CABLE:
613 return "Unsupported Cable";
614 case MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE:
615 return "High Temperature";
616 case MLX5_MODULE_EVENT_ERROR_CABLE_IS_SHORTED:
617 return "Cable is shorted";
620 return "Unknown error type";
624 unsigned int mlx5_query_module_status(struct mlx5_core_dev *dev, int module_num)
626 if (module_num < 0 || module_num >= MLX5_MAX_PORTS)
627 return 0; /* undefined */
628 return dev->module_status[module_num];
631 static void mlx5_port_module_event(struct mlx5_core_dev *dev,
632 struct mlx5_eqe *eqe)
634 unsigned int module_num;
635 unsigned int module_status;
636 unsigned int error_type;
637 struct mlx5_eqe_port_module_event *module_event_eqe;
638 struct pci_dev *pdev = dev->pdev;
640 module_event_eqe = &eqe->data.port_module_event;
642 module_num = (unsigned int)module_event_eqe->module;
643 module_status = (unsigned int)module_event_eqe->module_status &
644 PORT_MODULE_EVENT_MODULE_STATUS_MASK;
645 error_type = (unsigned int)module_event_eqe->error_type &
646 PORT_MODULE_EVENT_ERROR_TYPE_MASK;
648 switch (module_status) {
649 case MLX5_MODULE_STATUS_PLUGGED_ENABLED:
650 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: plugged and enabled\n", module_num);
653 case MLX5_MODULE_STATUS_UNPLUGGED:
654 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: unplugged\n", module_num);
657 case MLX5_MODULE_STATUS_ERROR:
658 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: error, %s\n", module_num, mlx5_port_module_event_error_type_to_string(error_type));
661 case MLX5_MODULE_STATUS_PLUGGED_DISABLED:
662 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: plugged but disabled\n", module_num);
666 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, unknown status\n", module_num);
668 /* store module status */
669 if (module_num < MLX5_MAX_PORTS)
670 dev->module_status[module_num] = module_status;
673 static void mlx5_port_general_notification_event(struct mlx5_core_dev *dev,
674 struct mlx5_eqe *eqe)
676 u8 port = (eqe->data.port.port >> 4) & 0xf;
678 struct mlx5_eqe_general_notification_event *general_event = NULL;
680 switch (eqe->sub_type) {
681 case MLX5_GEN_EVENT_SUBTYPE_DELAY_DROP_TIMEOUT:
682 general_event = &eqe->data.general_notifications;
683 rqn = be32_to_cpu(general_event->rq_user_index_delay_drop) &
688 "general event with unrecognized subtype: port %d, sub_type %d\n",
689 port, eqe->sub_type);