2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <linux/interrupt.h>
29 #include <linux/module.h>
30 #include <dev/mlx5/driver.h>
31 #include <dev/mlx5/mlx5_ifc.h>
32 #include "mlx5_core.h"
37 #include <net/rss_config.h>
38 #include <netinet/in_rss.h>
42 MLX5_EQE_SIZE = sizeof(struct mlx5_eqe),
43 MLX5_EQE_OWNER_INIT_VAL = 0x1,
47 MLX5_NUM_SPARE_EQE = 0x80,
48 MLX5_NUM_ASYNC_EQE = 0x100,
49 MLX5_NUM_CMD_EQE = 32,
53 MLX5_EQ_DOORBEL_OFFSET = 0x40,
56 #define MLX5_ASYNC_EVENT_MASK ((1ull << MLX5_EVENT_TYPE_PATH_MIG) | \
57 (1ull << MLX5_EVENT_TYPE_COMM_EST) | \
58 (1ull << MLX5_EVENT_TYPE_SQ_DRAINED) | \
59 (1ull << MLX5_EVENT_TYPE_CQ_ERROR) | \
60 (1ull << MLX5_EVENT_TYPE_WQ_CATAS_ERROR) | \
61 (1ull << MLX5_EVENT_TYPE_PATH_MIG_FAILED) | \
62 (1ull << MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \
63 (1ull << MLX5_EVENT_TYPE_WQ_ACCESS_ERROR) | \
64 (1ull << MLX5_EVENT_TYPE_PORT_CHANGE) | \
65 (1ull << MLX5_EVENT_TYPE_SRQ_CATAS_ERROR) | \
66 (1ull << MLX5_EVENT_TYPE_SRQ_LAST_WQE) | \
67 (1ull << MLX5_EVENT_TYPE_SRQ_RQ_LIMIT))
80 /*Function prototype*/
81 static void mlx5_port_module_event(struct mlx5_core_dev *dev,
82 struct mlx5_eqe *eqe);
83 static void mlx5_port_general_notification_event(struct mlx5_core_dev *dev,
84 struct mlx5_eqe *eqe);
86 static int mlx5_cmd_destroy_eq(struct mlx5_core_dev *dev, u8 eqn)
88 u32 in[MLX5_ST_SZ_DW(destroy_eq_in)];
89 u32 out[MLX5_ST_SZ_DW(destroy_eq_out)];
91 memset(in, 0, sizeof(in));
93 MLX5_SET(destroy_eq_in, in, opcode, MLX5_CMD_OP_DESTROY_EQ);
94 MLX5_SET(destroy_eq_in, in, eq_number, eqn);
96 memset(out, 0, sizeof(out));
97 return mlx5_cmd_exec_check_status(dev, in, sizeof(in),
101 static struct mlx5_eqe *get_eqe(struct mlx5_eq *eq, u32 entry)
103 return mlx5_buf_offset(&eq->buf, entry * MLX5_EQE_SIZE);
106 static struct mlx5_eqe *next_eqe_sw(struct mlx5_eq *eq)
108 struct mlx5_eqe *eqe = get_eqe(eq, eq->cons_index & (eq->nent - 1));
110 return ((eqe->owner & 1) ^ !!(eq->cons_index & eq->nent)) ? NULL : eqe;
113 static const char *eqe_type_str(u8 type)
116 case MLX5_EVENT_TYPE_COMP:
117 return "MLX5_EVENT_TYPE_COMP";
118 case MLX5_EVENT_TYPE_PATH_MIG:
119 return "MLX5_EVENT_TYPE_PATH_MIG";
120 case MLX5_EVENT_TYPE_COMM_EST:
121 return "MLX5_EVENT_TYPE_COMM_EST";
122 case MLX5_EVENT_TYPE_SQ_DRAINED:
123 return "MLX5_EVENT_TYPE_SQ_DRAINED";
124 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
125 return "MLX5_EVENT_TYPE_SRQ_LAST_WQE";
126 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
127 return "MLX5_EVENT_TYPE_SRQ_RQ_LIMIT";
128 case MLX5_EVENT_TYPE_CQ_ERROR:
129 return "MLX5_EVENT_TYPE_CQ_ERROR";
130 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
131 return "MLX5_EVENT_TYPE_WQ_CATAS_ERROR";
132 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
133 return "MLX5_EVENT_TYPE_PATH_MIG_FAILED";
134 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
135 return "MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR";
136 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
137 return "MLX5_EVENT_TYPE_WQ_ACCESS_ERROR";
138 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
139 return "MLX5_EVENT_TYPE_SRQ_CATAS_ERROR";
140 case MLX5_EVENT_TYPE_INTERNAL_ERROR:
141 return "MLX5_EVENT_TYPE_INTERNAL_ERROR";
142 case MLX5_EVENT_TYPE_PORT_CHANGE:
143 return "MLX5_EVENT_TYPE_PORT_CHANGE";
144 case MLX5_EVENT_TYPE_GPIO_EVENT:
145 return "MLX5_EVENT_TYPE_GPIO_EVENT";
146 case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT:
147 return "MLX5_EVENT_TYPE_PORT_MODULE_EVENT";
148 case MLX5_EVENT_TYPE_REMOTE_CONFIG:
149 return "MLX5_EVENT_TYPE_REMOTE_CONFIG";
150 case MLX5_EVENT_TYPE_DB_BF_CONGESTION:
151 return "MLX5_EVENT_TYPE_DB_BF_CONGESTION";
152 case MLX5_EVENT_TYPE_STALL_EVENT:
153 return "MLX5_EVENT_TYPE_STALL_EVENT";
154 case MLX5_EVENT_TYPE_CMD:
155 return "MLX5_EVENT_TYPE_CMD";
156 case MLX5_EVENT_TYPE_PAGE_REQUEST:
157 return "MLX5_EVENT_TYPE_PAGE_REQUEST";
158 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE:
159 return "MLX5_EVENT_TYPE_NIC_VPORT_CHANGE";
160 case MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT:
161 return "MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT";
162 case MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT:
163 return "MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT";
165 return "Unrecognized event";
169 static enum mlx5_dev_event port_subtype_event(u8 subtype)
172 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
173 return MLX5_DEV_EVENT_PORT_DOWN;
174 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
175 return MLX5_DEV_EVENT_PORT_UP;
176 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
177 return MLX5_DEV_EVENT_PORT_INITIALIZED;
178 case MLX5_PORT_CHANGE_SUBTYPE_LID:
179 return MLX5_DEV_EVENT_LID_CHANGE;
180 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
181 return MLX5_DEV_EVENT_PKEY_CHANGE;
182 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
183 return MLX5_DEV_EVENT_GUID_CHANGE;
184 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
185 return MLX5_DEV_EVENT_CLIENT_REREG;
190 static enum mlx5_dev_event dcbx_subevent(u8 subtype)
193 case MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX:
194 return MLX5_DEV_EVENT_ERROR_STATE_DCBX;
195 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE:
196 return MLX5_DEV_EVENT_REMOTE_CONFIG_CHANGE;
197 case MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE:
198 return MLX5_DEV_EVENT_LOCAL_OPER_CHANGE;
199 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE:
200 return MLX5_DEV_EVENT_REMOTE_CONFIG_APPLICATION_PRIORITY_CHANGE;
205 static void eq_update_ci(struct mlx5_eq *eq, int arm)
207 __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2);
208 u32 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24);
209 __raw_writel((__force u32) cpu_to_be32(val), addr);
210 /* We still want ordering, just not swabbing, so add a barrier */
214 static int mlx5_eq_int(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
216 struct mlx5_eqe *eqe;
223 while ((eqe = next_eqe_sw(eq))) {
225 * Make sure we read EQ entry contents after we've
226 * checked the ownership bit.
230 mlx5_core_dbg(eq->dev, "eqn %d, eqe type %s\n",
231 eq->eqn, eqe_type_str(eqe->type));
233 case MLX5_EVENT_TYPE_COMP:
234 cqn = be32_to_cpu(eqe->data.comp.cqn) & 0xffffff;
235 mlx5_cq_completion(dev, cqn);
238 case MLX5_EVENT_TYPE_PATH_MIG:
239 case MLX5_EVENT_TYPE_COMM_EST:
240 case MLX5_EVENT_TYPE_SQ_DRAINED:
241 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
242 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
243 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
244 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
245 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
246 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
247 mlx5_core_dbg(dev, "event %s(%d) arrived on resource 0x%x\n",
248 eqe_type_str(eqe->type), eqe->type, rsn);
249 mlx5_rsc_event(dev, rsn, eqe->type);
252 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT:
253 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR:
254 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff;
255 mlx5_core_dbg(dev, "SRQ event %s(%d): srqn 0x%x\n",
256 eqe_type_str(eqe->type), eqe->type, rsn);
257 mlx5_srq_event(dev, rsn, eqe->type);
260 case MLX5_EVENT_TYPE_CMD:
261 mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector));
264 case MLX5_EVENT_TYPE_PORT_CHANGE:
265 port = (eqe->data.port.port >> 4) & 0xf;
266 switch (eqe->sub_type) {
267 case MLX5_PORT_CHANGE_SUBTYPE_DOWN:
268 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE:
269 case MLX5_PORT_CHANGE_SUBTYPE_LID:
270 case MLX5_PORT_CHANGE_SUBTYPE_PKEY:
271 case MLX5_PORT_CHANGE_SUBTYPE_GUID:
272 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG:
273 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED:
275 dev->event(dev, port_subtype_event(eqe->sub_type),
276 (unsigned long)port);
279 mlx5_core_warn(dev, "Port event with unrecognized subtype: port %d, sub_type %d\n",
280 port, eqe->sub_type);
284 case MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT:
285 port = (eqe->data.port.port >> 4) & 0xf;
286 switch (eqe->sub_type) {
287 case MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX:
288 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE:
289 case MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE:
290 case MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE:
293 dcbx_subevent(eqe->sub_type),
298 "dcbx event with unrecognized subtype: port %d, sub_type %d\n",
299 port, eqe->sub_type);
303 case MLX5_EVENT_TYPE_CODING_GENERAL_NOTIFICATION_EVENT:
304 mlx5_port_general_notification_event(dev, eqe);
307 case MLX5_EVENT_TYPE_CQ_ERROR:
308 cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff;
309 mlx5_core_warn(dev, "CQ error on CQN 0x%x, syndrom 0x%x\n",
310 cqn, eqe->data.cq_err.syndrome);
311 mlx5_cq_event(dev, cqn, eqe->type);
314 case MLX5_EVENT_TYPE_PAGE_REQUEST:
316 u16 func_id = be16_to_cpu(eqe->data.req_pages.func_id);
317 s32 npages = be32_to_cpu(eqe->data.req_pages.num_pages);
319 mlx5_core_dbg(dev, "page request for func 0x%x, npages %d\n",
321 mlx5_core_req_pages_handler(dev, func_id, npages);
325 case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT:
326 mlx5_port_module_event(dev, eqe);
329 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE:
331 struct mlx5_eqe_vport_change *vc_eqe =
332 &eqe->data.vport_change;
333 u16 vport_num = be16_to_cpu(vc_eqe->vport_num);
337 MLX5_DEV_EVENT_VPORT_CHANGE,
338 (unsigned long)vport_num);
343 mlx5_core_warn(dev, "Unhandled event 0x%x on EQ 0x%x\n",
352 /* The HCA will think the queue has overflowed if we
353 * don't tell it we've been processing events. We
354 * create our EQs with MLX5_NUM_SPARE_EQE extra
355 * entries, so we must update our consumer index at
358 if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) {
369 static irqreturn_t mlx5_msix_handler(int irq, void *eq_ptr)
371 struct mlx5_eq *eq = eq_ptr;
372 struct mlx5_core_dev *dev = eq->dev;
374 mlx5_eq_int(dev, eq);
376 /* MSI-X vectors always belong to us */
380 static void init_eq_buf(struct mlx5_eq *eq)
382 struct mlx5_eqe *eqe;
385 for (i = 0; i < eq->nent; i++) {
386 eqe = get_eqe(eq, i);
387 eqe->owner = MLX5_EQE_OWNER_INIT_VAL;
391 int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx,
392 int nent, u64 mask, const char *name, struct mlx5_uar *uar)
394 struct mlx5_priv *priv = &dev->priv;
395 struct mlx5_create_eq_mbox_in *in;
396 struct mlx5_create_eq_mbox_out out;
400 eq->nent = roundup_pow_of_two(nent + MLX5_NUM_SPARE_EQE);
401 err = mlx5_buf_alloc(dev, eq->nent * MLX5_EQE_SIZE, 2 * PAGE_SIZE,
408 inlen = sizeof(*in) + sizeof(in->pas[0]) * eq->buf.npages;
409 in = mlx5_vzalloc(inlen);
414 memset(&out, 0, sizeof(out));
416 mlx5_fill_page_array(&eq->buf, in->pas);
418 in->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_CREATE_EQ);
419 in->ctx.log_sz_usr_page = cpu_to_be32(ilog2(eq->nent) << 24 | uar->index);
420 in->ctx.intr = vecidx;
421 in->ctx.log_page_size = eq->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT;
422 in->events_mask = cpu_to_be64(mask);
424 err = mlx5_cmd_exec(dev, in, inlen, &out, sizeof(out));
428 if (out.hdr.status) {
429 err = mlx5_cmd_status_to_err(&out.hdr);
433 eq->eqn = out.eq_number;
436 eq->doorbell = uar->map + MLX5_EQ_DOORBEL_OFFSET;
437 snprintf(priv->irq_info[vecidx].name, MLX5_MAX_IRQ_NAME, "%s@pci:%s",
438 name, pci_name(dev->pdev));
439 err = request_irq(priv->msix_arr[vecidx].vector, mlx5_msix_handler, 0,
440 priv->irq_info[vecidx].name, eq);
444 if (vecidx >= MLX5_EQ_VEC_COMP_BASE) {
445 u8 bucket = vecidx - MLX5_EQ_VEC_COMP_BASE;
446 err = bind_irq_to_cpu(priv->msix_arr[vecidx].vector,
447 rss_getcpu(bucket % rss_getnumbuckets()));
457 /* EQs are created in ARMED state
465 free_irq(priv->msix_arr[vecidx].vector, eq);
468 mlx5_cmd_destroy_eq(dev, eq->eqn);
474 mlx5_buf_free(dev, &eq->buf);
477 EXPORT_SYMBOL_GPL(mlx5_create_map_eq);
479 int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq)
483 free_irq(dev->priv.msix_arr[eq->irqn].vector, eq);
484 err = mlx5_cmd_destroy_eq(dev, eq->eqn);
486 mlx5_core_warn(dev, "failed to destroy a previously created eq: eqn %d\n",
488 mlx5_buf_free(dev, &eq->buf);
492 EXPORT_SYMBOL_GPL(mlx5_destroy_unmap_eq);
494 int mlx5_eq_init(struct mlx5_core_dev *dev)
498 spin_lock_init(&dev->priv.eq_table.lock);
506 void mlx5_eq_cleanup(struct mlx5_core_dev *dev)
510 int mlx5_start_eqs(struct mlx5_core_dev *dev)
512 struct mlx5_eq_table *table = &dev->priv.eq_table;
513 u64 async_event_mask = MLX5_ASYNC_EVENT_MASK;
516 if (MLX5_CAP_GEN(dev, port_module_event))
517 async_event_mask |= (1ull <<
518 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT);
520 if (MLX5_CAP_GEN(dev, nic_vport_change_event))
521 async_event_mask |= (1ull <<
522 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE);
524 if (MLX5_CAP_GEN(dev, dcbx))
525 async_event_mask |= (1ull <<
526 MLX5_EVENT_TYPE_CODING_DCBX_CHANGE_EVENT);
528 err = mlx5_create_map_eq(dev, &table->cmd_eq, MLX5_EQ_VEC_CMD,
529 MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD,
530 "mlx5_cmd_eq", &dev->priv.uuari.uars[0]);
532 mlx5_core_warn(dev, "failed to create cmd EQ %d\n", err);
536 mlx5_cmd_use_events(dev);
538 err = mlx5_create_map_eq(dev, &table->async_eq, MLX5_EQ_VEC_ASYNC,
539 MLX5_NUM_ASYNC_EQE, async_event_mask,
540 "mlx5_async_eq", &dev->priv.uuari.uars[0]);
542 mlx5_core_warn(dev, "failed to create async EQ %d\n", err);
546 err = mlx5_create_map_eq(dev, &table->pages_eq,
548 /* TODO: sriov max_vf + */ 1,
549 1 << MLX5_EVENT_TYPE_PAGE_REQUEST, "mlx5_pages_eq",
550 &dev->priv.uuari.uars[0]);
552 mlx5_core_warn(dev, "failed to create pages EQ %d\n", err);
559 mlx5_destroy_unmap_eq(dev, &table->async_eq);
562 mlx5_cmd_use_polling(dev);
563 mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
567 int mlx5_stop_eqs(struct mlx5_core_dev *dev)
569 struct mlx5_eq_table *table = &dev->priv.eq_table;
572 err = mlx5_destroy_unmap_eq(dev, &table->pages_eq);
576 mlx5_destroy_unmap_eq(dev, &table->async_eq);
577 mlx5_cmd_use_polling(dev);
579 err = mlx5_destroy_unmap_eq(dev, &table->cmd_eq);
581 mlx5_cmd_use_events(dev);
586 int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq,
587 struct mlx5_query_eq_mbox_out *out, int outlen)
589 struct mlx5_query_eq_mbox_in in;
592 memset(&in, 0, sizeof(in));
593 memset(out, 0, outlen);
594 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_QUERY_EQ);
596 err = mlx5_cmd_exec(dev, &in, sizeof(in), out, outlen);
601 err = mlx5_cmd_status_to_err(&out->hdr);
606 EXPORT_SYMBOL_GPL(mlx5_core_eq_query);
608 static const char *mlx5_port_module_event_error_type_to_string(u8 error_type)
610 switch (error_type) {
611 case MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED:
612 return "Power Budget Exceeded";
613 case MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE:
614 return "Long Range for non MLNX cable/module";
615 case MLX5_MODULE_EVENT_ERROR_BUS_STUCK:
616 return "Bus stuck(I2C or data shorted)";
617 case MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT:
618 return "No EEPROM/retry timeout";
619 case MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST:
620 return "Enforce part number list";
621 case MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER:
622 return "Unknown identifier";
623 case MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE:
624 return "High Temperature";
625 case MLX5_MODULE_EVENT_ERROR_CABLE_IS_SHORTED:
626 return "Cable is shorted";
629 return "Unknown error type";
633 unsigned int mlx5_query_module_status(struct mlx5_core_dev *dev, int module_num)
635 if (module_num < 0 || module_num >= MLX5_MAX_PORTS)
636 return 0; /* undefined */
637 return dev->module_status[module_num];
640 static void mlx5_port_module_event(struct mlx5_core_dev *dev,
641 struct mlx5_eqe *eqe)
643 unsigned int module_num;
644 unsigned int module_status;
645 unsigned int error_type;
646 struct mlx5_eqe_port_module_event *module_event_eqe;
647 struct pci_dev *pdev = dev->pdev;
649 module_event_eqe = &eqe->data.port_module_event;
651 module_num = (unsigned int)module_event_eqe->module;
652 module_status = (unsigned int)module_event_eqe->module_status &
653 PORT_MODULE_EVENT_MODULE_STATUS_MASK;
654 error_type = (unsigned int)module_event_eqe->error_type &
655 PORT_MODULE_EVENT_ERROR_TYPE_MASK;
657 switch (module_status) {
658 case MLX5_MODULE_STATUS_PLUGGED:
659 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: plugged\n", module_num);
662 case MLX5_MODULE_STATUS_UNPLUGGED:
663 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: unplugged\n", module_num);
666 case MLX5_MODULE_STATUS_ERROR:
667 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: error, %s\n", module_num, mlx5_port_module_event_error_type_to_string(error_type));
671 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, unknown status\n", module_num);
673 /* store module status */
674 if (module_num < MLX5_MAX_PORTS)
675 dev->module_status[module_num] = module_status;
678 static void mlx5_port_general_notification_event(struct mlx5_core_dev *dev,
679 struct mlx5_eqe *eqe)
681 u8 port = (eqe->data.port.port >> 4) & 0xf;
683 struct mlx5_eqe_general_notification_event *general_event = NULL;
685 switch (eqe->sub_type) {
686 case MLX5_GEN_EVENT_SUBTYPE_DELAY_DROP_TIMEOUT:
687 general_event = &eqe->data.general_notifications;
688 rqn = be32_to_cpu(general_event->rq_user_index_delay_drop) &
693 "general event with unrecognized subtype: port %d, sub_type %d\n",
694 port, eqe->sub_type);