2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <dev/mlx5/driver.h>
29 #include <linux/module.h>
30 #include "mlx5_core.h"
32 static int mlx5_cmd_query_adapter(struct mlx5_core_dev *dev, u32 *out,
35 u32 in[MLX5_ST_SZ_DW(query_adapter_in)];
38 memset(in, 0, sizeof(in));
40 MLX5_SET(query_adapter_in, in, opcode, MLX5_CMD_OP_QUERY_ADAPTER);
42 err = mlx5_cmd_exec(dev, in, sizeof(in), out, outlen);
46 int mlx5_query_board_id(struct mlx5_core_dev *dev)
49 int outlen = MLX5_ST_SZ_BYTES(query_adapter_out);
52 out = kzalloc(outlen, GFP_KERNEL);
54 err = mlx5_cmd_query_adapter(dev, out, outlen);
59 MLX5_ADDR_OF(query_adapter_out, out,
60 query_adapter_struct.vsd_contd_psid),
61 MLX5_FLD_SZ_BYTES(query_adapter_out,
62 query_adapter_struct.vsd_contd_psid));
70 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id)
73 int outlen = MLX5_ST_SZ_BYTES(query_adapter_out);
76 out = kzalloc(outlen, GFP_KERNEL);
78 err = mlx5_cmd_query_adapter(mdev, out, outlen);
82 *vendor_id = MLX5_GET(query_adapter_out, out,
83 query_adapter_struct.ieee_vendor_id);
90 EXPORT_SYMBOL(mlx5_core_query_vendor_id);
92 static int mlx5_core_query_special_contexts(struct mlx5_core_dev *dev)
94 u32 in[MLX5_ST_SZ_DW(query_special_contexts_in)];
95 u32 out[MLX5_ST_SZ_DW(query_special_contexts_out)];
98 memset(in, 0, sizeof(in));
99 memset(out, 0, sizeof(out));
101 MLX5_SET(query_special_contexts_in, in, opcode,
102 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS);
103 err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
107 dev->special_contexts.resd_lkey = MLX5_GET(query_special_contexts_out,
113 static int mlx5_get_qcam_reg(struct mlx5_core_dev *dev)
115 return mlx5_query_qcam_reg(dev, dev->caps.qcam,
116 MLX5_QCAM_FEATURE_ENHANCED_FEATURES,
117 MLX5_QCAM_REGS_FIRST_128);
120 static int mlx5_get_pcam_reg(struct mlx5_core_dev *dev)
122 return mlx5_query_pcam_reg(dev, dev->caps.pcam,
123 MLX5_PCAM_FEATURE_ENHANCED_FEATURES,
124 MLX5_PCAM_REGS_5000_TO_507F);
127 static int mlx5_get_mcam_reg(struct mlx5_core_dev *dev)
129 return mlx5_query_mcam_reg(dev, dev->caps.mcam,
130 MLX5_MCAM_FEATURE_ENHANCED_FEATURES,
131 MLX5_MCAM_REGS_FIRST_128);
134 int mlx5_query_hca_caps(struct mlx5_core_dev *dev)
138 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
142 if (MLX5_CAP_GEN(dev, eth_net_offloads)) {
143 err = mlx5_core_get_caps(dev, MLX5_CAP_ETHERNET_OFFLOADS);
148 if (MLX5_CAP_GEN(dev, pg)) {
149 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
154 if (MLX5_CAP_GEN(dev, atomic)) {
155 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
160 if (MLX5_CAP_GEN(dev, roce)) {
161 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE);
166 if ((MLX5_CAP_GEN(dev, port_type) ==
167 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET &&
168 MLX5_CAP_GEN(dev, nic_flow_table)) ||
169 (MLX5_CAP_GEN(dev, port_type) == MLX5_CMD_HCA_CAP_PORT_TYPE_IB &&
170 MLX5_CAP_GEN(dev, ipoib_enhanced_offloads))) {
171 err = mlx5_core_get_caps(dev, MLX5_CAP_FLOW_TABLE);
176 if (MLX5_CAP_GEN(dev, eswitch_flow_table)) {
177 err = mlx5_core_get_caps(dev, MLX5_CAP_ESWITCH_FLOW_TABLE);
182 if (MLX5_CAP_GEN(dev, vport_group_manager)) {
183 err = mlx5_core_get_caps(dev, MLX5_CAP_ESWITCH);
188 if (MLX5_CAP_GEN(dev, snapshot)) {
189 err = mlx5_core_get_caps(dev, MLX5_CAP_SNAPSHOT);
194 if (MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) {
195 err = mlx5_core_get_caps(dev, MLX5_CAP_EOIB_OFFLOADS);
200 if (MLX5_CAP_GEN(dev, debug)) {
201 err = mlx5_core_get_caps(dev, MLX5_CAP_DEBUG);
206 if (MLX5_CAP_GEN(dev, qos)) {
207 err = mlx5_core_get_caps(dev, MLX5_CAP_QOS);
212 if (MLX5_CAP_GEN(dev, qcam_reg)) {
213 err = mlx5_get_qcam_reg(dev);
218 if (MLX5_CAP_GEN(dev, mcam_reg)) {
219 err = mlx5_get_mcam_reg(dev);
224 if (MLX5_CAP_GEN(dev, pcam_reg)) {
225 err = mlx5_get_pcam_reg(dev);
230 if (MLX5_CAP_GEN(dev, tls)) {
231 err = mlx5_core_get_caps(dev, MLX5_CAP_TLS);
236 err = mlx5_core_query_special_contexts(dev);
243 int mlx5_cmd_init_hca(struct mlx5_core_dev *dev)
245 u32 in[MLX5_ST_SZ_DW(init_hca_in)];
246 u32 out[MLX5_ST_SZ_DW(init_hca_out)];
248 memset(in, 0, sizeof(in));
250 MLX5_SET(init_hca_in, in, opcode, MLX5_CMD_OP_INIT_HCA);
252 memset(out, 0, sizeof(out));
253 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
256 int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev)
258 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0};
259 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0};
261 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
262 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
265 int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev)
267 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0};
268 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0};
272 if (!MLX5_CAP_GEN(dev, force_teardown)) {
273 mlx5_core_dbg(dev, "force teardown is not supported in the firmware\n");
277 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
278 MLX5_SET(teardown_hca_in, in, profile, MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE);
280 ret = mlx5_cmd_exec_polling(dev, in, sizeof(in), out, sizeof(out));
284 force_state = MLX5_GET(teardown_hca_out, out, state);
285 if (force_state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL) {
286 mlx5_core_err(dev, "teardown with force mode failed\n");
293 #define MLX5_FAST_TEARDOWN_WAIT_MS 3000
294 int mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev *dev)
296 int end, delay_ms = MLX5_FAST_TEARDOWN_WAIT_MS;
297 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {};
298 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {};
302 if (!MLX5_CAP_GEN(dev, fast_teardown)) {
303 mlx5_core_dbg(dev, "fast teardown is not supported in the firmware\n");
307 MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
308 MLX5_SET(teardown_hca_in, in, profile,
309 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN);
311 ret = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
315 state = MLX5_GET(teardown_hca_out, out, state);
316 if (state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL) {
317 mlx5_core_warn(dev, "teardown with fast mode failed\n");
321 mlx5_set_nic_state(dev, MLX5_NIC_IFC_DISABLED);
323 /* Loop until device state turns to disable */
324 end = jiffies + msecs_to_jiffies(delay_ms);
326 if (mlx5_get_nic_state(dev) == MLX5_NIC_IFC_DISABLED)
330 } while (!time_after(jiffies, end));
332 if (mlx5_get_nic_state(dev) != MLX5_NIC_IFC_DISABLED) {
333 mlx5_core_err(dev, "NIC IFC still %d after %ums.\n",
334 mlx5_get_nic_state(dev), delay_ms);
340 int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable,
343 u32 in[MLX5_ST_SZ_DW(set_dc_cnak_trace_in)] = {0};
344 u32 out[MLX5_ST_SZ_DW(set_dc_cnak_trace_out)] = {0};
348 MLX5_SET(set_dc_cnak_trace_in, in, opcode, MLX5_CMD_OP_SET_DC_CNAK_TRACE);
349 MLX5_SET(set_dc_cnak_trace_in, in, enable, enable);
350 pas = MLX5_ADDR_OF(set_dc_cnak_trace_in, in, pas);
351 be_addr = cpu_to_be64(addr);
352 memcpy(MLX5_ADDR_OF(cmd_pas, pas, pa_h), &be_addr, sizeof(be_addr));
354 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
357 enum mlxsw_reg_mcc_instruction {
358 MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01,
359 MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02,
360 MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03,
361 MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04,
362 MLX5_REG_MCC_INSTRUCTION_ACTIVATE = 0x06,
363 MLX5_REG_MCC_INSTRUCTION_CANCEL = 0x08,
366 static int mlx5_reg_mcc_set(struct mlx5_core_dev *dev,
367 enum mlxsw_reg_mcc_instruction instr,
368 u16 component_index, u32 update_handle,
371 u32 out[MLX5_ST_SZ_DW(mcc_reg)];
372 u32 in[MLX5_ST_SZ_DW(mcc_reg)];
374 memset(in, 0, sizeof(in));
376 MLX5_SET(mcc_reg, in, instruction, instr);
377 MLX5_SET(mcc_reg, in, component_index, component_index);
378 MLX5_SET(mcc_reg, in, update_handle, update_handle);
379 MLX5_SET(mcc_reg, in, component_size, component_size);
381 return mlx5_core_access_reg(dev, in, sizeof(in), out,
382 sizeof(out), MLX5_REG_MCC, 0, 1);
385 static int mlx5_reg_mcc_query(struct mlx5_core_dev *dev,
386 u32 *update_handle, u8 *error_code,
389 u32 out[MLX5_ST_SZ_DW(mcc_reg)];
390 u32 in[MLX5_ST_SZ_DW(mcc_reg)];
393 memset(in, 0, sizeof(in));
394 memset(out, 0, sizeof(out));
395 MLX5_SET(mcc_reg, in, update_handle, *update_handle);
397 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
398 sizeof(out), MLX5_REG_MCC, 0, 0);
402 *update_handle = MLX5_GET(mcc_reg, out, update_handle);
403 *error_code = MLX5_GET(mcc_reg, out, error_code);
404 *control_state = MLX5_GET(mcc_reg, out, control_state);
410 static int mlx5_reg_mcda_set(struct mlx5_core_dev *dev,
412 u32 offset, u16 size,
415 int err, in_size = MLX5_ST_SZ_BYTES(mcda_reg) + size;
416 u32 out[MLX5_ST_SZ_DW(mcda_reg)];
417 int i, j, dw_size = size >> 2;
421 in = kzalloc(in_size, GFP_KERNEL);
425 MLX5_SET(mcda_reg, in, update_handle, update_handle);
426 MLX5_SET(mcda_reg, in, offset, offset);
427 MLX5_SET(mcda_reg, in, size, size);
429 for (i = 0; i < dw_size; i++) {
431 data_element = htonl(*(u32 *)&data[j]);
432 memcpy(MLX5_ADDR_OF(mcda_reg, in, data) + j, &data_element, 4);
435 err = mlx5_core_access_reg(dev, in, in_size, out,
436 sizeof(out), MLX5_REG_MCDA, 0, 1);
441 static int mlx5_reg_mcqi_query(struct mlx5_core_dev *dev,
443 u32 *max_component_size,
444 u8 *log_mcda_word_size,
445 u16 *mcda_max_write_size)
447 u32 out[MLX5_ST_SZ_DW(mcqi_reg) + MLX5_ST_SZ_DW(mcqi_cap)];
448 int offset = MLX5_ST_SZ_DW(mcqi_reg);
449 u32 in[MLX5_ST_SZ_DW(mcqi_reg)];
452 memset(in, 0, sizeof(in));
453 memset(out, 0, sizeof(out));
455 MLX5_SET(mcqi_reg, in, component_index, component_index);
456 MLX5_SET(mcqi_reg, in, data_size, MLX5_ST_SZ_BYTES(mcqi_cap));
458 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
459 sizeof(out), MLX5_REG_MCQI, 0, 0);
463 *max_component_size = MLX5_GET(mcqi_cap, out + offset, max_component_size);
464 *log_mcda_word_size = MLX5_GET(mcqi_cap, out + offset, log_mcda_word_size);
465 *mcda_max_write_size = MLX5_GET(mcqi_cap, out + offset, mcda_max_write_size);
471 struct mlx5_mlxfw_dev {
472 struct mlxfw_dev mlxfw_dev;
473 struct mlx5_core_dev *mlx5_core_dev;
476 static int mlx5_component_query(struct mlxfw_dev *mlxfw_dev,
477 u16 component_index, u32 *p_max_size,
478 u8 *p_align_bits, u16 *p_max_write_size)
480 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
481 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
482 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
484 return mlx5_reg_mcqi_query(dev, component_index, p_max_size,
485 p_align_bits, p_max_write_size);
488 static int mlx5_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
490 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
491 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
492 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
493 u8 control_state, error_code;
497 err = mlx5_reg_mcc_query(dev, fwhandle, &error_code, &control_state);
501 if (control_state != MLXFW_FSM_STATE_IDLE)
504 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
508 static int mlx5_fsm_component_update(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
509 u16 component_index, u32 component_size)
511 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
512 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
513 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
515 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
516 component_index, fwhandle, component_size);
519 static int mlx5_fsm_block_download(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
520 u8 *data, u16 size, u32 offset)
522 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
523 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
524 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
526 return mlx5_reg_mcda_set(dev, fwhandle, offset, size, data);
529 static int mlx5_fsm_component_verify(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
532 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
533 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
534 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
536 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
537 component_index, fwhandle, 0);
540 static int mlx5_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
542 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
543 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
544 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
546 return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_ACTIVATE, 0,
550 static int mlx5_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
551 enum mlxfw_fsm_state *fsm_state,
552 enum mlxfw_fsm_state_err *fsm_state_err)
554 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
555 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
556 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
557 u8 control_state, error_code;
560 err = mlx5_reg_mcc_query(dev, &fwhandle, &error_code, &control_state);
564 *fsm_state = control_state;
565 *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
566 MLXFW_FSM_STATE_ERR_MAX);
570 static void mlx5_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
572 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
573 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
574 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
576 mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_CANCEL, 0, fwhandle, 0);
579 static void mlx5_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
581 struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
582 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
583 struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
585 mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
589 static const struct mlxfw_dev_ops mlx5_mlxfw_dev_ops = {
590 .component_query = mlx5_component_query,
591 .fsm_lock = mlx5_fsm_lock,
592 .fsm_component_update = mlx5_fsm_component_update,
593 .fsm_block_download = mlx5_fsm_block_download,
594 .fsm_component_verify = mlx5_fsm_component_verify,
595 .fsm_activate = mlx5_fsm_activate,
596 .fsm_query_state = mlx5_fsm_query_state,
597 .fsm_cancel = mlx5_fsm_cancel,
598 .fsm_release = mlx5_fsm_release
601 int mlx5_firmware_flash(struct mlx5_core_dev *dev,
602 const struct firmware *firmware)
604 struct mlx5_mlxfw_dev mlx5_mlxfw_dev = {
606 .ops = &mlx5_mlxfw_dev_ops,
607 .psid = dev->board_id,
608 .psid_size = strlen(dev->board_id),
613 if (!MLX5_CAP_GEN(dev, mcam_reg) ||
614 !MLX5_CAP_MCAM_REG(dev, mcqi) ||
615 !MLX5_CAP_MCAM_REG(dev, mcc) ||
616 !MLX5_CAP_MCAM_REG(dev, mcda)) {
617 pr_info("%s flashing isn't supported by the running FW\n", __func__);
621 return mlxfw_firmware_flash(&mlx5_mlxfw_dev.mlxfw_dev, firmware);