sys/dev/mlx5/mlx5_core/mlx5_fw.c

   1 /*-
   2  * Copyright (c) 2013-2017, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include <dev/mlx5/driver.h>
  29 #include <linux/module.h>
  30 #include "mlx5_core.h"
  31
  32 static int mlx5_cmd_query_adapter(struct mlx5_core_dev *dev, u32 *out,
  33                                   int outlen)
  34 {
  35         u32 in[MLX5_ST_SZ_DW(query_adapter_in)];
  36         int err;
  37
  38         memset(in, 0, sizeof(in));
  39
  40         MLX5_SET(query_adapter_in, in, opcode, MLX5_CMD_OP_QUERY_ADAPTER);
  41
  42         err = mlx5_cmd_exec(dev, in, sizeof(in), out, outlen);
  43         return err;
  44 }
  45
  46 int mlx5_query_board_id(struct mlx5_core_dev *dev)
  47 {
  48         u32 *out;
  49         int outlen = MLX5_ST_SZ_BYTES(query_adapter_out);
  50         int err;
  51
  52         out = kzalloc(outlen, GFP_KERNEL);
  53
  54         err = mlx5_cmd_query_adapter(dev, out, outlen);
  55         if (err)
  56                 goto out_out;
  57
  58         memcpy(dev->board_id,
  59                MLX5_ADDR_OF(query_adapter_out, out,
  60                             query_adapter_struct.vsd_contd_psid),
  61                MLX5_FLD_SZ_BYTES(query_adapter_out,
  62                                  query_adapter_struct.vsd_contd_psid));
  63
  64 out_out:
  65         kfree(out);
  66
  67         return err;
  68 }
  69
  70 int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id)
  71 {
  72         u32 *out;
  73         int outlen = MLX5_ST_SZ_BYTES(query_adapter_out);
  74         int err;
  75
  76         out = kzalloc(outlen, GFP_KERNEL);
  77
  78         err = mlx5_cmd_query_adapter(mdev, out, outlen);
  79         if (err)
  80                 goto out_out;
  81
  82         *vendor_id = MLX5_GET(query_adapter_out, out,
  83                               query_adapter_struct.ieee_vendor_id);
  84
  85 out_out:
  86         kfree(out);
  87
  88         return err;
  89 }
  90 EXPORT_SYMBOL(mlx5_core_query_vendor_id);
  91
  92 static int mlx5_core_query_special_contexts(struct mlx5_core_dev *dev)
  93 {
  94         u32 in[MLX5_ST_SZ_DW(query_special_contexts_in)];
  95         u32 out[MLX5_ST_SZ_DW(query_special_contexts_out)];
  96         int err;
  97
  98         memset(in, 0, sizeof(in));
  99         memset(out, 0, sizeof(out));
 100
 101         MLX5_SET(query_special_contexts_in, in, opcode,
 102                  MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS);
 103         err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
 104         if (err)
 105                 return err;
 106
 107         dev->special_contexts.resd_lkey = MLX5_GET(query_special_contexts_out,
 108                                                    out, resd_lkey);
 109
 110         return err;
 111 }
 112
 113 static int mlx5_get_qcam_reg(struct mlx5_core_dev *dev)
 114 {
 115         return mlx5_query_qcam_reg(dev, dev->caps.qcam,
 116                                    MLX5_QCAM_FEATURE_ENHANCED_FEATURES,
 117                                    MLX5_QCAM_REGS_FIRST_128);
 118 }
 119
 120 static int mlx5_get_pcam_reg(struct mlx5_core_dev *dev)
 121 {
 122         return mlx5_query_pcam_reg(dev, dev->caps.pcam,
 123                                    MLX5_PCAM_FEATURE_ENHANCED_FEATURES,
 124                                    MLX5_PCAM_REGS_5000_TO_507F);
 125 }
 126
 127 static int mlx5_get_mcam_reg(struct mlx5_core_dev *dev)
 128 {
 129         return mlx5_query_mcam_reg(dev, dev->caps.mcam,
 130                                    MLX5_MCAM_FEATURE_ENHANCED_FEATURES,
 131                                    MLX5_MCAM_REGS_FIRST_128);
 132 }
 133
 134 int mlx5_query_hca_caps(struct mlx5_core_dev *dev)
 135 {
 136         int err;
 137
 138         err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
 139         if (err)
 140                 return err;
 141
 142         if (MLX5_CAP_GEN(dev, eth_net_offloads)) {
 143                 err = mlx5_core_get_caps(dev, MLX5_CAP_ETHERNET_OFFLOADS);
 144                 if (err)
 145                         return err;
 146         }
 147
 148         if (MLX5_CAP_GEN(dev, pg)) {
 149                 err = mlx5_core_get_caps(dev, MLX5_CAP_ODP);
 150                 if (err)
 151                         return err;
 152         }
 153
 154         if (MLX5_CAP_GEN(dev, atomic)) {
 155                 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
 156                 if (err)
 157                         return err;
 158         }
 159
 160         if (MLX5_CAP_GEN(dev, roce)) {
 161                 err = mlx5_core_get_caps(dev, MLX5_CAP_ROCE);
 162                 if (err)
 163                         return err;
 164         }
 165
 166         if ((MLX5_CAP_GEN(dev, port_type) ==
 167             MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET &&
 168             MLX5_CAP_GEN(dev, nic_flow_table)) ||
 169             (MLX5_CAP_GEN(dev, port_type) == MLX5_CMD_HCA_CAP_PORT_TYPE_IB &&
 170             MLX5_CAP_GEN(dev, ipoib_enhanced_offloads))) {
 171                 err = mlx5_core_get_caps(dev, MLX5_CAP_FLOW_TABLE);
 172                 if (err)
 173                         return err;
 174         }
 175
 176         if (MLX5_CAP_GEN(dev, eswitch_flow_table)) {
 177                 err = mlx5_core_get_caps(dev, MLX5_CAP_ESWITCH_FLOW_TABLE);
 178                 if (err)
 179                         return err;
 180         }
 181
 182         if (MLX5_CAP_GEN(dev, vport_group_manager)) {
 183                 err = mlx5_core_get_caps(dev, MLX5_CAP_ESWITCH);
 184                 if (err)
 185                         return err;
 186         }
 187
 188         if (MLX5_CAP_GEN(dev, snapshot)) {
 189                 err = mlx5_core_get_caps(dev, MLX5_CAP_SNAPSHOT);
 190                 if (err)
 191                         return err;
 192         }
 193
 194         if (MLX5_CAP_GEN(dev, ipoib_enhanced_offloads)) {
 195                 err = mlx5_core_get_caps(dev, MLX5_CAP_EOIB_OFFLOADS);
 196                 if (err)
 197                         return err;
 198         }
 199
 200         if (MLX5_CAP_GEN(dev, debug)) {
 201                 err = mlx5_core_get_caps(dev, MLX5_CAP_DEBUG);
 202                 if (err)
 203                         return err;
 204         }
 205
 206         if (MLX5_CAP_GEN(dev, qos)) {
 207                 err = mlx5_core_get_caps(dev, MLX5_CAP_QOS);
 208                 if (err)
 209                         return err;
 210         }
 211
 212         if (MLX5_CAP_GEN(dev, qcam_reg)) {
 213                 err = mlx5_get_qcam_reg(dev);
 214                 if (err)
 215                         return err;
 216         }
 217
 218         if (MLX5_CAP_GEN(dev, mcam_reg)) {
 219                 err = mlx5_get_mcam_reg(dev);
 220                 if (err)
 221                         return err;
 222         }
 223
 224         err = mlx5_core_query_special_contexts(dev);
 225         if (err)
 226                 return err;
 227
 228         return 0;
 229 }
 230
 231 int mlx5_cmd_init_hca(struct mlx5_core_dev *dev)
 232 {
 233         u32 in[MLX5_ST_SZ_DW(init_hca_in)];
 234         u32 out[MLX5_ST_SZ_DW(init_hca_out)];
 235
 236         memset(in, 0, sizeof(in));
 237
 238         MLX5_SET(init_hca_in, in, opcode, MLX5_CMD_OP_INIT_HCA);
 239
 240         memset(out, 0, sizeof(out));
 241         return mlx5_cmd_exec(dev, in,  sizeof(in), out, sizeof(out));
 242 }
 243
 244 int mlx5_cmd_teardown_hca(struct mlx5_core_dev *dev)
 245 {
 246         u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0};
 247         u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0};
 248
 249         MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
 250         return mlx5_cmd_exec(dev, in,  sizeof(in), out, sizeof(out));
 251 }
 252
 253 int mlx5_cmd_force_teardown_hca(struct mlx5_core_dev *dev)
 254 {
 255         u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0};
 256         u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0};
 257         int force_state;
 258         int ret;
 259
 260         if (!MLX5_CAP_GEN(dev, force_teardown)) {
 261                 mlx5_core_dbg(dev, "force teardown is not supported in the firmware\n");
 262                 return -EOPNOTSUPP;
 263         }
 264
 265         MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
 266         MLX5_SET(teardown_hca_in, in, profile, MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE);
 267
 268         ret = mlx5_cmd_exec_polling(dev, in, sizeof(in), out, sizeof(out));
 269         if (ret)
 270                 return ret;
 271
 272         force_state = MLX5_GET(teardown_hca_out, out, state);
 273         if (force_state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL)  {
 274                 mlx5_core_err(dev, "teardown with force mode failed\n");
 275                 return -EIO;
 276         }
 277
 278         return 0;
 279 }
 280
 281 #define MLX5_FAST_TEARDOWN_WAIT_MS 3000
 282 int mlx5_cmd_fast_teardown_hca(struct mlx5_core_dev *dev)
 283 {
 284         int end, delay_ms = MLX5_FAST_TEARDOWN_WAIT_MS;
 285         u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {};
 286         u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {};
 287         int state;
 288         int ret;
 289
 290         if (!MLX5_CAP_GEN(dev, fast_teardown)) {
 291                 mlx5_core_dbg(dev, "fast teardown is not supported in the firmware\n");
 292                 return -EOPNOTSUPP;
 293         }
 294
 295         MLX5_SET(teardown_hca_in, in, opcode, MLX5_CMD_OP_TEARDOWN_HCA);
 296         MLX5_SET(teardown_hca_in, in, profile,
 297                  MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN);
 298
 299         ret = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
 300         if (ret)
 301                 return ret;
 302
 303         state = MLX5_GET(teardown_hca_out, out, state);
 304         if (state == MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL) {
 305                 mlx5_core_warn(dev, "teardown with fast mode failed\n");
 306                 return -EIO;
 307         }
 308
 309         mlx5_set_nic_state(dev, MLX5_NIC_IFC_DISABLED);
 310
 311         /* Loop until device state turns to disable */
 312         end = jiffies + msecs_to_jiffies(delay_ms);
 313         do {
 314                 if (mlx5_get_nic_state(dev) == MLX5_NIC_IFC_DISABLED)
 315                         break;
 316
 317                 pause("W", 1);
 318         } while (!time_after(jiffies, end));
 319
 320         if (mlx5_get_nic_state(dev) != MLX5_NIC_IFC_DISABLED) {
 321                 dev_err(&dev->pdev->dev, "NIC IFC still %d after %ums.\n",
 322                         mlx5_get_nic_state(dev), delay_ms);
 323                 return -EIO;
 324         }
 325         return 0;
 326 }
 327
 328 int mlx5_core_set_dc_cnak_trace(struct mlx5_core_dev *dev, int enable,
 329                                 u64 addr)
 330 {
 331         u32 in[MLX5_ST_SZ_DW(set_dc_cnak_trace_in)] = {0};
 332         u32 out[MLX5_ST_SZ_DW(set_dc_cnak_trace_out)] = {0};
 333         __be64 be_addr;
 334         void *pas;
 335
 336         MLX5_SET(set_dc_cnak_trace_in, in, opcode, MLX5_CMD_OP_SET_DC_CNAK_TRACE);
 337         MLX5_SET(set_dc_cnak_trace_in, in, enable, enable);
 338         pas = MLX5_ADDR_OF(set_dc_cnak_trace_in, in, pas);
 339         be_addr = cpu_to_be64(addr);
 340         memcpy(MLX5_ADDR_OF(cmd_pas, pas, pa_h), &be_addr, sizeof(be_addr));
 341
 342         return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
 343 }
 344
 345 enum mlxsw_reg_mcc_instruction {
 346         MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01,
 347         MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02,
 348         MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03,
 349         MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04,
 350         MLX5_REG_MCC_INSTRUCTION_ACTIVATE = 0x06,
 351         MLX5_REG_MCC_INSTRUCTION_CANCEL = 0x08,
 352 };
 353
 354 static int mlx5_reg_mcc_set(struct mlx5_core_dev *dev,
 355                             enum mlxsw_reg_mcc_instruction instr,
 356                             u16 component_index, u32 update_handle,
 357                             u32 component_size)
 358 {
 359         u32 out[MLX5_ST_SZ_DW(mcc_reg)];
 360         u32 in[MLX5_ST_SZ_DW(mcc_reg)];
 361
 362         memset(in, 0, sizeof(in));
 363
 364         MLX5_SET(mcc_reg, in, instruction, instr);
 365         MLX5_SET(mcc_reg, in, component_index, component_index);
 366         MLX5_SET(mcc_reg, in, update_handle, update_handle);
 367         MLX5_SET(mcc_reg, in, component_size, component_size);
 368
 369         return mlx5_core_access_reg(dev, in, sizeof(in), out,
 370                                     sizeof(out), MLX5_REG_MCC, 0, 1);
 371 }
 372
 373 static int mlx5_reg_mcc_query(struct mlx5_core_dev *dev,
 374                               u32 *update_handle, u8 *error_code,
 375                               u8 *control_state)
 376 {
 377         u32 out[MLX5_ST_SZ_DW(mcc_reg)];
 378         u32 in[MLX5_ST_SZ_DW(mcc_reg)];
 379         int err;
 380
 381         memset(in, 0, sizeof(in));
 382         memset(out, 0, sizeof(out));
 383         MLX5_SET(mcc_reg, in, update_handle, *update_handle);
 384
 385         err = mlx5_core_access_reg(dev, in, sizeof(in), out,
 386                                    sizeof(out), MLX5_REG_MCC, 0, 0);
 387         if (err)
 388                 goto out;
 389
 390         *update_handle = MLX5_GET(mcc_reg, out, update_handle);
 391         *error_code = MLX5_GET(mcc_reg, out, error_code);
 392         *control_state = MLX5_GET(mcc_reg, out, control_state);
 393
 394 out:
 395         return err;
 396 }
 397
 398 static int mlx5_reg_mcda_set(struct mlx5_core_dev *dev,
 399                              u32 update_handle,
 400                              u32 offset, u16 size,
 401                              u8 *data)
 402 {
 403         int err, in_size = MLX5_ST_SZ_BYTES(mcda_reg) + size;
 404         u32 out[MLX5_ST_SZ_DW(mcda_reg)];
 405         int i, j, dw_size = size >> 2;
 406         __be32 data_element;
 407         u32 *in;
 408
 409         in = kzalloc(in_size, GFP_KERNEL);
 410         if (!in)
 411                 return -ENOMEM;
 412
 413         MLX5_SET(mcda_reg, in, update_handle, update_handle);
 414         MLX5_SET(mcda_reg, in, offset, offset);
 415         MLX5_SET(mcda_reg, in, size, size);
 416
 417         for (i = 0; i < dw_size; i++) {
 418                 j = i * 4;
 419                 data_element = htonl(*(u32 *)&data[j]);
 420                 memcpy(MLX5_ADDR_OF(mcda_reg, in, data) + j, &data_element, 4);
 421         }
 422
 423         err = mlx5_core_access_reg(dev, in, in_size, out,
 424                                    sizeof(out), MLX5_REG_MCDA, 0, 1);
 425         kfree(in);
 426         return err;
 427 }
 428
 429 static int mlx5_reg_mcqi_query(struct mlx5_core_dev *dev,
 430                                u16 component_index,
 431                                u32 *max_component_size,
 432                                u8 *log_mcda_word_size,
 433                                u16 *mcda_max_write_size)
 434 {
 435         u32 out[MLX5_ST_SZ_DW(mcqi_reg) + MLX5_ST_SZ_DW(mcqi_cap)];
 436         int offset = MLX5_ST_SZ_DW(mcqi_reg);
 437         u32 in[MLX5_ST_SZ_DW(mcqi_reg)];
 438         int err;
 439
 440         memset(in, 0, sizeof(in));
 441         memset(out, 0, sizeof(out));
 442
 443         MLX5_SET(mcqi_reg, in, component_index, component_index);
 444         MLX5_SET(mcqi_reg, in, data_size, MLX5_ST_SZ_BYTES(mcqi_cap));
 445
 446         err = mlx5_core_access_reg(dev, in, sizeof(in), out,
 447                                    sizeof(out), MLX5_REG_MCQI, 0, 0);
 448         if (err)
 449                 goto out;
 450
 451         *max_component_size = MLX5_GET(mcqi_cap, out + offset, max_component_size);
 452         *log_mcda_word_size = MLX5_GET(mcqi_cap, out + offset, log_mcda_word_size);
 453         *mcda_max_write_size = MLX5_GET(mcqi_cap, out + offset, mcda_max_write_size);
 454
 455 out:
 456         return err;
 457 }
 458
 459 struct mlx5_mlxfw_dev {
 460         struct mlxfw_dev mlxfw_dev;
 461         struct mlx5_core_dev *mlx5_core_dev;
 462 };
 463
 464 static int mlx5_component_query(struct mlxfw_dev *mlxfw_dev,
 465                                 u16 component_index, u32 *p_max_size,
 466                                 u8 *p_align_bits, u16 *p_max_write_size)
 467 {
 468         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 469                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 470         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 471
 472         return mlx5_reg_mcqi_query(dev, component_index, p_max_size,
 473                                    p_align_bits, p_max_write_size);
 474 }
 475
 476 static int mlx5_fsm_lock(struct mlxfw_dev *mlxfw_dev, u32 *fwhandle)
 477 {
 478         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 479                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 480         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 481         u8 control_state, error_code;
 482         int err;
 483
 484         *fwhandle = 0;
 485         err = mlx5_reg_mcc_query(dev, fwhandle, &error_code, &control_state);
 486         if (err)
 487                 return err;
 488
 489         if (control_state != MLXFW_FSM_STATE_IDLE)
 490                 return -EBUSY;
 491
 492         return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE,
 493                                 0, *fwhandle, 0);
 494 }
 495
 496 static int mlx5_fsm_component_update(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
 497                                      u16 component_index, u32 component_size)
 498 {
 499         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 500                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 501         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 502
 503         return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_UPDATE_COMPONENT,
 504                                 component_index, fwhandle, component_size);
 505 }
 506
 507 static int mlx5_fsm_block_download(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
 508                                    u8 *data, u16 size, u32 offset)
 509 {
 510         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 511                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 512         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 513
 514         return mlx5_reg_mcda_set(dev, fwhandle, offset, size, data);
 515 }
 516
 517 static int mlx5_fsm_component_verify(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
 518                                      u16 component_index)
 519 {
 520         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 521                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 522         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 523
 524         return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_VERIFY_COMPONENT,
 525                                 component_index, fwhandle, 0);
 526 }
 527
 528 static int mlx5_fsm_activate(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
 529 {
 530         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 531                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 532         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 533
 534         return mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_ACTIVATE, 0,
 535                                 fwhandle, 0);
 536 }
 537
 538 static int mlx5_fsm_query_state(struct mlxfw_dev *mlxfw_dev, u32 fwhandle,
 539                                 enum mlxfw_fsm_state *fsm_state,
 540                                 enum mlxfw_fsm_state_err *fsm_state_err)
 541 {
 542         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 543                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 544         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 545         u8 control_state, error_code;
 546         int err;
 547
 548         err = mlx5_reg_mcc_query(dev, &fwhandle, &error_code, &control_state);
 549         if (err)
 550                 return err;
 551
 552         *fsm_state = control_state;
 553         *fsm_state_err = min_t(enum mlxfw_fsm_state_err, error_code,
 554                                MLXFW_FSM_STATE_ERR_MAX);
 555         return 0;
 556 }
 557
 558 static void mlx5_fsm_cancel(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
 559 {
 560         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 561                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 562         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 563
 564         mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_CANCEL, 0, fwhandle, 0);
 565 }
 566
 567 static void mlx5_fsm_release(struct mlxfw_dev *mlxfw_dev, u32 fwhandle)
 568 {
 569         struct mlx5_mlxfw_dev *mlx5_mlxfw_dev =
 570                 container_of(mlxfw_dev, struct mlx5_mlxfw_dev, mlxfw_dev);
 571         struct mlx5_core_dev *dev = mlx5_mlxfw_dev->mlx5_core_dev;
 572
 573         mlx5_reg_mcc_set(dev, MLX5_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE, 0,
 574                          fwhandle, 0);
 575 }
 576
 577 static const struct mlxfw_dev_ops mlx5_mlxfw_dev_ops = {
 578         .component_query        = mlx5_component_query,
 579         .fsm_lock               = mlx5_fsm_lock,
 580         .fsm_component_update   = mlx5_fsm_component_update,
 581         .fsm_block_download     = mlx5_fsm_block_download,
 582         .fsm_component_verify   = mlx5_fsm_component_verify,
 583         .fsm_activate           = mlx5_fsm_activate,
 584         .fsm_query_state        = mlx5_fsm_query_state,
 585         .fsm_cancel             = mlx5_fsm_cancel,
 586         .fsm_release            = mlx5_fsm_release
 587 };
 588
 589 int mlx5_firmware_flash(struct mlx5_core_dev *dev,
 590                         const struct firmware *firmware)
 591 {
 592         struct mlx5_mlxfw_dev mlx5_mlxfw_dev = {
 593                 .mlxfw_dev = {
 594                         .ops = &mlx5_mlxfw_dev_ops,
 595                         .psid = dev->board_id,
 596                         .psid_size = strlen(dev->board_id),
 597                 },
 598                 .mlx5_core_dev = dev
 599         };
 600
 601         if (!MLX5_CAP_GEN(dev, mcam_reg)  ||
 602             !MLX5_CAP_MCAM_REG(dev, mcqi) ||
 603             !MLX5_CAP_MCAM_REG(dev, mcc)  ||
 604             !MLX5_CAP_MCAM_REG(dev, mcda)) {
 605                 pr_info("%s flashing isn't supported by the running FW\n", __func__);
 606                 return -EOPNOTSUPP;
 607         }
 608
 609         return mlxfw_firmware_flash(&mlx5_mlxfw_dev.mlxfw_dev, firmware);
 610 }