2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #define LINUXKPI_PARAM_PREFIX mlx5_
30 #include <linux/kmod.h>
31 #include <linux/module.h>
32 #include <linux/errno.h>
33 #include <linux/pci.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/slab.h>
36 #include <linux/io-mapping.h>
37 #include <linux/interrupt.h>
38 #include <dev/mlx5/driver.h>
39 #include <dev/mlx5/cq.h>
40 #include <dev/mlx5/qp.h>
41 #include <dev/mlx5/srq.h>
42 #include <linux/delay.h>
43 #include <dev/mlx5/mlx5_ifc.h>
44 #include "mlx5_core.h"
46 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
47 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
48 MODULE_LICENSE("Dual BSD/GPL");
49 #if (__FreeBSD_version >= 1100000)
50 MODULE_DEPEND(mlx5, linuxkpi, 1, 1, 1);
52 MODULE_VERSION(mlx5, 1);
54 int mlx5_core_debug_mask;
55 module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
56 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
58 #define MLX5_DEFAULT_PROF 2
59 static int prof_sel = MLX5_DEFAULT_PROF;
60 module_param_named(prof_sel, prof_sel, int, 0444);
61 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
63 #define NUMA_NO_NODE -1
65 struct workqueue_struct *mlx5_core_wq;
66 static LIST_HEAD(intf_list);
67 static LIST_HEAD(dev_list);
68 static DEFINE_MUTEX(intf_mutex);
70 struct mlx5_device_context {
71 struct list_head list;
72 struct mlx5_interface *intf;
76 static struct mlx5_profile profiles[] = {
81 .mask = MLX5_PROF_MASK_QP_SIZE,
85 .mask = MLX5_PROF_MASK_QP_SIZE |
86 MLX5_PROF_MASK_MR_CACHE,
150 .mask = MLX5_PROF_MASK_QP_SIZE,
155 static int set_dma_caps(struct pci_dev *pdev)
159 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
161 device_printf((&pdev->dev)->bsddev, "WARN: ""Warning: couldn't set 64-bit PCI DMA mask\n");
162 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
164 device_printf((&pdev->dev)->bsddev, "ERR: ""Can't set PCI DMA mask, aborting\n");
169 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
171 device_printf((&pdev->dev)->bsddev, "WARN: ""Warning: couldn't set 64-bit consistent PCI DMA mask\n");
172 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
174 device_printf((&pdev->dev)->bsddev, "ERR: ""Can't set consistent PCI DMA mask, aborting\n");
179 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
183 static int request_bar(struct pci_dev *pdev)
187 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
188 device_printf((&pdev->dev)->bsddev, "ERR: ""Missing registers BAR, aborting\n");
192 err = pci_request_regions(pdev, DRIVER_NAME);
194 device_printf((&pdev->dev)->bsddev, "ERR: ""Couldn't get PCI resources, aborting\n");
199 static void release_bar(struct pci_dev *pdev)
201 pci_release_regions(pdev);
204 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
206 struct mlx5_priv *priv = &dev->priv;
207 struct mlx5_eq_table *table = &priv->eq_table;
208 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
212 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
213 MLX5_EQ_VEC_COMP_BASE;
214 nvec = min_t(int, nvec, num_eqs);
215 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
218 priv->msix_arr = kzalloc(nvec * sizeof(*priv->msix_arr), GFP_KERNEL);
220 priv->irq_info = kzalloc(nvec * sizeof(*priv->irq_info), GFP_KERNEL);
222 for (i = 0; i < nvec; i++)
223 priv->msix_arr[i].entry = i;
225 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
226 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
230 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
236 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
238 struct mlx5_priv *priv = &dev->priv;
240 pci_disable_msix(dev->pdev);
241 kfree(priv->irq_info);
242 kfree(priv->msix_arr);
245 struct mlx5_reg_host_endianess {
251 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
254 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
255 MLX5_DEV_CAP_FLAG_DCT |
256 MLX5_DEV_CAP_FLAG_DRAIN_SIGERR,
259 static u16 to_fw_pkey_sz(u32 size)
275 printf("mlx5_core: WARN: ""invalid pkey table size %d\n", size);
280 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
281 enum mlx5_cap_mode cap_mode)
283 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
284 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
285 void *out, *hca_caps;
286 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
289 memset(in, 0, sizeof(in));
290 out = kzalloc(out_sz, GFP_KERNEL);
292 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
293 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
294 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
298 err = mlx5_cmd_status_to_err_v2(out);
301 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
302 cap_type, cap_mode, err);
306 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
309 case HCA_CAP_OPMOD_GET_MAX:
310 memcpy(dev->hca_caps_max[cap_type], hca_caps,
311 MLX5_UN_SZ_BYTES(hca_cap_union));
313 case HCA_CAP_OPMOD_GET_CUR:
314 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
315 MLX5_UN_SZ_BYTES(hca_cap_union));
319 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
329 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
331 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)];
334 memset(out, 0, sizeof(out));
336 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
337 err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
341 err = mlx5_cmd_status_to_err_v2(out);
346 static int handle_hca_cap(struct mlx5_core_dev *dev)
348 void *set_ctx = NULL;
349 struct mlx5_profile *prof = dev->profile;
351 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
354 set_ctx = kzalloc(set_sz, GFP_KERNEL);
356 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_MAX);
360 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_CUR);
364 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
366 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
367 MLX5_ST_SZ_BYTES(cmd_hca_cap));
369 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
370 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
372 /* we limit the size of the pkey table to 128 entries for now */
373 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
376 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
377 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
380 /* disable cmdif checksum */
381 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
383 /* enable drain sigerr */
384 MLX5_SET(cmd_hca_cap, set_hca_cap, drain_sigerr, 1);
386 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
388 err = set_caps(dev, set_ctx, set_sz);
395 static int set_hca_ctrl(struct mlx5_core_dev *dev)
397 struct mlx5_reg_host_endianess he_in;
398 struct mlx5_reg_host_endianess he_out;
401 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH &&
402 !MLX5_CAP_GEN(dev, roce))
405 memset(&he_in, 0, sizeof(he_in));
406 he_in.he = MLX5_SET_HOST_ENDIANNESS;
407 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
408 &he_out, sizeof(he_out),
409 MLX5_REG_HOST_ENDIANNESS, 0, 1);
413 static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
415 u32 in[MLX5_ST_SZ_DW(enable_hca_in)];
416 u32 out[MLX5_ST_SZ_DW(enable_hca_out)];
418 memset(in, 0, sizeof(in));
419 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
420 memset(out, 0, sizeof(out));
421 return mlx5_cmd_exec_check_status(dev, in, sizeof(in),
425 static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
427 u32 in[MLX5_ST_SZ_DW(disable_hca_in)];
428 u32 out[MLX5_ST_SZ_DW(disable_hca_out)];
430 memset(in, 0, sizeof(in));
432 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
433 memset(out, 0, sizeof(out));
434 return mlx5_cmd_exec_check_status(dev, in, sizeof(in),
438 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
440 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)];
441 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)];
442 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)];
443 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)];
447 memset(query_in, 0, sizeof(query_in));
448 memset(query_out, 0, sizeof(query_out));
450 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
452 err = mlx5_cmd_exec_check_status(dev, query_in, sizeof(query_in),
453 query_out, sizeof(query_out));
455 if (((struct mlx5_outbox_hdr *)query_out)->status ==
456 MLX5_CMD_STAT_BAD_OP_ERR) {
457 pr_debug("Only ISSI 0 is supported\n");
461 printf("mlx5_core: ERR: ""failed to query ISSI\n");
465 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
467 if (sup_issi & (1 << 1)) {
468 memset(set_in, 0, sizeof(set_in));
469 memset(set_out, 0, sizeof(set_out));
471 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
472 MLX5_SET(set_issi_in, set_in, current_issi, 1);
474 err = mlx5_cmd_exec_check_status(dev, set_in, sizeof(set_in),
475 set_out, sizeof(set_out));
477 printf("mlx5_core: ERR: ""failed to set ISSI=1\n");
484 } else if (sup_issi & (1 << 0)) {
492 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn)
494 struct mlx5_eq_table *table = &dev->priv.eq_table;
498 spin_lock(&table->lock);
499 list_for_each_entry(eq, &table->comp_eqs_list, list) {
500 if (eq->index == vector) {
507 spin_unlock(&table->lock);
511 EXPORT_SYMBOL(mlx5_vector2eqn);
513 int mlx5_rename_eq(struct mlx5_core_dev *dev, int eq_ix, char *name)
515 struct mlx5_priv *priv = &dev->priv;
516 struct mlx5_eq_table *table = &priv->eq_table;
520 spin_lock(&table->lock);
521 list_for_each_entry(eq, &table->comp_eqs_list, list) {
522 if (eq->index == eq_ix) {
523 int irq_ix = eq_ix + MLX5_EQ_VEC_COMP_BASE;
525 snprintf(priv->irq_info[irq_ix].name, MLX5_MAX_IRQ_NAME,
526 "%s-%d", name, eq_ix);
532 spin_unlock(&table->lock);
537 static void free_comp_eqs(struct mlx5_core_dev *dev)
539 struct mlx5_eq_table *table = &dev->priv.eq_table;
540 struct mlx5_eq *eq, *n;
542 spin_lock(&table->lock);
543 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
545 spin_unlock(&table->lock);
546 if (mlx5_destroy_unmap_eq(dev, eq))
547 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
550 spin_lock(&table->lock);
552 spin_unlock(&table->lock);
555 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
557 struct mlx5_eq_table *table = &dev->priv.eq_table;
558 char name[MLX5_MAX_IRQ_NAME];
565 INIT_LIST_HEAD(&table->comp_eqs_list);
566 ncomp_vec = table->num_comp_vectors;
567 nent = MLX5_COMP_EQ_SIZE;
568 for (i = 0; i < ncomp_vec; i++) {
569 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
571 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
572 err = mlx5_create_map_eq(dev, eq,
573 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
574 name, &dev->priv.uuari.uars[0]);
579 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
581 spin_lock(&table->lock);
582 list_add_tail(&eq->list, &table->comp_eqs_list);
583 spin_unlock(&table->lock);
593 static int map_bf_area(struct mlx5_core_dev *dev)
595 resource_size_t bf_start = pci_resource_start(dev->pdev, 0);
596 resource_size_t bf_len = pci_resource_len(dev->pdev, 0);
598 dev->priv.bf_mapping = io_mapping_create_wc(bf_start, bf_len);
600 return dev->priv.bf_mapping ? 0 : -ENOMEM;
603 static void unmap_bf_area(struct mlx5_core_dev *dev)
605 if (dev->priv.bf_mapping)
606 io_mapping_free(dev->priv.bf_mapping);
609 static inline int fw_initializing(struct mlx5_core_dev *dev)
611 return ioread32be(&dev->iseg->initializing) >> 31;
614 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
616 u64 end = jiffies + msecs_to_jiffies(max_wait_mili);
619 while (fw_initializing(dev)) {
620 if (time_after(jiffies, end)) {
624 msleep(FW_INIT_WAIT_MS);
630 static int mlx5_dev_init(struct mlx5_core_dev *dev, struct pci_dev *pdev)
632 struct mlx5_priv *priv = &dev->priv;
636 pci_set_drvdata(dev->pdev, dev);
637 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
638 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
640 mutex_init(&priv->pgdir_mutex);
641 INIT_LIST_HEAD(&priv->pgdir_list);
642 spin_lock_init(&priv->mkey_lock);
644 priv->numa_node = NUMA_NO_NODE;
646 err = pci_enable_device(pdev);
648 device_printf((&pdev->dev)->bsddev, "ERR: ""Cannot enable PCI device, aborting\n");
652 err = request_bar(pdev);
654 device_printf((&pdev->dev)->bsddev, "ERR: ""error requesting BARs, aborting\n");
658 pci_set_master(pdev);
660 err = set_dma_caps(pdev);
662 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed setting DMA capabilities mask, aborting\n");
666 dev->iseg = ioremap(pci_resource_start(dev->pdev, 0),
670 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed mapping initialization segment, aborting\n");
673 device_printf((&pdev->dev)->bsddev, "INFO: ""firmware version: %d.%d.%d\n", fw_rev_maj(dev), fw_rev_min(dev), fw_rev_sub(dev));
676 * On load removing any previous indication of internal error,
679 dev->state = MLX5_DEVICE_STATE_UP;
681 err = mlx5_cmd_init(dev);
683 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed initializing command interface, aborting\n");
687 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
689 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""Firmware over %d MS in initializing state, aborting\n", FW_INIT_TIMEOUT_MILI);
690 goto err_cmd_cleanup;
693 mlx5_pagealloc_init(dev);
695 err = mlx5_core_enable_hca(dev);
697 device_printf((&pdev->dev)->bsddev, "ERR: ""enable hca failed\n");
698 goto err_pagealloc_cleanup;
701 err = mlx5_core_set_issi(dev);
703 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to set issi\n");
704 goto err_disable_hca;
707 err = mlx5_pagealloc_start(dev);
709 device_printf((&pdev->dev)->bsddev, "ERR: ""mlx5_pagealloc_start failed\n");
710 goto err_disable_hca;
713 err = mlx5_satisfy_startup_pages(dev, 1);
715 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to allocate boot pages\n");
716 goto err_pagealloc_stop;
719 err = handle_hca_cap(dev);
721 device_printf((&pdev->dev)->bsddev, "ERR: ""handle_hca_cap failed\n");
722 goto reclaim_boot_pages;
725 err = set_hca_ctrl(dev);
727 device_printf((&pdev->dev)->bsddev, "ERR: ""set_hca_ctrl failed\n");
728 goto reclaim_boot_pages;
731 err = mlx5_satisfy_startup_pages(dev, 0);
733 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to allocate init pages\n");
734 goto reclaim_boot_pages;
737 err = mlx5_cmd_init_hca(dev);
739 device_printf((&pdev->dev)->bsddev, "ERR: ""init hca failed\n");
740 goto reclaim_boot_pages;
743 mlx5_start_health_poll(dev);
745 err = mlx5_query_hca_caps(dev);
747 device_printf((&pdev->dev)->bsddev, "ERR: ""query hca failed\n");
751 err = mlx5_query_board_id(dev);
753 device_printf((&pdev->dev)->bsddev, "ERR: ""query board id failed\n");
757 err = mlx5_enable_msix(dev);
759 device_printf((&pdev->dev)->bsddev, "ERR: ""enable msix failed\n");
763 err = mlx5_eq_init(dev);
765 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to initialize eq\n");
769 err = mlx5_alloc_uuars(dev, &priv->uuari);
771 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed allocating uar, aborting\n");
775 err = mlx5_start_eqs(dev);
777 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to start pages and async EQs\n");
781 err = alloc_comp_eqs(dev);
783 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to alloc completion EQs\n");
787 if (map_bf_area(dev))
788 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to map blue flame area\n");
790 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
792 mlx5_init_cq_table(dev);
793 mlx5_init_qp_table(dev);
794 mlx5_init_srq_table(dev);
795 mlx5_init_mr_table(dev);
803 mlx5_free_uuars(dev, &priv->uuari);
806 mlx5_eq_cleanup(dev);
809 mlx5_disable_msix(dev);
812 mlx5_stop_health_poll(dev);
813 if (mlx5_cmd_teardown_hca(dev)) {
814 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""tear_down_hca failed, skip cleanup\n");
819 mlx5_reclaim_startup_pages(dev);
822 mlx5_pagealloc_stop(dev);
825 mlx5_core_disable_hca(dev);
827 err_pagealloc_cleanup:
828 mlx5_pagealloc_cleanup(dev);
830 mlx5_cmd_cleanup(dev);
836 pci_clear_master(dev->pdev);
837 release_bar(dev->pdev);
840 pci_disable_device(dev->pdev);
843 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
847 static void mlx5_dev_cleanup(struct mlx5_core_dev *dev)
849 struct mlx5_priv *priv = &dev->priv;
851 mlx5_cleanup_mr_table(dev);
852 mlx5_cleanup_srq_table(dev);
853 mlx5_cleanup_qp_table(dev);
854 mlx5_cleanup_cq_table(dev);
856 mlx5_wait_for_reclaim_vfs_pages(dev);
859 mlx5_free_uuars(dev, &priv->uuari);
860 mlx5_eq_cleanup(dev);
861 mlx5_disable_msix(dev);
862 mlx5_stop_health_poll(dev);
863 if (mlx5_cmd_teardown_hca(dev)) {
864 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""tear_down_hca failed, skip cleanup\n");
867 mlx5_pagealloc_stop(dev);
868 mlx5_reclaim_startup_pages(dev);
869 mlx5_core_disable_hca(dev);
870 mlx5_pagealloc_cleanup(dev);
871 mlx5_cmd_cleanup(dev);
873 pci_clear_master(dev->pdev);
874 release_bar(dev->pdev);
875 pci_disable_device(dev->pdev);
878 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
880 struct mlx5_device_context *dev_ctx;
881 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
883 dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
885 dev_ctx->intf = intf;
886 dev_ctx->context = intf->add(dev);
888 if (dev_ctx->context) {
889 spin_lock_irq(&priv->ctx_lock);
890 list_add_tail(&dev_ctx->list, &priv->ctx_list);
891 spin_unlock_irq(&priv->ctx_lock);
897 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
899 struct mlx5_device_context *dev_ctx;
900 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
902 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
903 if (dev_ctx->intf == intf) {
904 spin_lock_irq(&priv->ctx_lock);
905 list_del(&dev_ctx->list);
906 spin_unlock_irq(&priv->ctx_lock);
908 intf->remove(dev, dev_ctx->context);
913 static int mlx5_register_device(struct mlx5_core_dev *dev)
915 struct mlx5_priv *priv = &dev->priv;
916 struct mlx5_interface *intf;
918 mutex_lock(&intf_mutex);
919 list_add_tail(&priv->dev_list, &dev_list);
920 list_for_each_entry(intf, &intf_list, list)
921 mlx5_add_device(intf, priv);
922 mutex_unlock(&intf_mutex);
926 static void mlx5_unregister_device(struct mlx5_core_dev *dev)
928 struct mlx5_priv *priv = &dev->priv;
929 struct mlx5_interface *intf;
931 mutex_lock(&intf_mutex);
932 list_for_each_entry(intf, &intf_list, list)
933 mlx5_remove_device(intf, priv);
934 list_del(&priv->dev_list);
935 mutex_unlock(&intf_mutex);
938 int mlx5_register_interface(struct mlx5_interface *intf)
940 struct mlx5_priv *priv;
942 if (!intf->add || !intf->remove)
945 mutex_lock(&intf_mutex);
946 list_add_tail(&intf->list, &intf_list);
947 list_for_each_entry(priv, &dev_list, dev_list)
948 mlx5_add_device(intf, priv);
949 mutex_unlock(&intf_mutex);
953 EXPORT_SYMBOL(mlx5_register_interface);
955 void mlx5_unregister_interface(struct mlx5_interface *intf)
957 struct mlx5_priv *priv;
959 mutex_lock(&intf_mutex);
960 list_for_each_entry(priv, &dev_list, dev_list)
961 mlx5_remove_device(intf, priv);
962 list_del(&intf->list);
963 mutex_unlock(&intf_mutex);
965 EXPORT_SYMBOL(mlx5_unregister_interface);
967 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
969 struct mlx5_priv *priv = &mdev->priv;
970 struct mlx5_device_context *dev_ctx;
974 spin_lock_irqsave(&priv->ctx_lock, flags);
976 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
977 if ((dev_ctx->intf->protocol == protocol) &&
978 dev_ctx->intf->get_dev) {
979 result = dev_ctx->intf->get_dev(dev_ctx->context);
983 spin_unlock_irqrestore(&priv->ctx_lock, flags);
987 EXPORT_SYMBOL(mlx5_get_protocol_dev);
989 static void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
992 struct mlx5_priv *priv = &dev->priv;
993 struct mlx5_device_context *dev_ctx;
996 spin_lock_irqsave(&priv->ctx_lock, flags);
998 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
999 if (dev_ctx->intf->event)
1000 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
1002 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1005 struct mlx5_core_event_handler {
1006 void (*event)(struct mlx5_core_dev *dev,
1007 enum mlx5_dev_event event,
1012 static int init_one(struct pci_dev *pdev,
1013 const struct pci_device_id *id)
1015 struct mlx5_core_dev *dev;
1016 struct mlx5_priv *priv;
1019 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1022 priv->pci_dev_data = id->driver_data;
1024 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profiles)) {
1025 printf("mlx5_core: WARN: ""selected profile out of range, selecting default (%d)\n", MLX5_DEFAULT_PROF);
1026 prof_sel = MLX5_DEFAULT_PROF;
1028 dev->profile = &profiles[prof_sel];
1029 dev->event = mlx5_core_event;
1031 INIT_LIST_HEAD(&priv->ctx_list);
1032 spin_lock_init(&priv->ctx_lock);
1033 err = mlx5_dev_init(dev, pdev);
1035 device_printf((&pdev->dev)->bsddev, "ERR: ""mlx5_dev_init failed %d\n", err);
1039 err = mlx5_register_device(dev);
1041 device_printf((&pdev->dev)->bsddev, "ERR: ""mlx5_register_device failed %d\n", err);
1049 mlx5_dev_cleanup(dev);
1055 static void remove_one(struct pci_dev *pdev)
1057 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1059 mlx5_unregister_device(dev);
1060 mlx5_dev_cleanup(dev);
1064 static const struct pci_device_id mlx5_core_pci_table[] = {
1065 { PCI_VDEVICE(MELLANOX, 4113) }, /* Connect-IB */
1066 { PCI_VDEVICE(MELLANOX, 4114) }, /* Connect-IB VF */
1067 { PCI_VDEVICE(MELLANOX, 4115) }, /* ConnectX-4 */
1068 { PCI_VDEVICE(MELLANOX, 4116) }, /* ConnectX-4 VF */
1069 { PCI_VDEVICE(MELLANOX, 4117) }, /* ConnectX-4LX */
1070 { PCI_VDEVICE(MELLANOX, 4118) }, /* ConnectX-4LX VF */
1071 { PCI_VDEVICE(MELLANOX, 4119) }, /* ConnectX-5 */
1072 { PCI_VDEVICE(MELLANOX, 4120) }, /* ConnectX-5 VF */
1073 { PCI_VDEVICE(MELLANOX, 4121) },
1074 { PCI_VDEVICE(MELLANOX, 4122) },
1075 { PCI_VDEVICE(MELLANOX, 4123) },
1076 { PCI_VDEVICE(MELLANOX, 4124) },
1077 { PCI_VDEVICE(MELLANOX, 4125) },
1078 { PCI_VDEVICE(MELLANOX, 4126) },
1079 { PCI_VDEVICE(MELLANOX, 4127) },
1080 { PCI_VDEVICE(MELLANOX, 4128) },
1081 { PCI_VDEVICE(MELLANOX, 4129) },
1082 { PCI_VDEVICE(MELLANOX, 4130) },
1083 { PCI_VDEVICE(MELLANOX, 4131) },
1084 { PCI_VDEVICE(MELLANOX, 4132) },
1085 { PCI_VDEVICE(MELLANOX, 4133) },
1086 { PCI_VDEVICE(MELLANOX, 4134) },
1087 { PCI_VDEVICE(MELLANOX, 4135) },
1088 { PCI_VDEVICE(MELLANOX, 4136) },
1089 { PCI_VDEVICE(MELLANOX, 4137) },
1090 { PCI_VDEVICE(MELLANOX, 4138) },
1091 { PCI_VDEVICE(MELLANOX, 4139) },
1092 { PCI_VDEVICE(MELLANOX, 4140) },
1093 { PCI_VDEVICE(MELLANOX, 4141) },
1094 { PCI_VDEVICE(MELLANOX, 4142) },
1095 { PCI_VDEVICE(MELLANOX, 4143) },
1096 { PCI_VDEVICE(MELLANOX, 4144) },
1100 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1102 static struct pci_driver mlx5_core_driver = {
1103 .name = DRIVER_NAME,
1104 .id_table = mlx5_core_pci_table,
1106 .remove = remove_one
1109 static int __init init(void)
1113 mlx5_core_wq = create_singlethread_workqueue("mlx5_core_wq");
1114 if (!mlx5_core_wq) {
1120 err = pci_register_driver(&mlx5_core_driver);
1128 mlx5_health_cleanup();
1129 destroy_workqueue(mlx5_core_wq);
1134 static void __exit cleanup(void)
1136 pci_unregister_driver(&mlx5_core_driver);
1137 mlx5_health_cleanup();
1138 destroy_workqueue(mlx5_core_wq);
1142 module_exit(cleanup);
1144 void mlx5_enter_error_state(struct mlx5_core_dev *dev)
1146 if (dev->state != MLX5_DEVICE_STATE_UP)
1149 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1150 mlx5_trigger_cmd_completions(dev);
1152 EXPORT_SYMBOL(mlx5_enter_error_state);