sys/dev/mlx5/mlx5_core/mlx5_main.c

   1 /*-
   2  * Copyright (c) 2013-2019, Mellanox Technologies, Ltd.  All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include <linux/kmod.h>
  29 #include <linux/module.h>
  30 #include <linux/errno.h>
  31 #include <linux/pci.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/slab.h>
  34 #include <linux/io-mapping.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/hardirq.h>
  37 #include <dev/mlx5/driver.h>
  38 #include <dev/mlx5/cq.h>
  39 #include <dev/mlx5/qp.h>
  40 #include <dev/mlx5/srq.h>
  41 #include <dev/mlx5/mpfs.h>
  42 #include <dev/mlx5/vport.h>
  43 #include <linux/delay.h>
  44 #include <dev/mlx5/mlx5_ifc.h>
  45 #include <dev/mlx5/mlx5_fpga/core.h>
  46 #include <dev/mlx5/mlx5_lib/mlx5.h>
  47 #include "mlx5_core.h"
  48 #include "eswitch.h"
  49 #include "fs_core.h"
  50 #ifdef PCI_IOV
  51 #include <sys/nv.h>
  52 #include <dev/pci/pci_iov.h>
  53 #include <sys/iov_schema.h>
  54 #endif
  55
  56 static const char mlx5_version[] = "Mellanox Core driver "
  57         DRIVER_VERSION " (" DRIVER_RELDATE ")";
  58 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
  59 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
  60 MODULE_LICENSE("Dual BSD/GPL");
  61 MODULE_DEPEND(mlx5, linuxkpi, 1, 1, 1);
  62 MODULE_DEPEND(mlx5, mlxfw, 1, 1, 1);
  63 MODULE_DEPEND(mlx5, firmware, 1, 1, 1);
  64 MODULE_VERSION(mlx5, 1);
  65
  66 SYSCTL_NODE(_hw, OID_AUTO, mlx5, CTLFLAG_RW, 0, "mlx5 hardware controls");
  67
  68 int mlx5_core_debug_mask;
  69 SYSCTL_INT(_hw_mlx5, OID_AUTO, debug_mask, CTLFLAG_RWTUN,
  70     &mlx5_core_debug_mask, 0,
  71     "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
  72
  73 #define MLX5_DEFAULT_PROF       2
  74 static int mlx5_prof_sel = MLX5_DEFAULT_PROF;
  75 SYSCTL_INT(_hw_mlx5, OID_AUTO, prof_sel, CTLFLAG_RWTUN,
  76     &mlx5_prof_sel, 0,
  77     "profile selector. Valid range 0 - 2");
  78
  79 static int mlx5_fast_unload_enabled = 1;
  80 SYSCTL_INT(_hw_mlx5, OID_AUTO, fast_unload_enabled, CTLFLAG_RWTUN,
  81     &mlx5_fast_unload_enabled, 0,
  82     "Set to enable fast unload. Clear to disable.");
  83
  84 #define NUMA_NO_NODE       -1
  85
  86 static LIST_HEAD(intf_list);
  87 static LIST_HEAD(dev_list);
  88 static DEFINE_MUTEX(intf_mutex);
  89
  90 struct mlx5_device_context {
  91         struct list_head        list;
  92         struct mlx5_interface  *intf;
  93         void                   *context;
  94 };
  95
  96 enum {
  97         MLX5_ATOMIC_REQ_MODE_BE = 0x0,
  98         MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
  99 };
 100
 101 static struct mlx5_profile profiles[] = {
 102         [0] = {
 103                 .mask           = 0,
 104         },
 105         [1] = {
 106                 .mask           = MLX5_PROF_MASK_QP_SIZE,
 107                 .log_max_qp     = 12,
 108         },
 109         [2] = {
 110                 .mask           = MLX5_PROF_MASK_QP_SIZE |
 111                                   MLX5_PROF_MASK_MR_CACHE,
 112                 .log_max_qp     = 17,
 113                 .mr_cache[0]    = {
 114                         .size   = 500,
 115                         .limit  = 250
 116                 },
 117                 .mr_cache[1]    = {
 118                         .size   = 500,
 119                         .limit  = 250
 120                 },
 121                 .mr_cache[2]    = {
 122                         .size   = 500,
 123                         .limit  = 250
 124                 },
 125                 .mr_cache[3]    = {
 126                         .size   = 500,
 127                         .limit  = 250
 128                 },
 129                 .mr_cache[4]    = {
 130                         .size   = 500,
 131                         .limit  = 250
 132                 },
 133                 .mr_cache[5]    = {
 134                         .size   = 500,
 135                         .limit  = 250
 136                 },
 137                 .mr_cache[6]    = {
 138                         .size   = 500,
 139                         .limit  = 250
 140                 },
 141                 .mr_cache[7]    = {
 142                         .size   = 500,
 143                         .limit  = 250
 144                 },
 145                 .mr_cache[8]    = {
 146                         .size   = 500,
 147                         .limit  = 250
 148                 },
 149                 .mr_cache[9]    = {
 150                         .size   = 500,
 151                         .limit  = 250
 152                 },
 153                 .mr_cache[10]   = {
 154                         .size   = 500,
 155                         .limit  = 250
 156                 },
 157                 .mr_cache[11]   = {
 158                         .size   = 500,
 159                         .limit  = 250
 160                 },
 161                 .mr_cache[12]   = {
 162                         .size   = 64,
 163                         .limit  = 32
 164                 },
 165                 .mr_cache[13]   = {
 166                         .size   = 32,
 167                         .limit  = 16
 168                 },
 169                 .mr_cache[14]   = {
 170                         .size   = 16,
 171                         .limit  = 8
 172                 },
 173         },
 174         [3] = {
 175                 .mask           = MLX5_PROF_MASK_QP_SIZE,
 176                 .log_max_qp     = 17,
 177         },
 178 };
 179
 180 #ifdef PCI_IOV
 181 static const char iov_mac_addr_name[] = "mac-addr";
 182 #endif
 183
 184 static int set_dma_caps(struct pci_dev *pdev)
 185 {
 186         struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
 187         int err;
 188
 189         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
 190         if (err) {
 191                 mlx5_core_warn(dev, "couldn't set 64-bit PCI DMA mask\n");
 192                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
 193                 if (err) {
 194                         mlx5_core_err(dev, "Can't set PCI DMA mask, aborting\n");
 195                         return err;
 196                 }
 197         }
 198
 199         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
 200         if (err) {
 201                 mlx5_core_warn(dev, "couldn't set 64-bit consistent PCI DMA mask\n");
 202                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
 203                 if (err) {
 204                         mlx5_core_err(dev, "Can't set consistent PCI DMA mask, aborting\n");
 205                         return err;
 206                 }
 207         }
 208
 209         dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
 210         return err;
 211 }
 212
 213 int mlx5_pci_read_power_status(struct mlx5_core_dev *dev,
 214                                u16 *p_power, u8 *p_status)
 215 {
 216         u32 in[MLX5_ST_SZ_DW(mpein_reg)] = {};
 217         u32 out[MLX5_ST_SZ_DW(mpein_reg)] = {};
 218         int err;
 219
 220         err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
 221             MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MPEIN, 0, 0);
 222
 223         *p_status = MLX5_GET(mpein_reg, out, pwr_status);
 224         *p_power = MLX5_GET(mpein_reg, out, pci_power);
 225         return err;
 226 }
 227
 228 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
 229 {
 230         struct pci_dev *pdev = dev->pdev;
 231         int err = 0;
 232
 233         mutex_lock(&dev->pci_status_mutex);
 234         if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
 235                 err = pci_enable_device(pdev);
 236                 if (!err)
 237                         dev->pci_status = MLX5_PCI_STATUS_ENABLED;
 238         }
 239         mutex_unlock(&dev->pci_status_mutex);
 240
 241         return err;
 242 }
 243
 244 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
 245 {
 246         struct pci_dev *pdev = dev->pdev;
 247
 248         mutex_lock(&dev->pci_status_mutex);
 249         if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
 250                 pci_disable_device(pdev);
 251                 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
 252         }
 253         mutex_unlock(&dev->pci_status_mutex);
 254 }
 255
 256 static int request_bar(struct pci_dev *pdev)
 257 {
 258         struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
 259         int err = 0;
 260
 261         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
 262                 mlx5_core_err(dev, "Missing registers BAR, aborting\n");
 263                 return -ENODEV;
 264         }
 265
 266         err = pci_request_regions(pdev, DRIVER_NAME);
 267         if (err)
 268                 mlx5_core_err(dev, "Couldn't get PCI resources, aborting\n");
 269
 270         return err;
 271 }
 272
 273 static void release_bar(struct pci_dev *pdev)
 274 {
 275         pci_release_regions(pdev);
 276 }
 277
 278 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
 279 {
 280         struct mlx5_priv *priv = &dev->priv;
 281         struct mlx5_eq_table *table = &priv->eq_table;
 282         int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
 283         int limit = dev->msix_eqvec;
 284         int nvec = MLX5_EQ_VEC_COMP_BASE;
 285         int i;
 286
 287         if (limit > 0)
 288                 nvec += limit;
 289         else
 290                 nvec += MLX5_CAP_GEN(dev, num_ports) * num_online_cpus();
 291
 292         if (nvec > num_eqs)
 293                 nvec = num_eqs;
 294         if (nvec > 256)
 295                 nvec = 256;     /* limit of firmware API */
 296         if (nvec <= MLX5_EQ_VEC_COMP_BASE)
 297                 return -ENOMEM;
 298
 299         priv->msix_arr = kzalloc(nvec * sizeof(*priv->msix_arr), GFP_KERNEL);
 300
 301         for (i = 0; i < nvec; i++)
 302                 priv->msix_arr[i].entry = i;
 303
 304         nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
 305                                      MLX5_EQ_VEC_COMP_BASE + 1, nvec);
 306         if (nvec < 0)
 307                 return nvec;
 308
 309         table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
 310         return 0;
 311 }
 312
 313 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
 314 {
 315         struct mlx5_priv *priv = &dev->priv;
 316
 317         pci_disable_msix(dev->pdev);
 318         kfree(priv->msix_arr);
 319 }
 320
 321 struct mlx5_reg_host_endianess {
 322         u8      he;
 323         u8      rsvd[15];
 324 };
 325
 326
 327 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
 328
 329 enum {
 330         MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
 331                                 MLX5_DEV_CAP_FLAG_DCT |
 332                                 MLX5_DEV_CAP_FLAG_DRAIN_SIGERR,
 333 };
 334
 335 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
 336 {
 337         switch (size) {
 338         case 128:
 339                 return 0;
 340         case 256:
 341                 return 1;
 342         case 512:
 343                 return 2;
 344         case 1024:
 345                 return 3;
 346         case 2048:
 347                 return 4;
 348         case 4096:
 349                 return 5;
 350         default:
 351                 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
 352                 return 0;
 353         }
 354 }
 355
 356 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
 357                                    enum mlx5_cap_type cap_type,
 358                                    enum mlx5_cap_mode cap_mode)
 359 {
 360         u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
 361         int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
 362         void *out, *hca_caps;
 363         u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
 364         int err;
 365
 366         memset(in, 0, sizeof(in));
 367         out = kzalloc(out_sz, GFP_KERNEL);
 368
 369         MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
 370         MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
 371         err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
 372         if (err) {
 373                 mlx5_core_warn(dev,
 374                                "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
 375                                cap_type, cap_mode, err);
 376                 goto query_ex;
 377         }
 378
 379         hca_caps =  MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 380
 381         switch (cap_mode) {
 382         case HCA_CAP_OPMOD_GET_MAX:
 383                 memcpy(dev->hca_caps_max[cap_type], hca_caps,
 384                        MLX5_UN_SZ_BYTES(hca_cap_union));
 385                 break;
 386         case HCA_CAP_OPMOD_GET_CUR:
 387                 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
 388                        MLX5_UN_SZ_BYTES(hca_cap_union));
 389                 break;
 390         default:
 391                 mlx5_core_warn(dev,
 392                                "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
 393                                cap_type, cap_mode);
 394                 err = -EINVAL;
 395                 break;
 396         }
 397 query_ex:
 398         kfree(out);
 399         return err;
 400 }
 401
 402 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
 403 {
 404         int ret;
 405
 406         ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
 407         if (ret)
 408                 return ret;
 409
 410         return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
 411 }
 412
 413 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
 414 {
 415         u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0};
 416
 417         MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
 418
 419         return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
 420 }
 421
 422 static int handle_hca_cap(struct mlx5_core_dev *dev)
 423 {
 424         void *set_ctx = NULL;
 425         struct mlx5_profile *prof = dev->profile;
 426         int err = -ENOMEM;
 427         int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
 428         void *set_hca_cap;
 429
 430         set_ctx = kzalloc(set_sz, GFP_KERNEL);
 431
 432         err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
 433         if (err)
 434                 goto query_ex;
 435
 436         set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
 437                                    capability);
 438         memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
 439                MLX5_ST_SZ_BYTES(cmd_hca_cap));
 440
 441         mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
 442                       mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
 443                       128);
 444         /* we limit the size of the pkey table to 128 entries for now */
 445         MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
 446                  to_fw_pkey_sz(dev, 128));
 447
 448         if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
 449                 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
 450                          prof->log_max_qp);
 451
 452         /* disable cmdif checksum */
 453         MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
 454
 455         /* enable drain sigerr */
 456         MLX5_SET(cmd_hca_cap, set_hca_cap, drain_sigerr, 1);
 457
 458         MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
 459
 460         err = set_caps(dev, set_ctx, set_sz);
 461
 462 query_ex:
 463         kfree(set_ctx);
 464         return err;
 465 }
 466
 467 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
 468 {
 469         void *set_ctx;
 470         void *set_hca_cap;
 471         int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
 472         int req_endianness;
 473         int err;
 474
 475         if (MLX5_CAP_GEN(dev, atomic)) {
 476                 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
 477                 if (err)
 478                         return err;
 479         } else {
 480                 return 0;
 481         }
 482
 483         req_endianness =
 484                 MLX5_CAP_ATOMIC(dev,
 485                                 supported_atomic_req_8B_endianess_mode_1);
 486
 487         if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
 488                 return 0;
 489
 490         set_ctx = kzalloc(set_sz, GFP_KERNEL);
 491         if (!set_ctx)
 492                 return -ENOMEM;
 493
 494         MLX5_SET(set_hca_cap_in, set_ctx, op_mod,
 495                  MLX5_SET_HCA_CAP_OP_MOD_ATOMIC << 1);
 496         set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
 497
 498         /* Set requestor to host endianness */
 499         MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode,
 500                  MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
 501
 502         err = set_caps(dev, set_ctx, set_sz);
 503
 504         kfree(set_ctx);
 505         return err;
 506 }
 507
 508 static int set_hca_ctrl(struct mlx5_core_dev *dev)
 509 {
 510         struct mlx5_reg_host_endianess he_in;
 511         struct mlx5_reg_host_endianess he_out;
 512         int err;
 513
 514         if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH &&
 515             !MLX5_CAP_GEN(dev, roce))
 516                 return 0;
 517
 518         memset(&he_in, 0, sizeof(he_in));
 519         he_in.he = MLX5_SET_HOST_ENDIANNESS;
 520         err = mlx5_core_access_reg(dev, &he_in,  sizeof(he_in),
 521                                         &he_out, sizeof(he_out),
 522                                         MLX5_REG_HOST_ENDIANNESS, 0, 1);
 523         return err;
 524 }
 525
 526 static int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
 527 {
 528         u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0};
 529         u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0};
 530
 531         MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
 532         MLX5_SET(enable_hca_in, in, function_id, func_id);
 533         return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
 534 }
 535
 536 static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
 537 {
 538         u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0};
 539         u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0};
 540
 541         MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
 542         return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
 543 }
 544
 545 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
 546 {
 547         u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0};
 548         u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0};
 549         u32 sup_issi;
 550         int err;
 551
 552         MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
 553
 554         err = mlx5_cmd_exec(dev, query_in, sizeof(query_in), query_out, sizeof(query_out));
 555         if (err) {
 556                 u32 syndrome;
 557                 u8 status;
 558
 559                 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
 560                 if (status == MLX5_CMD_STAT_BAD_OP_ERR) {
 561                         mlx5_core_dbg(dev, "Only ISSI 0 is supported\n");
 562                         return 0;
 563                 }
 564
 565                 mlx5_core_err(dev, "failed to query ISSI\n");
 566                 return err;
 567         }
 568
 569         sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
 570
 571         if (sup_issi & (1 << 1)) {
 572                 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)]   = {0};
 573                 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0};
 574
 575                 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
 576                 MLX5_SET(set_issi_in, set_in, current_issi, 1);
 577
 578                 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in), set_out, sizeof(set_out));
 579                 if (err) {
 580                         mlx5_core_err(dev, "failed to set ISSI=1 err(%d)\n", err);
 581                         return err;
 582                 }
 583
 584                 dev->issi = 1;
 585
 586                 return 0;
 587         } else if (sup_issi & (1 << 0)) {
 588                 return 0;
 589         }
 590
 591         return -ENOTSUPP;
 592 }
 593
 594
 595 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn)
 596 {
 597         struct mlx5_eq_table *table = &dev->priv.eq_table;
 598         struct mlx5_eq *eq;
 599         int err = -ENOENT;
 600
 601         spin_lock(&table->lock);
 602         list_for_each_entry(eq, &table->comp_eqs_list, list) {
 603                 if (eq->index == vector) {
 604                         *eqn = eq->eqn;
 605                         *irqn = eq->irqn;
 606                         err = 0;
 607                         break;
 608                 }
 609         }
 610         spin_unlock(&table->lock);
 611
 612         return err;
 613 }
 614 EXPORT_SYMBOL(mlx5_vector2eqn);
 615
 616 static void free_comp_eqs(struct mlx5_core_dev *dev)
 617 {
 618         struct mlx5_eq_table *table = &dev->priv.eq_table;
 619         struct mlx5_eq *eq, *n;
 620
 621         spin_lock(&table->lock);
 622         list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
 623                 list_del(&eq->list);
 624                 spin_unlock(&table->lock);
 625                 if (mlx5_destroy_unmap_eq(dev, eq))
 626                         mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
 627                                        eq->eqn);
 628                 kfree(eq);
 629                 spin_lock(&table->lock);
 630         }
 631         spin_unlock(&table->lock);
 632 }
 633
 634 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
 635 {
 636         struct mlx5_eq_table *table = &dev->priv.eq_table;
 637         struct mlx5_eq *eq;
 638         int ncomp_vec;
 639         int nent;
 640         int err;
 641         int i;
 642
 643         INIT_LIST_HEAD(&table->comp_eqs_list);
 644         ncomp_vec = table->num_comp_vectors;
 645         nent = MLX5_COMP_EQ_SIZE;
 646         for (i = 0; i < ncomp_vec; i++) {
 647                 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
 648
 649                 err = mlx5_create_map_eq(dev, eq,
 650                                          i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
 651                                          &dev->priv.uuari.uars[0]);
 652                 if (err) {
 653                         kfree(eq);
 654                         goto clean;
 655                 }
 656                 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
 657                 eq->index = i;
 658                 spin_lock(&table->lock);
 659                 list_add_tail(&eq->list, &table->comp_eqs_list);
 660                 spin_unlock(&table->lock);
 661         }
 662
 663         return 0;
 664
 665 clean:
 666         free_comp_eqs(dev);
 667         return err;
 668 }
 669
 670 static int map_bf_area(struct mlx5_core_dev *dev)
 671 {
 672         resource_size_t bf_start = pci_resource_start(dev->pdev, 0);
 673         resource_size_t bf_len = pci_resource_len(dev->pdev, 0);
 674
 675         dev->priv.bf_mapping = io_mapping_create_wc(bf_start, bf_len);
 676
 677         return dev->priv.bf_mapping ? 0 : -ENOMEM;
 678 }
 679
 680 static void unmap_bf_area(struct mlx5_core_dev *dev)
 681 {
 682         if (dev->priv.bf_mapping)
 683                 io_mapping_free(dev->priv.bf_mapping);
 684 }
 685
 686 static inline int fw_initializing(struct mlx5_core_dev *dev)
 687 {
 688         return ioread32be(&dev->iseg->initializing) >> 31;
 689 }
 690
 691 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
 692                         u32 warn_time_mili)
 693 {
 694         int warn = jiffies + msecs_to_jiffies(warn_time_mili);
 695         int end = jiffies + msecs_to_jiffies(max_wait_mili);
 696         int err = 0;
 697
 698         MPASS(max_wait_mili > warn_time_mili);
 699
 700         while (fw_initializing(dev) == 1) {
 701                 if (time_after(jiffies, end)) {
 702                         err = -EBUSY;
 703                         break;
 704                 }
 705                 if (warn_time_mili && time_after(jiffies, warn)) {
 706                         mlx5_core_warn(dev,
 707                             "Waiting for FW initialization, timeout abort in %u s\n",
 708                             (unsigned int)(jiffies_to_msecs(end - warn) / 1000));
 709                         warn = jiffies + msecs_to_jiffies(warn_time_mili);
 710                 }
 711                 msleep(FW_INIT_WAIT_MS);
 712         }
 713
 714         if (err != 0)
 715                 mlx5_core_dbg(dev, "Full initializing bit dword = 0x%x\n",
 716                     ioread32be(&dev->iseg->initializing));
 717
 718         return err;
 719 }
 720
 721 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
 722 {
 723         struct mlx5_device_context *dev_ctx;
 724         struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
 725
 726         dev_ctx = kzalloc(sizeof(*dev_ctx), GFP_KERNEL);
 727         if (!dev_ctx)
 728                 return;
 729
 730         dev_ctx->intf    = intf;
 731         CURVNET_SET_QUIET(vnet0);
 732         dev_ctx->context = intf->add(dev);
 733         CURVNET_RESTORE();
 734
 735         if (dev_ctx->context) {
 736                 spin_lock_irq(&priv->ctx_lock);
 737                 list_add_tail(&dev_ctx->list, &priv->ctx_list);
 738                 spin_unlock_irq(&priv->ctx_lock);
 739         } else {
 740                 kfree(dev_ctx);
 741         }
 742 }
 743
 744 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
 745 {
 746         struct mlx5_device_context *dev_ctx;
 747         struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
 748
 749         list_for_each_entry(dev_ctx, &priv->ctx_list, list)
 750                 if (dev_ctx->intf == intf) {
 751                         spin_lock_irq(&priv->ctx_lock);
 752                         list_del(&dev_ctx->list);
 753                         spin_unlock_irq(&priv->ctx_lock);
 754
 755                         intf->remove(dev, dev_ctx->context);
 756                         kfree(dev_ctx);
 757                         return;
 758                 }
 759 }
 760
 761 int
 762 mlx5_register_device(struct mlx5_core_dev *dev)
 763 {
 764         struct mlx5_priv *priv = &dev->priv;
 765         struct mlx5_interface *intf;
 766
 767         mutex_lock(&intf_mutex);
 768         list_add_tail(&priv->dev_list, &dev_list);
 769         list_for_each_entry(intf, &intf_list, list)
 770                 mlx5_add_device(intf, priv);
 771         mutex_unlock(&intf_mutex);
 772
 773         return 0;
 774 }
 775
 776 void
 777 mlx5_unregister_device(struct mlx5_core_dev *dev)
 778 {
 779         struct mlx5_priv *priv = &dev->priv;
 780         struct mlx5_interface *intf;
 781
 782         mutex_lock(&intf_mutex);
 783         list_for_each_entry(intf, &intf_list, list)
 784                 mlx5_remove_device(intf, priv);
 785         list_del(&priv->dev_list);
 786         mutex_unlock(&intf_mutex);
 787 }
 788
 789 int mlx5_register_interface(struct mlx5_interface *intf)
 790 {
 791         struct mlx5_priv *priv;
 792
 793         if (!intf->add || !intf->remove)
 794                 return -EINVAL;
 795
 796         mutex_lock(&intf_mutex);
 797         list_add_tail(&intf->list, &intf_list);
 798         list_for_each_entry(priv, &dev_list, dev_list)
 799                 mlx5_add_device(intf, priv);
 800         mutex_unlock(&intf_mutex);
 801
 802         return 0;
 803 }
 804 EXPORT_SYMBOL(mlx5_register_interface);
 805
 806 void mlx5_unregister_interface(struct mlx5_interface *intf)
 807 {
 808         struct mlx5_priv *priv;
 809
 810         mutex_lock(&intf_mutex);
 811         list_for_each_entry(priv, &dev_list, dev_list)
 812                 mlx5_remove_device(intf, priv);
 813         list_del(&intf->list);
 814         mutex_unlock(&intf_mutex);
 815 }
 816 EXPORT_SYMBOL(mlx5_unregister_interface);
 817
 818 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
 819 {
 820         struct mlx5_priv *priv = &mdev->priv;
 821         struct mlx5_device_context *dev_ctx;
 822         unsigned long flags;
 823         void *result = NULL;
 824
 825         spin_lock_irqsave(&priv->ctx_lock, flags);
 826
 827         list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
 828                 if ((dev_ctx->intf->protocol == protocol) &&
 829                     dev_ctx->intf->get_dev) {
 830                         result = dev_ctx->intf->get_dev(dev_ctx->context);
 831                         break;
 832                 }
 833
 834         spin_unlock_irqrestore(&priv->ctx_lock, flags);
 835
 836         return result;
 837 }
 838 EXPORT_SYMBOL(mlx5_get_protocol_dev);
 839
 840 static int mlx5_auto_fw_update;
 841 SYSCTL_INT(_hw_mlx5, OID_AUTO, auto_fw_update, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
 842     &mlx5_auto_fw_update, 0,
 843     "Allow automatic firmware update on driver start");
 844 static int
 845 mlx5_firmware_update(struct mlx5_core_dev *dev)
 846 {
 847         const struct firmware *fw;
 848         int err;
 849
 850         TUNABLE_INT_FETCH("hw.mlx5.auto_fw_update", &mlx5_auto_fw_update);
 851         if (!mlx5_auto_fw_update)
 852                 return (0);
 853         fw = firmware_get("mlx5fw_mfa");
 854         if (fw) {
 855                 err = mlx5_firmware_flash(dev, fw);
 856                 firmware_put(fw, FIRMWARE_UNLOAD);
 857         }
 858         else
 859                 return (-ENOENT);
 860
 861         return err;
 862 }
 863
 864 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
 865 {
 866         struct pci_dev *pdev = dev->pdev;
 867         device_t bsddev;
 868         int err;
 869
 870         pdev = dev->pdev;
 871         bsddev = pdev->dev.bsddev;
 872         pci_set_drvdata(dev->pdev, dev);
 873         strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
 874         priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
 875
 876         mutex_init(&priv->pgdir_mutex);
 877         INIT_LIST_HEAD(&priv->pgdir_list);
 878         spin_lock_init(&priv->mkey_lock);
 879
 880         priv->numa_node = NUMA_NO_NODE;
 881
 882         err = mlx5_pci_enable_device(dev);
 883         if (err) {
 884                 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n");
 885                 goto err_dbg;
 886         }
 887
 888         err = request_bar(pdev);
 889         if (err) {
 890                 mlx5_core_err(dev, "error requesting BARs, aborting\n");
 891                 goto err_disable;
 892         }
 893
 894         pci_set_master(pdev);
 895
 896         err = set_dma_caps(pdev);
 897         if (err) {
 898                 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n");
 899                 goto err_clr_master;
 900         }
 901
 902         dev->iseg_base = pci_resource_start(dev->pdev, 0);
 903         dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
 904         if (!dev->iseg) {
 905                 err = -ENOMEM;
 906                 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n");
 907                 goto err_clr_master;
 908         }
 909
 910         return 0;
 911
 912 err_clr_master:
 913         release_bar(dev->pdev);
 914 err_disable:
 915         mlx5_pci_disable_device(dev);
 916 err_dbg:
 917         return err;
 918 }
 919
 920 static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
 921 {
 922 #ifdef PCI_IOV
 923         if (MLX5_CAP_GEN(dev, eswitch_flow_table))
 924                 pci_iov_detach(dev->pdev->dev.bsddev);
 925 #endif
 926         iounmap(dev->iseg);
 927         release_bar(dev->pdev);
 928         mlx5_pci_disable_device(dev);
 929 }
 930
 931 static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
 932 {
 933         int err;
 934
 935         err = mlx5_vsc_find_cap(dev);
 936         if (err)
 937                 mlx5_core_err(dev, "Unable to find vendor specific capabilities\n");
 938
 939         err = mlx5_query_hca_caps(dev);
 940         if (err) {
 941                 mlx5_core_err(dev, "query hca failed\n");
 942                 goto out;
 943         }
 944
 945         err = mlx5_query_board_id(dev);
 946         if (err) {
 947                 mlx5_core_err(dev, "query board id failed\n");
 948                 goto out;
 949         }
 950
 951         err = mlx5_eq_init(dev);
 952         if (err) {
 953                 mlx5_core_err(dev, "failed to initialize eq\n");
 954                 goto out;
 955         }
 956
 957         MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
 958
 959         err = mlx5_init_cq_table(dev);
 960         if (err) {
 961                 mlx5_core_err(dev, "failed to initialize cq table\n");
 962                 goto err_eq_cleanup;
 963         }
 964
 965         mlx5_init_qp_table(dev);
 966         mlx5_init_srq_table(dev);
 967         mlx5_init_mr_table(dev);
 968
 969         mlx5_init_reserved_gids(dev);
 970         mlx5_fpga_init(dev);
 971
 972 #ifdef RATELIMIT
 973         err = mlx5_init_rl_table(dev);
 974         if (err) {
 975                 mlx5_core_err(dev, "Failed to init rate limiting\n");
 976                 goto err_tables_cleanup;
 977         }
 978 #endif
 979         return 0;
 980
 981 #ifdef RATELIMIT
 982 err_tables_cleanup:
 983         mlx5_cleanup_mr_table(dev);
 984         mlx5_cleanup_srq_table(dev);
 985         mlx5_cleanup_qp_table(dev);
 986         mlx5_cleanup_cq_table(dev);
 987 #endif
 988
 989 err_eq_cleanup:
 990         mlx5_eq_cleanup(dev);
 991
 992 out:
 993         return err;
 994 }
 995
 996 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
 997 {
 998 #ifdef RATELIMIT
 999         mlx5_cleanup_rl_table(dev);
1000 #endif
1001         mlx5_fpga_cleanup(dev);
1002         mlx5_cleanup_reserved_gids(dev);
1003         mlx5_cleanup_mr_table(dev);
1004         mlx5_cleanup_srq_table(dev);
1005         mlx5_cleanup_qp_table(dev);
1006         mlx5_cleanup_cq_table(dev);
1007         mlx5_eq_cleanup(dev);
1008 }
1009
1010 static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1011                          bool boot)
1012 {
1013         int err;
1014
1015         mutex_lock(&dev->intf_state_mutex);
1016         if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1017                 mlx5_core_warn(dev, "interface is up, NOP\n");
1018                 goto out;
1019         }
1020
1021         mlx5_core_dbg(dev, "firmware version: %d.%d.%d\n",
1022             fw_rev_maj(dev), fw_rev_min(dev), fw_rev_sub(dev));
1023
1024         /*
1025          * On load removing any previous indication of internal error,
1026          * device is up
1027          */
1028         dev->state = MLX5_DEVICE_STATE_UP;
1029
1030         /* wait for firmware to accept initialization segments configurations
1031         */
1032         err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI,
1033             FW_INIT_WARN_MESSAGE_INTERVAL);
1034         if (err) {
1035                 dev_err(&dev->pdev->dev,
1036                     "Firmware over %d MS in pre-initializing state, aborting\n",
1037                     FW_PRE_INIT_TIMEOUT_MILI);
1038                 goto out_err;
1039         }
1040
1041         err = mlx5_cmd_init(dev);
1042         if (err) {
1043                 mlx5_core_err(dev,
1044                     "Failed initializing command interface, aborting\n");
1045                 goto out_err;
1046         }
1047
1048         err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI, 0);
1049         if (err) {
1050                 mlx5_core_err(dev,
1051                     "Firmware over %d MS in initializing state, aborting\n",
1052                     FW_INIT_TIMEOUT_MILI);
1053                 goto err_cmd_cleanup;
1054         }
1055
1056         err = mlx5_core_enable_hca(dev, 0);
1057         if (err) {
1058                 mlx5_core_err(dev, "enable hca failed\n");
1059                 goto err_cmd_cleanup;
1060         }
1061
1062         err = mlx5_core_set_issi(dev);
1063         if (err) {
1064                 mlx5_core_err(dev, "failed to set issi\n");
1065                 goto err_disable_hca;
1066         }
1067
1068         err = mlx5_pagealloc_start(dev);
1069         if (err) {
1070                 mlx5_core_err(dev, "mlx5_pagealloc_start failed\n");
1071                 goto err_disable_hca;
1072         }
1073
1074         err = mlx5_satisfy_startup_pages(dev, 1);
1075         if (err) {
1076                 mlx5_core_err(dev, "failed to allocate boot pages\n");
1077                 goto err_pagealloc_stop;
1078         }
1079
1080         err = set_hca_ctrl(dev);
1081         if (err) {
1082                 mlx5_core_err(dev, "set_hca_ctrl failed\n");
1083                 goto reclaim_boot_pages;
1084         }
1085
1086         err = handle_hca_cap(dev);
1087         if (err) {
1088                 mlx5_core_err(dev, "handle_hca_cap failed\n");
1089                 goto reclaim_boot_pages;
1090         }
1091
1092         err = handle_hca_cap_atomic(dev);
1093         if (err) {
1094                 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n");
1095                 goto reclaim_boot_pages;
1096         }
1097
1098         err = mlx5_satisfy_startup_pages(dev, 0);
1099         if (err) {
1100                 mlx5_core_err(dev, "failed to allocate init pages\n");
1101                 goto reclaim_boot_pages;
1102         }
1103
1104         err = mlx5_cmd_init_hca(dev);
1105         if (err) {
1106                 mlx5_core_err(dev, "init hca failed\n");
1107                 goto reclaim_boot_pages;
1108         }
1109
1110         mlx5_start_health_poll(dev);
1111
1112         if (boot && mlx5_init_once(dev, priv)) {
1113                 mlx5_core_err(dev, "sw objs init failed\n");
1114                 goto err_stop_poll;
1115         }
1116
1117         err = mlx5_enable_msix(dev);
1118         if (err) {
1119                 mlx5_core_err(dev, "enable msix failed\n");
1120                 goto err_cleanup_once;
1121         }
1122
1123         err = mlx5_alloc_uuars(dev, &priv->uuari);
1124         if (err) {
1125                 mlx5_core_err(dev, "Failed allocating uar, aborting\n");
1126                 goto err_disable_msix;
1127         }
1128
1129         err = mlx5_start_eqs(dev);
1130         if (err) {
1131                 mlx5_core_err(dev, "Failed to start pages and async EQs\n");
1132                 goto err_free_uar;
1133         }
1134
1135         err = alloc_comp_eqs(dev);
1136         if (err) {
1137                 mlx5_core_err(dev, "Failed to alloc completion EQs\n");
1138                 goto err_stop_eqs;
1139         }
1140
1141         if (map_bf_area(dev))
1142                 mlx5_core_err(dev, "Failed to map blue flame area\n");
1143
1144         err = mlx5_init_fs(dev);
1145         if (err) {
1146                 mlx5_core_err(dev, "flow steering init %d\n", err);
1147                 goto err_free_comp_eqs;
1148         }
1149
1150         err = mlx5_mpfs_init(dev);
1151         if (err) {
1152                 mlx5_core_err(dev, "mpfs init failed %d\n", err);
1153                 goto err_fs;
1154         }
1155
1156         err = mlx5_fpga_device_start(dev);
1157         if (err) {
1158                 mlx5_core_err(dev, "fpga device start failed %d\n", err);
1159                 goto err_mpfs;
1160         }
1161
1162         err = mlx5_register_device(dev);
1163         if (err) {
1164                 mlx5_core_err(dev, "mlx5_register_device failed %d\n", err);
1165                 goto err_fpga;
1166         }
1167
1168         set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1169
1170 out:
1171         mutex_unlock(&dev->intf_state_mutex);
1172         return 0;
1173
1174 err_fpga:
1175         mlx5_fpga_device_stop(dev);
1176
1177 err_mpfs:
1178         mlx5_mpfs_destroy(dev);
1179
1180 err_fs:
1181         mlx5_cleanup_fs(dev);
1182
1183 err_free_comp_eqs:
1184         free_comp_eqs(dev);
1185         unmap_bf_area(dev);
1186
1187 err_stop_eqs:
1188         mlx5_stop_eqs(dev);
1189
1190 err_free_uar:
1191         mlx5_free_uuars(dev, &priv->uuari);
1192
1193 err_disable_msix:
1194         mlx5_disable_msix(dev);
1195
1196 err_cleanup_once:
1197         if (boot)
1198                 mlx5_cleanup_once(dev);
1199
1200 err_stop_poll:
1201         mlx5_stop_health_poll(dev, boot);
1202         if (mlx5_cmd_teardown_hca(dev)) {
1203                 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1204                 goto out_err;
1205         }
1206
1207 reclaim_boot_pages:
1208         mlx5_reclaim_startup_pages(dev);
1209
1210 err_pagealloc_stop:
1211         mlx5_pagealloc_stop(dev);
1212
1213 err_disable_hca:
1214         mlx5_core_disable_hca(dev);
1215
1216 err_cmd_cleanup:
1217         mlx5_cmd_cleanup(dev);
1218
1219 out_err:
1220         dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1221         mutex_unlock(&dev->intf_state_mutex);
1222
1223         return err;
1224 }
1225
1226 static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1227                            bool cleanup)
1228 {
1229         int err = 0;
1230
1231         if (cleanup)
1232                 mlx5_drain_health_recovery(dev);
1233
1234         mutex_lock(&dev->intf_state_mutex);
1235         if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1236                 mlx5_core_warn(dev, "%s: interface is down, NOP\n", __func__);
1237                 if (cleanup)
1238                         mlx5_cleanup_once(dev);
1239                 goto out;
1240         }
1241
1242         mlx5_unregister_device(dev);
1243
1244         mlx5_eswitch_cleanup(dev->priv.eswitch);
1245         mlx5_fpga_device_stop(dev);
1246         mlx5_mpfs_destroy(dev);
1247         mlx5_cleanup_fs(dev);
1248         unmap_bf_area(dev);
1249         mlx5_wait_for_reclaim_vfs_pages(dev);
1250         free_comp_eqs(dev);
1251         mlx5_stop_eqs(dev);
1252         mlx5_free_uuars(dev, &priv->uuari);
1253         mlx5_disable_msix(dev);
1254         if (cleanup)
1255                 mlx5_cleanup_once(dev);
1256         mlx5_stop_health_poll(dev, cleanup);
1257         err = mlx5_cmd_teardown_hca(dev);
1258         if (err) {
1259                 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1260                 goto out;
1261         }
1262         mlx5_pagealloc_stop(dev);
1263         mlx5_reclaim_startup_pages(dev);
1264         mlx5_core_disable_hca(dev);
1265         mlx5_cmd_cleanup(dev);
1266
1267 out:
1268         clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1269         mutex_unlock(&dev->intf_state_mutex);
1270         return err;
1271 }
1272
1273 void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
1274                      unsigned long param)
1275 {
1276         struct mlx5_priv *priv = &dev->priv;
1277         struct mlx5_device_context *dev_ctx;
1278         unsigned long flags;
1279
1280         spin_lock_irqsave(&priv->ctx_lock, flags);
1281
1282         list_for_each_entry(dev_ctx, &priv->ctx_list, list)
1283                 if (dev_ctx->intf->event)
1284                         dev_ctx->intf->event(dev, dev_ctx->context, event, param);
1285
1286         spin_unlock_irqrestore(&priv->ctx_lock, flags);
1287 }
1288
1289 struct mlx5_core_event_handler {
1290         void (*event)(struct mlx5_core_dev *dev,
1291                       enum mlx5_dev_event event,
1292                       void *data);
1293 };
1294
1295 #define MLX5_STATS_DESC(a, b, c, d, e, ...) d, e,
1296
1297 #define MLX5_PORT_MODULE_ERROR_STATS(m)                         \
1298 m(+1, u64, power_budget_exceeded, "power_budget", "Module Power Budget Exceeded") \
1299 m(+1, u64, long_range, "long_range", "Module Long Range for non MLNX cable/module") \
1300 m(+1, u64, bus_stuck, "bus_stuck", "Module Bus stuck(I2C or data shorted)") \
1301 m(+1, u64, no_eeprom, "no_eeprom", "No EEPROM/retry timeout") \
1302 m(+1, u64, enforce_part_number, "enforce_part_number", "Module Enforce part number list") \
1303 m(+1, u64, unknown_id, "unknown_id", "Module Unknown identifier") \
1304 m(+1, u64, high_temp, "high_temp", "Module High Temperature") \
1305 m(+1, u64, cable_shorted, "cable_shorted", "Module Cable is shorted") \
1306 m(+1, u64, pmd_type_not_enabled, "pmd_type_not_enabled", "PMD type is not enabled") \
1307 m(+1, u64, laster_tec_failure, "laster_tec_failure", "Laster TEC failure") \
1308 m(+1, u64, high_current, "high_current", "High current") \
1309 m(+1, u64, high_voltage, "high_voltage", "High voltage") \
1310 m(+1, u64, pcie_sys_power_slot_exceeded, "pcie_sys_power_slot_exceeded", "PCIe system power slot Exceeded") \
1311 m(+1, u64, high_power, "high_power", "High power")                      \
1312 m(+1, u64, module_state_machine_fault, "module_state_machine_fault", "Module State Machine fault")
1313
1314 static const char *mlx5_pme_err_desc[] = {
1315         MLX5_PORT_MODULE_ERROR_STATS(MLX5_STATS_DESC)
1316 };
1317
1318 static int init_one(struct pci_dev *pdev,
1319                     const struct pci_device_id *id)
1320 {
1321         struct mlx5_core_dev *dev;
1322         struct mlx5_priv *priv;
1323         device_t bsddev = pdev->dev.bsddev;
1324 #ifdef PCI_IOV
1325         nvlist_t *pf_schema, *vf_schema;
1326         int num_vfs, sriov_pos;
1327 #endif
1328         int i,err;
1329         struct sysctl_oid *pme_sysctl_node;
1330         struct sysctl_oid *pme_err_sysctl_node;
1331         struct sysctl_oid *cap_sysctl_node;
1332         struct sysctl_oid *current_cap_sysctl_node;
1333         struct sysctl_oid *max_cap_sysctl_node;
1334
1335         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1336         priv = &dev->priv;
1337         if (id)
1338                 priv->pci_dev_data = id->driver_data;
1339
1340         if (mlx5_prof_sel < 0 || mlx5_prof_sel >= ARRAY_SIZE(profiles)) {
1341                 device_printf(bsddev,
1342                     "WARN: selected profile out of range, selecting default (%d)\n",
1343                     MLX5_DEFAULT_PROF);
1344                 mlx5_prof_sel = MLX5_DEFAULT_PROF;
1345         }
1346         dev->profile = &profiles[mlx5_prof_sel];
1347         dev->pdev = pdev;
1348         dev->event = mlx5_core_event;
1349
1350         /* Set desc */
1351         device_set_desc(bsddev, mlx5_version);
1352
1353         sysctl_ctx_init(&dev->sysctl_ctx);
1354         SYSCTL_ADD_INT(&dev->sysctl_ctx,
1355             SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)),
1356             OID_AUTO, "msix_eqvec", CTLFLAG_RDTUN, &dev->msix_eqvec, 0,
1357             "Maximum number of MSIX event queue vectors, if set");
1358         SYSCTL_ADD_INT(&dev->sysctl_ctx,
1359             SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)),
1360             OID_AUTO, "power_status", CTLFLAG_RD, &dev->pwr_status, 0,
1361             "0:Invalid 1:Sufficient 2:Insufficient");
1362         SYSCTL_ADD_INT(&dev->sysctl_ctx,
1363             SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)),
1364             OID_AUTO, "power_value", CTLFLAG_RD, &dev->pwr_value, 0,
1365             "Current power value in Watts");
1366
1367         pme_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx,
1368             SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)),
1369             OID_AUTO, "pme_stats", CTLFLAG_RD, NULL,
1370             "Port module event statistics");
1371         if (pme_sysctl_node == NULL) {
1372                 err = -ENOMEM;
1373                 goto clean_sysctl_ctx;
1374         }
1375         pme_err_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx,
1376             SYSCTL_CHILDREN(pme_sysctl_node),
1377             OID_AUTO, "errors", CTLFLAG_RD, NULL,
1378             "Port module event error statistics");
1379         if (pme_err_sysctl_node == NULL) {
1380                 err = -ENOMEM;
1381                 goto clean_sysctl_ctx;
1382         }
1383         SYSCTL_ADD_U64(&dev->sysctl_ctx,
1384             SYSCTL_CHILDREN(pme_sysctl_node), OID_AUTO,
1385             "module_plug", CTLFLAG_RD | CTLFLAG_MPSAFE,
1386             &dev->priv.pme_stats.status_counters[MLX5_MODULE_STATUS_PLUGGED_ENABLED],
1387             0, "Number of time module plugged");
1388         SYSCTL_ADD_U64(&dev->sysctl_ctx,
1389             SYSCTL_CHILDREN(pme_sysctl_node), OID_AUTO,
1390             "module_unplug", CTLFLAG_RD | CTLFLAG_MPSAFE,
1391             &dev->priv.pme_stats.status_counters[MLX5_MODULE_STATUS_UNPLUGGED],
1392             0, "Number of time module unplugged");
1393         for (i = 0 ; i < MLX5_MODULE_EVENT_ERROR_NUM; i++) {
1394                 SYSCTL_ADD_U64(&dev->sysctl_ctx,
1395                     SYSCTL_CHILDREN(pme_err_sysctl_node), OID_AUTO,
1396                     mlx5_pme_err_desc[2 * i], CTLFLAG_RD | CTLFLAG_MPSAFE,
1397                     &dev->priv.pme_stats.error_counters[i],
1398                     0, mlx5_pme_err_desc[2 * i + 1]);
1399         }
1400
1401         cap_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx,
1402             SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)),
1403             OID_AUTO, "caps", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
1404             "hardware capabilities raw bitstrings");
1405         if (cap_sysctl_node == NULL) {
1406                 err = -ENOMEM;
1407                 goto clean_sysctl_ctx;
1408         }
1409         current_cap_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx,
1410             SYSCTL_CHILDREN(cap_sysctl_node),
1411             OID_AUTO, "current", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
1412             "");
1413         if (current_cap_sysctl_node == NULL) {
1414                 err = -ENOMEM;
1415                 goto clean_sysctl_ctx;
1416         }
1417         max_cap_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx,
1418             SYSCTL_CHILDREN(cap_sysctl_node),
1419             OID_AUTO, "max", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
1420             "");
1421         if (max_cap_sysctl_node == NULL) {
1422                 err = -ENOMEM;
1423                 goto clean_sysctl_ctx;
1424         }
1425         SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1426             SYSCTL_CHILDREN(current_cap_sysctl_node),
1427             OID_AUTO, "general", CTLFLAG_RD | CTLFLAG_MPSAFE,
1428             &dev->hca_caps_cur[MLX5_CAP_GENERAL],
1429             MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1430         SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1431             SYSCTL_CHILDREN(max_cap_sysctl_node),
1432             OID_AUTO, "general", CTLFLAG_RD | CTLFLAG_MPSAFE,
1433             &dev->hca_caps_max[MLX5_CAP_GENERAL],
1434             MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1435         SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1436             SYSCTL_CHILDREN(current_cap_sysctl_node),
1437             OID_AUTO, "ether", CTLFLAG_RD | CTLFLAG_MPSAFE,
1438             &dev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS],
1439             MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1440         SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1441             SYSCTL_CHILDREN(max_cap_sysctl_node),
1442             OID_AUTO, "ether", CTLFLAG_RD | CTLFLAG_MPSAFE,
1443             &dev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS],
1444             MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1445         SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1446             SYSCTL_CHILDREN(current_cap_sysctl_node),
1447             OID_AUTO, "odp", CTLFLAG_RD | CTLFLAG_MPSAFE,
1448             &dev->hca_caps_cur[MLX5_CAP_ODP],
1449             MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1450         SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1451             SYSCTL_CHILDREN(max_cap_sysctl_node),
1452             OID_AUTO, "odp", CTLFLAG_RD | CTLFLAG_MPSAFE,
1453             &dev->hca_caps_max[MLX5_CAP_ODP],
1454             MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1455         SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1456             SYSCTL_CHILDREN(current_cap_sysctl_node),
1457             OID_AUTO, "atomic", CTLFLAG_RD | CTLFLAG_MPSAFE,
1458             &dev->hca_caps_cur[MLX5_CAP_ATOMIC],
1459             MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1460         SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1461             SYSCTL_CHILDREN(max_cap_sysctl_node),
1462             OID_AUTO, "atomic", CTLFLAG_RD | CTLFLAG_MPSAFE,
1463             &dev->hca_caps_max[MLX5_CAP_ATOMIC],
1464             MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1465         SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1466             SYSCTL_CHILDREN(current_cap_sysctl_node),
1467             OID_AUTO, "roce", CTLFLAG_RD | CTLFLAG_MPSAFE,
1468             &dev->hca_caps_cur[MLX5_CAP_ROCE],
1469             MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1470         SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1471             SYSCTL_CHILDREN(max_cap_sysctl_node),
1472             OID_AUTO, "roce", CTLFLAG_RD | CTLFLAG_MPSAFE,
1473             &dev->hca_caps_max[MLX5_CAP_ROCE],
1474             MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1475         SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1476             SYSCTL_CHILDREN(current_cap_sysctl_node),
1477             OID_AUTO, "ipoib", CTLFLAG_RD | CTLFLAG_MPSAFE,
1478             &dev->hca_caps_cur[MLX5_CAP_IPOIB_OFFLOADS],
1479             MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1480         SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1481             SYSCTL_CHILDREN(max_cap_sysctl_node),
1482             OID_AUTO, "ipoib", CTLFLAG_RD | CTLFLAG_MPSAFE,
1483             &dev->hca_caps_max[MLX5_CAP_IPOIB_OFFLOADS],
1484             MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1485         SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1486             SYSCTL_CHILDREN(current_cap_sysctl_node),
1487             OID_AUTO, "eoib", CTLFLAG_RD | CTLFLAG_MPSAFE,
1488             &dev->hca_caps_cur[MLX5_CAP_EOIB_OFFLOADS],
1489             MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1490         SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1491             SYSCTL_CHILDREN(max_cap_sysctl_node),
1492             OID_AUTO, "eoib", CTLFLAG_RD | CTLFLAG_MPSAFE,
1493             &dev->hca_caps_max[MLX5_CAP_EOIB_OFFLOADS],
1494             MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1495         SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1496             SYSCTL_CHILDREN(current_cap_sysctl_node),
1497             OID_AUTO, "flow_table", CTLFLAG_RD | CTLFLAG_MPSAFE,
1498             &dev->hca_caps_cur[MLX5_CAP_FLOW_TABLE],
1499             MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1500         SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1501             SYSCTL_CHILDREN(max_cap_sysctl_node),
1502             OID_AUTO, "flow_table", CTLFLAG_RD | CTLFLAG_MPSAFE,
1503             &dev->hca_caps_max[MLX5_CAP_FLOW_TABLE],
1504             MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1505         SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1506             SYSCTL_CHILDREN(current_cap_sysctl_node),
1507             OID_AUTO, "eswitch_flow_table", CTLFLAG_RD | CTLFLAG_MPSAFE,
1508             &dev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE],
1509             MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1510         SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1511             SYSCTL_CHILDREN(max_cap_sysctl_node),
1512             OID_AUTO, "eswitch_flow_table", CTLFLAG_RD | CTLFLAG_MPSAFE,
1513             &dev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE],
1514             MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1515         SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1516             SYSCTL_CHILDREN(current_cap_sysctl_node),
1517             OID_AUTO, "eswitch", CTLFLAG_RD | CTLFLAG_MPSAFE,
1518             &dev->hca_caps_cur[MLX5_CAP_ESWITCH],
1519             MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1520         SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1521             SYSCTL_CHILDREN(max_cap_sysctl_node),
1522             OID_AUTO, "eswitch", CTLFLAG_RD | CTLFLAG_MPSAFE,
1523             &dev->hca_caps_max[MLX5_CAP_ESWITCH],
1524             MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1525         SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1526             SYSCTL_CHILDREN(current_cap_sysctl_node),
1527             OID_AUTO, "snapshot", CTLFLAG_RD | CTLFLAG_MPSAFE,
1528             &dev->hca_caps_cur[MLX5_CAP_SNAPSHOT],
1529             MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1530         SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1531             SYSCTL_CHILDREN(max_cap_sysctl_node),
1532             OID_AUTO, "snapshot", CTLFLAG_RD | CTLFLAG_MPSAFE,
1533             &dev->hca_caps_max[MLX5_CAP_SNAPSHOT],
1534             MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1535         SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1536             SYSCTL_CHILDREN(current_cap_sysctl_node),
1537             OID_AUTO, "vector_calc", CTLFLAG_RD | CTLFLAG_MPSAFE,
1538             &dev->hca_caps_cur[MLX5_CAP_VECTOR_CALC],
1539             MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1540         SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1541             SYSCTL_CHILDREN(max_cap_sysctl_node),
1542             OID_AUTO, "vector_calc", CTLFLAG_RD | CTLFLAG_MPSAFE,
1543             &dev->hca_caps_max[MLX5_CAP_VECTOR_CALC],
1544             MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1545         SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1546             SYSCTL_CHILDREN(current_cap_sysctl_node),
1547             OID_AUTO, "qos", CTLFLAG_RD | CTLFLAG_MPSAFE,
1548             &dev->hca_caps_cur[MLX5_CAP_QOS],
1549             MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1550         SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1551             SYSCTL_CHILDREN(max_cap_sysctl_node),
1552             OID_AUTO, "qos", CTLFLAG_RD | CTLFLAG_MPSAFE,
1553             &dev->hca_caps_max[MLX5_CAP_QOS],
1554             MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1555         SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1556             SYSCTL_CHILDREN(current_cap_sysctl_node),
1557             OID_AUTO, "debug", CTLFLAG_RD | CTLFLAG_MPSAFE,
1558             &dev->hca_caps_cur[MLX5_CAP_DEBUG],
1559             MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1560         SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1561             SYSCTL_CHILDREN(max_cap_sysctl_node),
1562             OID_AUTO, "debug", CTLFLAG_RD | CTLFLAG_MPSAFE,
1563             &dev->hca_caps_max[MLX5_CAP_DEBUG],
1564             MLX5_UN_SZ_DW(hca_cap_union) * sizeof(u32), "IU", "");
1565         SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1566             SYSCTL_CHILDREN(cap_sysctl_node),
1567             OID_AUTO, "pcam", CTLFLAG_RD | CTLFLAG_MPSAFE,
1568             &dev->caps.pcam, sizeof(dev->caps.pcam), "IU", "");
1569         SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1570             SYSCTL_CHILDREN(cap_sysctl_node),
1571             OID_AUTO, "mcam", CTLFLAG_RD | CTLFLAG_MPSAFE,
1572             &dev->caps.mcam, sizeof(dev->caps.mcam), "IU", "");
1573         SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1574             SYSCTL_CHILDREN(cap_sysctl_node),
1575             OID_AUTO, "qcam", CTLFLAG_RD | CTLFLAG_MPSAFE,
1576             &dev->caps.qcam, sizeof(dev->caps.qcam), "IU", "");
1577         SYSCTL_ADD_OPAQUE(&dev->sysctl_ctx,
1578             SYSCTL_CHILDREN(cap_sysctl_node),
1579             OID_AUTO, "fpga", CTLFLAG_RD | CTLFLAG_MPSAFE,
1580             &dev->caps.fpga, sizeof(dev->caps.fpga), "IU", "");
1581
1582         INIT_LIST_HEAD(&priv->ctx_list);
1583         spin_lock_init(&priv->ctx_lock);
1584         mutex_init(&dev->pci_status_mutex);
1585         mutex_init(&dev->intf_state_mutex);
1586         mtx_init(&dev->dump_lock, "mlx5dmp", NULL, MTX_DEF | MTX_NEW);
1587         err = mlx5_pci_init(dev, priv);
1588         if (err) {
1589                 mlx5_core_err(dev, "mlx5_pci_init failed %d\n", err);
1590                 goto clean_dev;
1591         }
1592
1593         err = mlx5_health_init(dev);
1594         if (err) {
1595                 mlx5_core_err(dev, "mlx5_health_init failed %d\n", err);
1596                 goto close_pci;
1597         }
1598
1599         mlx5_pagealloc_init(dev);
1600
1601         err = mlx5_load_one(dev, priv, true);
1602         if (err) {
1603                 mlx5_core_err(dev, "mlx5_load_one failed %d\n", err);
1604                 goto clean_health;
1605         }
1606
1607         mlx5_fwdump_prep(dev);
1608
1609         mlx5_firmware_update(dev);
1610
1611 #ifdef PCI_IOV
1612         if (MLX5_CAP_GEN(dev, vport_group_manager)) {
1613                 if (pci_find_extcap(bsddev, PCIZ_SRIOV, &sriov_pos) == 0) {
1614                         num_vfs = pci_read_config(bsddev, sriov_pos +
1615                             PCIR_SRIOV_TOTAL_VFS, 2);
1616                 } else {
1617                         mlx5_core_info(dev, "cannot find SR-IOV PCIe cap\n");
1618                         num_vfs = 0;
1619                 }
1620                 err = mlx5_eswitch_init(dev, 1 + num_vfs);
1621                 if (err == 0) {
1622                         pf_schema = pci_iov_schema_alloc_node();
1623                         vf_schema = pci_iov_schema_alloc_node();
1624                         pci_iov_schema_add_unicast_mac(vf_schema,
1625                             iov_mac_addr_name, 0, NULL);
1626                         err = pci_iov_attach(bsddev, pf_schema, vf_schema);
1627                         if (err != 0) {
1628                                 device_printf(bsddev,
1629                             "Failed to initialize SR-IOV support, error %d\n",
1630                                     err);
1631                         }
1632                 } else {
1633                         mlx5_core_err(dev, "eswitch init failed, error %d\n",
1634                             err);
1635                 }
1636         }
1637 #endif
1638
1639         pci_save_state(bsddev);
1640         return 0;
1641
1642 clean_health:
1643         mlx5_pagealloc_cleanup(dev);
1644         mlx5_health_cleanup(dev);
1645 close_pci:
1646         mlx5_pci_close(dev, priv);
1647 clean_dev:
1648         mtx_destroy(&dev->dump_lock);
1649 clean_sysctl_ctx:
1650         sysctl_ctx_free(&dev->sysctl_ctx);
1651         kfree(dev);
1652         return err;
1653 }
1654
1655 static void remove_one(struct pci_dev *pdev)
1656 {
1657         struct mlx5_core_dev *dev  = pci_get_drvdata(pdev);
1658         struct mlx5_priv *priv = &dev->priv;
1659
1660         if (mlx5_unload_one(dev, priv, true)) {
1661                 mlx5_core_err(dev, "mlx5_unload_one failed\n");
1662                 mlx5_health_cleanup(dev);
1663                 return;
1664         }
1665
1666         mlx5_pagealloc_cleanup(dev);
1667         mlx5_health_cleanup(dev);
1668         mlx5_fwdump_clean(dev);
1669         mlx5_pci_close(dev, priv);
1670         mtx_destroy(&dev->dump_lock);
1671         pci_set_drvdata(pdev, NULL);
1672         sysctl_ctx_free(&dev->sysctl_ctx);
1673         kfree(dev);
1674 }
1675
1676 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1677                                               pci_channel_state_t state)
1678 {
1679         struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1680         struct mlx5_priv *priv = &dev->priv;
1681
1682         mlx5_core_info(dev, "%s was called\n", __func__);
1683         mlx5_enter_error_state(dev, false);
1684         mlx5_unload_one(dev, priv, false);
1685
1686         if (state) {
1687                 mlx5_drain_health_wq(dev);
1688                 mlx5_pci_disable_device(dev);
1689         }
1690
1691         return state == pci_channel_io_perm_failure ?
1692                 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1693 }
1694
1695 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1696 {
1697         struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1698         int err = 0;
1699
1700         mlx5_core_info(dev,"%s was called\n", __func__);
1701
1702         err = mlx5_pci_enable_device(dev);
1703         if (err) {
1704                 mlx5_core_err(dev, "mlx5_pci_enable_device failed with error code: %d\n"
1705                         ,err);
1706                 return PCI_ERS_RESULT_DISCONNECT;
1707         }
1708         pci_set_master(pdev);
1709         pci_set_powerstate(pdev->dev.bsddev, PCI_POWERSTATE_D0);
1710         pci_restore_state(pdev->dev.bsddev);
1711         pci_save_state(pdev->dev.bsddev);
1712
1713         return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
1714 }
1715
1716 /* wait for the device to show vital signs. For now we check
1717  * that we can read the device ID and that the health buffer
1718  * shows a non zero value which is different than 0xffffffff
1719  */
1720 static void wait_vital(struct pci_dev *pdev)
1721 {
1722         struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1723         struct mlx5_core_health *health = &dev->priv.health;
1724         const int niter = 100;
1725         u32 count;
1726         u16 did;
1727         int i;
1728
1729         /* Wait for firmware to be ready after reset */
1730         msleep(1000);
1731         for (i = 0; i < niter; i++) {
1732                 if (pci_read_config_word(pdev, 2, &did)) {
1733                         mlx5_core_warn(dev, "failed reading config word\n");
1734                         break;
1735                 }
1736                 if (did == pdev->device) {
1737                         mlx5_core_info(dev,
1738                             "device ID correctly read after %d iterations\n", i);
1739                         break;
1740                 }
1741                 msleep(50);
1742         }
1743         if (i == niter)
1744                 mlx5_core_warn(dev, "could not read device ID\n");
1745
1746         for (i = 0; i < niter; i++) {
1747                 count = ioread32be(health->health_counter);
1748                 if (count && count != 0xffffffff) {
1749                         mlx5_core_info(dev,
1750                         "Counter value 0x%x after %d iterations\n", count, i);
1751                         break;
1752                 }
1753                 msleep(50);
1754         }
1755
1756         if (i == niter)
1757                 mlx5_core_warn(dev, "could not read device ID\n");
1758 }
1759
1760 static void mlx5_pci_resume(struct pci_dev *pdev)
1761 {
1762         struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1763         struct mlx5_priv *priv = &dev->priv;
1764         int err;
1765
1766         mlx5_core_info(dev,"%s was called\n", __func__);
1767
1768         wait_vital(pdev);
1769
1770         err = mlx5_load_one(dev, priv, false);
1771         if (err)
1772                 mlx5_core_err(dev,
1773                     "mlx5_load_one failed with error code: %d\n" ,err);
1774         else
1775                 mlx5_core_info(dev,"device recovered\n");
1776 }
1777
1778 static const struct pci_error_handlers mlx5_err_handler = {
1779         .error_detected = mlx5_pci_err_detected,
1780         .slot_reset     = mlx5_pci_slot_reset,
1781         .resume         = mlx5_pci_resume
1782 };
1783
1784 #ifdef PCI_IOV
1785 static int
1786 mlx5_iov_init(device_t dev, uint16_t num_vfs, const nvlist_t *pf_config)
1787 {
1788         struct pci_dev *pdev;
1789         struct mlx5_core_dev *core_dev;
1790         struct mlx5_priv *priv;
1791         int err;
1792
1793         pdev = device_get_softc(dev);
1794         core_dev = pci_get_drvdata(pdev);
1795         priv = &core_dev->priv;
1796
1797         if (priv->eswitch == NULL)
1798                 return (ENXIO);
1799         if (priv->eswitch->total_vports < num_vfs + 1)
1800                 num_vfs = priv->eswitch->total_vports - 1;
1801         err = mlx5_eswitch_enable_sriov(priv->eswitch, num_vfs);
1802         return (-err);
1803 }
1804
1805 static void
1806 mlx5_iov_uninit(device_t dev)
1807 {
1808         struct pci_dev *pdev;
1809         struct mlx5_core_dev *core_dev;
1810         struct mlx5_priv *priv;
1811
1812         pdev = device_get_softc(dev);
1813         core_dev = pci_get_drvdata(pdev);
1814         priv = &core_dev->priv;
1815
1816         mlx5_eswitch_disable_sriov(priv->eswitch);
1817 }
1818
1819 static int
1820 mlx5_iov_add_vf(device_t dev, uint16_t vfnum, const nvlist_t *vf_config)
1821 {
1822         struct pci_dev *pdev;
1823         struct mlx5_core_dev *core_dev;
1824         struct mlx5_priv *priv;
1825         const void *mac;
1826         size_t mac_size;
1827         int error;
1828
1829         pdev = device_get_softc(dev);
1830         core_dev = pci_get_drvdata(pdev);
1831         priv = &core_dev->priv;
1832
1833         if (vfnum + 1 >= priv->eswitch->total_vports)
1834                 return (ENXIO);
1835
1836         if (nvlist_exists_binary(vf_config, iov_mac_addr_name)) {
1837                 mac = nvlist_get_binary(vf_config, iov_mac_addr_name,
1838                     &mac_size);
1839                 error = -mlx5_eswitch_set_vport_mac(priv->eswitch,
1840                     vfnum + 1, __DECONST(u8 *, mac));
1841                 if (error != 0) {
1842                         mlx5_core_err(core_dev,
1843                             "setting MAC for VF %d failed, error %d\n",
1844                             vfnum + 1, error);
1845                 }
1846         }
1847
1848         error = -mlx5_eswitch_set_vport_state(priv->eswitch, vfnum + 1,
1849             VPORT_STATE_FOLLOW);
1850         if (error != 0) {
1851                 mlx5_core_err(core_dev,
1852                     "upping vport for VF %d failed, error %d\n",
1853                     vfnum + 1, error);
1854         }
1855         error = -mlx5_core_enable_hca(core_dev, vfnum + 1);
1856         if (error != 0) {
1857                 mlx5_core_err(core_dev, "enabling VF %d failed, error %d\n",
1858                     vfnum + 1, error);
1859         }
1860         return (error);
1861 }
1862 #endif
1863
1864 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1865 {
1866         bool fast_teardown, force_teardown;
1867         int err;
1868
1869         if (!mlx5_fast_unload_enabled) {
1870                 mlx5_core_dbg(dev, "fast unload is disabled by user\n");
1871                 return -EOPNOTSUPP;
1872         }
1873
1874         fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
1875         force_teardown = MLX5_CAP_GEN(dev, force_teardown);
1876
1877         mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
1878         mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
1879
1880         if (!fast_teardown && !force_teardown)
1881                 return -EOPNOTSUPP;
1882
1883         if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1884                 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1885                 return -EAGAIN;
1886         }
1887
1888         /* Panic tear down fw command will stop the PCI bus communication
1889          * with the HCA, so the health polll is no longer needed.
1890          */
1891         mlx5_drain_health_wq(dev);
1892         mlx5_stop_health_poll(dev, false);
1893
1894         err = mlx5_cmd_fast_teardown_hca(dev);
1895         if (!err)
1896                 goto done;
1897
1898         err = mlx5_cmd_force_teardown_hca(dev);
1899         if (!err)
1900                 goto done;
1901
1902         mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", err);
1903         mlx5_start_health_poll(dev);
1904         return err;
1905 done:
1906         mlx5_enter_error_state(dev, true);
1907         return 0;
1908 }
1909
1910 static void mlx5_shutdown_disable_interrupts(struct mlx5_core_dev *mdev)
1911 {
1912         int nvec = mdev->priv.eq_table.num_comp_vectors + MLX5_EQ_VEC_COMP_BASE;
1913         int x;
1914
1915         mdev->priv.disable_irqs = 1;
1916
1917         /* wait for all IRQ handlers to finish processing */
1918         for (x = 0; x != nvec; x++)
1919                 synchronize_irq(mdev->priv.msix_arr[x].vector);
1920 }
1921
1922 static void shutdown_one(struct pci_dev *pdev)
1923 {
1924         struct mlx5_core_dev *dev  = pci_get_drvdata(pdev);
1925         struct mlx5_priv *priv = &dev->priv;
1926         int err;
1927
1928         /* enter polling mode */
1929         mlx5_cmd_use_polling(dev);
1930
1931         set_bit(MLX5_INTERFACE_STATE_TEARDOWN, &dev->intf_state);
1932
1933         /* disable all interrupts */
1934         mlx5_shutdown_disable_interrupts(dev);
1935
1936         err = mlx5_try_fast_unload(dev);
1937         if (err)
1938                 mlx5_unload_one(dev, priv, false);
1939         mlx5_pci_disable_device(dev);
1940 }
1941
1942 static const struct pci_device_id mlx5_core_pci_table[] = {
1943         { PCI_VDEVICE(MELLANOX, 4113) }, /* Connect-IB */
1944         { PCI_VDEVICE(MELLANOX, 4114) }, /* Connect-IB VF */
1945         { PCI_VDEVICE(MELLANOX, 4115) }, /* ConnectX-4 */
1946         { PCI_VDEVICE(MELLANOX, 4116) }, /* ConnectX-4 VF */
1947         { PCI_VDEVICE(MELLANOX, 4117) }, /* ConnectX-4LX */
1948         { PCI_VDEVICE(MELLANOX, 4118) }, /* ConnectX-4LX VF */
1949         { PCI_VDEVICE(MELLANOX, 4119) }, /* ConnectX-5 */
1950         { PCI_VDEVICE(MELLANOX, 4120) }, /* ConnectX-5 VF */
1951         { PCI_VDEVICE(MELLANOX, 4121) },
1952         { PCI_VDEVICE(MELLANOX, 4122) },
1953         { PCI_VDEVICE(MELLANOX, 4123) },
1954         { PCI_VDEVICE(MELLANOX, 4124) },
1955         { PCI_VDEVICE(MELLANOX, 4125) },
1956         { PCI_VDEVICE(MELLANOX, 4126) },
1957         { PCI_VDEVICE(MELLANOX, 4127) },
1958         { PCI_VDEVICE(MELLANOX, 4128) },
1959         { PCI_VDEVICE(MELLANOX, 4129) },
1960         { PCI_VDEVICE(MELLANOX, 4130) },
1961         { PCI_VDEVICE(MELLANOX, 4131) },
1962         { PCI_VDEVICE(MELLANOX, 4132) },
1963         { PCI_VDEVICE(MELLANOX, 4133) },
1964         { PCI_VDEVICE(MELLANOX, 4134) },
1965         { PCI_VDEVICE(MELLANOX, 4135) },
1966         { PCI_VDEVICE(MELLANOX, 4136) },
1967         { PCI_VDEVICE(MELLANOX, 4137) },
1968         { PCI_VDEVICE(MELLANOX, 4138) },
1969         { PCI_VDEVICE(MELLANOX, 4139) },
1970         { PCI_VDEVICE(MELLANOX, 4140) },
1971         { PCI_VDEVICE(MELLANOX, 4141) },
1972         { PCI_VDEVICE(MELLANOX, 4142) },
1973         { PCI_VDEVICE(MELLANOX, 4143) },
1974         { PCI_VDEVICE(MELLANOX, 4144) },
1975         { 0, }
1976 };
1977
1978 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1979
1980 void mlx5_disable_device(struct mlx5_core_dev *dev)
1981 {
1982         mlx5_pci_err_detected(dev->pdev, 0);
1983 }
1984
1985 void mlx5_recover_device(struct mlx5_core_dev *dev)
1986 {
1987         mlx5_pci_disable_device(dev);
1988         if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
1989                 mlx5_pci_resume(dev->pdev);
1990 }
1991
1992 struct pci_driver mlx5_core_driver = {
1993         .name           = DRIVER_NAME,
1994         .id_table       = mlx5_core_pci_table,
1995         .shutdown       = shutdown_one,
1996         .probe          = init_one,
1997         .remove         = remove_one,
1998         .err_handler    = &mlx5_err_handler,
1999 #ifdef PCI_IOV
2000         .bsd_iov_init   = mlx5_iov_init,
2001         .bsd_iov_uninit = mlx5_iov_uninit,
2002         .bsd_iov_add_vf = mlx5_iov_add_vf,
2003 #endif
2004 };
2005
2006 static int __init init(void)
2007 {
2008         int err;
2009
2010         err = pci_register_driver(&mlx5_core_driver);
2011         if (err)
2012                 goto err_debug;
2013
2014         err = mlx5_ctl_init();
2015         if (err)
2016                 goto err_ctl;
2017
2018         return 0;
2019
2020 err_ctl:
2021         pci_unregister_driver(&mlx5_core_driver);
2022
2023 err_debug:
2024         return err;
2025 }
2026
2027 static void __exit cleanup(void)
2028 {
2029         mlx5_ctl_fini();
2030         pci_unregister_driver(&mlx5_core_driver);
2031 }
2032
2033 module_init_order(init, SI_ORDER_FIRST);
2034 module_exit_order(cleanup, SI_ORDER_FIRST);