2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #define LINUXKPI_PARAM_PREFIX mlx5_
30 #include <linux/kmod.h>
31 #include <linux/module.h>
32 #include <linux/errno.h>
33 #include <linux/pci.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/slab.h>
36 #include <linux/io-mapping.h>
37 #include <linux/interrupt.h>
38 #include <dev/mlx5/driver.h>
39 #include <dev/mlx5/cq.h>
40 #include <dev/mlx5/qp.h>
41 #include <dev/mlx5/srq.h>
42 #include <linux/delay.h>
43 #include <dev/mlx5/mlx5_ifc.h>
44 #include "mlx5_core.h"
47 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
48 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
49 MODULE_LICENSE("Dual BSD/GPL");
50 #if (__FreeBSD_version >= 1100000)
51 MODULE_DEPEND(mlx5, linuxkpi, 1, 1, 1);
53 MODULE_VERSION(mlx5, 1);
55 int mlx5_core_debug_mask;
56 module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
57 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
59 #define MLX5_DEFAULT_PROF 2
60 static int prof_sel = MLX5_DEFAULT_PROF;
61 module_param_named(prof_sel, prof_sel, int, 0444);
62 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
64 #define NUMA_NO_NODE -1
66 struct workqueue_struct *mlx5_core_wq;
67 static LIST_HEAD(intf_list);
68 static LIST_HEAD(dev_list);
69 static DEFINE_MUTEX(intf_mutex);
71 struct mlx5_device_context {
72 struct list_head list;
73 struct mlx5_interface *intf;
78 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
79 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
82 static struct mlx5_profile profiles[] = {
87 .mask = MLX5_PROF_MASK_QP_SIZE,
91 .mask = MLX5_PROF_MASK_QP_SIZE |
92 MLX5_PROF_MASK_MR_CACHE,
156 .mask = MLX5_PROF_MASK_QP_SIZE,
161 static int set_dma_caps(struct pci_dev *pdev)
165 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
167 device_printf((&pdev->dev)->bsddev, "WARN: ""Warning: couldn't set 64-bit PCI DMA mask\n");
168 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
170 device_printf((&pdev->dev)->bsddev, "ERR: ""Can't set PCI DMA mask, aborting\n");
175 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
177 device_printf((&pdev->dev)->bsddev, "WARN: ""Warning: couldn't set 64-bit consistent PCI DMA mask\n");
178 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
180 device_printf((&pdev->dev)->bsddev, "ERR: ""Can't set consistent PCI DMA mask, aborting\n");
185 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
189 static int request_bar(struct pci_dev *pdev)
193 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
194 device_printf((&pdev->dev)->bsddev, "ERR: ""Missing registers BAR, aborting\n");
198 err = pci_request_regions(pdev, DRIVER_NAME);
200 device_printf((&pdev->dev)->bsddev, "ERR: ""Couldn't get PCI resources, aborting\n");
205 static void release_bar(struct pci_dev *pdev)
207 pci_release_regions(pdev);
210 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
212 struct mlx5_priv *priv = &dev->priv;
213 struct mlx5_eq_table *table = &priv->eq_table;
214 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
218 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
219 MLX5_EQ_VEC_COMP_BASE;
220 nvec = min_t(int, nvec, num_eqs);
221 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
224 priv->msix_arr = kzalloc(nvec * sizeof(*priv->msix_arr), GFP_KERNEL);
226 priv->irq_info = kzalloc(nvec * sizeof(*priv->irq_info), GFP_KERNEL);
228 for (i = 0; i < nvec; i++)
229 priv->msix_arr[i].entry = i;
231 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
232 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
236 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
242 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
244 struct mlx5_priv *priv = &dev->priv;
246 pci_disable_msix(dev->pdev);
247 kfree(priv->irq_info);
248 kfree(priv->msix_arr);
251 struct mlx5_reg_host_endianess {
257 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
260 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
261 MLX5_DEV_CAP_FLAG_DCT |
262 MLX5_DEV_CAP_FLAG_DRAIN_SIGERR,
265 static u16 to_fw_pkey_sz(u32 size)
281 printf("mlx5_core: WARN: ""invalid pkey table size %d\n", size);
286 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
287 enum mlx5_cap_mode cap_mode)
289 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
290 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
291 void *out, *hca_caps;
292 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
295 memset(in, 0, sizeof(in));
296 out = kzalloc(out_sz, GFP_KERNEL);
298 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
299 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
300 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
304 err = mlx5_cmd_status_to_err_v2(out);
307 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
308 cap_type, cap_mode, err);
312 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
315 case HCA_CAP_OPMOD_GET_MAX:
316 memcpy(dev->hca_caps_max[cap_type], hca_caps,
317 MLX5_UN_SZ_BYTES(hca_cap_union));
319 case HCA_CAP_OPMOD_GET_CUR:
320 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
321 MLX5_UN_SZ_BYTES(hca_cap_union));
325 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
335 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
337 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)];
340 memset(out, 0, sizeof(out));
342 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
343 err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
347 err = mlx5_cmd_status_to_err_v2(out);
352 static int handle_hca_cap(struct mlx5_core_dev *dev)
354 void *set_ctx = NULL;
355 struct mlx5_profile *prof = dev->profile;
357 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
360 set_ctx = kzalloc(set_sz, GFP_KERNEL);
362 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_MAX);
366 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_CUR);
370 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
372 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
373 MLX5_ST_SZ_BYTES(cmd_hca_cap));
375 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
376 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
378 /* we limit the size of the pkey table to 128 entries for now */
379 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
382 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
383 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
386 /* disable cmdif checksum */
387 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
389 /* enable drain sigerr */
390 MLX5_SET(cmd_hca_cap, set_hca_cap, drain_sigerr, 1);
392 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
394 err = set_caps(dev, set_ctx, set_sz);
401 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
405 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
409 if (MLX5_CAP_GEN(dev, atomic)) {
410 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC,
411 HCA_CAP_OPMOD_GET_MAX);
415 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC,
416 HCA_CAP_OPMOD_GET_CUR);
425 supported_atomic_req_8B_endianess_mode_1);
427 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
430 set_ctx = kzalloc(set_sz, GFP_KERNEL);
434 MLX5_SET(set_hca_cap_in, set_ctx, op_mod,
435 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC << 1);
436 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
438 /* Set requestor to host endianness */
439 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode,
440 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
442 err = set_caps(dev, set_ctx, set_sz);
448 static int set_hca_ctrl(struct mlx5_core_dev *dev)
450 struct mlx5_reg_host_endianess he_in;
451 struct mlx5_reg_host_endianess he_out;
454 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH &&
455 !MLX5_CAP_GEN(dev, roce))
458 memset(&he_in, 0, sizeof(he_in));
459 he_in.he = MLX5_SET_HOST_ENDIANNESS;
460 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
461 &he_out, sizeof(he_out),
462 MLX5_REG_HOST_ENDIANNESS, 0, 1);
466 static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
468 u32 in[MLX5_ST_SZ_DW(enable_hca_in)];
469 u32 out[MLX5_ST_SZ_DW(enable_hca_out)];
471 memset(in, 0, sizeof(in));
472 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
473 memset(out, 0, sizeof(out));
474 return mlx5_cmd_exec_check_status(dev, in, sizeof(in),
478 static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
480 u32 in[MLX5_ST_SZ_DW(disable_hca_in)];
481 u32 out[MLX5_ST_SZ_DW(disable_hca_out)];
483 memset(in, 0, sizeof(in));
485 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
486 memset(out, 0, sizeof(out));
487 return mlx5_cmd_exec_check_status(dev, in, sizeof(in),
491 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
493 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)];
494 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)];
495 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)];
496 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)];
500 memset(query_in, 0, sizeof(query_in));
501 memset(query_out, 0, sizeof(query_out));
503 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
505 err = mlx5_cmd_exec_check_status(dev, query_in, sizeof(query_in),
506 query_out, sizeof(query_out));
508 if (((struct mlx5_outbox_hdr *)query_out)->status ==
509 MLX5_CMD_STAT_BAD_OP_ERR) {
510 pr_debug("Only ISSI 0 is supported\n");
514 printf("mlx5_core: ERR: ""failed to query ISSI\n");
518 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
520 if (sup_issi & (1 << 1)) {
521 memset(set_in, 0, sizeof(set_in));
522 memset(set_out, 0, sizeof(set_out));
524 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
525 MLX5_SET(set_issi_in, set_in, current_issi, 1);
527 err = mlx5_cmd_exec_check_status(dev, set_in, sizeof(set_in),
528 set_out, sizeof(set_out));
530 printf("mlx5_core: ERR: ""failed to set ISSI=1\n");
537 } else if (sup_issi & (1 << 0)) {
545 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn)
547 struct mlx5_eq_table *table = &dev->priv.eq_table;
551 spin_lock(&table->lock);
552 list_for_each_entry(eq, &table->comp_eqs_list, list) {
553 if (eq->index == vector) {
560 spin_unlock(&table->lock);
564 EXPORT_SYMBOL(mlx5_vector2eqn);
566 int mlx5_rename_eq(struct mlx5_core_dev *dev, int eq_ix, char *name)
568 struct mlx5_priv *priv = &dev->priv;
569 struct mlx5_eq_table *table = &priv->eq_table;
573 spin_lock(&table->lock);
574 list_for_each_entry(eq, &table->comp_eqs_list, list) {
575 if (eq->index == eq_ix) {
576 int irq_ix = eq_ix + MLX5_EQ_VEC_COMP_BASE;
578 snprintf(priv->irq_info[irq_ix].name, MLX5_MAX_IRQ_NAME,
579 "%s-%d", name, eq_ix);
585 spin_unlock(&table->lock);
590 static void free_comp_eqs(struct mlx5_core_dev *dev)
592 struct mlx5_eq_table *table = &dev->priv.eq_table;
593 struct mlx5_eq *eq, *n;
595 spin_lock(&table->lock);
596 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
598 spin_unlock(&table->lock);
599 if (mlx5_destroy_unmap_eq(dev, eq))
600 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
603 spin_lock(&table->lock);
605 spin_unlock(&table->lock);
608 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
610 struct mlx5_eq_table *table = &dev->priv.eq_table;
611 char name[MLX5_MAX_IRQ_NAME];
618 INIT_LIST_HEAD(&table->comp_eqs_list);
619 ncomp_vec = table->num_comp_vectors;
620 nent = MLX5_COMP_EQ_SIZE;
621 for (i = 0; i < ncomp_vec; i++) {
622 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
624 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
625 err = mlx5_create_map_eq(dev, eq,
626 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
627 name, &dev->priv.uuari.uars[0]);
632 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
634 spin_lock(&table->lock);
635 list_add_tail(&eq->list, &table->comp_eqs_list);
636 spin_unlock(&table->lock);
646 static int map_bf_area(struct mlx5_core_dev *dev)
648 resource_size_t bf_start = pci_resource_start(dev->pdev, 0);
649 resource_size_t bf_len = pci_resource_len(dev->pdev, 0);
651 dev->priv.bf_mapping = io_mapping_create_wc(bf_start, bf_len);
653 return dev->priv.bf_mapping ? 0 : -ENOMEM;
656 static void unmap_bf_area(struct mlx5_core_dev *dev)
658 if (dev->priv.bf_mapping)
659 io_mapping_free(dev->priv.bf_mapping);
662 static inline int fw_initializing(struct mlx5_core_dev *dev)
664 return ioread32be(&dev->iseg->initializing) >> 31;
667 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
669 u64 end = jiffies + msecs_to_jiffies(max_wait_mili);
672 while (fw_initializing(dev)) {
673 if (time_after(jiffies, end)) {
677 msleep(FW_INIT_WAIT_MS);
683 static int mlx5_dev_init(struct mlx5_core_dev *dev, struct pci_dev *pdev)
685 struct mlx5_priv *priv = &dev->priv;
689 pci_set_drvdata(dev->pdev, dev);
690 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
691 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
693 mutex_init(&priv->pgdir_mutex);
694 INIT_LIST_HEAD(&priv->pgdir_list);
695 spin_lock_init(&priv->mkey_lock);
697 priv->numa_node = NUMA_NO_NODE;
699 err = pci_enable_device(pdev);
701 device_printf((&pdev->dev)->bsddev, "ERR: ""Cannot enable PCI device, aborting\n");
705 err = request_bar(pdev);
707 device_printf((&pdev->dev)->bsddev, "ERR: ""error requesting BARs, aborting\n");
711 pci_set_master(pdev);
713 err = set_dma_caps(pdev);
715 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed setting DMA capabilities mask, aborting\n");
719 dev->iseg_base = pci_resource_start(dev->pdev, 0);
720 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
723 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed mapping initialization segment, aborting\n");
726 device_printf((&pdev->dev)->bsddev, "INFO: ""firmware version: %d.%d.%d\n", fw_rev_maj(dev), fw_rev_min(dev), fw_rev_sub(dev));
729 * On load removing any previous indication of internal error,
732 dev->state = MLX5_DEVICE_STATE_UP;
734 err = mlx5_cmd_init(dev);
736 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed initializing command interface, aborting\n");
740 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
742 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""Firmware over %d MS in initializing state, aborting\n", FW_INIT_TIMEOUT_MILI);
743 goto err_cmd_cleanup;
746 mlx5_pagealloc_init(dev);
748 err = mlx5_core_enable_hca(dev);
750 device_printf((&pdev->dev)->bsddev, "ERR: ""enable hca failed\n");
751 goto err_pagealloc_cleanup;
754 err = mlx5_core_set_issi(dev);
756 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to set issi\n");
757 goto err_disable_hca;
760 err = mlx5_pagealloc_start(dev);
762 device_printf((&pdev->dev)->bsddev, "ERR: ""mlx5_pagealloc_start failed\n");
763 goto err_disable_hca;
766 err = mlx5_satisfy_startup_pages(dev, 1);
768 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to allocate boot pages\n");
769 goto err_pagealloc_stop;
772 err = set_hca_ctrl(dev);
774 device_printf((&pdev->dev)->bsddev, "ERR: ""set_hca_ctrl failed\n");
775 goto reclaim_boot_pages;
778 err = handle_hca_cap(dev);
780 device_printf((&pdev->dev)->bsddev, "ERR: ""handle_hca_cap failed\n");
781 goto reclaim_boot_pages;
784 err = handle_hca_cap_atomic(dev);
786 device_printf((&pdev->dev)->bsddev, "ERR: ""handle_hca_cap_atomic failed\n");
787 goto reclaim_boot_pages;
790 err = mlx5_satisfy_startup_pages(dev, 0);
792 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to allocate init pages\n");
793 goto reclaim_boot_pages;
796 err = mlx5_cmd_init_hca(dev);
798 device_printf((&pdev->dev)->bsddev, "ERR: ""init hca failed\n");
799 goto reclaim_boot_pages;
802 mlx5_start_health_poll(dev);
804 err = mlx5_query_hca_caps(dev);
806 device_printf((&pdev->dev)->bsddev, "ERR: ""query hca failed\n");
810 err = mlx5_query_board_id(dev);
812 device_printf((&pdev->dev)->bsddev, "ERR: ""query board id failed\n");
816 err = mlx5_enable_msix(dev);
818 device_printf((&pdev->dev)->bsddev, "ERR: ""enable msix failed\n");
822 err = mlx5_eq_init(dev);
824 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to initialize eq\n");
828 err = mlx5_alloc_uuars(dev, &priv->uuari);
830 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed allocating uar, aborting\n");
834 err = mlx5_start_eqs(dev);
836 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to start pages and async EQs\n");
840 err = alloc_comp_eqs(dev);
842 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to alloc completion EQs\n");
846 if (map_bf_area(dev))
847 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to map blue flame area\n");
849 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
851 mlx5_init_cq_table(dev);
852 mlx5_init_qp_table(dev);
853 mlx5_init_srq_table(dev);
854 mlx5_init_mr_table(dev);
856 err = mlx5_init_fs(dev);
858 mlx5_core_err(dev, "flow steering init %d\n", err);
859 goto err_init_tables;
865 mlx5_cleanup_mr_table(dev);
866 mlx5_cleanup_srq_table(dev);
867 mlx5_cleanup_qp_table(dev);
868 mlx5_cleanup_cq_table(dev);
875 mlx5_free_uuars(dev, &priv->uuari);
878 mlx5_eq_cleanup(dev);
881 mlx5_disable_msix(dev);
884 mlx5_stop_health_poll(dev);
885 if (mlx5_cmd_teardown_hca(dev)) {
886 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""tear_down_hca failed, skip cleanup\n");
891 mlx5_reclaim_startup_pages(dev);
894 mlx5_pagealloc_stop(dev);
897 mlx5_core_disable_hca(dev);
899 err_pagealloc_cleanup:
900 mlx5_pagealloc_cleanup(dev);
902 mlx5_cmd_cleanup(dev);
908 pci_clear_master(dev->pdev);
909 release_bar(dev->pdev);
912 pci_disable_device(dev->pdev);
915 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
919 static void mlx5_dev_cleanup(struct mlx5_core_dev *dev)
921 struct mlx5_priv *priv = &dev->priv;
923 mlx5_cleanup_fs(dev);
924 mlx5_cleanup_mr_table(dev);
925 mlx5_cleanup_srq_table(dev);
926 mlx5_cleanup_qp_table(dev);
927 mlx5_cleanup_cq_table(dev);
929 mlx5_wait_for_reclaim_vfs_pages(dev);
932 mlx5_free_uuars(dev, &priv->uuari);
933 mlx5_eq_cleanup(dev);
934 mlx5_disable_msix(dev);
935 mlx5_stop_health_poll(dev);
936 if (mlx5_cmd_teardown_hca(dev)) {
937 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""tear_down_hca failed, skip cleanup\n");
940 mlx5_pagealloc_stop(dev);
941 mlx5_reclaim_startup_pages(dev);
942 mlx5_core_disable_hca(dev);
943 mlx5_pagealloc_cleanup(dev);
944 mlx5_cmd_cleanup(dev);
946 pci_clear_master(dev->pdev);
947 release_bar(dev->pdev);
948 pci_disable_device(dev->pdev);
951 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
953 struct mlx5_device_context *dev_ctx;
954 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
956 dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
958 dev_ctx->intf = intf;
959 dev_ctx->context = intf->add(dev);
961 if (dev_ctx->context) {
962 spin_lock_irq(&priv->ctx_lock);
963 list_add_tail(&dev_ctx->list, &priv->ctx_list);
964 spin_unlock_irq(&priv->ctx_lock);
970 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
972 struct mlx5_device_context *dev_ctx;
973 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
975 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
976 if (dev_ctx->intf == intf) {
977 spin_lock_irq(&priv->ctx_lock);
978 list_del(&dev_ctx->list);
979 spin_unlock_irq(&priv->ctx_lock);
981 intf->remove(dev, dev_ctx->context);
986 static int mlx5_register_device(struct mlx5_core_dev *dev)
988 struct mlx5_priv *priv = &dev->priv;
989 struct mlx5_interface *intf;
991 mutex_lock(&intf_mutex);
992 list_add_tail(&priv->dev_list, &dev_list);
993 list_for_each_entry(intf, &intf_list, list)
994 mlx5_add_device(intf, priv);
995 mutex_unlock(&intf_mutex);
999 static void mlx5_unregister_device(struct mlx5_core_dev *dev)
1001 struct mlx5_priv *priv = &dev->priv;
1002 struct mlx5_interface *intf;
1004 mutex_lock(&intf_mutex);
1005 list_for_each_entry(intf, &intf_list, list)
1006 mlx5_remove_device(intf, priv);
1007 list_del(&priv->dev_list);
1008 mutex_unlock(&intf_mutex);
1011 int mlx5_register_interface(struct mlx5_interface *intf)
1013 struct mlx5_priv *priv;
1015 if (!intf->add || !intf->remove)
1018 mutex_lock(&intf_mutex);
1019 list_add_tail(&intf->list, &intf_list);
1020 list_for_each_entry(priv, &dev_list, dev_list)
1021 mlx5_add_device(intf, priv);
1022 mutex_unlock(&intf_mutex);
1026 EXPORT_SYMBOL(mlx5_register_interface);
1028 void mlx5_unregister_interface(struct mlx5_interface *intf)
1030 struct mlx5_priv *priv;
1032 mutex_lock(&intf_mutex);
1033 list_for_each_entry(priv, &dev_list, dev_list)
1034 mlx5_remove_device(intf, priv);
1035 list_del(&intf->list);
1036 mutex_unlock(&intf_mutex);
1038 EXPORT_SYMBOL(mlx5_unregister_interface);
1040 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
1042 struct mlx5_priv *priv = &mdev->priv;
1043 struct mlx5_device_context *dev_ctx;
1044 unsigned long flags;
1045 void *result = NULL;
1047 spin_lock_irqsave(&priv->ctx_lock, flags);
1049 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
1050 if ((dev_ctx->intf->protocol == protocol) &&
1051 dev_ctx->intf->get_dev) {
1052 result = dev_ctx->intf->get_dev(dev_ctx->context);
1056 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1060 EXPORT_SYMBOL(mlx5_get_protocol_dev);
1062 static void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
1063 unsigned long param)
1065 struct mlx5_priv *priv = &dev->priv;
1066 struct mlx5_device_context *dev_ctx;
1067 unsigned long flags;
1069 spin_lock_irqsave(&priv->ctx_lock, flags);
1071 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
1072 if (dev_ctx->intf->event)
1073 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
1075 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1078 struct mlx5_core_event_handler {
1079 void (*event)(struct mlx5_core_dev *dev,
1080 enum mlx5_dev_event event,
1085 static int init_one(struct pci_dev *pdev,
1086 const struct pci_device_id *id)
1088 struct mlx5_core_dev *dev;
1089 struct mlx5_priv *priv;
1092 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1095 priv->pci_dev_data = id->driver_data;
1097 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profiles)) {
1098 printf("mlx5_core: WARN: ""selected profile out of range, selecting default (%d)\n", MLX5_DEFAULT_PROF);
1099 prof_sel = MLX5_DEFAULT_PROF;
1101 dev->profile = &profiles[prof_sel];
1102 dev->event = mlx5_core_event;
1104 INIT_LIST_HEAD(&priv->ctx_list);
1105 spin_lock_init(&priv->ctx_lock);
1106 err = mlx5_dev_init(dev, pdev);
1108 device_printf((&pdev->dev)->bsddev, "ERR: ""mlx5_dev_init failed %d\n", err);
1112 err = mlx5_register_device(dev);
1114 device_printf((&pdev->dev)->bsddev, "ERR: ""mlx5_register_device failed %d\n", err);
1122 mlx5_dev_cleanup(dev);
1128 static void remove_one(struct pci_dev *pdev)
1130 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1132 mlx5_unregister_device(dev);
1133 mlx5_dev_cleanup(dev);
1137 static void shutdown_one(struct pci_dev *pdev)
1139 /* prevent device from accessing host memory after shutdown */
1140 pci_clear_master(pdev);
1143 static const struct pci_device_id mlx5_core_pci_table[] = {
1144 { PCI_VDEVICE(MELLANOX, 4113) }, /* Connect-IB */
1145 { PCI_VDEVICE(MELLANOX, 4114) }, /* Connect-IB VF */
1146 { PCI_VDEVICE(MELLANOX, 4115) }, /* ConnectX-4 */
1147 { PCI_VDEVICE(MELLANOX, 4116) }, /* ConnectX-4 VF */
1148 { PCI_VDEVICE(MELLANOX, 4117) }, /* ConnectX-4LX */
1149 { PCI_VDEVICE(MELLANOX, 4118) }, /* ConnectX-4LX VF */
1150 { PCI_VDEVICE(MELLANOX, 4119) }, /* ConnectX-5 */
1151 { PCI_VDEVICE(MELLANOX, 4120) }, /* ConnectX-5 VF */
1152 { PCI_VDEVICE(MELLANOX, 4121) },
1153 { PCI_VDEVICE(MELLANOX, 4122) },
1154 { PCI_VDEVICE(MELLANOX, 4123) },
1155 { PCI_VDEVICE(MELLANOX, 4124) },
1156 { PCI_VDEVICE(MELLANOX, 4125) },
1157 { PCI_VDEVICE(MELLANOX, 4126) },
1158 { PCI_VDEVICE(MELLANOX, 4127) },
1159 { PCI_VDEVICE(MELLANOX, 4128) },
1160 { PCI_VDEVICE(MELLANOX, 4129) },
1161 { PCI_VDEVICE(MELLANOX, 4130) },
1162 { PCI_VDEVICE(MELLANOX, 4131) },
1163 { PCI_VDEVICE(MELLANOX, 4132) },
1164 { PCI_VDEVICE(MELLANOX, 4133) },
1165 { PCI_VDEVICE(MELLANOX, 4134) },
1166 { PCI_VDEVICE(MELLANOX, 4135) },
1167 { PCI_VDEVICE(MELLANOX, 4136) },
1168 { PCI_VDEVICE(MELLANOX, 4137) },
1169 { PCI_VDEVICE(MELLANOX, 4138) },
1170 { PCI_VDEVICE(MELLANOX, 4139) },
1171 { PCI_VDEVICE(MELLANOX, 4140) },
1172 { PCI_VDEVICE(MELLANOX, 4141) },
1173 { PCI_VDEVICE(MELLANOX, 4142) },
1174 { PCI_VDEVICE(MELLANOX, 4143) },
1175 { PCI_VDEVICE(MELLANOX, 4144) },
1179 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1181 static struct pci_driver mlx5_core_driver = {
1182 .name = DRIVER_NAME,
1183 .id_table = mlx5_core_pci_table,
1184 .shutdown = shutdown_one,
1186 .remove = remove_one
1189 static int __init init(void)
1193 mlx5_core_wq = create_singlethread_workqueue("mlx5_core_wq");
1194 if (!mlx5_core_wq) {
1200 err = pci_register_driver(&mlx5_core_driver);
1208 mlx5_health_cleanup();
1209 destroy_workqueue(mlx5_core_wq);
1214 static void __exit cleanup(void)
1216 pci_unregister_driver(&mlx5_core_driver);
1217 mlx5_health_cleanup();
1218 destroy_workqueue(mlx5_core_wq);
1222 module_exit(cleanup);
1224 void mlx5_enter_error_state(struct mlx5_core_dev *dev)
1226 if (dev->state != MLX5_DEVICE_STATE_UP)
1229 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1230 mlx5_trigger_cmd_completions(dev);
1232 EXPORT_SYMBOL(mlx5_enter_error_state);