2 * Copyright (c) 2013-2019, Mellanox Technologies, Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <linux/kmod.h>
29 #include <linux/module.h>
30 #include <linux/errno.h>
31 #include <linux/pci.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/slab.h>
34 #include <linux/io-mapping.h>
35 #include <linux/interrupt.h>
36 #include <linux/hardirq.h>
37 #include <dev/mlx5/driver.h>
38 #include <dev/mlx5/cq.h>
39 #include <dev/mlx5/qp.h>
40 #include <dev/mlx5/srq.h>
41 #include <linux/delay.h>
42 #include <dev/mlx5/mlx5_ifc.h>
43 #include <dev/mlx5/mlx5_fpga/core.h>
44 #include <dev/mlx5/mlx5_lib/mlx5.h>
45 #include "mlx5_core.h"
48 static const char mlx5_version[] = "Mellanox Core driver "
49 DRIVER_VERSION " (" DRIVER_RELDATE ")";
50 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
51 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
52 MODULE_LICENSE("Dual BSD/GPL");
53 MODULE_DEPEND(mlx5, linuxkpi, 1, 1, 1);
54 MODULE_DEPEND(mlx5, mlxfw, 1, 1, 1);
55 MODULE_VERSION(mlx5, 1);
57 SYSCTL_NODE(_hw, OID_AUTO, mlx5, CTLFLAG_RW, 0, "mlx5 hardware controls");
59 int mlx5_core_debug_mask;
60 SYSCTL_INT(_hw_mlx5, OID_AUTO, debug_mask, CTLFLAG_RWTUN,
61 &mlx5_core_debug_mask, 0,
62 "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
64 #define MLX5_DEFAULT_PROF 2
65 static int mlx5_prof_sel = MLX5_DEFAULT_PROF;
66 SYSCTL_INT(_hw_mlx5, OID_AUTO, prof_sel, CTLFLAG_RWTUN,
68 "profile selector. Valid range 0 - 2");
70 static int mlx5_fast_unload_enabled = 1;
71 SYSCTL_INT(_hw_mlx5, OID_AUTO, fast_unload_enabled, CTLFLAG_RWTUN,
72 &mlx5_fast_unload_enabled, 0,
73 "Set to enable fast unload. Clear to disable.");
75 #define NUMA_NO_NODE -1
77 static LIST_HEAD(intf_list);
78 static LIST_HEAD(dev_list);
79 static DEFINE_MUTEX(intf_mutex);
81 struct mlx5_device_context {
82 struct list_head list;
83 struct mlx5_interface *intf;
88 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
89 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
92 static struct mlx5_profile profiles[] = {
97 .mask = MLX5_PROF_MASK_QP_SIZE,
101 .mask = MLX5_PROF_MASK_QP_SIZE |
102 MLX5_PROF_MASK_MR_CACHE,
166 .mask = MLX5_PROF_MASK_QP_SIZE,
171 static int set_dma_caps(struct pci_dev *pdev)
175 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
177 device_printf((&pdev->dev)->bsddev, "WARN: ""Warning: couldn't set 64-bit PCI DMA mask\n");
178 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
180 device_printf((&pdev->dev)->bsddev, "ERR: ""Can't set PCI DMA mask, aborting\n");
185 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
187 device_printf((&pdev->dev)->bsddev, "WARN: ""Warning: couldn't set 64-bit consistent PCI DMA mask\n");
188 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
190 device_printf((&pdev->dev)->bsddev, "ERR: ""Can't set consistent PCI DMA mask, aborting\n");
195 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
199 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
201 struct pci_dev *pdev = dev->pdev;
204 mutex_lock(&dev->pci_status_mutex);
205 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
206 err = pci_enable_device(pdev);
208 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
210 mutex_unlock(&dev->pci_status_mutex);
215 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
217 struct pci_dev *pdev = dev->pdev;
219 mutex_lock(&dev->pci_status_mutex);
220 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
221 pci_disable_device(pdev);
222 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
224 mutex_unlock(&dev->pci_status_mutex);
227 static int request_bar(struct pci_dev *pdev)
231 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
232 device_printf((&pdev->dev)->bsddev, "ERR: ""Missing registers BAR, aborting\n");
236 err = pci_request_regions(pdev, DRIVER_NAME);
238 device_printf((&pdev->dev)->bsddev, "ERR: ""Couldn't get PCI resources, aborting\n");
243 static void release_bar(struct pci_dev *pdev)
245 pci_release_regions(pdev);
248 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
250 struct mlx5_priv *priv = &dev->priv;
251 struct mlx5_eq_table *table = &priv->eq_table;
252 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
253 int limit = dev->msix_eqvec;
254 int nvec = MLX5_EQ_VEC_COMP_BASE;
260 nvec += MLX5_CAP_GEN(dev, num_ports) * num_online_cpus();
262 nvec = min_t(int, nvec, num_eqs);
263 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
266 priv->msix_arr = kzalloc(nvec * sizeof(*priv->msix_arr), GFP_KERNEL);
268 priv->irq_info = kzalloc(nvec * sizeof(*priv->irq_info), GFP_KERNEL);
270 for (i = 0; i < nvec; i++)
271 priv->msix_arr[i].entry = i;
273 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
274 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
278 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
284 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
286 struct mlx5_priv *priv = &dev->priv;
288 pci_disable_msix(dev->pdev);
289 kfree(priv->irq_info);
290 kfree(priv->msix_arr);
293 struct mlx5_reg_host_endianess {
299 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
302 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
303 MLX5_DEV_CAP_FLAG_DCT |
304 MLX5_DEV_CAP_FLAG_DRAIN_SIGERR,
307 static u16 to_fw_pkey_sz(u32 size)
323 printf("mlx5_core: WARN: ""invalid pkey table size %d\n", size);
328 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
329 enum mlx5_cap_type cap_type,
330 enum mlx5_cap_mode cap_mode)
332 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
333 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
334 void *out, *hca_caps;
335 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
338 memset(in, 0, sizeof(in));
339 out = kzalloc(out_sz, GFP_KERNEL);
341 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
342 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
343 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
346 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
347 cap_type, cap_mode, err);
351 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
354 case HCA_CAP_OPMOD_GET_MAX:
355 memcpy(dev->hca_caps_max[cap_type], hca_caps,
356 MLX5_UN_SZ_BYTES(hca_cap_union));
358 case HCA_CAP_OPMOD_GET_CUR:
359 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
360 MLX5_UN_SZ_BYTES(hca_cap_union));
364 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
374 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
378 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
382 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
385 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
387 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0};
389 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
391 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
394 static int handle_hca_cap(struct mlx5_core_dev *dev)
396 void *set_ctx = NULL;
397 struct mlx5_profile *prof = dev->profile;
399 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
402 set_ctx = kzalloc(set_sz, GFP_KERNEL);
404 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
408 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
410 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
411 MLX5_ST_SZ_BYTES(cmd_hca_cap));
413 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
414 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
416 /* we limit the size of the pkey table to 128 entries for now */
417 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
420 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
421 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
424 /* disable cmdif checksum */
425 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
427 /* enable drain sigerr */
428 MLX5_SET(cmd_hca_cap, set_hca_cap, drain_sigerr, 1);
430 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
432 err = set_caps(dev, set_ctx, set_sz);
439 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
443 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
447 if (MLX5_CAP_GEN(dev, atomic)) {
448 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
457 supported_atomic_req_8B_endianess_mode_1);
459 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
462 set_ctx = kzalloc(set_sz, GFP_KERNEL);
466 MLX5_SET(set_hca_cap_in, set_ctx, op_mod,
467 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC << 1);
468 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
470 /* Set requestor to host endianness */
471 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode,
472 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
474 err = set_caps(dev, set_ctx, set_sz);
480 static int set_hca_ctrl(struct mlx5_core_dev *dev)
482 struct mlx5_reg_host_endianess he_in;
483 struct mlx5_reg_host_endianess he_out;
486 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH &&
487 !MLX5_CAP_GEN(dev, roce))
490 memset(&he_in, 0, sizeof(he_in));
491 he_in.he = MLX5_SET_HOST_ENDIANNESS;
492 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
493 &he_out, sizeof(he_out),
494 MLX5_REG_HOST_ENDIANNESS, 0, 1);
498 static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
500 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0};
501 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0};
503 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
504 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
507 static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
509 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0};
510 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0};
512 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
513 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
516 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
518 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0};
519 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0};
523 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
525 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in), query_out, sizeof(query_out));
530 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
531 if (status == MLX5_CMD_STAT_BAD_OP_ERR) {
532 pr_debug("Only ISSI 0 is supported\n");
536 printf("mlx5_core: ERR: ""failed to query ISSI\n");
540 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
542 if (sup_issi & (1 << 1)) {
543 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0};
544 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0};
546 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
547 MLX5_SET(set_issi_in, set_in, current_issi, 1);
549 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in), set_out, sizeof(set_out));
551 printf("mlx5_core: ERR: ""failed to set ISSI=1 err(%d)\n", err);
558 } else if (sup_issi & (1 << 0)) {
566 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn)
568 struct mlx5_eq_table *table = &dev->priv.eq_table;
572 spin_lock(&table->lock);
573 list_for_each_entry(eq, &table->comp_eqs_list, list) {
574 if (eq->index == vector) {
581 spin_unlock(&table->lock);
585 EXPORT_SYMBOL(mlx5_vector2eqn);
587 int mlx5_rename_eq(struct mlx5_core_dev *dev, int eq_ix, char *name)
589 struct mlx5_priv *priv = &dev->priv;
590 struct mlx5_eq_table *table = &priv->eq_table;
594 spin_lock(&table->lock);
595 list_for_each_entry(eq, &table->comp_eqs_list, list) {
596 if (eq->index == eq_ix) {
597 int irq_ix = eq_ix + MLX5_EQ_VEC_COMP_BASE;
599 snprintf(priv->irq_info[irq_ix].name, MLX5_MAX_IRQ_NAME,
600 "%s-%d", name, eq_ix);
606 spin_unlock(&table->lock);
611 static void free_comp_eqs(struct mlx5_core_dev *dev)
613 struct mlx5_eq_table *table = &dev->priv.eq_table;
614 struct mlx5_eq *eq, *n;
616 spin_lock(&table->lock);
617 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
619 spin_unlock(&table->lock);
620 if (mlx5_destroy_unmap_eq(dev, eq))
621 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
624 spin_lock(&table->lock);
626 spin_unlock(&table->lock);
629 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
631 struct mlx5_eq_table *table = &dev->priv.eq_table;
632 char name[MLX5_MAX_IRQ_NAME];
639 INIT_LIST_HEAD(&table->comp_eqs_list);
640 ncomp_vec = table->num_comp_vectors;
641 nent = MLX5_COMP_EQ_SIZE;
642 for (i = 0; i < ncomp_vec; i++) {
643 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
645 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
646 err = mlx5_create_map_eq(dev, eq,
647 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
648 name, &dev->priv.uuari.uars[0]);
653 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
655 spin_lock(&table->lock);
656 list_add_tail(&eq->list, &table->comp_eqs_list);
657 spin_unlock(&table->lock);
667 static int map_bf_area(struct mlx5_core_dev *dev)
669 resource_size_t bf_start = pci_resource_start(dev->pdev, 0);
670 resource_size_t bf_len = pci_resource_len(dev->pdev, 0);
672 dev->priv.bf_mapping = io_mapping_create_wc(bf_start, bf_len);
674 return dev->priv.bf_mapping ? 0 : -ENOMEM;
677 static void unmap_bf_area(struct mlx5_core_dev *dev)
679 if (dev->priv.bf_mapping)
680 io_mapping_free(dev->priv.bf_mapping);
683 static inline int fw_initializing(struct mlx5_core_dev *dev)
685 return ioread32be(&dev->iseg->initializing) >> 31;
688 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
690 u64 end = jiffies + msecs_to_jiffies(max_wait_mili);
693 while (fw_initializing(dev)) {
694 if (time_after(jiffies, end)) {
698 msleep(FW_INIT_WAIT_MS);
704 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
706 struct mlx5_device_context *dev_ctx;
707 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
709 dev_ctx = kzalloc(sizeof(*dev_ctx), GFP_KERNEL);
713 dev_ctx->intf = intf;
714 CURVNET_SET_QUIET(vnet0);
715 dev_ctx->context = intf->add(dev);
718 if (dev_ctx->context) {
719 spin_lock_irq(&priv->ctx_lock);
720 list_add_tail(&dev_ctx->list, &priv->ctx_list);
721 spin_unlock_irq(&priv->ctx_lock);
727 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
729 struct mlx5_device_context *dev_ctx;
730 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
732 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
733 if (dev_ctx->intf == intf) {
734 spin_lock_irq(&priv->ctx_lock);
735 list_del(&dev_ctx->list);
736 spin_unlock_irq(&priv->ctx_lock);
738 intf->remove(dev, dev_ctx->context);
745 mlx5_register_device(struct mlx5_core_dev *dev)
747 struct mlx5_priv *priv = &dev->priv;
748 struct mlx5_interface *intf;
750 mutex_lock(&intf_mutex);
751 list_add_tail(&priv->dev_list, &dev_list);
752 list_for_each_entry(intf, &intf_list, list)
753 mlx5_add_device(intf, priv);
754 mutex_unlock(&intf_mutex);
760 mlx5_unregister_device(struct mlx5_core_dev *dev)
762 struct mlx5_priv *priv = &dev->priv;
763 struct mlx5_interface *intf;
765 mutex_lock(&intf_mutex);
766 list_for_each_entry(intf, &intf_list, list)
767 mlx5_remove_device(intf, priv);
768 list_del(&priv->dev_list);
769 mutex_unlock(&intf_mutex);
772 int mlx5_register_interface(struct mlx5_interface *intf)
774 struct mlx5_priv *priv;
776 if (!intf->add || !intf->remove)
779 mutex_lock(&intf_mutex);
780 list_add_tail(&intf->list, &intf_list);
781 list_for_each_entry(priv, &dev_list, dev_list)
782 mlx5_add_device(intf, priv);
783 mutex_unlock(&intf_mutex);
787 EXPORT_SYMBOL(mlx5_register_interface);
789 void mlx5_unregister_interface(struct mlx5_interface *intf)
791 struct mlx5_priv *priv;
793 mutex_lock(&intf_mutex);
794 list_for_each_entry(priv, &dev_list, dev_list)
795 mlx5_remove_device(intf, priv);
796 list_del(&intf->list);
797 mutex_unlock(&intf_mutex);
799 EXPORT_SYMBOL(mlx5_unregister_interface);
801 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
803 struct mlx5_priv *priv = &mdev->priv;
804 struct mlx5_device_context *dev_ctx;
808 spin_lock_irqsave(&priv->ctx_lock, flags);
810 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
811 if ((dev_ctx->intf->protocol == protocol) &&
812 dev_ctx->intf->get_dev) {
813 result = dev_ctx->intf->get_dev(dev_ctx->context);
817 spin_unlock_irqrestore(&priv->ctx_lock, flags);
821 EXPORT_SYMBOL(mlx5_get_protocol_dev);
823 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
825 struct pci_dev *pdev = dev->pdev;
828 pci_set_drvdata(dev->pdev, dev);
829 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
830 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
832 mutex_init(&priv->pgdir_mutex);
833 INIT_LIST_HEAD(&priv->pgdir_list);
834 spin_lock_init(&priv->mkey_lock);
836 priv->numa_node = NUMA_NO_NODE;
838 err = mlx5_pci_enable_device(dev);
840 device_printf((&pdev->dev)->bsddev, "ERR: ""Cannot enable PCI device, aborting\n");
844 err = request_bar(pdev);
846 device_printf((&pdev->dev)->bsddev, "ERR: ""error requesting BARs, aborting\n");
850 pci_set_master(pdev);
852 err = set_dma_caps(pdev);
854 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed setting DMA capabilities mask, aborting\n");
858 dev->iseg_base = pci_resource_start(dev->pdev, 0);
859 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
862 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed mapping initialization segment, aborting\n");
869 release_bar(dev->pdev);
871 mlx5_pci_disable_device(dev);
876 static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
879 release_bar(dev->pdev);
880 mlx5_pci_disable_device(dev);
883 static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
885 struct pci_dev *pdev = dev->pdev;
888 err = mlx5_vsc_find_cap(dev);
890 dev_err(&pdev->dev, "Unable to find vendor specific capabilities\n");
892 err = mlx5_query_hca_caps(dev);
894 dev_err(&pdev->dev, "query hca failed\n");
898 err = mlx5_query_board_id(dev);
900 dev_err(&pdev->dev, "query board id failed\n");
904 err = mlx5_eq_init(dev);
906 dev_err(&pdev->dev, "failed to initialize eq\n");
910 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
912 err = mlx5_init_cq_table(dev);
914 dev_err(&pdev->dev, "failed to initialize cq table\n");
918 mlx5_init_qp_table(dev);
919 mlx5_init_srq_table(dev);
920 mlx5_init_mr_table(dev);
922 mlx5_init_reserved_gids(dev);
928 mlx5_eq_cleanup(dev);
934 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
936 mlx5_fpga_cleanup(dev);
937 mlx5_cleanup_reserved_gids(dev);
938 mlx5_cleanup_mr_table(dev);
939 mlx5_cleanup_srq_table(dev);
940 mlx5_cleanup_qp_table(dev);
941 mlx5_cleanup_cq_table(dev);
942 mlx5_eq_cleanup(dev);
945 static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
948 struct pci_dev *pdev = dev->pdev;
951 mutex_lock(&dev->intf_state_mutex);
952 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
953 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
958 device_printf((&pdev->dev)->bsddev, "INFO: ""firmware version: %d.%d.%d\n", fw_rev_maj(dev), fw_rev_min(dev), fw_rev_sub(dev));
961 * On load removing any previous indication of internal error,
964 dev->state = MLX5_DEVICE_STATE_UP;
966 err = mlx5_cmd_init(dev);
968 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed initializing command interface, aborting\n");
972 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
974 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""Firmware over %d MS in initializing state, aborting\n", FW_INIT_TIMEOUT_MILI);
975 goto err_cmd_cleanup;
978 err = mlx5_core_enable_hca(dev);
980 device_printf((&pdev->dev)->bsddev, "ERR: ""enable hca failed\n");
981 goto err_cmd_cleanup;
984 err = mlx5_core_set_issi(dev);
986 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to set issi\n");
987 goto err_disable_hca;
990 err = mlx5_pagealloc_start(dev);
992 device_printf((&pdev->dev)->bsddev, "ERR: ""mlx5_pagealloc_start failed\n");
993 goto err_disable_hca;
996 err = mlx5_satisfy_startup_pages(dev, 1);
998 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to allocate boot pages\n");
999 goto err_pagealloc_stop;
1002 err = set_hca_ctrl(dev);
1004 device_printf((&pdev->dev)->bsddev, "ERR: ""set_hca_ctrl failed\n");
1005 goto reclaim_boot_pages;
1008 err = handle_hca_cap(dev);
1010 device_printf((&pdev->dev)->bsddev, "ERR: ""handle_hca_cap failed\n");
1011 goto reclaim_boot_pages;
1014 err = handle_hca_cap_atomic(dev);
1016 device_printf((&pdev->dev)->bsddev, "ERR: ""handle_hca_cap_atomic failed\n");
1017 goto reclaim_boot_pages;
1020 err = mlx5_satisfy_startup_pages(dev, 0);
1022 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to allocate init pages\n");
1023 goto reclaim_boot_pages;
1026 err = mlx5_cmd_init_hca(dev);
1028 device_printf((&pdev->dev)->bsddev, "ERR: ""init hca failed\n");
1029 goto reclaim_boot_pages;
1032 mlx5_start_health_poll(dev);
1034 if (boot && mlx5_init_once(dev, priv)) {
1035 dev_err(&pdev->dev, "sw objs init failed\n");
1039 err = mlx5_enable_msix(dev);
1041 device_printf((&pdev->dev)->bsddev, "ERR: ""enable msix failed\n");
1042 goto err_cleanup_once;
1045 err = mlx5_alloc_uuars(dev, &priv->uuari);
1047 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed allocating uar, aborting\n");
1048 goto err_disable_msix;
1051 err = mlx5_start_eqs(dev);
1053 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to start pages and async EQs\n");
1057 err = alloc_comp_eqs(dev);
1059 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to alloc completion EQs\n");
1063 if (map_bf_area(dev))
1064 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to map blue flame area\n");
1066 err = mlx5_init_fs(dev);
1068 mlx5_core_err(dev, "flow steering init %d\n", err);
1069 goto err_free_comp_eqs;
1072 err = mlx5_fpga_device_start(dev);
1074 dev_err(&pdev->dev, "fpga device start failed %d\n", err);
1075 goto err_fpga_start;
1078 err = mlx5_register_device(dev);
1080 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1084 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1087 mutex_unlock(&dev->intf_state_mutex);
1092 mlx5_cleanup_fs(dev);
1102 mlx5_free_uuars(dev, &priv->uuari);
1105 mlx5_disable_msix(dev);
1109 mlx5_cleanup_once(dev);
1112 mlx5_stop_health_poll(dev, boot);
1113 if (mlx5_cmd_teardown_hca(dev)) {
1114 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""tear_down_hca failed, skip cleanup\n");
1119 mlx5_reclaim_startup_pages(dev);
1122 mlx5_pagealloc_stop(dev);
1125 mlx5_core_disable_hca(dev);
1128 mlx5_cmd_cleanup(dev);
1131 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1132 mutex_unlock(&dev->intf_state_mutex);
1137 static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1143 mlx5_drain_health_recovery(dev);
1145 mutex_lock(&dev->intf_state_mutex);
1146 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1147 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n", __func__);
1149 mlx5_cleanup_once(dev);
1153 mlx5_unregister_device(dev);
1155 mlx5_fpga_device_stop(dev);
1156 mlx5_cleanup_fs(dev);
1158 mlx5_wait_for_reclaim_vfs_pages(dev);
1161 mlx5_free_uuars(dev, &priv->uuari);
1162 mlx5_disable_msix(dev);
1164 mlx5_cleanup_once(dev);
1165 mlx5_stop_health_poll(dev, cleanup);
1166 err = mlx5_cmd_teardown_hca(dev);
1168 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""tear_down_hca failed, skip cleanup\n");
1171 mlx5_pagealloc_stop(dev);
1172 mlx5_reclaim_startup_pages(dev);
1173 mlx5_core_disable_hca(dev);
1174 mlx5_cmd_cleanup(dev);
1177 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1178 mutex_unlock(&dev->intf_state_mutex);
1182 void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
1183 unsigned long param)
1185 struct mlx5_priv *priv = &dev->priv;
1186 struct mlx5_device_context *dev_ctx;
1187 unsigned long flags;
1189 spin_lock_irqsave(&priv->ctx_lock, flags);
1191 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
1192 if (dev_ctx->intf->event)
1193 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
1195 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1198 struct mlx5_core_event_handler {
1199 void (*event)(struct mlx5_core_dev *dev,
1200 enum mlx5_dev_event event,
1204 static int init_one(struct pci_dev *pdev,
1205 const struct pci_device_id *id)
1207 struct mlx5_core_dev *dev;
1208 struct mlx5_priv *priv;
1209 device_t bsddev = pdev->dev.bsddev;
1212 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1215 priv->pci_dev_data = id->driver_data;
1217 if (mlx5_prof_sel < 0 || mlx5_prof_sel >= ARRAY_SIZE(profiles)) {
1218 device_printf(bsddev, "WARN: selected profile out of range, selecting default (%d)\n", MLX5_DEFAULT_PROF);
1219 mlx5_prof_sel = MLX5_DEFAULT_PROF;
1221 dev->profile = &profiles[mlx5_prof_sel];
1223 dev->event = mlx5_core_event;
1226 device_set_desc(bsddev, mlx5_version);
1228 sysctl_ctx_init(&dev->sysctl_ctx);
1229 SYSCTL_ADD_INT(&dev->sysctl_ctx,
1230 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)),
1231 OID_AUTO, "msix_eqvec", CTLFLAG_RDTUN, &dev->msix_eqvec, 0,
1232 "Maximum number of MSIX event queue vectors, if set");
1234 INIT_LIST_HEAD(&priv->ctx_list);
1235 spin_lock_init(&priv->ctx_lock);
1236 mutex_init(&dev->pci_status_mutex);
1237 mutex_init(&dev->intf_state_mutex);
1238 err = mlx5_pci_init(dev, priv);
1240 device_printf(bsddev, "ERR: mlx5_pci_init failed %d\n", err);
1244 err = mlx5_health_init(dev);
1246 device_printf(bsddev, "ERR: mlx5_health_init failed %d\n", err);
1250 mlx5_pagealloc_init(dev);
1252 err = mlx5_load_one(dev, priv, true);
1254 device_printf(bsddev, "ERR: mlx5_load_one failed %d\n", err);
1258 mlx5_fwdump_prep(dev);
1260 pci_save_state(bsddev);
1264 mlx5_pagealloc_cleanup(dev);
1265 mlx5_health_cleanup(dev);
1267 mlx5_pci_close(dev, priv);
1269 sysctl_ctx_free(&dev->sysctl_ctx);
1274 static void remove_one(struct pci_dev *pdev)
1276 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1277 struct mlx5_priv *priv = &dev->priv;
1279 if (mlx5_unload_one(dev, priv, true)) {
1280 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
1281 mlx5_health_cleanup(dev);
1285 mlx5_fwdump_clean(dev);
1286 mlx5_pagealloc_cleanup(dev);
1287 mlx5_health_cleanup(dev);
1288 mlx5_pci_close(dev, priv);
1289 pci_set_drvdata(pdev, NULL);
1290 sysctl_ctx_free(&dev->sysctl_ctx);
1294 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1295 pci_channel_state_t state)
1297 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1298 struct mlx5_priv *priv = &dev->priv;
1300 dev_info(&pdev->dev, "%s was called\n", __func__);
1301 mlx5_enter_error_state(dev, false);
1302 mlx5_unload_one(dev, priv, false);
1305 mlx5_drain_health_wq(dev);
1306 mlx5_pci_disable_device(dev);
1309 return state == pci_channel_io_perm_failure ?
1310 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1313 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1315 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1318 dev_info(&pdev->dev, "%s was called\n", __func__);
1320 err = mlx5_pci_enable_device(dev);
1322 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1324 return PCI_ERS_RESULT_DISCONNECT;
1326 pci_set_master(pdev);
1327 pci_set_powerstate(pdev->dev.bsddev, PCI_POWERSTATE_D0);
1328 pci_restore_state(pdev->dev.bsddev);
1329 pci_save_state(pdev->dev.bsddev);
1331 return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
1334 /* wait for the device to show vital signs. For now we check
1335 * that we can read the device ID and that the health buffer
1336 * shows a non zero value which is different than 0xffffffff
1338 static void wait_vital(struct pci_dev *pdev)
1340 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1341 struct mlx5_core_health *health = &dev->priv.health;
1342 const int niter = 100;
1347 /* Wait for firmware to be ready after reset */
1349 for (i = 0; i < niter; i++) {
1350 if (pci_read_config_word(pdev, 2, &did)) {
1351 dev_warn(&pdev->dev, "failed reading config word\n");
1354 if (did == pdev->device) {
1355 dev_info(&pdev->dev, "device ID correctly read after %d iterations\n", i);
1361 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__);
1363 for (i = 0; i < niter; i++) {
1364 count = ioread32be(health->health_counter);
1365 if (count && count != 0xffffffff) {
1366 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1373 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__);
1376 static void mlx5_pci_resume(struct pci_dev *pdev)
1378 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1379 struct mlx5_priv *priv = &dev->priv;
1382 dev_info(&pdev->dev, "%s was called\n", __func__);
1386 err = mlx5_load_one(dev, priv, false);
1388 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1391 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1394 static const struct pci_error_handlers mlx5_err_handler = {
1395 .error_detected = mlx5_pci_err_detected,
1396 .slot_reset = mlx5_pci_slot_reset,
1397 .resume = mlx5_pci_resume
1400 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1402 bool fast_teardown, force_teardown;
1405 if (!mlx5_fast_unload_enabled) {
1406 mlx5_core_dbg(dev, "fast unload is disabled by user\n");
1410 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
1411 force_teardown = MLX5_CAP_GEN(dev, force_teardown);
1413 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
1414 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
1416 if (!fast_teardown && !force_teardown)
1419 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1420 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1424 /* Panic tear down fw command will stop the PCI bus communication
1425 * with the HCA, so the health polll is no longer needed.
1427 mlx5_drain_health_wq(dev);
1428 mlx5_stop_health_poll(dev, false);
1430 err = mlx5_cmd_fast_teardown_hca(dev);
1434 err = mlx5_cmd_force_teardown_hca(dev);
1438 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", err);
1439 mlx5_start_health_poll(dev);
1442 mlx5_enter_error_state(dev, true);
1446 static void mlx5_disable_interrupts(struct mlx5_core_dev *mdev)
1448 int nvec = mdev->priv.eq_table.num_comp_vectors + MLX5_EQ_VEC_COMP_BASE;
1451 mdev->priv.disable_irqs = 1;
1453 /* wait for all IRQ handlers to finish processing */
1454 for (x = 0; x != nvec; x++)
1455 synchronize_irq(mdev->priv.msix_arr[x].vector);
1458 static void shutdown_one(struct pci_dev *pdev)
1460 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1461 struct mlx5_priv *priv = &dev->priv;
1464 /* enter polling mode */
1465 mlx5_cmd_use_polling(dev);
1467 /* disable all interrupts */
1468 mlx5_disable_interrupts(dev);
1470 err = mlx5_try_fast_unload(dev);
1472 mlx5_unload_one(dev, priv, false);
1473 mlx5_pci_disable_device(dev);
1476 static const struct pci_device_id mlx5_core_pci_table[] = {
1477 { PCI_VDEVICE(MELLANOX, 4113) }, /* Connect-IB */
1478 { PCI_VDEVICE(MELLANOX, 4114) }, /* Connect-IB VF */
1479 { PCI_VDEVICE(MELLANOX, 4115) }, /* ConnectX-4 */
1480 { PCI_VDEVICE(MELLANOX, 4116) }, /* ConnectX-4 VF */
1481 { PCI_VDEVICE(MELLANOX, 4117) }, /* ConnectX-4LX */
1482 { PCI_VDEVICE(MELLANOX, 4118) }, /* ConnectX-4LX VF */
1483 { PCI_VDEVICE(MELLANOX, 4119) }, /* ConnectX-5 */
1484 { PCI_VDEVICE(MELLANOX, 4120) }, /* ConnectX-5 VF */
1485 { PCI_VDEVICE(MELLANOX, 4121) },
1486 { PCI_VDEVICE(MELLANOX, 4122) },
1487 { PCI_VDEVICE(MELLANOX, 4123) },
1488 { PCI_VDEVICE(MELLANOX, 4124) },
1489 { PCI_VDEVICE(MELLANOX, 4125) },
1490 { PCI_VDEVICE(MELLANOX, 4126) },
1491 { PCI_VDEVICE(MELLANOX, 4127) },
1492 { PCI_VDEVICE(MELLANOX, 4128) },
1493 { PCI_VDEVICE(MELLANOX, 4129) },
1494 { PCI_VDEVICE(MELLANOX, 4130) },
1495 { PCI_VDEVICE(MELLANOX, 4131) },
1496 { PCI_VDEVICE(MELLANOX, 4132) },
1497 { PCI_VDEVICE(MELLANOX, 4133) },
1498 { PCI_VDEVICE(MELLANOX, 4134) },
1499 { PCI_VDEVICE(MELLANOX, 4135) },
1500 { PCI_VDEVICE(MELLANOX, 4136) },
1501 { PCI_VDEVICE(MELLANOX, 4137) },
1502 { PCI_VDEVICE(MELLANOX, 4138) },
1503 { PCI_VDEVICE(MELLANOX, 4139) },
1504 { PCI_VDEVICE(MELLANOX, 4140) },
1505 { PCI_VDEVICE(MELLANOX, 4141) },
1506 { PCI_VDEVICE(MELLANOX, 4142) },
1507 { PCI_VDEVICE(MELLANOX, 4143) },
1508 { PCI_VDEVICE(MELLANOX, 4144) },
1512 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1514 void mlx5_disable_device(struct mlx5_core_dev *dev)
1516 mlx5_pci_err_detected(dev->pdev, 0);
1519 void mlx5_recover_device(struct mlx5_core_dev *dev)
1521 mlx5_pci_disable_device(dev);
1522 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
1523 mlx5_pci_resume(dev->pdev);
1526 struct pci_driver mlx5_core_driver = {
1527 .name = DRIVER_NAME,
1528 .id_table = mlx5_core_pci_table,
1529 .shutdown = shutdown_one,
1531 .remove = remove_one,
1532 .err_handler = &mlx5_err_handler
1535 static int __init init(void)
1539 err = pci_register_driver(&mlx5_core_driver);
1543 err = mlx5_fwdump_init();
1550 pci_unregister_driver(&mlx5_core_driver);
1556 static void __exit cleanup(void)
1559 pci_unregister_driver(&mlx5_core_driver);
1563 module_exit(cleanup);