2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #define LINUXKPI_PARAM_PREFIX mlx5_
30 #include <linux/kmod.h>
31 #include <linux/module.h>
32 #include <linux/errno.h>
33 #include <linux/pci.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/slab.h>
36 #include <linux/io-mapping.h>
37 #include <linux/interrupt.h>
38 #include <dev/mlx5/driver.h>
39 #include <dev/mlx5/cq.h>
40 #include <dev/mlx5/qp.h>
41 #include <dev/mlx5/srq.h>
42 #include <linux/delay.h>
43 #include <dev/mlx5/mlx5_ifc.h>
44 #include "mlx5_core.h"
47 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
48 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
49 MODULE_LICENSE("Dual BSD/GPL");
50 #if (__FreeBSD_version >= 1100000)
51 MODULE_DEPEND(mlx5, linuxkpi, 1, 1, 1);
53 MODULE_VERSION(mlx5, 1);
55 int mlx5_core_debug_mask;
56 module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
57 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
59 #define MLX5_DEFAULT_PROF 2
60 static int prof_sel = MLX5_DEFAULT_PROF;
61 module_param_named(prof_sel, prof_sel, int, 0444);
62 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
64 #define NUMA_NO_NODE -1
66 static LIST_HEAD(intf_list);
67 static LIST_HEAD(dev_list);
68 static DEFINE_MUTEX(intf_mutex);
70 struct mlx5_device_context {
71 struct list_head list;
72 struct mlx5_interface *intf;
77 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
78 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
81 static struct mlx5_profile profiles[] = {
86 .mask = MLX5_PROF_MASK_QP_SIZE,
90 .mask = MLX5_PROF_MASK_QP_SIZE |
91 MLX5_PROF_MASK_MR_CACHE,
155 .mask = MLX5_PROF_MASK_QP_SIZE,
160 static int set_dma_caps(struct pci_dev *pdev)
164 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
166 device_printf((&pdev->dev)->bsddev, "WARN: ""Warning: couldn't set 64-bit PCI DMA mask\n");
167 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
169 device_printf((&pdev->dev)->bsddev, "ERR: ""Can't set PCI DMA mask, aborting\n");
174 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
176 device_printf((&pdev->dev)->bsddev, "WARN: ""Warning: couldn't set 64-bit consistent PCI DMA mask\n");
177 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
179 device_printf((&pdev->dev)->bsddev, "ERR: ""Can't set consistent PCI DMA mask, aborting\n");
184 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
188 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
190 struct pci_dev *pdev = dev->pdev;
193 mutex_lock(&dev->pci_status_mutex);
194 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
195 err = pci_enable_device(pdev);
197 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
199 mutex_unlock(&dev->pci_status_mutex);
204 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
206 struct pci_dev *pdev = dev->pdev;
208 mutex_lock(&dev->pci_status_mutex);
209 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
210 pci_disable_device(pdev);
211 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
213 mutex_unlock(&dev->pci_status_mutex);
216 static int request_bar(struct pci_dev *pdev)
220 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
221 device_printf((&pdev->dev)->bsddev, "ERR: ""Missing registers BAR, aborting\n");
225 err = pci_request_regions(pdev, DRIVER_NAME);
227 device_printf((&pdev->dev)->bsddev, "ERR: ""Couldn't get PCI resources, aborting\n");
232 static void release_bar(struct pci_dev *pdev)
234 pci_release_regions(pdev);
237 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
239 struct mlx5_priv *priv = &dev->priv;
240 struct mlx5_eq_table *table = &priv->eq_table;
241 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
245 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
246 MLX5_EQ_VEC_COMP_BASE;
247 nvec = min_t(int, nvec, num_eqs);
248 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
251 priv->msix_arr = kzalloc(nvec * sizeof(*priv->msix_arr), GFP_KERNEL);
253 priv->irq_info = kzalloc(nvec * sizeof(*priv->irq_info), GFP_KERNEL);
255 for (i = 0; i < nvec; i++)
256 priv->msix_arr[i].entry = i;
258 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
259 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
263 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
269 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
271 struct mlx5_priv *priv = &dev->priv;
273 pci_disable_msix(dev->pdev);
274 kfree(priv->irq_info);
275 kfree(priv->msix_arr);
278 struct mlx5_reg_host_endianess {
284 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
287 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
288 MLX5_DEV_CAP_FLAG_DCT |
289 MLX5_DEV_CAP_FLAG_DRAIN_SIGERR,
292 static u16 to_fw_pkey_sz(u32 size)
308 printf("mlx5_core: WARN: ""invalid pkey table size %d\n", size);
313 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
314 enum mlx5_cap_type cap_type,
315 enum mlx5_cap_mode cap_mode)
317 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
318 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
319 void *out, *hca_caps;
320 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
323 memset(in, 0, sizeof(in));
324 out = kzalloc(out_sz, GFP_KERNEL);
326 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
327 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
328 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
331 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
332 cap_type, cap_mode, err);
336 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
339 case HCA_CAP_OPMOD_GET_MAX:
340 memcpy(dev->hca_caps_max[cap_type], hca_caps,
341 MLX5_UN_SZ_BYTES(hca_cap_union));
343 case HCA_CAP_OPMOD_GET_CUR:
344 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
345 MLX5_UN_SZ_BYTES(hca_cap_union));
349 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
359 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
363 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
367 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
370 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
372 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0};
374 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
376 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
379 static int handle_hca_cap(struct mlx5_core_dev *dev)
381 void *set_ctx = NULL;
382 struct mlx5_profile *prof = dev->profile;
384 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
387 set_ctx = kzalloc(set_sz, GFP_KERNEL);
389 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
393 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
395 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
396 MLX5_ST_SZ_BYTES(cmd_hca_cap));
398 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
399 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
401 /* we limit the size of the pkey table to 128 entries for now */
402 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
405 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
406 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
409 /* disable cmdif checksum */
410 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
412 /* enable drain sigerr */
413 MLX5_SET(cmd_hca_cap, set_hca_cap, drain_sigerr, 1);
415 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
417 err = set_caps(dev, set_ctx, set_sz);
424 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
428 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
432 if (MLX5_CAP_GEN(dev, atomic)) {
433 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
442 supported_atomic_req_8B_endianess_mode_1);
444 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
447 set_ctx = kzalloc(set_sz, GFP_KERNEL);
451 MLX5_SET(set_hca_cap_in, set_ctx, op_mod,
452 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC << 1);
453 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
455 /* Set requestor to host endianness */
456 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode,
457 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
459 err = set_caps(dev, set_ctx, set_sz);
465 static int set_hca_ctrl(struct mlx5_core_dev *dev)
467 struct mlx5_reg_host_endianess he_in;
468 struct mlx5_reg_host_endianess he_out;
471 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH &&
472 !MLX5_CAP_GEN(dev, roce))
475 memset(&he_in, 0, sizeof(he_in));
476 he_in.he = MLX5_SET_HOST_ENDIANNESS;
477 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
478 &he_out, sizeof(he_out),
479 MLX5_REG_HOST_ENDIANNESS, 0, 1);
483 static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
485 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0};
486 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0};
488 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
489 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
492 static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
494 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0};
495 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0};
497 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
498 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
501 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
503 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0};
504 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0};
508 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
510 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in), query_out, sizeof(query_out));
515 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
516 if (status == MLX5_CMD_STAT_BAD_OP_ERR) {
517 pr_debug("Only ISSI 0 is supported\n");
521 printf("mlx5_core: ERR: ""failed to query ISSI\n");
525 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
527 if (sup_issi & (1 << 1)) {
528 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0};
529 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0};
531 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
532 MLX5_SET(set_issi_in, set_in, current_issi, 1);
534 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in), set_out, sizeof(set_out));
536 printf("mlx5_core: ERR: ""failed to set ISSI=1 err(%d)\n", err);
543 } else if (sup_issi & (1 << 0)) {
551 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn)
553 struct mlx5_eq_table *table = &dev->priv.eq_table;
557 spin_lock(&table->lock);
558 list_for_each_entry(eq, &table->comp_eqs_list, list) {
559 if (eq->index == vector) {
566 spin_unlock(&table->lock);
570 EXPORT_SYMBOL(mlx5_vector2eqn);
572 int mlx5_rename_eq(struct mlx5_core_dev *dev, int eq_ix, char *name)
574 struct mlx5_priv *priv = &dev->priv;
575 struct mlx5_eq_table *table = &priv->eq_table;
579 spin_lock(&table->lock);
580 list_for_each_entry(eq, &table->comp_eqs_list, list) {
581 if (eq->index == eq_ix) {
582 int irq_ix = eq_ix + MLX5_EQ_VEC_COMP_BASE;
584 snprintf(priv->irq_info[irq_ix].name, MLX5_MAX_IRQ_NAME,
585 "%s-%d", name, eq_ix);
591 spin_unlock(&table->lock);
596 static void free_comp_eqs(struct mlx5_core_dev *dev)
598 struct mlx5_eq_table *table = &dev->priv.eq_table;
599 struct mlx5_eq *eq, *n;
601 spin_lock(&table->lock);
602 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
604 spin_unlock(&table->lock);
605 if (mlx5_destroy_unmap_eq(dev, eq))
606 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
609 spin_lock(&table->lock);
611 spin_unlock(&table->lock);
614 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
616 struct mlx5_eq_table *table = &dev->priv.eq_table;
617 char name[MLX5_MAX_IRQ_NAME];
624 INIT_LIST_HEAD(&table->comp_eqs_list);
625 ncomp_vec = table->num_comp_vectors;
626 nent = MLX5_COMP_EQ_SIZE;
627 for (i = 0; i < ncomp_vec; i++) {
628 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
630 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
631 err = mlx5_create_map_eq(dev, eq,
632 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
633 name, &dev->priv.uuari.uars[0]);
638 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
640 spin_lock(&table->lock);
641 list_add_tail(&eq->list, &table->comp_eqs_list);
642 spin_unlock(&table->lock);
652 static int map_bf_area(struct mlx5_core_dev *dev)
654 resource_size_t bf_start = pci_resource_start(dev->pdev, 0);
655 resource_size_t bf_len = pci_resource_len(dev->pdev, 0);
657 dev->priv.bf_mapping = io_mapping_create_wc(bf_start, bf_len);
659 return dev->priv.bf_mapping ? 0 : -ENOMEM;
662 static void unmap_bf_area(struct mlx5_core_dev *dev)
664 if (dev->priv.bf_mapping)
665 io_mapping_free(dev->priv.bf_mapping);
668 static inline int fw_initializing(struct mlx5_core_dev *dev)
670 return ioread32be(&dev->iseg->initializing) >> 31;
673 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
675 u64 end = jiffies + msecs_to_jiffies(max_wait_mili);
678 while (fw_initializing(dev)) {
679 if (time_after(jiffies, end)) {
683 msleep(FW_INIT_WAIT_MS);
689 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
691 struct mlx5_device_context *dev_ctx;
692 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
694 dev_ctx = kzalloc(sizeof(*dev_ctx), GFP_KERNEL);
698 dev_ctx->intf = intf;
699 CURVNET_SET_QUIET(vnet0);
700 dev_ctx->context = intf->add(dev);
703 if (dev_ctx->context) {
704 spin_lock_irq(&priv->ctx_lock);
705 list_add_tail(&dev_ctx->list, &priv->ctx_list);
706 spin_unlock_irq(&priv->ctx_lock);
712 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
714 struct mlx5_device_context *dev_ctx;
715 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
717 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
718 if (dev_ctx->intf == intf) {
719 spin_lock_irq(&priv->ctx_lock);
720 list_del(&dev_ctx->list);
721 spin_unlock_irq(&priv->ctx_lock);
723 intf->remove(dev, dev_ctx->context);
729 static int mlx5_register_device(struct mlx5_core_dev *dev)
731 struct mlx5_priv *priv = &dev->priv;
732 struct mlx5_interface *intf;
734 mutex_lock(&intf_mutex);
735 list_add_tail(&priv->dev_list, &dev_list);
736 list_for_each_entry(intf, &intf_list, list)
737 mlx5_add_device(intf, priv);
738 mutex_unlock(&intf_mutex);
743 static void mlx5_unregister_device(struct mlx5_core_dev *dev)
745 struct mlx5_priv *priv = &dev->priv;
746 struct mlx5_interface *intf;
748 mutex_lock(&intf_mutex);
749 list_for_each_entry(intf, &intf_list, list)
750 mlx5_remove_device(intf, priv);
751 list_del(&priv->dev_list);
752 mutex_unlock(&intf_mutex);
755 int mlx5_register_interface(struct mlx5_interface *intf)
757 struct mlx5_priv *priv;
759 if (!intf->add || !intf->remove)
762 mutex_lock(&intf_mutex);
763 list_add_tail(&intf->list, &intf_list);
764 list_for_each_entry(priv, &dev_list, dev_list)
765 mlx5_add_device(intf, priv);
766 mutex_unlock(&intf_mutex);
770 EXPORT_SYMBOL(mlx5_register_interface);
772 void mlx5_unregister_interface(struct mlx5_interface *intf)
774 struct mlx5_priv *priv;
776 mutex_lock(&intf_mutex);
777 list_for_each_entry(priv, &dev_list, dev_list)
778 mlx5_remove_device(intf, priv);
779 list_del(&intf->list);
780 mutex_unlock(&intf_mutex);
782 EXPORT_SYMBOL(mlx5_unregister_interface);
784 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
786 struct mlx5_priv *priv = &mdev->priv;
787 struct mlx5_device_context *dev_ctx;
791 spin_lock_irqsave(&priv->ctx_lock, flags);
793 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
794 if ((dev_ctx->intf->protocol == protocol) &&
795 dev_ctx->intf->get_dev) {
796 result = dev_ctx->intf->get_dev(dev_ctx->context);
800 spin_unlock_irqrestore(&priv->ctx_lock, flags);
804 EXPORT_SYMBOL(mlx5_get_protocol_dev);
806 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
808 struct pci_dev *pdev = dev->pdev;
811 pci_set_drvdata(dev->pdev, dev);
812 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
813 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
815 mutex_init(&priv->pgdir_mutex);
816 INIT_LIST_HEAD(&priv->pgdir_list);
817 spin_lock_init(&priv->mkey_lock);
819 priv->numa_node = NUMA_NO_NODE;
821 err = mlx5_pci_enable_device(dev);
823 device_printf((&pdev->dev)->bsddev, "ERR: ""Cannot enable PCI device, aborting\n");
827 err = request_bar(pdev);
829 device_printf((&pdev->dev)->bsddev, "ERR: ""error requesting BARs, aborting\n");
833 pci_set_master(pdev);
835 err = set_dma_caps(pdev);
837 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed setting DMA capabilities mask, aborting\n");
841 dev->iseg_base = pci_resource_start(dev->pdev, 0);
842 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
845 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed mapping initialization segment, aborting\n");
849 if (mlx5_vsc_find_cap(dev))
850 dev_err(&pdev->dev, "Unable to find vendor specific capabilities\n");
855 pci_clear_master(dev->pdev);
856 release_bar(dev->pdev);
858 mlx5_pci_disable_device(dev);
863 static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
866 pci_clear_master(dev->pdev);
867 release_bar(dev->pdev);
868 mlx5_pci_disable_device(dev);
871 static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
873 struct pci_dev *pdev = dev->pdev;
878 err = mlx5_query_hca_caps(dev);
880 dev_err(&pdev->dev, "query hca failed\n");
884 err = mlx5_query_board_id(dev);
886 dev_err(&pdev->dev, "query board id failed\n");
890 err = mlx5_eq_init(dev);
892 dev_err(&pdev->dev, "failed to initialize eq\n");
896 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
898 err = mlx5_init_cq_table(dev);
900 dev_err(&pdev->dev, "failed to initialize cq table\n");
904 mlx5_init_qp_table(dev);
905 mlx5_init_srq_table(dev);
906 mlx5_init_mr_table(dev);
911 mlx5_eq_cleanup(dev);
917 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
919 mlx5_cleanup_mr_table(dev);
920 mlx5_cleanup_srq_table(dev);
921 mlx5_cleanup_qp_table(dev);
922 mlx5_cleanup_cq_table(dev);
923 mlx5_eq_cleanup(dev);
926 static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
929 struct pci_dev *pdev = dev->pdev;
932 mutex_lock(&dev->intf_state_mutex);
933 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
934 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
939 device_printf((&pdev->dev)->bsddev, "INFO: ""firmware version: %d.%d.%d\n", fw_rev_maj(dev), fw_rev_min(dev), fw_rev_sub(dev));
942 * On load removing any previous indication of internal error,
945 dev->state = MLX5_DEVICE_STATE_UP;
947 err = mlx5_cmd_init(dev);
949 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed initializing command interface, aborting\n");
953 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
955 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""Firmware over %d MS in initializing state, aborting\n", FW_INIT_TIMEOUT_MILI);
956 goto err_cmd_cleanup;
959 err = mlx5_core_enable_hca(dev);
961 device_printf((&pdev->dev)->bsddev, "ERR: ""enable hca failed\n");
962 goto err_cmd_cleanup;
965 err = mlx5_core_set_issi(dev);
967 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to set issi\n");
968 goto err_disable_hca;
971 err = mlx5_pagealloc_start(dev);
973 device_printf((&pdev->dev)->bsddev, "ERR: ""mlx5_pagealloc_start failed\n");
974 goto err_disable_hca;
977 err = mlx5_satisfy_startup_pages(dev, 1);
979 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to allocate boot pages\n");
980 goto err_pagealloc_stop;
983 err = set_hca_ctrl(dev);
985 device_printf((&pdev->dev)->bsddev, "ERR: ""set_hca_ctrl failed\n");
986 goto reclaim_boot_pages;
989 err = handle_hca_cap(dev);
991 device_printf((&pdev->dev)->bsddev, "ERR: ""handle_hca_cap failed\n");
992 goto reclaim_boot_pages;
995 err = handle_hca_cap_atomic(dev);
997 device_printf((&pdev->dev)->bsddev, "ERR: ""handle_hca_cap_atomic failed\n");
998 goto reclaim_boot_pages;
1001 err = mlx5_satisfy_startup_pages(dev, 0);
1003 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to allocate init pages\n");
1004 goto reclaim_boot_pages;
1007 err = mlx5_cmd_init_hca(dev);
1009 device_printf((&pdev->dev)->bsddev, "ERR: ""init hca failed\n");
1010 goto reclaim_boot_pages;
1013 mlx5_start_health_poll(dev);
1015 if (boot && mlx5_init_once(dev, priv)) {
1016 dev_err(&pdev->dev, "sw objs init failed\n");
1020 err = mlx5_enable_msix(dev);
1022 device_printf((&pdev->dev)->bsddev, "ERR: ""enable msix failed\n");
1023 goto err_cleanup_once;
1026 err = mlx5_alloc_uuars(dev, &priv->uuari);
1028 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed allocating uar, aborting\n");
1029 goto err_disable_msix;
1032 err = mlx5_start_eqs(dev);
1034 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to start pages and async EQs\n");
1038 err = alloc_comp_eqs(dev);
1040 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to alloc completion EQs\n");
1044 if (map_bf_area(dev))
1045 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to map blue flame area\n");
1047 err = mlx5_init_fs(dev);
1049 mlx5_core_err(dev, "flow steering init %d\n", err);
1050 goto err_free_comp_eqs;
1053 err = mlx5_register_device(dev);
1055 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1059 mlx5_fwdump_prep(dev);
1061 clear_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state);
1062 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1065 mutex_unlock(&dev->intf_state_mutex);
1069 mlx5_cleanup_fs(dev);
1079 mlx5_free_uuars(dev, &priv->uuari);
1082 mlx5_disable_msix(dev);
1086 mlx5_cleanup_once(dev);
1089 mlx5_stop_health_poll(dev);
1090 if (mlx5_cmd_teardown_hca(dev)) {
1091 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""tear_down_hca failed, skip cleanup\n");
1096 mlx5_reclaim_startup_pages(dev);
1099 mlx5_pagealloc_stop(dev);
1102 mlx5_core_disable_hca(dev);
1105 mlx5_cmd_cleanup(dev);
1108 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1109 mutex_unlock(&dev->intf_state_mutex);
1114 static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1120 mlx5_drain_health_recovery(dev);
1122 mutex_lock(&dev->intf_state_mutex);
1123 if (test_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state)) {
1124 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n", __func__);
1126 mlx5_cleanup_once(dev);
1130 mlx5_fwdump_clean(dev);
1131 mlx5_unregister_device(dev);
1133 mlx5_cleanup_fs(dev);
1135 mlx5_wait_for_reclaim_vfs_pages(dev);
1138 mlx5_free_uuars(dev, &priv->uuari);
1139 mlx5_disable_msix(dev);
1141 mlx5_cleanup_once(dev);
1142 mlx5_stop_health_poll(dev);
1143 err = mlx5_cmd_teardown_hca(dev);
1145 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""tear_down_hca failed, skip cleanup\n");
1148 mlx5_pagealloc_stop(dev);
1149 mlx5_reclaim_startup_pages(dev);
1150 mlx5_core_disable_hca(dev);
1151 mlx5_cmd_cleanup(dev);
1154 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1155 set_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state);
1156 mutex_unlock(&dev->intf_state_mutex);
1160 void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
1161 unsigned long param)
1163 struct mlx5_priv *priv = &dev->priv;
1164 struct mlx5_device_context *dev_ctx;
1165 unsigned long flags;
1167 spin_lock_irqsave(&priv->ctx_lock, flags);
1169 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
1170 if (dev_ctx->intf->event)
1171 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
1173 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1176 struct mlx5_core_event_handler {
1177 void (*event)(struct mlx5_core_dev *dev,
1178 enum mlx5_dev_event event,
1183 static int init_one(struct pci_dev *pdev,
1184 const struct pci_device_id *id)
1186 struct mlx5_core_dev *dev;
1187 struct mlx5_priv *priv;
1190 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1193 priv->pci_dev_data = id->driver_data;
1195 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profiles)) {
1196 printf("mlx5_core: WARN: ""selected profile out of range, selecting default (%d)\n", MLX5_DEFAULT_PROF);
1197 prof_sel = MLX5_DEFAULT_PROF;
1199 dev->profile = &profiles[prof_sel];
1201 dev->event = mlx5_core_event;
1203 INIT_LIST_HEAD(&priv->ctx_list);
1204 spin_lock_init(&priv->ctx_lock);
1205 mutex_init(&dev->pci_status_mutex);
1206 mutex_init(&dev->intf_state_mutex);
1207 err = mlx5_pci_init(dev, priv);
1209 device_printf((&pdev->dev)->bsddev, "ERR: ""mlx5_pci_init failed %d\n", err);
1213 err = mlx5_health_init(dev);
1215 device_printf((&pdev->dev)->bsddev, "ERR: ""mlx5_health_init failed %d\n", err);
1219 mlx5_pagealloc_init(dev);
1221 err = mlx5_load_one(dev, priv, true);
1223 device_printf((&pdev->dev)->bsddev, "ERR: ""mlx5_register_device failed %d\n", err);
1227 pci_save_state(pdev->dev.bsddev);
1231 mlx5_pagealloc_cleanup(dev);
1232 mlx5_health_cleanup(dev);
1234 mlx5_pci_close(dev, priv);
1240 static void remove_one(struct pci_dev *pdev)
1242 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1243 struct mlx5_priv *priv = &dev->priv;
1245 if (mlx5_unload_one(dev, priv, true)) {
1246 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
1247 mlx5_health_cleanup(dev);
1251 mlx5_pagealloc_cleanup(dev);
1252 mlx5_health_cleanup(dev);
1253 mlx5_pci_close(dev, priv);
1254 pci_set_drvdata(pdev, NULL);
1258 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1259 pci_channel_state_t state)
1261 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1262 struct mlx5_priv *priv = &dev->priv;
1264 dev_info(&pdev->dev, "%s was called\n", __func__);
1265 mlx5_enter_error_state(dev, false);
1266 mlx5_unload_one(dev, priv, false);
1268 mlx5_drain_health_wq(dev);
1269 mlx5_pci_disable_device(dev);
1272 return state == pci_channel_io_perm_failure ?
1273 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1276 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1278 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1281 dev_info(&pdev->dev, "%s was called\n", __func__);
1283 err = mlx5_pci_enable_device(dev);
1285 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1287 return PCI_ERS_RESULT_DISCONNECT;
1289 pci_set_master(pdev);
1290 pci_set_powerstate(pdev->dev.bsddev, PCI_POWERSTATE_D0);
1291 pci_restore_state(pdev->dev.bsddev);
1292 pci_save_state(pdev->dev.bsddev);
1294 return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
1297 /* wait for the device to show vital signs. For now we check
1298 * that we can read the device ID and that the health buffer
1299 * shows a non zero value which is different than 0xffffffff
1301 static void wait_vital(struct pci_dev *pdev)
1303 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1304 struct mlx5_core_health *health = &dev->priv.health;
1305 const int niter = 100;
1310 /* Wait for firmware to be ready after reset */
1312 for (i = 0; i < niter; i++) {
1313 if (pci_read_config_word(pdev, 2, &did)) {
1314 dev_warn(&pdev->dev, "failed reading config word\n");
1317 if (did == pdev->device) {
1318 dev_info(&pdev->dev, "device ID correctly read after %d iterations\n", i);
1324 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__);
1326 for (i = 0; i < niter; i++) {
1327 count = ioread32be(health->health_counter);
1328 if (count && count != 0xffffffff) {
1329 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1336 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__);
1339 static void mlx5_pci_resume(struct pci_dev *pdev)
1341 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1342 struct mlx5_priv *priv = &dev->priv;
1345 dev_info(&pdev->dev, "%s was called\n", __func__);
1349 err = mlx5_load_one(dev, priv, false);
1351 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1354 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1357 static const struct pci_error_handlers mlx5_err_handler = {
1358 .error_detected = mlx5_pci_err_detected,
1359 .slot_reset = mlx5_pci_slot_reset,
1360 .resume = mlx5_pci_resume
1363 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1367 if (!MLX5_CAP_GEN(dev, force_teardown)) {
1368 mlx5_core_dbg(dev, "force teardown is not supported in the firmware\n");
1372 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1373 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1377 err = mlx5_cmd_force_teardown_hca(dev);
1379 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", err);
1383 mlx5_enter_error_state(dev, true);
1388 static void shutdown_one(struct pci_dev *pdev)
1390 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1391 struct mlx5_priv *priv = &dev->priv;
1394 set_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &dev->intf_state);
1395 err = mlx5_try_fast_unload(dev);
1397 mlx5_unload_one(dev, priv, false);
1398 mlx5_pci_disable_device(dev);
1401 static const struct pci_device_id mlx5_core_pci_table[] = {
1402 { PCI_VDEVICE(MELLANOX, 4113) }, /* Connect-IB */
1403 { PCI_VDEVICE(MELLANOX, 4114) }, /* Connect-IB VF */
1404 { PCI_VDEVICE(MELLANOX, 4115) }, /* ConnectX-4 */
1405 { PCI_VDEVICE(MELLANOX, 4116) }, /* ConnectX-4 VF */
1406 { PCI_VDEVICE(MELLANOX, 4117) }, /* ConnectX-4LX */
1407 { PCI_VDEVICE(MELLANOX, 4118) }, /* ConnectX-4LX VF */
1408 { PCI_VDEVICE(MELLANOX, 4119) }, /* ConnectX-5 */
1409 { PCI_VDEVICE(MELLANOX, 4120) }, /* ConnectX-5 VF */
1410 { PCI_VDEVICE(MELLANOX, 4121) },
1411 { PCI_VDEVICE(MELLANOX, 4122) },
1412 { PCI_VDEVICE(MELLANOX, 4123) },
1413 { PCI_VDEVICE(MELLANOX, 4124) },
1414 { PCI_VDEVICE(MELLANOX, 4125) },
1415 { PCI_VDEVICE(MELLANOX, 4126) },
1416 { PCI_VDEVICE(MELLANOX, 4127) },
1417 { PCI_VDEVICE(MELLANOX, 4128) },
1418 { PCI_VDEVICE(MELLANOX, 4129) },
1419 { PCI_VDEVICE(MELLANOX, 4130) },
1420 { PCI_VDEVICE(MELLANOX, 4131) },
1421 { PCI_VDEVICE(MELLANOX, 4132) },
1422 { PCI_VDEVICE(MELLANOX, 4133) },
1423 { PCI_VDEVICE(MELLANOX, 4134) },
1424 { PCI_VDEVICE(MELLANOX, 4135) },
1425 { PCI_VDEVICE(MELLANOX, 4136) },
1426 { PCI_VDEVICE(MELLANOX, 4137) },
1427 { PCI_VDEVICE(MELLANOX, 4138) },
1428 { PCI_VDEVICE(MELLANOX, 4139) },
1429 { PCI_VDEVICE(MELLANOX, 4140) },
1430 { PCI_VDEVICE(MELLANOX, 4141) },
1431 { PCI_VDEVICE(MELLANOX, 4142) },
1432 { PCI_VDEVICE(MELLANOX, 4143) },
1433 { PCI_VDEVICE(MELLANOX, 4144) },
1437 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1439 void mlx5_disable_device(struct mlx5_core_dev *dev)
1441 mlx5_pci_err_detected(dev->pdev, 0);
1444 void mlx5_recover_device(struct mlx5_core_dev *dev)
1446 mlx5_pci_disable_device(dev);
1447 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
1448 mlx5_pci_resume(dev->pdev);
1451 struct pci_driver mlx5_core_driver = {
1452 .name = DRIVER_NAME,
1453 .id_table = mlx5_core_pci_table,
1454 .shutdown = shutdown_one,
1456 .remove = remove_one,
1457 .err_handler = &mlx5_err_handler
1460 static int __init init(void)
1464 err = pci_register_driver(&mlx5_core_driver);
1468 err = mlx5_fwdump_init();
1475 pci_unregister_driver(&mlx5_core_driver);
1481 static void __exit cleanup(void)
1484 pci_unregister_driver(&mlx5_core_driver);
1488 module_exit(cleanup);