2 * Copyright (c) 2013-2019, Mellanox Technologies, Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <linux/kmod.h>
29 #include <linux/module.h>
30 #include <linux/errno.h>
31 #include <linux/pci.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/slab.h>
34 #include <linux/io-mapping.h>
35 #include <linux/interrupt.h>
36 #include <linux/hardirq.h>
37 #include <dev/mlx5/driver.h>
38 #include <dev/mlx5/cq.h>
39 #include <dev/mlx5/qp.h>
40 #include <dev/mlx5/srq.h>
41 #include <dev/mlx5/mpfs.h>
42 #include <linux/delay.h>
43 #include <dev/mlx5/mlx5_ifc.h>
44 #include <dev/mlx5/mlx5_fpga/core.h>
45 #include <dev/mlx5/mlx5_lib/mlx5.h>
46 #include "mlx5_core.h"
49 static const char mlx5_version[] = "Mellanox Core driver "
50 DRIVER_VERSION " (" DRIVER_RELDATE ")";
51 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
52 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
53 MODULE_LICENSE("Dual BSD/GPL");
54 MODULE_DEPEND(mlx5, linuxkpi, 1, 1, 1);
55 MODULE_DEPEND(mlx5, mlxfw, 1, 1, 1);
56 MODULE_DEPEND(mlx5, firmware, 1, 1, 1);
57 MODULE_VERSION(mlx5, 1);
59 SYSCTL_NODE(_hw, OID_AUTO, mlx5, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
60 "mlx5 hardware controls");
62 int mlx5_core_debug_mask;
63 SYSCTL_INT(_hw_mlx5, OID_AUTO, debug_mask, CTLFLAG_RWTUN,
64 &mlx5_core_debug_mask, 0,
65 "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
67 #define MLX5_DEFAULT_PROF 2
68 static int mlx5_prof_sel = MLX5_DEFAULT_PROF;
69 SYSCTL_INT(_hw_mlx5, OID_AUTO, prof_sel, CTLFLAG_RWTUN,
71 "profile selector. Valid range 0 - 2");
73 static int mlx5_fast_unload_enabled = 1;
74 SYSCTL_INT(_hw_mlx5, OID_AUTO, fast_unload_enabled, CTLFLAG_RWTUN,
75 &mlx5_fast_unload_enabled, 0,
76 "Set to enable fast unload. Clear to disable.");
78 #define NUMA_NO_NODE -1
80 static LIST_HEAD(intf_list);
81 static LIST_HEAD(dev_list);
82 static DEFINE_MUTEX(intf_mutex);
84 struct mlx5_device_context {
85 struct list_head list;
86 struct mlx5_interface *intf;
91 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
92 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
95 static struct mlx5_profile profiles[] = {
100 .mask = MLX5_PROF_MASK_QP_SIZE,
104 .mask = MLX5_PROF_MASK_QP_SIZE |
105 MLX5_PROF_MASK_MR_CACHE,
169 .mask = MLX5_PROF_MASK_QP_SIZE,
174 static int set_dma_caps(struct pci_dev *pdev)
176 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
179 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
181 mlx5_core_warn(dev, "couldn't set 64-bit PCI DMA mask\n");
182 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
184 mlx5_core_err(dev, "Can't set PCI DMA mask, aborting\n");
189 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
191 mlx5_core_warn(dev, "couldn't set 64-bit consistent PCI DMA mask\n");
192 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
194 mlx5_core_err(dev, "Can't set consistent PCI DMA mask, aborting\n");
199 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
203 int mlx5_pci_read_power_status(struct mlx5_core_dev *dev,
204 u16 *p_power, u8 *p_status)
206 u32 in[MLX5_ST_SZ_DW(mpein_reg)] = {};
207 u32 out[MLX5_ST_SZ_DW(mpein_reg)] = {};
210 err = mlx5_core_access_reg(dev, in, sizeof(in), out, sizeof(out),
211 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MPEIN, 0, 0);
213 *p_status = MLX5_GET(mpein_reg, out, pwr_status);
214 *p_power = MLX5_GET(mpein_reg, out, pci_power);
218 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
220 struct pci_dev *pdev = dev->pdev;
223 mutex_lock(&dev->pci_status_mutex);
224 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
225 err = pci_enable_device(pdev);
227 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
229 mutex_unlock(&dev->pci_status_mutex);
234 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
236 struct pci_dev *pdev = dev->pdev;
238 mutex_lock(&dev->pci_status_mutex);
239 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
240 pci_disable_device(pdev);
241 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
243 mutex_unlock(&dev->pci_status_mutex);
246 static int request_bar(struct pci_dev *pdev)
248 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
251 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
252 mlx5_core_err(dev, "Missing registers BAR, aborting\n");
256 err = pci_request_regions(pdev, DRIVER_NAME);
258 mlx5_core_err(dev, "Couldn't get PCI resources, aborting\n");
263 static void release_bar(struct pci_dev *pdev)
265 pci_release_regions(pdev);
268 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
270 struct mlx5_priv *priv = &dev->priv;
271 struct mlx5_eq_table *table = &priv->eq_table;
272 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
273 int limit = dev->msix_eqvec;
274 int nvec = MLX5_EQ_VEC_COMP_BASE;
280 nvec += MLX5_CAP_GEN(dev, num_ports) * num_online_cpus();
285 nvec = 256; /* limit of firmware API */
286 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
289 priv->msix_arr = kzalloc(nvec * sizeof(*priv->msix_arr), GFP_KERNEL);
291 for (i = 0; i < nvec; i++)
292 priv->msix_arr[i].entry = i;
294 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
295 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
299 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
303 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
305 struct mlx5_priv *priv = &dev->priv;
307 pci_disable_msix(dev->pdev);
308 kfree(priv->msix_arr);
311 struct mlx5_reg_host_endianess {
317 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
320 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
321 MLX5_DEV_CAP_FLAG_DCT |
322 MLX5_DEV_CAP_FLAG_DRAIN_SIGERR,
325 static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
341 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
346 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
347 enum mlx5_cap_type cap_type,
348 enum mlx5_cap_mode cap_mode)
350 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
351 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
352 void *out, *hca_caps;
353 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
356 memset(in, 0, sizeof(in));
357 out = kzalloc(out_sz, GFP_KERNEL);
359 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
360 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
361 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
364 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
365 cap_type, cap_mode, err);
369 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
372 case HCA_CAP_OPMOD_GET_MAX:
373 memcpy(dev->hca_caps_max[cap_type], hca_caps,
374 MLX5_UN_SZ_BYTES(hca_cap_union));
376 case HCA_CAP_OPMOD_GET_CUR:
377 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
378 MLX5_UN_SZ_BYTES(hca_cap_union));
382 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
392 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
396 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
400 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
403 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
405 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0};
407 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
409 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
412 static int handle_hca_cap(struct mlx5_core_dev *dev)
414 void *set_ctx = NULL;
415 struct mlx5_profile *prof = dev->profile;
417 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
420 set_ctx = kzalloc(set_sz, GFP_KERNEL);
422 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
426 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
428 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
429 MLX5_ST_SZ_BYTES(cmd_hca_cap));
431 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
432 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
434 /* we limit the size of the pkey table to 128 entries for now */
435 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
436 to_fw_pkey_sz(dev, 128));
438 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
439 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
442 /* disable cmdif checksum */
443 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
445 /* enable drain sigerr */
446 MLX5_SET(cmd_hca_cap, set_hca_cap, drain_sigerr, 1);
448 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
450 err = set_caps(dev, set_ctx, set_sz);
457 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
461 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
465 if (MLX5_CAP_GEN(dev, atomic)) {
466 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
475 supported_atomic_req_8B_endianess_mode_1);
477 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
480 set_ctx = kzalloc(set_sz, GFP_KERNEL);
484 MLX5_SET(set_hca_cap_in, set_ctx, op_mod,
485 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC << 1);
486 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
488 /* Set requestor to host endianness */
489 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode,
490 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
492 err = set_caps(dev, set_ctx, set_sz);
498 static int set_hca_ctrl(struct mlx5_core_dev *dev)
500 struct mlx5_reg_host_endianess he_in;
501 struct mlx5_reg_host_endianess he_out;
504 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH &&
505 !MLX5_CAP_GEN(dev, roce))
508 memset(&he_in, 0, sizeof(he_in));
509 he_in.he = MLX5_SET_HOST_ENDIANNESS;
510 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
511 &he_out, sizeof(he_out),
512 MLX5_REG_HOST_ENDIANNESS, 0, 1);
516 static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
518 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0};
519 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0};
521 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
522 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
525 static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
527 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0};
528 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0};
530 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
531 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
534 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
536 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0};
537 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0};
541 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
543 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in), query_out, sizeof(query_out));
548 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
549 if (status == MLX5_CMD_STAT_BAD_OP_ERR) {
550 mlx5_core_dbg(dev, "Only ISSI 0 is supported\n");
554 mlx5_core_err(dev, "failed to query ISSI\n");
558 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
560 if (sup_issi & (1 << 1)) {
561 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0};
562 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0};
564 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
565 MLX5_SET(set_issi_in, set_in, current_issi, 1);
567 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in), set_out, sizeof(set_out));
569 mlx5_core_err(dev, "failed to set ISSI=1 err(%d)\n", err);
576 } else if (sup_issi & (1 << 0)) {
584 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn)
586 struct mlx5_eq_table *table = &dev->priv.eq_table;
590 spin_lock(&table->lock);
591 list_for_each_entry(eq, &table->comp_eqs_list, list) {
592 if (eq->index == vector) {
599 spin_unlock(&table->lock);
603 EXPORT_SYMBOL(mlx5_vector2eqn);
605 static void free_comp_eqs(struct mlx5_core_dev *dev)
607 struct mlx5_eq_table *table = &dev->priv.eq_table;
608 struct mlx5_eq *eq, *n;
610 spin_lock(&table->lock);
611 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
613 spin_unlock(&table->lock);
614 if (mlx5_destroy_unmap_eq(dev, eq))
615 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
618 spin_lock(&table->lock);
620 spin_unlock(&table->lock);
623 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
625 struct mlx5_eq_table *table = &dev->priv.eq_table;
632 INIT_LIST_HEAD(&table->comp_eqs_list);
633 ncomp_vec = table->num_comp_vectors;
634 nent = MLX5_COMP_EQ_SIZE;
635 for (i = 0; i < ncomp_vec; i++) {
636 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
638 err = mlx5_create_map_eq(dev, eq,
639 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
640 &dev->priv.uuari.uars[0]);
645 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
647 spin_lock(&table->lock);
648 list_add_tail(&eq->list, &table->comp_eqs_list);
649 spin_unlock(&table->lock);
659 static int map_bf_area(struct mlx5_core_dev *dev)
661 resource_size_t bf_start = pci_resource_start(dev->pdev, 0);
662 resource_size_t bf_len = pci_resource_len(dev->pdev, 0);
664 dev->priv.bf_mapping = io_mapping_create_wc(bf_start, bf_len);
666 return dev->priv.bf_mapping ? 0 : -ENOMEM;
669 static void unmap_bf_area(struct mlx5_core_dev *dev)
671 if (dev->priv.bf_mapping)
672 io_mapping_free(dev->priv.bf_mapping);
675 static inline int fw_initializing(struct mlx5_core_dev *dev)
677 return ioread32be(&dev->iseg->initializing) >> 31;
680 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili,
683 int warn = jiffies + msecs_to_jiffies(warn_time_mili);
684 int end = jiffies + msecs_to_jiffies(max_wait_mili);
687 MPASS(max_wait_mili > warn_time_mili);
689 while (fw_initializing(dev) == 1) {
690 if (time_after(jiffies, end)) {
694 if (warn_time_mili && time_after(jiffies, warn)) {
696 "Waiting for FW initialization, timeout abort in %u s\n",
697 (unsigned int)(jiffies_to_msecs(end - warn) / 1000));
698 warn = jiffies + msecs_to_jiffies(warn_time_mili);
700 msleep(FW_INIT_WAIT_MS);
704 mlx5_core_dbg(dev, "Full initializing bit dword = 0x%x\n",
705 ioread32be(&dev->iseg->initializing));
710 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
712 struct mlx5_device_context *dev_ctx;
713 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
715 dev_ctx = kzalloc(sizeof(*dev_ctx), GFP_KERNEL);
719 dev_ctx->intf = intf;
720 CURVNET_SET_QUIET(vnet0);
721 dev_ctx->context = intf->add(dev);
724 if (dev_ctx->context) {
725 spin_lock_irq(&priv->ctx_lock);
726 list_add_tail(&dev_ctx->list, &priv->ctx_list);
727 spin_unlock_irq(&priv->ctx_lock);
733 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
735 struct mlx5_device_context *dev_ctx;
736 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
738 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
739 if (dev_ctx->intf == intf) {
740 spin_lock_irq(&priv->ctx_lock);
741 list_del(&dev_ctx->list);
742 spin_unlock_irq(&priv->ctx_lock);
744 intf->remove(dev, dev_ctx->context);
751 mlx5_register_device(struct mlx5_core_dev *dev)
753 struct mlx5_priv *priv = &dev->priv;
754 struct mlx5_interface *intf;
756 mutex_lock(&intf_mutex);
757 list_add_tail(&priv->dev_list, &dev_list);
758 list_for_each_entry(intf, &intf_list, list)
759 mlx5_add_device(intf, priv);
760 mutex_unlock(&intf_mutex);
766 mlx5_unregister_device(struct mlx5_core_dev *dev)
768 struct mlx5_priv *priv = &dev->priv;
769 struct mlx5_interface *intf;
771 mutex_lock(&intf_mutex);
772 list_for_each_entry(intf, &intf_list, list)
773 mlx5_remove_device(intf, priv);
774 list_del(&priv->dev_list);
775 mutex_unlock(&intf_mutex);
778 int mlx5_register_interface(struct mlx5_interface *intf)
780 struct mlx5_priv *priv;
782 if (!intf->add || !intf->remove)
785 mutex_lock(&intf_mutex);
786 list_add_tail(&intf->list, &intf_list);
787 list_for_each_entry(priv, &dev_list, dev_list)
788 mlx5_add_device(intf, priv);
789 mutex_unlock(&intf_mutex);
793 EXPORT_SYMBOL(mlx5_register_interface);
795 void mlx5_unregister_interface(struct mlx5_interface *intf)
797 struct mlx5_priv *priv;
799 mutex_lock(&intf_mutex);
800 list_for_each_entry(priv, &dev_list, dev_list)
801 mlx5_remove_device(intf, priv);
802 list_del(&intf->list);
803 mutex_unlock(&intf_mutex);
805 EXPORT_SYMBOL(mlx5_unregister_interface);
807 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
809 struct mlx5_priv *priv = &mdev->priv;
810 struct mlx5_device_context *dev_ctx;
814 spin_lock_irqsave(&priv->ctx_lock, flags);
816 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
817 if ((dev_ctx->intf->protocol == protocol) &&
818 dev_ctx->intf->get_dev) {
819 result = dev_ctx->intf->get_dev(dev_ctx->context);
823 spin_unlock_irqrestore(&priv->ctx_lock, flags);
827 EXPORT_SYMBOL(mlx5_get_protocol_dev);
829 static int mlx5_auto_fw_update;
830 SYSCTL_INT(_hw_mlx5, OID_AUTO, auto_fw_update, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
831 &mlx5_auto_fw_update, 0,
832 "Allow automatic firmware update on driver start");
834 mlx5_firmware_update(struct mlx5_core_dev *dev)
836 const struct firmware *fw;
839 TUNABLE_INT_FETCH("hw.mlx5.auto_fw_update", &mlx5_auto_fw_update);
840 if (!mlx5_auto_fw_update)
842 fw = firmware_get("mlx5fw_mfa");
844 err = mlx5_firmware_flash(dev, fw);
845 firmware_put(fw, FIRMWARE_UNLOAD);
853 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
855 struct pci_dev *pdev = dev->pdev;
858 pci_set_drvdata(dev->pdev, dev);
859 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
860 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
862 mutex_init(&priv->pgdir_mutex);
863 INIT_LIST_HEAD(&priv->pgdir_list);
864 spin_lock_init(&priv->mkey_lock);
866 priv->numa_node = NUMA_NO_NODE;
868 err = mlx5_pci_enable_device(dev);
870 mlx5_core_err(dev, "Cannot enable PCI device, aborting\n");
874 err = request_bar(pdev);
876 mlx5_core_err(dev, "error requesting BARs, aborting\n");
880 pci_set_master(pdev);
882 err = set_dma_caps(pdev);
884 mlx5_core_err(dev, "Failed setting DMA capabilities mask, aborting\n");
888 dev->iseg_base = pci_resource_start(dev->pdev, 0);
889 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
892 mlx5_core_err(dev, "Failed mapping initialization segment, aborting\n");
899 release_bar(dev->pdev);
901 mlx5_pci_disable_device(dev);
906 static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
909 release_bar(dev->pdev);
910 mlx5_pci_disable_device(dev);
913 static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
917 err = mlx5_vsc_find_cap(dev);
919 mlx5_core_err(dev, "Unable to find vendor specific capabilities\n");
921 err = mlx5_query_hca_caps(dev);
923 mlx5_core_err(dev, "query hca failed\n");
927 err = mlx5_query_board_id(dev);
929 mlx5_core_err(dev, "query board id failed\n");
933 err = mlx5_eq_init(dev);
935 mlx5_core_err(dev, "failed to initialize eq\n");
939 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
941 err = mlx5_init_cq_table(dev);
943 mlx5_core_err(dev, "failed to initialize cq table\n");
947 mlx5_init_qp_table(dev);
948 mlx5_init_srq_table(dev);
949 mlx5_init_mr_table(dev);
951 mlx5_init_reserved_gids(dev);
955 err = mlx5_init_rl_table(dev);
957 mlx5_core_err(dev, "Failed to init rate limiting\n");
958 goto err_tables_cleanup;
965 mlx5_cleanup_mr_table(dev);
966 mlx5_cleanup_srq_table(dev);
967 mlx5_cleanup_qp_table(dev);
968 mlx5_cleanup_cq_table(dev);
972 mlx5_eq_cleanup(dev);
978 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
981 mlx5_cleanup_rl_table(dev);
983 mlx5_fpga_cleanup(dev);
984 mlx5_cleanup_reserved_gids(dev);
985 mlx5_cleanup_mr_table(dev);
986 mlx5_cleanup_srq_table(dev);
987 mlx5_cleanup_qp_table(dev);
988 mlx5_cleanup_cq_table(dev);
989 mlx5_eq_cleanup(dev);
992 static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
997 mutex_lock(&dev->intf_state_mutex);
998 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
999 mlx5_core_warn(dev, "interface is up, NOP\n");
1003 mlx5_core_dbg(dev, "firmware version: %d.%d.%d\n",
1004 fw_rev_maj(dev), fw_rev_min(dev), fw_rev_sub(dev));
1007 * On load removing any previous indication of internal error,
1010 dev->state = MLX5_DEVICE_STATE_UP;
1012 /* wait for firmware to accept initialization segments configurations
1014 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI,
1015 FW_INIT_WARN_MESSAGE_INTERVAL);
1017 dev_err(&dev->pdev->dev,
1018 "Firmware over %d MS in pre-initializing state, aborting\n",
1019 FW_PRE_INIT_TIMEOUT_MILI);
1023 err = mlx5_cmd_init(dev);
1026 "Failed initializing command interface, aborting\n");
1030 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI, 0);
1033 "Firmware over %d MS in initializing state, aborting\n",
1034 FW_INIT_TIMEOUT_MILI);
1035 goto err_cmd_cleanup;
1038 err = mlx5_core_enable_hca(dev);
1040 mlx5_core_err(dev, "enable hca failed\n");
1041 goto err_cmd_cleanup;
1044 err = mlx5_core_set_issi(dev);
1046 mlx5_core_err(dev, "failed to set issi\n");
1047 goto err_disable_hca;
1050 err = mlx5_pagealloc_start(dev);
1052 mlx5_core_err(dev, "mlx5_pagealloc_start failed\n");
1053 goto err_disable_hca;
1056 err = mlx5_satisfy_startup_pages(dev, 1);
1058 mlx5_core_err(dev, "failed to allocate boot pages\n");
1059 goto err_pagealloc_stop;
1062 err = set_hca_ctrl(dev);
1064 mlx5_core_err(dev, "set_hca_ctrl failed\n");
1065 goto reclaim_boot_pages;
1068 err = handle_hca_cap(dev);
1070 mlx5_core_err(dev, "handle_hca_cap failed\n");
1071 goto reclaim_boot_pages;
1074 err = handle_hca_cap_atomic(dev);
1076 mlx5_core_err(dev, "handle_hca_cap_atomic failed\n");
1077 goto reclaim_boot_pages;
1080 err = mlx5_satisfy_startup_pages(dev, 0);
1082 mlx5_core_err(dev, "failed to allocate init pages\n");
1083 goto reclaim_boot_pages;
1086 err = mlx5_cmd_init_hca(dev);
1088 mlx5_core_err(dev, "init hca failed\n");
1089 goto reclaim_boot_pages;
1092 mlx5_start_health_poll(dev);
1094 if (boot && mlx5_init_once(dev, priv)) {
1095 mlx5_core_err(dev, "sw objs init failed\n");
1099 err = mlx5_enable_msix(dev);
1101 mlx5_core_err(dev, "enable msix failed\n");
1102 goto err_cleanup_once;
1105 err = mlx5_alloc_uuars(dev, &priv->uuari);
1107 mlx5_core_err(dev, "Failed allocating uar, aborting\n");
1108 goto err_disable_msix;
1111 err = mlx5_start_eqs(dev);
1113 mlx5_core_err(dev, "Failed to start pages and async EQs\n");
1117 err = alloc_comp_eqs(dev);
1119 mlx5_core_err(dev, "Failed to alloc completion EQs\n");
1123 if (map_bf_area(dev))
1124 mlx5_core_err(dev, "Failed to map blue flame area\n");
1126 err = mlx5_init_fs(dev);
1128 mlx5_core_err(dev, "flow steering init %d\n", err);
1129 goto err_free_comp_eqs;
1132 err = mlx5_mpfs_init(dev);
1134 mlx5_core_err(dev, "mpfs init failed %d\n", err);
1138 err = mlx5_fpga_device_start(dev);
1140 mlx5_core_err(dev, "fpga device start failed %d\n", err);
1144 err = mlx5_register_device(dev);
1146 mlx5_core_err(dev, "mlx5_register_device failed %d\n", err);
1150 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1153 mutex_unlock(&dev->intf_state_mutex);
1157 mlx5_fpga_device_stop(dev);
1160 mlx5_mpfs_destroy(dev);
1163 mlx5_cleanup_fs(dev);
1173 mlx5_free_uuars(dev, &priv->uuari);
1176 mlx5_disable_msix(dev);
1180 mlx5_cleanup_once(dev);
1183 mlx5_stop_health_poll(dev, boot);
1184 if (mlx5_cmd_teardown_hca(dev)) {
1185 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1190 mlx5_reclaim_startup_pages(dev);
1193 mlx5_pagealloc_stop(dev);
1196 mlx5_core_disable_hca(dev);
1199 mlx5_cmd_cleanup(dev);
1202 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1203 mutex_unlock(&dev->intf_state_mutex);
1208 static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1214 mlx5_drain_health_recovery(dev);
1216 mutex_lock(&dev->intf_state_mutex);
1217 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1218 mlx5_core_warn(dev, "%s: interface is down, NOP\n", __func__);
1220 mlx5_cleanup_once(dev);
1224 mlx5_unregister_device(dev);
1226 mlx5_fpga_device_stop(dev);
1227 mlx5_mpfs_destroy(dev);
1228 mlx5_cleanup_fs(dev);
1230 mlx5_wait_for_reclaim_vfs_pages(dev);
1233 mlx5_free_uuars(dev, &priv->uuari);
1234 mlx5_disable_msix(dev);
1236 mlx5_cleanup_once(dev);
1237 mlx5_stop_health_poll(dev, cleanup);
1238 err = mlx5_cmd_teardown_hca(dev);
1240 mlx5_core_err(dev, "tear_down_hca failed, skip cleanup\n");
1243 mlx5_pagealloc_stop(dev);
1244 mlx5_reclaim_startup_pages(dev);
1245 mlx5_core_disable_hca(dev);
1246 mlx5_cmd_cleanup(dev);
1249 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1250 mutex_unlock(&dev->intf_state_mutex);
1254 void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
1255 unsigned long param)
1257 struct mlx5_priv *priv = &dev->priv;
1258 struct mlx5_device_context *dev_ctx;
1259 unsigned long flags;
1261 spin_lock_irqsave(&priv->ctx_lock, flags);
1263 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
1264 if (dev_ctx->intf->event)
1265 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
1267 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1270 struct mlx5_core_event_handler {
1271 void (*event)(struct mlx5_core_dev *dev,
1272 enum mlx5_dev_event event,
1276 #define MLX5_STATS_DESC(a, b, c, d, e, ...) d, e,
1278 #define MLX5_PORT_MODULE_ERROR_STATS(m) \
1279 m(+1, u64, power_budget_exceeded, "power_budget", "Module Power Budget Exceeded") \
1280 m(+1, u64, long_range, "long_range", "Module Long Range for non MLNX cable/module") \
1281 m(+1, u64, bus_stuck, "bus_stuck", "Module Bus stuck(I2C or data shorted)") \
1282 m(+1, u64, no_eeprom, "no_eeprom", "No EEPROM/retry timeout") \
1283 m(+1, u64, enforce_part_number, "enforce_part_number", "Module Enforce part number list") \
1284 m(+1, u64, unknown_id, "unknown_id", "Module Unknown identifier") \
1285 m(+1, u64, high_temp, "high_temp", "Module High Temperature") \
1286 m(+1, u64, cable_shorted, "cable_shorted", "Module Cable is shorted")
1288 static const char *mlx5_pme_err_desc[] = {
1289 MLX5_PORT_MODULE_ERROR_STATS(MLX5_STATS_DESC)
1292 static int init_one(struct pci_dev *pdev,
1293 const struct pci_device_id *id)
1295 struct mlx5_core_dev *dev;
1296 struct mlx5_priv *priv;
1297 device_t bsddev = pdev->dev.bsddev;
1299 struct sysctl_oid *pme_sysctl_node;
1300 struct sysctl_oid *pme_err_sysctl_node;
1302 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1305 priv->pci_dev_data = id->driver_data;
1307 if (mlx5_prof_sel < 0 || mlx5_prof_sel >= ARRAY_SIZE(profiles)) {
1308 device_printf(bsddev,
1309 "WARN: selected profile out of range, selecting default (%d)\n",
1311 mlx5_prof_sel = MLX5_DEFAULT_PROF;
1313 dev->profile = &profiles[mlx5_prof_sel];
1315 dev->event = mlx5_core_event;
1318 device_set_desc(bsddev, mlx5_version);
1320 sysctl_ctx_init(&dev->sysctl_ctx);
1321 SYSCTL_ADD_INT(&dev->sysctl_ctx,
1322 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)),
1323 OID_AUTO, "msix_eqvec", CTLFLAG_RDTUN, &dev->msix_eqvec, 0,
1324 "Maximum number of MSIX event queue vectors, if set");
1325 SYSCTL_ADD_INT(&dev->sysctl_ctx,
1326 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)),
1327 OID_AUTO, "power_status", CTLFLAG_RD, &dev->pwr_status, 0,
1328 "0:Invalid 1:Sufficient 2:Insufficient");
1329 SYSCTL_ADD_INT(&dev->sysctl_ctx,
1330 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)),
1331 OID_AUTO, "power_value", CTLFLAG_RD, &dev->pwr_value, 0,
1332 "Current power value in Watts");
1334 pme_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx,
1335 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)),
1336 OID_AUTO, "pme_stats", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
1337 "Port module event statistics");
1338 if (pme_sysctl_node == NULL) {
1340 goto clean_sysctl_ctx;
1342 pme_err_sysctl_node = SYSCTL_ADD_NODE(&dev->sysctl_ctx,
1343 SYSCTL_CHILDREN(pme_sysctl_node),
1344 OID_AUTO, "errors", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL,
1345 "Port module event error statistics");
1346 if (pme_err_sysctl_node == NULL) {
1348 goto clean_sysctl_ctx;
1350 SYSCTL_ADD_U64(&dev->sysctl_ctx,
1351 SYSCTL_CHILDREN(pme_sysctl_node), OID_AUTO,
1352 "module_plug", CTLFLAG_RD | CTLFLAG_MPSAFE,
1353 &dev->priv.pme_stats.status_counters[MLX5_MODULE_STATUS_PLUGGED_ENABLED],
1354 0, "Number of time module plugged");
1355 SYSCTL_ADD_U64(&dev->sysctl_ctx,
1356 SYSCTL_CHILDREN(pme_sysctl_node), OID_AUTO,
1357 "module_unplug", CTLFLAG_RD | CTLFLAG_MPSAFE,
1358 &dev->priv.pme_stats.status_counters[MLX5_MODULE_STATUS_UNPLUGGED],
1359 0, "Number of time module unplugged");
1360 for (i = 0 ; i < MLX5_MODULE_EVENT_ERROR_NUM; i++) {
1361 SYSCTL_ADD_U64(&dev->sysctl_ctx,
1362 SYSCTL_CHILDREN(pme_err_sysctl_node), OID_AUTO,
1363 mlx5_pme_err_desc[2 * i], CTLFLAG_RD | CTLFLAG_MPSAFE,
1364 &dev->priv.pme_stats.error_counters[i],
1365 0, mlx5_pme_err_desc[2 * i + 1]);
1369 INIT_LIST_HEAD(&priv->ctx_list);
1370 spin_lock_init(&priv->ctx_lock);
1371 mutex_init(&dev->pci_status_mutex);
1372 mutex_init(&dev->intf_state_mutex);
1373 mtx_init(&dev->dump_lock, "mlx5dmp", NULL, MTX_DEF | MTX_NEW);
1374 err = mlx5_pci_init(dev, priv);
1376 mlx5_core_err(dev, "mlx5_pci_init failed %d\n", err);
1380 err = mlx5_health_init(dev);
1382 mlx5_core_err(dev, "mlx5_health_init failed %d\n", err);
1386 mlx5_pagealloc_init(dev);
1388 err = mlx5_load_one(dev, priv, true);
1390 mlx5_core_err(dev, "mlx5_load_one failed %d\n", err);
1394 mlx5_fwdump_prep(dev);
1396 mlx5_firmware_update(dev);
1398 pci_save_state(bsddev);
1402 mlx5_pagealloc_cleanup(dev);
1403 mlx5_health_cleanup(dev);
1405 mlx5_pci_close(dev, priv);
1407 mtx_destroy(&dev->dump_lock);
1409 sysctl_ctx_free(&dev->sysctl_ctx);
1414 static void remove_one(struct pci_dev *pdev)
1416 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1417 struct mlx5_priv *priv = &dev->priv;
1419 if (mlx5_unload_one(dev, priv, true)) {
1420 mlx5_core_err(dev, "mlx5_unload_one failed\n");
1421 mlx5_health_cleanup(dev);
1425 mlx5_pagealloc_cleanup(dev);
1426 mlx5_health_cleanup(dev);
1427 mlx5_fwdump_clean(dev);
1428 mlx5_pci_close(dev, priv);
1429 mtx_destroy(&dev->dump_lock);
1430 pci_set_drvdata(pdev, NULL);
1431 sysctl_ctx_free(&dev->sysctl_ctx);
1435 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1436 pci_channel_state_t state)
1438 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1439 struct mlx5_priv *priv = &dev->priv;
1441 mlx5_core_info(dev, "%s was called\n", __func__);
1442 mlx5_enter_error_state(dev, false);
1443 mlx5_unload_one(dev, priv, false);
1446 mlx5_drain_health_wq(dev);
1447 mlx5_pci_disable_device(dev);
1450 return state == pci_channel_io_perm_failure ?
1451 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1454 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1456 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1459 mlx5_core_info(dev,"%s was called\n", __func__);
1461 err = mlx5_pci_enable_device(dev);
1463 mlx5_core_err(dev, "mlx5_pci_enable_device failed with error code: %d\n"
1465 return PCI_ERS_RESULT_DISCONNECT;
1467 pci_set_master(pdev);
1468 pci_set_powerstate(pdev->dev.bsddev, PCI_POWERSTATE_D0);
1469 pci_restore_state(pdev->dev.bsddev);
1470 pci_save_state(pdev->dev.bsddev);
1472 return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
1475 /* wait for the device to show vital signs. For now we check
1476 * that we can read the device ID and that the health buffer
1477 * shows a non zero value which is different than 0xffffffff
1479 static void wait_vital(struct pci_dev *pdev)
1481 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1482 struct mlx5_core_health *health = &dev->priv.health;
1483 const int niter = 100;
1488 /* Wait for firmware to be ready after reset */
1490 for (i = 0; i < niter; i++) {
1491 if (pci_read_config_word(pdev, 2, &did)) {
1492 mlx5_core_warn(dev, "failed reading config word\n");
1495 if (did == pdev->device) {
1497 "device ID correctly read after %d iterations\n", i);
1503 mlx5_core_warn(dev, "could not read device ID\n");
1505 for (i = 0; i < niter; i++) {
1506 count = ioread32be(health->health_counter);
1507 if (count && count != 0xffffffff) {
1509 "Counter value 0x%x after %d iterations\n", count, i);
1516 mlx5_core_warn(dev, "could not read device ID\n");
1519 static void mlx5_pci_resume(struct pci_dev *pdev)
1521 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1522 struct mlx5_priv *priv = &dev->priv;
1525 mlx5_core_info(dev,"%s was called\n", __func__);
1529 err = mlx5_load_one(dev, priv, false);
1532 "mlx5_load_one failed with error code: %d\n" ,err);
1534 mlx5_core_info(dev,"device recovered\n");
1537 static const struct pci_error_handlers mlx5_err_handler = {
1538 .error_detected = mlx5_pci_err_detected,
1539 .slot_reset = mlx5_pci_slot_reset,
1540 .resume = mlx5_pci_resume
1543 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1545 bool fast_teardown, force_teardown;
1548 if (!mlx5_fast_unload_enabled) {
1549 mlx5_core_dbg(dev, "fast unload is disabled by user\n");
1553 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
1554 force_teardown = MLX5_CAP_GEN(dev, force_teardown);
1556 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
1557 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
1559 if (!fast_teardown && !force_teardown)
1562 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1563 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1567 /* Panic tear down fw command will stop the PCI bus communication
1568 * with the HCA, so the health polll is no longer needed.
1570 mlx5_drain_health_wq(dev);
1571 mlx5_stop_health_poll(dev, false);
1573 err = mlx5_cmd_fast_teardown_hca(dev);
1577 err = mlx5_cmd_force_teardown_hca(dev);
1581 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", err);
1582 mlx5_start_health_poll(dev);
1585 mlx5_enter_error_state(dev, true);
1589 static void mlx5_shutdown_disable_interrupts(struct mlx5_core_dev *mdev)
1591 int nvec = mdev->priv.eq_table.num_comp_vectors + MLX5_EQ_VEC_COMP_BASE;
1594 mdev->priv.disable_irqs = 1;
1596 /* wait for all IRQ handlers to finish processing */
1597 for (x = 0; x != nvec; x++)
1598 synchronize_irq(mdev->priv.msix_arr[x].vector);
1601 static void shutdown_one(struct pci_dev *pdev)
1603 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1604 struct mlx5_priv *priv = &dev->priv;
1607 /* enter polling mode */
1608 mlx5_cmd_use_polling(dev);
1610 set_bit(MLX5_INTERFACE_STATE_TEARDOWN, &dev->intf_state);
1612 /* disable all interrupts */
1613 mlx5_shutdown_disable_interrupts(dev);
1615 err = mlx5_try_fast_unload(dev);
1617 mlx5_unload_one(dev, priv, false);
1618 mlx5_pci_disable_device(dev);
1621 static const struct pci_device_id mlx5_core_pci_table[] = {
1622 { PCI_VDEVICE(MELLANOX, 4113) }, /* Connect-IB */
1623 { PCI_VDEVICE(MELLANOX, 4114) }, /* Connect-IB VF */
1624 { PCI_VDEVICE(MELLANOX, 4115) }, /* ConnectX-4 */
1625 { PCI_VDEVICE(MELLANOX, 4116) }, /* ConnectX-4 VF */
1626 { PCI_VDEVICE(MELLANOX, 4117) }, /* ConnectX-4LX */
1627 { PCI_VDEVICE(MELLANOX, 4118) }, /* ConnectX-4LX VF */
1628 { PCI_VDEVICE(MELLANOX, 4119) }, /* ConnectX-5 */
1629 { PCI_VDEVICE(MELLANOX, 4120) }, /* ConnectX-5 VF */
1630 { PCI_VDEVICE(MELLANOX, 4121) },
1631 { PCI_VDEVICE(MELLANOX, 4122) },
1632 { PCI_VDEVICE(MELLANOX, 4123) },
1633 { PCI_VDEVICE(MELLANOX, 4124) },
1634 { PCI_VDEVICE(MELLANOX, 4125) },
1635 { PCI_VDEVICE(MELLANOX, 4126) },
1636 { PCI_VDEVICE(MELLANOX, 4127) },
1637 { PCI_VDEVICE(MELLANOX, 4128) },
1638 { PCI_VDEVICE(MELLANOX, 4129) },
1639 { PCI_VDEVICE(MELLANOX, 4130) },
1640 { PCI_VDEVICE(MELLANOX, 4131) },
1641 { PCI_VDEVICE(MELLANOX, 4132) },
1642 { PCI_VDEVICE(MELLANOX, 4133) },
1643 { PCI_VDEVICE(MELLANOX, 4134) },
1644 { PCI_VDEVICE(MELLANOX, 4135) },
1645 { PCI_VDEVICE(MELLANOX, 4136) },
1646 { PCI_VDEVICE(MELLANOX, 4137) },
1647 { PCI_VDEVICE(MELLANOX, 4138) },
1648 { PCI_VDEVICE(MELLANOX, 4139) },
1649 { PCI_VDEVICE(MELLANOX, 4140) },
1650 { PCI_VDEVICE(MELLANOX, 4141) },
1651 { PCI_VDEVICE(MELLANOX, 4142) },
1652 { PCI_VDEVICE(MELLANOX, 4143) },
1653 { PCI_VDEVICE(MELLANOX, 4144) },
1657 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1659 void mlx5_disable_device(struct mlx5_core_dev *dev)
1661 mlx5_pci_err_detected(dev->pdev, 0);
1664 void mlx5_recover_device(struct mlx5_core_dev *dev)
1666 mlx5_pci_disable_device(dev);
1667 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
1668 mlx5_pci_resume(dev->pdev);
1671 struct pci_driver mlx5_core_driver = {
1672 .name = DRIVER_NAME,
1673 .id_table = mlx5_core_pci_table,
1674 .shutdown = shutdown_one,
1676 .remove = remove_one,
1677 .err_handler = &mlx5_err_handler
1680 static int __init init(void)
1684 err = pci_register_driver(&mlx5_core_driver);
1688 err = mlx5_ctl_init();
1695 pci_unregister_driver(&mlx5_core_driver);
1701 static void __exit cleanup(void)
1704 pci_unregister_driver(&mlx5_core_driver);
1708 module_exit(cleanup);