2 * Copyright (c) 2013-2019, Mellanox Technologies, Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <linux/kmod.h>
29 #include <linux/module.h>
30 #include <linux/errno.h>
31 #include <linux/pci.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/slab.h>
34 #include <linux/io-mapping.h>
35 #include <linux/interrupt.h>
36 #include <linux/hardirq.h>
37 #include <dev/mlx5/driver.h>
38 #include <dev/mlx5/cq.h>
39 #include <dev/mlx5/qp.h>
40 #include <dev/mlx5/srq.h>
41 #include <linux/delay.h>
42 #include <dev/mlx5/mlx5_ifc.h>
43 #include <dev/mlx5/mlx5_fpga/core.h>
44 #include <dev/mlx5/mlx5_lib/mlx5.h>
45 #include "mlx5_core.h"
48 static const char mlx5_version[] = "Mellanox Core driver "
49 DRIVER_VERSION " (" DRIVER_RELDATE ")";
50 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
51 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
52 MODULE_LICENSE("Dual BSD/GPL");
53 MODULE_DEPEND(mlx5, linuxkpi, 1, 1, 1);
54 MODULE_DEPEND(mlx5, mlxfw, 1, 1, 1);
55 MODULE_DEPEND(mlx5, firmware, 1, 1, 1);
56 MODULE_VERSION(mlx5, 1);
58 SYSCTL_NODE(_hw, OID_AUTO, mlx5, CTLFLAG_RW, 0, "mlx5 hardware controls");
60 int mlx5_core_debug_mask;
61 SYSCTL_INT(_hw_mlx5, OID_AUTO, debug_mask, CTLFLAG_RWTUN,
62 &mlx5_core_debug_mask, 0,
63 "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
65 #define MLX5_DEFAULT_PROF 2
66 static int mlx5_prof_sel = MLX5_DEFAULT_PROF;
67 SYSCTL_INT(_hw_mlx5, OID_AUTO, prof_sel, CTLFLAG_RWTUN,
69 "profile selector. Valid range 0 - 2");
71 static int mlx5_fast_unload_enabled = 1;
72 SYSCTL_INT(_hw_mlx5, OID_AUTO, fast_unload_enabled, CTLFLAG_RWTUN,
73 &mlx5_fast_unload_enabled, 0,
74 "Set to enable fast unload. Clear to disable.");
76 #define NUMA_NO_NODE -1
78 static LIST_HEAD(intf_list);
79 static LIST_HEAD(dev_list);
80 static DEFINE_MUTEX(intf_mutex);
82 struct mlx5_device_context {
83 struct list_head list;
84 struct mlx5_interface *intf;
89 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
90 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
93 static struct mlx5_profile profiles[] = {
98 .mask = MLX5_PROF_MASK_QP_SIZE,
102 .mask = MLX5_PROF_MASK_QP_SIZE |
103 MLX5_PROF_MASK_MR_CACHE,
167 .mask = MLX5_PROF_MASK_QP_SIZE,
172 static int set_dma_caps(struct pci_dev *pdev)
176 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
178 device_printf((&pdev->dev)->bsddev, "WARN: ""Warning: couldn't set 64-bit PCI DMA mask\n");
179 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
181 device_printf((&pdev->dev)->bsddev, "ERR: ""Can't set PCI DMA mask, aborting\n");
186 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
188 device_printf((&pdev->dev)->bsddev, "WARN: ""Warning: couldn't set 64-bit consistent PCI DMA mask\n");
189 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
191 device_printf((&pdev->dev)->bsddev, "ERR: ""Can't set consistent PCI DMA mask, aborting\n");
196 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
200 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
202 struct pci_dev *pdev = dev->pdev;
205 mutex_lock(&dev->pci_status_mutex);
206 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
207 err = pci_enable_device(pdev);
209 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
211 mutex_unlock(&dev->pci_status_mutex);
216 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
218 struct pci_dev *pdev = dev->pdev;
220 mutex_lock(&dev->pci_status_mutex);
221 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
222 pci_disable_device(pdev);
223 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
225 mutex_unlock(&dev->pci_status_mutex);
228 static int request_bar(struct pci_dev *pdev)
232 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
233 device_printf((&pdev->dev)->bsddev, "ERR: ""Missing registers BAR, aborting\n");
237 err = pci_request_regions(pdev, DRIVER_NAME);
239 device_printf((&pdev->dev)->bsddev, "ERR: ""Couldn't get PCI resources, aborting\n");
244 static void release_bar(struct pci_dev *pdev)
246 pci_release_regions(pdev);
249 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
251 struct mlx5_priv *priv = &dev->priv;
252 struct mlx5_eq_table *table = &priv->eq_table;
253 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
254 int limit = dev->msix_eqvec;
255 int nvec = MLX5_EQ_VEC_COMP_BASE;
261 nvec += MLX5_CAP_GEN(dev, num_ports) * num_online_cpus();
263 nvec = min_t(int, nvec, num_eqs);
264 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
267 priv->msix_arr = kzalloc(nvec * sizeof(*priv->msix_arr), GFP_KERNEL);
269 priv->irq_info = kzalloc(nvec * sizeof(*priv->irq_info), GFP_KERNEL);
271 for (i = 0; i < nvec; i++)
272 priv->msix_arr[i].entry = i;
274 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
275 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
279 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
285 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
287 struct mlx5_priv *priv = &dev->priv;
289 pci_disable_msix(dev->pdev);
290 kfree(priv->irq_info);
291 kfree(priv->msix_arr);
294 struct mlx5_reg_host_endianess {
300 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
303 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
304 MLX5_DEV_CAP_FLAG_DCT |
305 MLX5_DEV_CAP_FLAG_DRAIN_SIGERR,
308 static u16 to_fw_pkey_sz(u32 size)
324 printf("mlx5_core: WARN: ""invalid pkey table size %d\n", size);
329 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
330 enum mlx5_cap_type cap_type,
331 enum mlx5_cap_mode cap_mode)
333 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
334 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
335 void *out, *hca_caps;
336 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
339 memset(in, 0, sizeof(in));
340 out = kzalloc(out_sz, GFP_KERNEL);
342 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
343 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
344 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
347 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
348 cap_type, cap_mode, err);
352 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
355 case HCA_CAP_OPMOD_GET_MAX:
356 memcpy(dev->hca_caps_max[cap_type], hca_caps,
357 MLX5_UN_SZ_BYTES(hca_cap_union));
359 case HCA_CAP_OPMOD_GET_CUR:
360 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
361 MLX5_UN_SZ_BYTES(hca_cap_union));
365 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
375 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
379 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
383 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
386 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
388 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0};
390 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
392 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
395 static int handle_hca_cap(struct mlx5_core_dev *dev)
397 void *set_ctx = NULL;
398 struct mlx5_profile *prof = dev->profile;
400 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
403 set_ctx = kzalloc(set_sz, GFP_KERNEL);
405 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
409 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
411 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
412 MLX5_ST_SZ_BYTES(cmd_hca_cap));
414 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
415 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
417 /* we limit the size of the pkey table to 128 entries for now */
418 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
421 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
422 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
425 /* disable cmdif checksum */
426 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
428 /* enable drain sigerr */
429 MLX5_SET(cmd_hca_cap, set_hca_cap, drain_sigerr, 1);
431 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
433 err = set_caps(dev, set_ctx, set_sz);
440 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
444 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
448 if (MLX5_CAP_GEN(dev, atomic)) {
449 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
458 supported_atomic_req_8B_endianess_mode_1);
460 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
463 set_ctx = kzalloc(set_sz, GFP_KERNEL);
467 MLX5_SET(set_hca_cap_in, set_ctx, op_mod,
468 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC << 1);
469 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
471 /* Set requestor to host endianness */
472 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode,
473 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
475 err = set_caps(dev, set_ctx, set_sz);
481 static int set_hca_ctrl(struct mlx5_core_dev *dev)
483 struct mlx5_reg_host_endianess he_in;
484 struct mlx5_reg_host_endianess he_out;
487 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH &&
488 !MLX5_CAP_GEN(dev, roce))
491 memset(&he_in, 0, sizeof(he_in));
492 he_in.he = MLX5_SET_HOST_ENDIANNESS;
493 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
494 &he_out, sizeof(he_out),
495 MLX5_REG_HOST_ENDIANNESS, 0, 1);
499 static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
501 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0};
502 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0};
504 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
505 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
508 static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
510 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0};
511 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0};
513 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
514 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
517 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
519 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0};
520 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0};
524 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
526 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in), query_out, sizeof(query_out));
531 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
532 if (status == MLX5_CMD_STAT_BAD_OP_ERR) {
533 pr_debug("Only ISSI 0 is supported\n");
537 printf("mlx5_core: ERR: ""failed to query ISSI\n");
541 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
543 if (sup_issi & (1 << 1)) {
544 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0};
545 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0};
547 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
548 MLX5_SET(set_issi_in, set_in, current_issi, 1);
550 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in), set_out, sizeof(set_out));
552 printf("mlx5_core: ERR: ""failed to set ISSI=1 err(%d)\n", err);
559 } else if (sup_issi & (1 << 0)) {
567 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn)
569 struct mlx5_eq_table *table = &dev->priv.eq_table;
573 spin_lock(&table->lock);
574 list_for_each_entry(eq, &table->comp_eqs_list, list) {
575 if (eq->index == vector) {
582 spin_unlock(&table->lock);
586 EXPORT_SYMBOL(mlx5_vector2eqn);
588 int mlx5_rename_eq(struct mlx5_core_dev *dev, int eq_ix, char *name)
590 struct mlx5_priv *priv = &dev->priv;
591 struct mlx5_eq_table *table = &priv->eq_table;
595 spin_lock(&table->lock);
596 list_for_each_entry(eq, &table->comp_eqs_list, list) {
597 if (eq->index == eq_ix) {
598 int irq_ix = eq_ix + MLX5_EQ_VEC_COMP_BASE;
600 snprintf(priv->irq_info[irq_ix].name, MLX5_MAX_IRQ_NAME,
601 "%s-%d", name, eq_ix);
607 spin_unlock(&table->lock);
612 static void free_comp_eqs(struct mlx5_core_dev *dev)
614 struct mlx5_eq_table *table = &dev->priv.eq_table;
615 struct mlx5_eq *eq, *n;
617 spin_lock(&table->lock);
618 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
620 spin_unlock(&table->lock);
621 if (mlx5_destroy_unmap_eq(dev, eq))
622 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
625 spin_lock(&table->lock);
627 spin_unlock(&table->lock);
630 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
632 struct mlx5_eq_table *table = &dev->priv.eq_table;
633 char name[MLX5_MAX_IRQ_NAME];
640 INIT_LIST_HEAD(&table->comp_eqs_list);
641 ncomp_vec = table->num_comp_vectors;
642 nent = MLX5_COMP_EQ_SIZE;
643 for (i = 0; i < ncomp_vec; i++) {
644 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
646 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
647 err = mlx5_create_map_eq(dev, eq,
648 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
649 name, &dev->priv.uuari.uars[0]);
654 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
656 spin_lock(&table->lock);
657 list_add_tail(&eq->list, &table->comp_eqs_list);
658 spin_unlock(&table->lock);
668 static int map_bf_area(struct mlx5_core_dev *dev)
670 resource_size_t bf_start = pci_resource_start(dev->pdev, 0);
671 resource_size_t bf_len = pci_resource_len(dev->pdev, 0);
673 dev->priv.bf_mapping = io_mapping_create_wc(bf_start, bf_len);
675 return dev->priv.bf_mapping ? 0 : -ENOMEM;
678 static void unmap_bf_area(struct mlx5_core_dev *dev)
680 if (dev->priv.bf_mapping)
681 io_mapping_free(dev->priv.bf_mapping);
684 static inline int fw_initializing(struct mlx5_core_dev *dev)
686 return ioread32be(&dev->iseg->initializing) >> 31;
689 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
691 u64 end = jiffies + msecs_to_jiffies(max_wait_mili);
694 while (fw_initializing(dev)) {
695 if (time_after(jiffies, end)) {
699 msleep(FW_INIT_WAIT_MS);
705 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
707 struct mlx5_device_context *dev_ctx;
708 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
710 dev_ctx = kzalloc(sizeof(*dev_ctx), GFP_KERNEL);
714 dev_ctx->intf = intf;
715 CURVNET_SET_QUIET(vnet0);
716 dev_ctx->context = intf->add(dev);
719 if (dev_ctx->context) {
720 spin_lock_irq(&priv->ctx_lock);
721 list_add_tail(&dev_ctx->list, &priv->ctx_list);
722 spin_unlock_irq(&priv->ctx_lock);
728 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
730 struct mlx5_device_context *dev_ctx;
731 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
733 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
734 if (dev_ctx->intf == intf) {
735 spin_lock_irq(&priv->ctx_lock);
736 list_del(&dev_ctx->list);
737 spin_unlock_irq(&priv->ctx_lock);
739 intf->remove(dev, dev_ctx->context);
746 mlx5_register_device(struct mlx5_core_dev *dev)
748 struct mlx5_priv *priv = &dev->priv;
749 struct mlx5_interface *intf;
751 mutex_lock(&intf_mutex);
752 list_add_tail(&priv->dev_list, &dev_list);
753 list_for_each_entry(intf, &intf_list, list)
754 mlx5_add_device(intf, priv);
755 mutex_unlock(&intf_mutex);
761 mlx5_unregister_device(struct mlx5_core_dev *dev)
763 struct mlx5_priv *priv = &dev->priv;
764 struct mlx5_interface *intf;
766 mutex_lock(&intf_mutex);
767 list_for_each_entry(intf, &intf_list, list)
768 mlx5_remove_device(intf, priv);
769 list_del(&priv->dev_list);
770 mutex_unlock(&intf_mutex);
773 int mlx5_register_interface(struct mlx5_interface *intf)
775 struct mlx5_priv *priv;
777 if (!intf->add || !intf->remove)
780 mutex_lock(&intf_mutex);
781 list_add_tail(&intf->list, &intf_list);
782 list_for_each_entry(priv, &dev_list, dev_list)
783 mlx5_add_device(intf, priv);
784 mutex_unlock(&intf_mutex);
788 EXPORT_SYMBOL(mlx5_register_interface);
790 void mlx5_unregister_interface(struct mlx5_interface *intf)
792 struct mlx5_priv *priv;
794 mutex_lock(&intf_mutex);
795 list_for_each_entry(priv, &dev_list, dev_list)
796 mlx5_remove_device(intf, priv);
797 list_del(&intf->list);
798 mutex_unlock(&intf_mutex);
800 EXPORT_SYMBOL(mlx5_unregister_interface);
802 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
804 struct mlx5_priv *priv = &mdev->priv;
805 struct mlx5_device_context *dev_ctx;
809 spin_lock_irqsave(&priv->ctx_lock, flags);
811 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
812 if ((dev_ctx->intf->protocol == protocol) &&
813 dev_ctx->intf->get_dev) {
814 result = dev_ctx->intf->get_dev(dev_ctx->context);
818 spin_unlock_irqrestore(&priv->ctx_lock, flags);
822 EXPORT_SYMBOL(mlx5_get_protocol_dev);
825 mlx5_firmware_update(struct mlx5_core_dev *dev)
827 const struct firmware *fw;
830 fw = firmware_get("mlx5fw_mfa");
832 err = mlx5_firmware_flash(dev, fw);
833 firmware_put(fw, FIRMWARE_UNLOAD);
841 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
843 struct pci_dev *pdev = dev->pdev;
846 pci_set_drvdata(dev->pdev, dev);
847 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
848 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
850 mutex_init(&priv->pgdir_mutex);
851 INIT_LIST_HEAD(&priv->pgdir_list);
852 spin_lock_init(&priv->mkey_lock);
854 priv->numa_node = NUMA_NO_NODE;
856 err = mlx5_pci_enable_device(dev);
858 device_printf((&pdev->dev)->bsddev, "ERR: ""Cannot enable PCI device, aborting\n");
862 err = request_bar(pdev);
864 device_printf((&pdev->dev)->bsddev, "ERR: ""error requesting BARs, aborting\n");
868 pci_set_master(pdev);
870 err = set_dma_caps(pdev);
872 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed setting DMA capabilities mask, aborting\n");
876 dev->iseg_base = pci_resource_start(dev->pdev, 0);
877 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
880 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed mapping initialization segment, aborting\n");
887 release_bar(dev->pdev);
889 mlx5_pci_disable_device(dev);
894 static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
897 release_bar(dev->pdev);
898 mlx5_pci_disable_device(dev);
901 static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
903 struct pci_dev *pdev = dev->pdev;
906 err = mlx5_vsc_find_cap(dev);
908 dev_err(&pdev->dev, "Unable to find vendor specific capabilities\n");
910 err = mlx5_query_hca_caps(dev);
912 dev_err(&pdev->dev, "query hca failed\n");
916 err = mlx5_query_board_id(dev);
918 dev_err(&pdev->dev, "query board id failed\n");
922 err = mlx5_eq_init(dev);
924 dev_err(&pdev->dev, "failed to initialize eq\n");
928 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
930 err = mlx5_init_cq_table(dev);
932 dev_err(&pdev->dev, "failed to initialize cq table\n");
936 mlx5_init_qp_table(dev);
937 mlx5_init_srq_table(dev);
938 mlx5_init_mr_table(dev);
940 mlx5_init_reserved_gids(dev);
944 err = mlx5_init_rl_table(dev);
946 dev_err(&pdev->dev, "Failed to init rate limiting\n");
947 goto err_tables_cleanup;
954 mlx5_cleanup_mr_table(dev);
955 mlx5_cleanup_srq_table(dev);
956 mlx5_cleanup_qp_table(dev);
957 mlx5_cleanup_cq_table(dev);
961 mlx5_eq_cleanup(dev);
967 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
970 mlx5_cleanup_rl_table(dev);
972 mlx5_fpga_cleanup(dev);
973 mlx5_cleanup_reserved_gids(dev);
974 mlx5_cleanup_mr_table(dev);
975 mlx5_cleanup_srq_table(dev);
976 mlx5_cleanup_qp_table(dev);
977 mlx5_cleanup_cq_table(dev);
978 mlx5_eq_cleanup(dev);
981 static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
984 struct pci_dev *pdev = dev->pdev;
987 mutex_lock(&dev->intf_state_mutex);
988 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
989 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
994 device_printf((&pdev->dev)->bsddev, "INFO: ""firmware version: %d.%d.%d\n", fw_rev_maj(dev), fw_rev_min(dev), fw_rev_sub(dev));
997 * On load removing any previous indication of internal error,
1000 dev->state = MLX5_DEVICE_STATE_UP;
1002 err = mlx5_cmd_init(dev);
1004 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed initializing command interface, aborting\n");
1008 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
1010 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""Firmware over %d MS in initializing state, aborting\n", FW_INIT_TIMEOUT_MILI);
1011 goto err_cmd_cleanup;
1014 err = mlx5_core_enable_hca(dev);
1016 device_printf((&pdev->dev)->bsddev, "ERR: ""enable hca failed\n");
1017 goto err_cmd_cleanup;
1020 err = mlx5_core_set_issi(dev);
1022 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to set issi\n");
1023 goto err_disable_hca;
1026 err = mlx5_pagealloc_start(dev);
1028 device_printf((&pdev->dev)->bsddev, "ERR: ""mlx5_pagealloc_start failed\n");
1029 goto err_disable_hca;
1032 err = mlx5_satisfy_startup_pages(dev, 1);
1034 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to allocate boot pages\n");
1035 goto err_pagealloc_stop;
1038 err = set_hca_ctrl(dev);
1040 device_printf((&pdev->dev)->bsddev, "ERR: ""set_hca_ctrl failed\n");
1041 goto reclaim_boot_pages;
1044 err = handle_hca_cap(dev);
1046 device_printf((&pdev->dev)->bsddev, "ERR: ""handle_hca_cap failed\n");
1047 goto reclaim_boot_pages;
1050 err = handle_hca_cap_atomic(dev);
1052 device_printf((&pdev->dev)->bsddev, "ERR: ""handle_hca_cap_atomic failed\n");
1053 goto reclaim_boot_pages;
1056 err = mlx5_satisfy_startup_pages(dev, 0);
1058 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to allocate init pages\n");
1059 goto reclaim_boot_pages;
1062 err = mlx5_cmd_init_hca(dev);
1064 device_printf((&pdev->dev)->bsddev, "ERR: ""init hca failed\n");
1065 goto reclaim_boot_pages;
1068 mlx5_start_health_poll(dev);
1070 if (boot && mlx5_init_once(dev, priv)) {
1071 dev_err(&pdev->dev, "sw objs init failed\n");
1075 err = mlx5_enable_msix(dev);
1077 device_printf((&pdev->dev)->bsddev, "ERR: ""enable msix failed\n");
1078 goto err_cleanup_once;
1081 err = mlx5_alloc_uuars(dev, &priv->uuari);
1083 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed allocating uar, aborting\n");
1084 goto err_disable_msix;
1087 err = mlx5_start_eqs(dev);
1089 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to start pages and async EQs\n");
1093 err = alloc_comp_eqs(dev);
1095 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to alloc completion EQs\n");
1099 if (map_bf_area(dev))
1100 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to map blue flame area\n");
1102 err = mlx5_init_fs(dev);
1104 mlx5_core_err(dev, "flow steering init %d\n", err);
1105 goto err_free_comp_eqs;
1108 err = mlx5_fpga_device_start(dev);
1110 dev_err(&pdev->dev, "fpga device start failed %d\n", err);
1111 goto err_fpga_start;
1114 err = mlx5_register_device(dev);
1116 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1120 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1123 mutex_unlock(&dev->intf_state_mutex);
1128 mlx5_cleanup_fs(dev);
1138 mlx5_free_uuars(dev, &priv->uuari);
1141 mlx5_disable_msix(dev);
1145 mlx5_cleanup_once(dev);
1148 mlx5_stop_health_poll(dev, boot);
1149 if (mlx5_cmd_teardown_hca(dev)) {
1150 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""tear_down_hca failed, skip cleanup\n");
1155 mlx5_reclaim_startup_pages(dev);
1158 mlx5_pagealloc_stop(dev);
1161 mlx5_core_disable_hca(dev);
1164 mlx5_cmd_cleanup(dev);
1167 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1168 mutex_unlock(&dev->intf_state_mutex);
1173 static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1179 mlx5_drain_health_recovery(dev);
1181 mutex_lock(&dev->intf_state_mutex);
1182 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1183 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n", __func__);
1185 mlx5_cleanup_once(dev);
1189 mlx5_unregister_device(dev);
1191 mlx5_fpga_device_stop(dev);
1192 mlx5_cleanup_fs(dev);
1194 mlx5_wait_for_reclaim_vfs_pages(dev);
1197 mlx5_free_uuars(dev, &priv->uuari);
1198 mlx5_disable_msix(dev);
1200 mlx5_cleanup_once(dev);
1201 mlx5_stop_health_poll(dev, cleanup);
1202 err = mlx5_cmd_teardown_hca(dev);
1204 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""tear_down_hca failed, skip cleanup\n");
1207 mlx5_pagealloc_stop(dev);
1208 mlx5_reclaim_startup_pages(dev);
1209 mlx5_core_disable_hca(dev);
1210 mlx5_cmd_cleanup(dev);
1213 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1214 mutex_unlock(&dev->intf_state_mutex);
1218 void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
1219 unsigned long param)
1221 struct mlx5_priv *priv = &dev->priv;
1222 struct mlx5_device_context *dev_ctx;
1223 unsigned long flags;
1225 spin_lock_irqsave(&priv->ctx_lock, flags);
1227 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
1228 if (dev_ctx->intf->event)
1229 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
1231 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1234 struct mlx5_core_event_handler {
1235 void (*event)(struct mlx5_core_dev *dev,
1236 enum mlx5_dev_event event,
1240 static int init_one(struct pci_dev *pdev,
1241 const struct pci_device_id *id)
1243 struct mlx5_core_dev *dev;
1244 struct mlx5_priv *priv;
1245 device_t bsddev = pdev->dev.bsddev;
1248 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1251 priv->pci_dev_data = id->driver_data;
1253 if (mlx5_prof_sel < 0 || mlx5_prof_sel >= ARRAY_SIZE(profiles)) {
1254 device_printf(bsddev, "WARN: selected profile out of range, selecting default (%d)\n", MLX5_DEFAULT_PROF);
1255 mlx5_prof_sel = MLX5_DEFAULT_PROF;
1257 dev->profile = &profiles[mlx5_prof_sel];
1259 dev->event = mlx5_core_event;
1262 device_set_desc(bsddev, mlx5_version);
1264 sysctl_ctx_init(&dev->sysctl_ctx);
1265 SYSCTL_ADD_INT(&dev->sysctl_ctx,
1266 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)),
1267 OID_AUTO, "msix_eqvec", CTLFLAG_RDTUN, &dev->msix_eqvec, 0,
1268 "Maximum number of MSIX event queue vectors, if set");
1270 INIT_LIST_HEAD(&priv->ctx_list);
1271 spin_lock_init(&priv->ctx_lock);
1272 mutex_init(&dev->pci_status_mutex);
1273 mutex_init(&dev->intf_state_mutex);
1274 err = mlx5_pci_init(dev, priv);
1276 device_printf(bsddev, "ERR: mlx5_pci_init failed %d\n", err);
1280 err = mlx5_health_init(dev);
1282 device_printf(bsddev, "ERR: mlx5_health_init failed %d\n", err);
1286 mlx5_pagealloc_init(dev);
1288 err = mlx5_load_one(dev, priv, true);
1290 device_printf(bsddev, "ERR: mlx5_load_one failed %d\n", err);
1294 mlx5_fwdump_prep(dev);
1296 mlx5_firmware_update(dev);
1298 pci_save_state(bsddev);
1302 mlx5_pagealloc_cleanup(dev);
1303 mlx5_health_cleanup(dev);
1305 mlx5_pci_close(dev, priv);
1307 sysctl_ctx_free(&dev->sysctl_ctx);
1312 static void remove_one(struct pci_dev *pdev)
1314 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1315 struct mlx5_priv *priv = &dev->priv;
1317 if (mlx5_unload_one(dev, priv, true)) {
1318 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
1319 mlx5_health_cleanup(dev);
1323 mlx5_fwdump_clean(dev);
1324 mlx5_pagealloc_cleanup(dev);
1325 mlx5_health_cleanup(dev);
1326 mlx5_pci_close(dev, priv);
1327 pci_set_drvdata(pdev, NULL);
1328 sysctl_ctx_free(&dev->sysctl_ctx);
1332 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1333 pci_channel_state_t state)
1335 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1336 struct mlx5_priv *priv = &dev->priv;
1338 dev_info(&pdev->dev, "%s was called\n", __func__);
1339 mlx5_enter_error_state(dev, false);
1340 mlx5_unload_one(dev, priv, false);
1343 mlx5_drain_health_wq(dev);
1344 mlx5_pci_disable_device(dev);
1347 return state == pci_channel_io_perm_failure ?
1348 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1351 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1353 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1356 dev_info(&pdev->dev, "%s was called\n", __func__);
1358 err = mlx5_pci_enable_device(dev);
1360 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1362 return PCI_ERS_RESULT_DISCONNECT;
1364 pci_set_master(pdev);
1365 pci_set_powerstate(pdev->dev.bsddev, PCI_POWERSTATE_D0);
1366 pci_restore_state(pdev->dev.bsddev);
1367 pci_save_state(pdev->dev.bsddev);
1369 return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
1372 /* wait for the device to show vital signs. For now we check
1373 * that we can read the device ID and that the health buffer
1374 * shows a non zero value which is different than 0xffffffff
1376 static void wait_vital(struct pci_dev *pdev)
1378 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1379 struct mlx5_core_health *health = &dev->priv.health;
1380 const int niter = 100;
1385 /* Wait for firmware to be ready after reset */
1387 for (i = 0; i < niter; i++) {
1388 if (pci_read_config_word(pdev, 2, &did)) {
1389 dev_warn(&pdev->dev, "failed reading config word\n");
1392 if (did == pdev->device) {
1393 dev_info(&pdev->dev, "device ID correctly read after %d iterations\n", i);
1399 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__);
1401 for (i = 0; i < niter; i++) {
1402 count = ioread32be(health->health_counter);
1403 if (count && count != 0xffffffff) {
1404 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1411 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__);
1414 static void mlx5_pci_resume(struct pci_dev *pdev)
1416 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1417 struct mlx5_priv *priv = &dev->priv;
1420 dev_info(&pdev->dev, "%s was called\n", __func__);
1424 err = mlx5_load_one(dev, priv, false);
1426 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1429 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1432 static const struct pci_error_handlers mlx5_err_handler = {
1433 .error_detected = mlx5_pci_err_detected,
1434 .slot_reset = mlx5_pci_slot_reset,
1435 .resume = mlx5_pci_resume
1438 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1440 bool fast_teardown, force_teardown;
1443 if (!mlx5_fast_unload_enabled) {
1444 mlx5_core_dbg(dev, "fast unload is disabled by user\n");
1448 fast_teardown = MLX5_CAP_GEN(dev, fast_teardown);
1449 force_teardown = MLX5_CAP_GEN(dev, force_teardown);
1451 mlx5_core_dbg(dev, "force teardown firmware support=%d\n", force_teardown);
1452 mlx5_core_dbg(dev, "fast teardown firmware support=%d\n", fast_teardown);
1454 if (!fast_teardown && !force_teardown)
1457 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1458 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1462 /* Panic tear down fw command will stop the PCI bus communication
1463 * with the HCA, so the health polll is no longer needed.
1465 mlx5_drain_health_wq(dev);
1466 mlx5_stop_health_poll(dev, false);
1468 err = mlx5_cmd_fast_teardown_hca(dev);
1472 err = mlx5_cmd_force_teardown_hca(dev);
1476 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", err);
1477 mlx5_start_health_poll(dev);
1480 mlx5_enter_error_state(dev, true);
1484 static void mlx5_disable_interrupts(struct mlx5_core_dev *mdev)
1486 int nvec = mdev->priv.eq_table.num_comp_vectors + MLX5_EQ_VEC_COMP_BASE;
1489 mdev->priv.disable_irqs = 1;
1491 /* wait for all IRQ handlers to finish processing */
1492 for (x = 0; x != nvec; x++)
1493 synchronize_irq(mdev->priv.msix_arr[x].vector);
1496 static void shutdown_one(struct pci_dev *pdev)
1498 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1499 struct mlx5_priv *priv = &dev->priv;
1502 /* enter polling mode */
1503 mlx5_cmd_use_polling(dev);
1505 /* disable all interrupts */
1506 mlx5_disable_interrupts(dev);
1508 err = mlx5_try_fast_unload(dev);
1510 mlx5_unload_one(dev, priv, false);
1511 mlx5_pci_disable_device(dev);
1514 static const struct pci_device_id mlx5_core_pci_table[] = {
1515 { PCI_VDEVICE(MELLANOX, 4113) }, /* Connect-IB */
1516 { PCI_VDEVICE(MELLANOX, 4114) }, /* Connect-IB VF */
1517 { PCI_VDEVICE(MELLANOX, 4115) }, /* ConnectX-4 */
1518 { PCI_VDEVICE(MELLANOX, 4116) }, /* ConnectX-4 VF */
1519 { PCI_VDEVICE(MELLANOX, 4117) }, /* ConnectX-4LX */
1520 { PCI_VDEVICE(MELLANOX, 4118) }, /* ConnectX-4LX VF */
1521 { PCI_VDEVICE(MELLANOX, 4119) }, /* ConnectX-5 */
1522 { PCI_VDEVICE(MELLANOX, 4120) }, /* ConnectX-5 VF */
1523 { PCI_VDEVICE(MELLANOX, 4121) },
1524 { PCI_VDEVICE(MELLANOX, 4122) },
1525 { PCI_VDEVICE(MELLANOX, 4123) },
1526 { PCI_VDEVICE(MELLANOX, 4124) },
1527 { PCI_VDEVICE(MELLANOX, 4125) },
1528 { PCI_VDEVICE(MELLANOX, 4126) },
1529 { PCI_VDEVICE(MELLANOX, 4127) },
1530 { PCI_VDEVICE(MELLANOX, 4128) },
1531 { PCI_VDEVICE(MELLANOX, 4129) },
1532 { PCI_VDEVICE(MELLANOX, 4130) },
1533 { PCI_VDEVICE(MELLANOX, 4131) },
1534 { PCI_VDEVICE(MELLANOX, 4132) },
1535 { PCI_VDEVICE(MELLANOX, 4133) },
1536 { PCI_VDEVICE(MELLANOX, 4134) },
1537 { PCI_VDEVICE(MELLANOX, 4135) },
1538 { PCI_VDEVICE(MELLANOX, 4136) },
1539 { PCI_VDEVICE(MELLANOX, 4137) },
1540 { PCI_VDEVICE(MELLANOX, 4138) },
1541 { PCI_VDEVICE(MELLANOX, 4139) },
1542 { PCI_VDEVICE(MELLANOX, 4140) },
1543 { PCI_VDEVICE(MELLANOX, 4141) },
1544 { PCI_VDEVICE(MELLANOX, 4142) },
1545 { PCI_VDEVICE(MELLANOX, 4143) },
1546 { PCI_VDEVICE(MELLANOX, 4144) },
1550 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1552 void mlx5_disable_device(struct mlx5_core_dev *dev)
1554 mlx5_pci_err_detected(dev->pdev, 0);
1557 void mlx5_recover_device(struct mlx5_core_dev *dev)
1559 mlx5_pci_disable_device(dev);
1560 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
1561 mlx5_pci_resume(dev->pdev);
1564 struct pci_driver mlx5_core_driver = {
1565 .name = DRIVER_NAME,
1566 .id_table = mlx5_core_pci_table,
1567 .shutdown = shutdown_one,
1569 .remove = remove_one,
1570 .err_handler = &mlx5_err_handler
1573 static int __init init(void)
1577 err = pci_register_driver(&mlx5_core_driver);
1581 err = mlx5_fwdump_init();
1588 pci_unregister_driver(&mlx5_core_driver);
1594 static void __exit cleanup(void)
1597 pci_unregister_driver(&mlx5_core_driver);
1601 module_exit(cleanup);