2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #define LINUXKPI_PARAM_PREFIX mlx5_
30 #include <linux/kmod.h>
31 #include <linux/module.h>
32 #include <linux/errno.h>
33 #include <linux/pci.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/slab.h>
36 #include <linux/io-mapping.h>
37 #include <linux/interrupt.h>
38 #include <dev/mlx5/driver.h>
39 #include <dev/mlx5/cq.h>
40 #include <dev/mlx5/qp.h>
41 #include <dev/mlx5/srq.h>
42 #include <linux/delay.h>
43 #include <dev/mlx5/mlx5_ifc.h>
44 #include "mlx5_core.h"
47 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
48 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
49 MODULE_LICENSE("Dual BSD/GPL");
50 #if (__FreeBSD_version >= 1100000)
51 MODULE_DEPEND(mlx5, linuxkpi, 1, 1, 1);
53 MODULE_VERSION(mlx5, 1);
55 int mlx5_core_debug_mask;
56 module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
57 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
59 #define MLX5_DEFAULT_PROF 2
60 static int prof_sel = MLX5_DEFAULT_PROF;
61 module_param_named(prof_sel, prof_sel, int, 0444);
62 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
64 #define NUMA_NO_NODE -1
66 static LIST_HEAD(intf_list);
67 static LIST_HEAD(dev_list);
68 static DEFINE_MUTEX(intf_mutex);
70 struct mlx5_device_context {
71 struct list_head list;
72 struct mlx5_interface *intf;
77 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
78 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
81 static struct mlx5_profile profiles[] = {
86 .mask = MLX5_PROF_MASK_QP_SIZE,
90 .mask = MLX5_PROF_MASK_QP_SIZE |
91 MLX5_PROF_MASK_MR_CACHE,
155 .mask = MLX5_PROF_MASK_QP_SIZE,
160 static int set_dma_caps(struct pci_dev *pdev)
164 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
166 device_printf((&pdev->dev)->bsddev, "WARN: ""Warning: couldn't set 64-bit PCI DMA mask\n");
167 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
169 device_printf((&pdev->dev)->bsddev, "ERR: ""Can't set PCI DMA mask, aborting\n");
174 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
176 device_printf((&pdev->dev)->bsddev, "WARN: ""Warning: couldn't set 64-bit consistent PCI DMA mask\n");
177 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
179 device_printf((&pdev->dev)->bsddev, "ERR: ""Can't set consistent PCI DMA mask, aborting\n");
184 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
188 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
190 struct pci_dev *pdev = dev->pdev;
193 mutex_lock(&dev->pci_status_mutex);
194 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
195 err = pci_enable_device(pdev);
197 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
199 mutex_unlock(&dev->pci_status_mutex);
204 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
206 struct pci_dev *pdev = dev->pdev;
208 mutex_lock(&dev->pci_status_mutex);
209 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
210 pci_disable_device(pdev);
211 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
213 mutex_unlock(&dev->pci_status_mutex);
216 static int request_bar(struct pci_dev *pdev)
220 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
221 device_printf((&pdev->dev)->bsddev, "ERR: ""Missing registers BAR, aborting\n");
225 err = pci_request_regions(pdev, DRIVER_NAME);
227 device_printf((&pdev->dev)->bsddev, "ERR: ""Couldn't get PCI resources, aborting\n");
232 static void release_bar(struct pci_dev *pdev)
234 pci_release_regions(pdev);
237 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
239 struct mlx5_priv *priv = &dev->priv;
240 struct mlx5_eq_table *table = &priv->eq_table;
241 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
242 int limit = dev->msix_eqvec;
243 int nvec = MLX5_EQ_VEC_COMP_BASE;
249 nvec += MLX5_CAP_GEN(dev, num_ports) * num_online_cpus();
251 nvec = min_t(int, nvec, num_eqs);
252 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
255 priv->msix_arr = kzalloc(nvec * sizeof(*priv->msix_arr), GFP_KERNEL);
257 priv->irq_info = kzalloc(nvec * sizeof(*priv->irq_info), GFP_KERNEL);
259 for (i = 0; i < nvec; i++)
260 priv->msix_arr[i].entry = i;
262 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
263 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
267 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
273 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
275 struct mlx5_priv *priv = &dev->priv;
277 pci_disable_msix(dev->pdev);
278 kfree(priv->irq_info);
279 kfree(priv->msix_arr);
282 struct mlx5_reg_host_endianess {
288 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
291 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
292 MLX5_DEV_CAP_FLAG_DCT |
293 MLX5_DEV_CAP_FLAG_DRAIN_SIGERR,
296 static u16 to_fw_pkey_sz(u32 size)
312 printf("mlx5_core: WARN: ""invalid pkey table size %d\n", size);
317 static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
318 enum mlx5_cap_type cap_type,
319 enum mlx5_cap_mode cap_mode)
321 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
322 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
323 void *out, *hca_caps;
324 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
327 memset(in, 0, sizeof(in));
328 out = kzalloc(out_sz, GFP_KERNEL);
330 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
331 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
332 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
335 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
336 cap_type, cap_mode, err);
340 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
343 case HCA_CAP_OPMOD_GET_MAX:
344 memcpy(dev->hca_caps_max[cap_type], hca_caps,
345 MLX5_UN_SZ_BYTES(hca_cap_union));
347 case HCA_CAP_OPMOD_GET_CUR:
348 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
349 MLX5_UN_SZ_BYTES(hca_cap_union));
353 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
363 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
367 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
371 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
374 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
376 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0};
378 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
380 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
383 static int handle_hca_cap(struct mlx5_core_dev *dev)
385 void *set_ctx = NULL;
386 struct mlx5_profile *prof = dev->profile;
388 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
391 set_ctx = kzalloc(set_sz, GFP_KERNEL);
393 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
397 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
399 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
400 MLX5_ST_SZ_BYTES(cmd_hca_cap));
402 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
403 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
405 /* we limit the size of the pkey table to 128 entries for now */
406 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
409 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
410 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
413 /* disable cmdif checksum */
414 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
416 /* enable drain sigerr */
417 MLX5_SET(cmd_hca_cap, set_hca_cap, drain_sigerr, 1);
419 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
421 err = set_caps(dev, set_ctx, set_sz);
428 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
432 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
436 if (MLX5_CAP_GEN(dev, atomic)) {
437 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
446 supported_atomic_req_8B_endianess_mode_1);
448 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
451 set_ctx = kzalloc(set_sz, GFP_KERNEL);
455 MLX5_SET(set_hca_cap_in, set_ctx, op_mod,
456 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC << 1);
457 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
459 /* Set requestor to host endianness */
460 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode,
461 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
463 err = set_caps(dev, set_ctx, set_sz);
469 static int set_hca_ctrl(struct mlx5_core_dev *dev)
471 struct mlx5_reg_host_endianess he_in;
472 struct mlx5_reg_host_endianess he_out;
475 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH &&
476 !MLX5_CAP_GEN(dev, roce))
479 memset(&he_in, 0, sizeof(he_in));
480 he_in.he = MLX5_SET_HOST_ENDIANNESS;
481 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
482 &he_out, sizeof(he_out),
483 MLX5_REG_HOST_ENDIANNESS, 0, 1);
487 static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
489 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0};
490 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0};
492 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
493 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
496 static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
498 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0};
499 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0};
501 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
502 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
505 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
507 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0};
508 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0};
512 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
514 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in), query_out, sizeof(query_out));
519 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
520 if (status == MLX5_CMD_STAT_BAD_OP_ERR) {
521 pr_debug("Only ISSI 0 is supported\n");
525 printf("mlx5_core: ERR: ""failed to query ISSI\n");
529 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
531 if (sup_issi & (1 << 1)) {
532 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0};
533 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0};
535 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
536 MLX5_SET(set_issi_in, set_in, current_issi, 1);
538 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in), set_out, sizeof(set_out));
540 printf("mlx5_core: ERR: ""failed to set ISSI=1 err(%d)\n", err);
547 } else if (sup_issi & (1 << 0)) {
555 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn)
557 struct mlx5_eq_table *table = &dev->priv.eq_table;
561 spin_lock(&table->lock);
562 list_for_each_entry(eq, &table->comp_eqs_list, list) {
563 if (eq->index == vector) {
570 spin_unlock(&table->lock);
574 EXPORT_SYMBOL(mlx5_vector2eqn);
576 int mlx5_rename_eq(struct mlx5_core_dev *dev, int eq_ix, char *name)
578 struct mlx5_priv *priv = &dev->priv;
579 struct mlx5_eq_table *table = &priv->eq_table;
583 spin_lock(&table->lock);
584 list_for_each_entry(eq, &table->comp_eqs_list, list) {
585 if (eq->index == eq_ix) {
586 int irq_ix = eq_ix + MLX5_EQ_VEC_COMP_BASE;
588 snprintf(priv->irq_info[irq_ix].name, MLX5_MAX_IRQ_NAME,
589 "%s-%d", name, eq_ix);
595 spin_unlock(&table->lock);
600 static void free_comp_eqs(struct mlx5_core_dev *dev)
602 struct mlx5_eq_table *table = &dev->priv.eq_table;
603 struct mlx5_eq *eq, *n;
605 spin_lock(&table->lock);
606 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
608 spin_unlock(&table->lock);
609 if (mlx5_destroy_unmap_eq(dev, eq))
610 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
613 spin_lock(&table->lock);
615 spin_unlock(&table->lock);
618 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
620 struct mlx5_eq_table *table = &dev->priv.eq_table;
621 char name[MLX5_MAX_IRQ_NAME];
628 INIT_LIST_HEAD(&table->comp_eqs_list);
629 ncomp_vec = table->num_comp_vectors;
630 nent = MLX5_COMP_EQ_SIZE;
631 for (i = 0; i < ncomp_vec; i++) {
632 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
634 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
635 err = mlx5_create_map_eq(dev, eq,
636 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
637 name, &dev->priv.uuari.uars[0]);
642 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
644 spin_lock(&table->lock);
645 list_add_tail(&eq->list, &table->comp_eqs_list);
646 spin_unlock(&table->lock);
656 static int map_bf_area(struct mlx5_core_dev *dev)
658 resource_size_t bf_start = pci_resource_start(dev->pdev, 0);
659 resource_size_t bf_len = pci_resource_len(dev->pdev, 0);
661 dev->priv.bf_mapping = io_mapping_create_wc(bf_start, bf_len);
663 return dev->priv.bf_mapping ? 0 : -ENOMEM;
666 static void unmap_bf_area(struct mlx5_core_dev *dev)
668 if (dev->priv.bf_mapping)
669 io_mapping_free(dev->priv.bf_mapping);
672 static inline int fw_initializing(struct mlx5_core_dev *dev)
674 return ioread32be(&dev->iseg->initializing) >> 31;
677 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
679 u64 end = jiffies + msecs_to_jiffies(max_wait_mili);
682 while (fw_initializing(dev)) {
683 if (time_after(jiffies, end)) {
687 msleep(FW_INIT_WAIT_MS);
693 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
695 struct mlx5_device_context *dev_ctx;
696 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
698 dev_ctx = kzalloc(sizeof(*dev_ctx), GFP_KERNEL);
702 dev_ctx->intf = intf;
703 CURVNET_SET_QUIET(vnet0);
704 dev_ctx->context = intf->add(dev);
707 if (dev_ctx->context) {
708 spin_lock_irq(&priv->ctx_lock);
709 list_add_tail(&dev_ctx->list, &priv->ctx_list);
710 spin_unlock_irq(&priv->ctx_lock);
716 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
718 struct mlx5_device_context *dev_ctx;
719 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
721 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
722 if (dev_ctx->intf == intf) {
723 spin_lock_irq(&priv->ctx_lock);
724 list_del(&dev_ctx->list);
725 spin_unlock_irq(&priv->ctx_lock);
727 intf->remove(dev, dev_ctx->context);
733 static int mlx5_register_device(struct mlx5_core_dev *dev)
735 struct mlx5_priv *priv = &dev->priv;
736 struct mlx5_interface *intf;
738 mutex_lock(&intf_mutex);
739 list_add_tail(&priv->dev_list, &dev_list);
740 list_for_each_entry(intf, &intf_list, list)
741 mlx5_add_device(intf, priv);
742 mutex_unlock(&intf_mutex);
747 static void mlx5_unregister_device(struct mlx5_core_dev *dev)
749 struct mlx5_priv *priv = &dev->priv;
750 struct mlx5_interface *intf;
752 mutex_lock(&intf_mutex);
753 list_for_each_entry(intf, &intf_list, list)
754 mlx5_remove_device(intf, priv);
755 list_del(&priv->dev_list);
756 mutex_unlock(&intf_mutex);
759 int mlx5_register_interface(struct mlx5_interface *intf)
761 struct mlx5_priv *priv;
763 if (!intf->add || !intf->remove)
766 mutex_lock(&intf_mutex);
767 list_add_tail(&intf->list, &intf_list);
768 list_for_each_entry(priv, &dev_list, dev_list)
769 mlx5_add_device(intf, priv);
770 mutex_unlock(&intf_mutex);
774 EXPORT_SYMBOL(mlx5_register_interface);
776 void mlx5_unregister_interface(struct mlx5_interface *intf)
778 struct mlx5_priv *priv;
780 mutex_lock(&intf_mutex);
781 list_for_each_entry(priv, &dev_list, dev_list)
782 mlx5_remove_device(intf, priv);
783 list_del(&intf->list);
784 mutex_unlock(&intf_mutex);
786 EXPORT_SYMBOL(mlx5_unregister_interface);
788 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
790 struct mlx5_priv *priv = &mdev->priv;
791 struct mlx5_device_context *dev_ctx;
795 spin_lock_irqsave(&priv->ctx_lock, flags);
797 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
798 if ((dev_ctx->intf->protocol == protocol) &&
799 dev_ctx->intf->get_dev) {
800 result = dev_ctx->intf->get_dev(dev_ctx->context);
804 spin_unlock_irqrestore(&priv->ctx_lock, flags);
808 EXPORT_SYMBOL(mlx5_get_protocol_dev);
810 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
812 struct pci_dev *pdev = dev->pdev;
815 pci_set_drvdata(dev->pdev, dev);
816 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
817 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
819 mutex_init(&priv->pgdir_mutex);
820 INIT_LIST_HEAD(&priv->pgdir_list);
821 spin_lock_init(&priv->mkey_lock);
823 priv->numa_node = NUMA_NO_NODE;
825 err = mlx5_pci_enable_device(dev);
827 device_printf((&pdev->dev)->bsddev, "ERR: ""Cannot enable PCI device, aborting\n");
831 err = request_bar(pdev);
833 device_printf((&pdev->dev)->bsddev, "ERR: ""error requesting BARs, aborting\n");
837 pci_set_master(pdev);
839 err = set_dma_caps(pdev);
841 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed setting DMA capabilities mask, aborting\n");
845 dev->iseg_base = pci_resource_start(dev->pdev, 0);
846 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
849 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed mapping initialization segment, aborting\n");
856 pci_clear_master(dev->pdev);
857 release_bar(dev->pdev);
859 mlx5_pci_disable_device(dev);
864 static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
867 pci_clear_master(dev->pdev);
868 release_bar(dev->pdev);
869 mlx5_pci_disable_device(dev);
872 static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
874 struct pci_dev *pdev = dev->pdev;
877 err = mlx5_vsc_find_cap(dev);
879 dev_err(&pdev->dev, "Unable to find vendor specific capabilities\n");
881 err = mlx5_query_hca_caps(dev);
883 dev_err(&pdev->dev, "query hca failed\n");
887 err = mlx5_query_board_id(dev);
889 dev_err(&pdev->dev, "query board id failed\n");
893 err = mlx5_eq_init(dev);
895 dev_err(&pdev->dev, "failed to initialize eq\n");
899 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
901 err = mlx5_init_cq_table(dev);
903 dev_err(&pdev->dev, "failed to initialize cq table\n");
907 mlx5_init_qp_table(dev);
908 mlx5_init_srq_table(dev);
909 mlx5_init_mr_table(dev);
912 err = mlx5_init_rl_table(dev);
914 dev_err(&pdev->dev, "Failed to init rate limiting\n");
915 goto err_tables_cleanup;
922 mlx5_cleanup_mr_table(dev);
923 mlx5_cleanup_srq_table(dev);
924 mlx5_cleanup_qp_table(dev);
925 mlx5_cleanup_cq_table(dev);
929 mlx5_eq_cleanup(dev);
935 static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
938 mlx5_cleanup_rl_table(dev);
940 mlx5_cleanup_mr_table(dev);
941 mlx5_cleanup_srq_table(dev);
942 mlx5_cleanup_qp_table(dev);
943 mlx5_cleanup_cq_table(dev);
944 mlx5_eq_cleanup(dev);
947 static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
950 struct pci_dev *pdev = dev->pdev;
953 mutex_lock(&dev->intf_state_mutex);
954 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
955 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
960 device_printf((&pdev->dev)->bsddev, "INFO: ""firmware version: %d.%d.%d\n", fw_rev_maj(dev), fw_rev_min(dev), fw_rev_sub(dev));
963 * On load removing any previous indication of internal error,
966 dev->state = MLX5_DEVICE_STATE_UP;
968 err = mlx5_cmd_init(dev);
970 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed initializing command interface, aborting\n");
974 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
976 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""Firmware over %d MS in initializing state, aborting\n", FW_INIT_TIMEOUT_MILI);
977 goto err_cmd_cleanup;
980 err = mlx5_core_enable_hca(dev);
982 device_printf((&pdev->dev)->bsddev, "ERR: ""enable hca failed\n");
983 goto err_cmd_cleanup;
986 err = mlx5_core_set_issi(dev);
988 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to set issi\n");
989 goto err_disable_hca;
992 err = mlx5_pagealloc_start(dev);
994 device_printf((&pdev->dev)->bsddev, "ERR: ""mlx5_pagealloc_start failed\n");
995 goto err_disable_hca;
998 err = mlx5_satisfy_startup_pages(dev, 1);
1000 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to allocate boot pages\n");
1001 goto err_pagealloc_stop;
1004 err = set_hca_ctrl(dev);
1006 device_printf((&pdev->dev)->bsddev, "ERR: ""set_hca_ctrl failed\n");
1007 goto reclaim_boot_pages;
1010 err = handle_hca_cap(dev);
1012 device_printf((&pdev->dev)->bsddev, "ERR: ""handle_hca_cap failed\n");
1013 goto reclaim_boot_pages;
1016 err = handle_hca_cap_atomic(dev);
1018 device_printf((&pdev->dev)->bsddev, "ERR: ""handle_hca_cap_atomic failed\n");
1019 goto reclaim_boot_pages;
1022 err = mlx5_satisfy_startup_pages(dev, 0);
1024 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to allocate init pages\n");
1025 goto reclaim_boot_pages;
1028 err = mlx5_cmd_init_hca(dev);
1030 device_printf((&pdev->dev)->bsddev, "ERR: ""init hca failed\n");
1031 goto reclaim_boot_pages;
1034 mlx5_start_health_poll(dev);
1036 if (boot && mlx5_init_once(dev, priv)) {
1037 dev_err(&pdev->dev, "sw objs init failed\n");
1041 err = mlx5_enable_msix(dev);
1043 device_printf((&pdev->dev)->bsddev, "ERR: ""enable msix failed\n");
1044 goto err_cleanup_once;
1047 err = mlx5_alloc_uuars(dev, &priv->uuari);
1049 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed allocating uar, aborting\n");
1050 goto err_disable_msix;
1053 err = mlx5_start_eqs(dev);
1055 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to start pages and async EQs\n");
1059 err = alloc_comp_eqs(dev);
1061 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to alloc completion EQs\n");
1065 if (map_bf_area(dev))
1066 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to map blue flame area\n");
1068 err = mlx5_init_fs(dev);
1070 mlx5_core_err(dev, "flow steering init %d\n", err);
1071 goto err_free_comp_eqs;
1074 err = mlx5_register_device(dev);
1076 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1080 clear_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state);
1081 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1084 mutex_unlock(&dev->intf_state_mutex);
1088 mlx5_cleanup_fs(dev);
1098 mlx5_free_uuars(dev, &priv->uuari);
1101 mlx5_disable_msix(dev);
1105 mlx5_cleanup_once(dev);
1108 mlx5_stop_health_poll(dev);
1109 if (mlx5_cmd_teardown_hca(dev)) {
1110 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""tear_down_hca failed, skip cleanup\n");
1115 mlx5_reclaim_startup_pages(dev);
1118 mlx5_pagealloc_stop(dev);
1121 mlx5_core_disable_hca(dev);
1124 mlx5_cmd_cleanup(dev);
1127 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1128 mutex_unlock(&dev->intf_state_mutex);
1133 static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1139 mlx5_drain_health_recovery(dev);
1141 mutex_lock(&dev->intf_state_mutex);
1142 if (test_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state)) {
1143 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n", __func__);
1145 mlx5_cleanup_once(dev);
1149 mlx5_unregister_device(dev);
1151 mlx5_cleanup_fs(dev);
1153 mlx5_wait_for_reclaim_vfs_pages(dev);
1156 mlx5_free_uuars(dev, &priv->uuari);
1157 mlx5_disable_msix(dev);
1159 mlx5_cleanup_once(dev);
1160 mlx5_stop_health_poll(dev);
1161 err = mlx5_cmd_teardown_hca(dev);
1163 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""tear_down_hca failed, skip cleanup\n");
1166 mlx5_pagealloc_stop(dev);
1167 mlx5_reclaim_startup_pages(dev);
1168 mlx5_core_disable_hca(dev);
1169 mlx5_cmd_cleanup(dev);
1172 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1173 set_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state);
1174 mutex_unlock(&dev->intf_state_mutex);
1178 void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
1179 unsigned long param)
1181 struct mlx5_priv *priv = &dev->priv;
1182 struct mlx5_device_context *dev_ctx;
1183 unsigned long flags;
1185 spin_lock_irqsave(&priv->ctx_lock, flags);
1187 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
1188 if (dev_ctx->intf->event)
1189 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
1191 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1194 struct mlx5_core_event_handler {
1195 void (*event)(struct mlx5_core_dev *dev,
1196 enum mlx5_dev_event event,
1200 static int init_one(struct pci_dev *pdev,
1201 const struct pci_device_id *id)
1203 struct mlx5_core_dev *dev;
1204 struct mlx5_priv *priv;
1205 device_t bsddev = pdev->dev.bsddev;
1208 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1211 priv->pci_dev_data = id->driver_data;
1213 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profiles)) {
1214 device_printf(bsddev, "WARN: selected profile out of range, selecting default (%d)\n", MLX5_DEFAULT_PROF);
1215 prof_sel = MLX5_DEFAULT_PROF;
1217 dev->profile = &profiles[prof_sel];
1219 dev->event = mlx5_core_event;
1221 sysctl_ctx_init(&dev->sysctl_ctx);
1222 SYSCTL_ADD_INT(&dev->sysctl_ctx,
1223 SYSCTL_CHILDREN(device_get_sysctl_tree(bsddev)),
1224 OID_AUTO, "msix_eqvec", CTLFLAG_RDTUN, &dev->msix_eqvec, 0,
1225 "Maximum number of MSIX event queue vectors, if set");
1227 INIT_LIST_HEAD(&priv->ctx_list);
1228 spin_lock_init(&priv->ctx_lock);
1229 mutex_init(&dev->pci_status_mutex);
1230 mutex_init(&dev->intf_state_mutex);
1231 err = mlx5_pci_init(dev, priv);
1233 device_printf(bsddev, "ERR: mlx5_pci_init failed %d\n", err);
1237 err = mlx5_health_init(dev);
1239 device_printf(bsddev, "ERR: mlx5_health_init failed %d\n", err);
1243 mlx5_pagealloc_init(dev);
1245 err = mlx5_load_one(dev, priv, true);
1247 device_printf(bsddev, "ERR: mlx5_load_one failed %d\n", err);
1251 mlx5_fwdump_prep(dev);
1253 pci_save_state(bsddev);
1257 mlx5_pagealloc_cleanup(dev);
1258 mlx5_health_cleanup(dev);
1260 mlx5_pci_close(dev, priv);
1262 sysctl_ctx_free(&dev->sysctl_ctx);
1267 static void remove_one(struct pci_dev *pdev)
1269 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1270 struct mlx5_priv *priv = &dev->priv;
1272 if (mlx5_unload_one(dev, priv, true)) {
1273 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
1274 mlx5_health_cleanup(dev);
1278 mlx5_fwdump_clean(dev);
1279 mlx5_pagealloc_cleanup(dev);
1280 mlx5_health_cleanup(dev);
1281 mlx5_pci_close(dev, priv);
1282 pci_set_drvdata(pdev, NULL);
1283 sysctl_ctx_free(&dev->sysctl_ctx);
1287 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1288 pci_channel_state_t state)
1290 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1291 struct mlx5_priv *priv = &dev->priv;
1293 dev_info(&pdev->dev, "%s was called\n", __func__);
1294 mlx5_enter_error_state(dev, false);
1295 mlx5_unload_one(dev, priv, false);
1298 mlx5_drain_health_wq(dev);
1299 mlx5_pci_disable_device(dev);
1302 return state == pci_channel_io_perm_failure ?
1303 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1306 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1308 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1311 dev_info(&pdev->dev, "%s was called\n", __func__);
1313 err = mlx5_pci_enable_device(dev);
1315 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1317 return PCI_ERS_RESULT_DISCONNECT;
1319 pci_set_master(pdev);
1320 pci_set_powerstate(pdev->dev.bsddev, PCI_POWERSTATE_D0);
1321 pci_restore_state(pdev->dev.bsddev);
1322 pci_save_state(pdev->dev.bsddev);
1324 return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
1327 /* wait for the device to show vital signs. For now we check
1328 * that we can read the device ID and that the health buffer
1329 * shows a non zero value which is different than 0xffffffff
1331 static void wait_vital(struct pci_dev *pdev)
1333 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1334 struct mlx5_core_health *health = &dev->priv.health;
1335 const int niter = 100;
1340 /* Wait for firmware to be ready after reset */
1342 for (i = 0; i < niter; i++) {
1343 if (pci_read_config_word(pdev, 2, &did)) {
1344 dev_warn(&pdev->dev, "failed reading config word\n");
1347 if (did == pdev->device) {
1348 dev_info(&pdev->dev, "device ID correctly read after %d iterations\n", i);
1354 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__);
1356 for (i = 0; i < niter; i++) {
1357 count = ioread32be(health->health_counter);
1358 if (count && count != 0xffffffff) {
1359 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1366 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__);
1369 static void mlx5_pci_resume(struct pci_dev *pdev)
1371 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1372 struct mlx5_priv *priv = &dev->priv;
1375 dev_info(&pdev->dev, "%s was called\n", __func__);
1379 err = mlx5_load_one(dev, priv, false);
1381 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1384 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1387 static const struct pci_error_handlers mlx5_err_handler = {
1388 .error_detected = mlx5_pci_err_detected,
1389 .slot_reset = mlx5_pci_slot_reset,
1390 .resume = mlx5_pci_resume
1393 static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1397 if (!MLX5_CAP_GEN(dev, force_teardown)) {
1398 mlx5_core_dbg(dev, "force teardown is not supported in the firmware\n");
1402 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1403 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1407 err = mlx5_cmd_force_teardown_hca(dev);
1409 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", err);
1413 mlx5_enter_error_state(dev, true);
1418 static void shutdown_one(struct pci_dev *pdev)
1420 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1421 struct mlx5_priv *priv = &dev->priv;
1424 set_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &dev->intf_state);
1425 err = mlx5_try_fast_unload(dev);
1427 mlx5_unload_one(dev, priv, false);
1428 mlx5_pci_disable_device(dev);
1431 static const struct pci_device_id mlx5_core_pci_table[] = {
1432 { PCI_VDEVICE(MELLANOX, 4113) }, /* Connect-IB */
1433 { PCI_VDEVICE(MELLANOX, 4114) }, /* Connect-IB VF */
1434 { PCI_VDEVICE(MELLANOX, 4115) }, /* ConnectX-4 */
1435 { PCI_VDEVICE(MELLANOX, 4116) }, /* ConnectX-4 VF */
1436 { PCI_VDEVICE(MELLANOX, 4117) }, /* ConnectX-4LX */
1437 { PCI_VDEVICE(MELLANOX, 4118) }, /* ConnectX-4LX VF */
1438 { PCI_VDEVICE(MELLANOX, 4119) }, /* ConnectX-5 */
1439 { PCI_VDEVICE(MELLANOX, 4120) }, /* ConnectX-5 VF */
1440 { PCI_VDEVICE(MELLANOX, 4121) },
1441 { PCI_VDEVICE(MELLANOX, 4122) },
1442 { PCI_VDEVICE(MELLANOX, 4123) },
1443 { PCI_VDEVICE(MELLANOX, 4124) },
1444 { PCI_VDEVICE(MELLANOX, 4125) },
1445 { PCI_VDEVICE(MELLANOX, 4126) },
1446 { PCI_VDEVICE(MELLANOX, 4127) },
1447 { PCI_VDEVICE(MELLANOX, 4128) },
1448 { PCI_VDEVICE(MELLANOX, 4129) },
1449 { PCI_VDEVICE(MELLANOX, 4130) },
1450 { PCI_VDEVICE(MELLANOX, 4131) },
1451 { PCI_VDEVICE(MELLANOX, 4132) },
1452 { PCI_VDEVICE(MELLANOX, 4133) },
1453 { PCI_VDEVICE(MELLANOX, 4134) },
1454 { PCI_VDEVICE(MELLANOX, 4135) },
1455 { PCI_VDEVICE(MELLANOX, 4136) },
1456 { PCI_VDEVICE(MELLANOX, 4137) },
1457 { PCI_VDEVICE(MELLANOX, 4138) },
1458 { PCI_VDEVICE(MELLANOX, 4139) },
1459 { PCI_VDEVICE(MELLANOX, 4140) },
1460 { PCI_VDEVICE(MELLANOX, 4141) },
1461 { PCI_VDEVICE(MELLANOX, 4142) },
1462 { PCI_VDEVICE(MELLANOX, 4143) },
1463 { PCI_VDEVICE(MELLANOX, 4144) },
1467 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1469 void mlx5_disable_device(struct mlx5_core_dev *dev)
1471 mlx5_pci_err_detected(dev->pdev, 0);
1474 void mlx5_recover_device(struct mlx5_core_dev *dev)
1476 mlx5_pci_disable_device(dev);
1477 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
1478 mlx5_pci_resume(dev->pdev);
1481 struct pci_driver mlx5_core_driver = {
1482 .name = DRIVER_NAME,
1483 .id_table = mlx5_core_pci_table,
1484 .shutdown = shutdown_one,
1486 .remove = remove_one,
1487 .err_handler = &mlx5_err_handler
1490 static int __init init(void)
1494 err = pci_register_driver(&mlx5_core_driver);
1498 err = mlx5_fwdump_init();
1505 pci_unregister_driver(&mlx5_core_driver);
1511 static void __exit cleanup(void)
1514 pci_unregister_driver(&mlx5_core_driver);
1518 module_exit(cleanup);