2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #define LINUXKPI_PARAM_PREFIX mlx5_
30 #include <linux/kmod.h>
31 #include <linux/module.h>
32 #include <linux/errno.h>
33 #include <linux/pci.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/slab.h>
36 #include <linux/io-mapping.h>
37 #include <linux/interrupt.h>
38 #include <dev/mlx5/driver.h>
39 #include <dev/mlx5/cq.h>
40 #include <dev/mlx5/qp.h>
41 #include <dev/mlx5/srq.h>
42 #include <linux/delay.h>
43 #include <dev/mlx5/mlx5_ifc.h>
44 #include "mlx5_core.h"
47 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
48 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
49 MODULE_LICENSE("Dual BSD/GPL");
50 #if (__FreeBSD_version >= 1100000)
51 MODULE_DEPEND(mlx5, linuxkpi, 1, 1, 1);
53 MODULE_VERSION(mlx5, 1);
55 int mlx5_core_debug_mask;
56 module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
57 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
59 #define MLX5_DEFAULT_PROF 2
60 static int prof_sel = MLX5_DEFAULT_PROF;
61 module_param_named(prof_sel, prof_sel, int, 0444);
62 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
64 #define NUMA_NO_NODE -1
66 static LIST_HEAD(intf_list);
67 static LIST_HEAD(dev_list);
68 static DEFINE_MUTEX(intf_mutex);
70 struct mlx5_device_context {
71 struct list_head list;
72 struct mlx5_interface *intf;
77 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
78 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
81 static struct mlx5_profile profiles[] = {
86 .mask = MLX5_PROF_MASK_QP_SIZE,
90 .mask = MLX5_PROF_MASK_QP_SIZE |
91 MLX5_PROF_MASK_MR_CACHE,
155 .mask = MLX5_PROF_MASK_QP_SIZE,
160 static int set_dma_caps(struct pci_dev *pdev)
164 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
166 device_printf((&pdev->dev)->bsddev, "WARN: ""Warning: couldn't set 64-bit PCI DMA mask\n");
167 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
169 device_printf((&pdev->dev)->bsddev, "ERR: ""Can't set PCI DMA mask, aborting\n");
174 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
176 device_printf((&pdev->dev)->bsddev, "WARN: ""Warning: couldn't set 64-bit consistent PCI DMA mask\n");
177 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
179 device_printf((&pdev->dev)->bsddev, "ERR: ""Can't set consistent PCI DMA mask, aborting\n");
184 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
188 static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
190 struct pci_dev *pdev = dev->pdev;
193 mutex_lock(&dev->pci_status_mutex);
194 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
195 err = pci_enable_device(pdev);
197 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
199 mutex_unlock(&dev->pci_status_mutex);
204 static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
206 struct pci_dev *pdev = dev->pdev;
208 mutex_lock(&dev->pci_status_mutex);
209 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
210 pci_disable_device(pdev);
211 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
213 mutex_unlock(&dev->pci_status_mutex);
216 static int request_bar(struct pci_dev *pdev)
220 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
221 device_printf((&pdev->dev)->bsddev, "ERR: ""Missing registers BAR, aborting\n");
225 err = pci_request_regions(pdev, DRIVER_NAME);
227 device_printf((&pdev->dev)->bsddev, "ERR: ""Couldn't get PCI resources, aborting\n");
232 static void release_bar(struct pci_dev *pdev)
234 pci_release_regions(pdev);
237 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
239 struct mlx5_priv *priv = &dev->priv;
240 struct mlx5_eq_table *table = &priv->eq_table;
241 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
245 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
246 MLX5_EQ_VEC_COMP_BASE;
247 nvec = min_t(int, nvec, num_eqs);
248 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
251 priv->msix_arr = kzalloc(nvec * sizeof(*priv->msix_arr), GFP_KERNEL);
253 priv->irq_info = kzalloc(nvec * sizeof(*priv->irq_info), GFP_KERNEL);
255 for (i = 0; i < nvec; i++)
256 priv->msix_arr[i].entry = i;
258 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
259 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
263 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
269 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
271 struct mlx5_priv *priv = &dev->priv;
273 pci_disable_msix(dev->pdev);
274 kfree(priv->irq_info);
275 kfree(priv->msix_arr);
278 struct mlx5_reg_host_endianess {
284 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
287 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
288 MLX5_DEV_CAP_FLAG_DCT |
289 MLX5_DEV_CAP_FLAG_DRAIN_SIGERR,
292 static u16 to_fw_pkey_sz(u32 size)
308 printf("mlx5_core: WARN: ""invalid pkey table size %d\n", size);
313 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
314 enum mlx5_cap_mode cap_mode)
316 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
317 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
318 void *out, *hca_caps;
319 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
322 memset(in, 0, sizeof(in));
323 out = kzalloc(out_sz, GFP_KERNEL);
325 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
326 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
327 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
331 err = mlx5_cmd_status_to_err_v2(out);
334 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
335 cap_type, cap_mode, err);
339 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
342 case HCA_CAP_OPMOD_GET_MAX:
343 memcpy(dev->hca_caps_max[cap_type], hca_caps,
344 MLX5_UN_SZ_BYTES(hca_cap_union));
346 case HCA_CAP_OPMOD_GET_CUR:
347 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
348 MLX5_UN_SZ_BYTES(hca_cap_union));
352 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
362 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
364 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)];
367 memset(out, 0, sizeof(out));
369 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
370 err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
374 err = mlx5_cmd_status_to_err_v2(out);
379 static int handle_hca_cap(struct mlx5_core_dev *dev)
381 void *set_ctx = NULL;
382 struct mlx5_profile *prof = dev->profile;
384 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
387 set_ctx = kzalloc(set_sz, GFP_KERNEL);
389 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_MAX);
393 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_CUR);
397 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
399 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
400 MLX5_ST_SZ_BYTES(cmd_hca_cap));
402 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
403 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
405 /* we limit the size of the pkey table to 128 entries for now */
406 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
409 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
410 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
413 /* disable cmdif checksum */
414 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
416 /* enable drain sigerr */
417 MLX5_SET(cmd_hca_cap, set_hca_cap, drain_sigerr, 1);
419 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
421 err = set_caps(dev, set_ctx, set_sz);
428 static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
432 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
436 if (MLX5_CAP_GEN(dev, atomic)) {
437 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC,
438 HCA_CAP_OPMOD_GET_MAX);
442 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC,
443 HCA_CAP_OPMOD_GET_CUR);
452 supported_atomic_req_8B_endianess_mode_1);
454 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
457 set_ctx = kzalloc(set_sz, GFP_KERNEL);
461 MLX5_SET(set_hca_cap_in, set_ctx, op_mod,
462 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC << 1);
463 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
465 /* Set requestor to host endianness */
466 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianess_mode,
467 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
469 err = set_caps(dev, set_ctx, set_sz);
475 static int set_hca_ctrl(struct mlx5_core_dev *dev)
477 struct mlx5_reg_host_endianess he_in;
478 struct mlx5_reg_host_endianess he_out;
481 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH &&
482 !MLX5_CAP_GEN(dev, roce))
485 memset(&he_in, 0, sizeof(he_in));
486 he_in.he = MLX5_SET_HOST_ENDIANNESS;
487 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
488 &he_out, sizeof(he_out),
489 MLX5_REG_HOST_ENDIANNESS, 0, 1);
493 static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
495 u32 in[MLX5_ST_SZ_DW(enable_hca_in)];
496 u32 out[MLX5_ST_SZ_DW(enable_hca_out)];
498 memset(in, 0, sizeof(in));
499 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
500 memset(out, 0, sizeof(out));
501 return mlx5_cmd_exec_check_status(dev, in, sizeof(in),
505 static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
507 u32 in[MLX5_ST_SZ_DW(disable_hca_in)];
508 u32 out[MLX5_ST_SZ_DW(disable_hca_out)];
510 memset(in, 0, sizeof(in));
512 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
513 memset(out, 0, sizeof(out));
514 return mlx5_cmd_exec_check_status(dev, in, sizeof(in),
518 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
520 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)];
521 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)];
522 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)];
523 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)];
527 memset(query_in, 0, sizeof(query_in));
528 memset(query_out, 0, sizeof(query_out));
530 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
532 err = mlx5_cmd_exec_check_status(dev, query_in, sizeof(query_in),
533 query_out, sizeof(query_out));
535 if (((struct mlx5_outbox_hdr *)query_out)->status ==
536 MLX5_CMD_STAT_BAD_OP_ERR) {
537 pr_debug("Only ISSI 0 is supported\n");
541 printf("mlx5_core: ERR: ""failed to query ISSI\n");
545 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
547 if (sup_issi & (1 << 1)) {
548 memset(set_in, 0, sizeof(set_in));
549 memset(set_out, 0, sizeof(set_out));
551 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
552 MLX5_SET(set_issi_in, set_in, current_issi, 1);
554 err = mlx5_cmd_exec_check_status(dev, set_in, sizeof(set_in),
555 set_out, sizeof(set_out));
557 printf("mlx5_core: ERR: ""failed to set ISSI=1\n");
564 } else if (sup_issi & (1 << 0)) {
572 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn)
574 struct mlx5_eq_table *table = &dev->priv.eq_table;
578 spin_lock(&table->lock);
579 list_for_each_entry(eq, &table->comp_eqs_list, list) {
580 if (eq->index == vector) {
587 spin_unlock(&table->lock);
591 EXPORT_SYMBOL(mlx5_vector2eqn);
593 int mlx5_rename_eq(struct mlx5_core_dev *dev, int eq_ix, char *name)
595 struct mlx5_priv *priv = &dev->priv;
596 struct mlx5_eq_table *table = &priv->eq_table;
600 spin_lock(&table->lock);
601 list_for_each_entry(eq, &table->comp_eqs_list, list) {
602 if (eq->index == eq_ix) {
603 int irq_ix = eq_ix + MLX5_EQ_VEC_COMP_BASE;
605 snprintf(priv->irq_info[irq_ix].name, MLX5_MAX_IRQ_NAME,
606 "%s-%d", name, eq_ix);
612 spin_unlock(&table->lock);
617 static void free_comp_eqs(struct mlx5_core_dev *dev)
619 struct mlx5_eq_table *table = &dev->priv.eq_table;
620 struct mlx5_eq *eq, *n;
622 spin_lock(&table->lock);
623 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
625 spin_unlock(&table->lock);
626 if (mlx5_destroy_unmap_eq(dev, eq))
627 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
630 spin_lock(&table->lock);
632 spin_unlock(&table->lock);
635 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
637 struct mlx5_eq_table *table = &dev->priv.eq_table;
638 char name[MLX5_MAX_IRQ_NAME];
645 INIT_LIST_HEAD(&table->comp_eqs_list);
646 ncomp_vec = table->num_comp_vectors;
647 nent = MLX5_COMP_EQ_SIZE;
648 for (i = 0; i < ncomp_vec; i++) {
649 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
651 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
652 err = mlx5_create_map_eq(dev, eq,
653 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
654 name, &dev->priv.uuari.uars[0]);
659 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
661 spin_lock(&table->lock);
662 list_add_tail(&eq->list, &table->comp_eqs_list);
663 spin_unlock(&table->lock);
673 static int map_bf_area(struct mlx5_core_dev *dev)
675 resource_size_t bf_start = pci_resource_start(dev->pdev, 0);
676 resource_size_t bf_len = pci_resource_len(dev->pdev, 0);
678 dev->priv.bf_mapping = io_mapping_create_wc(bf_start, bf_len);
680 return dev->priv.bf_mapping ? 0 : -ENOMEM;
683 static void unmap_bf_area(struct mlx5_core_dev *dev)
685 if (dev->priv.bf_mapping)
686 io_mapping_free(dev->priv.bf_mapping);
689 static inline int fw_initializing(struct mlx5_core_dev *dev)
691 return ioread32be(&dev->iseg->initializing) >> 31;
694 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
696 u64 end = jiffies + msecs_to_jiffies(max_wait_mili);
699 while (fw_initializing(dev)) {
700 if (time_after(jiffies, end)) {
704 msleep(FW_INIT_WAIT_MS);
710 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
712 struct mlx5_device_context *dev_ctx;
713 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
715 dev_ctx = kzalloc(sizeof(*dev_ctx), GFP_KERNEL);
719 dev_ctx->intf = intf;
720 CURVNET_SET_QUIET(vnet0);
721 dev_ctx->context = intf->add(dev);
724 if (dev_ctx->context) {
725 spin_lock_irq(&priv->ctx_lock);
726 list_add_tail(&dev_ctx->list, &priv->ctx_list);
727 spin_unlock_irq(&priv->ctx_lock);
733 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
735 struct mlx5_device_context *dev_ctx;
736 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
738 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
739 if (dev_ctx->intf == intf) {
740 spin_lock_irq(&priv->ctx_lock);
741 list_del(&dev_ctx->list);
742 spin_unlock_irq(&priv->ctx_lock);
744 intf->remove(dev, dev_ctx->context);
750 static int mlx5_register_device(struct mlx5_core_dev *dev)
752 struct mlx5_priv *priv = &dev->priv;
753 struct mlx5_interface *intf;
755 mutex_lock(&intf_mutex);
756 list_add_tail(&priv->dev_list, &dev_list);
757 list_for_each_entry(intf, &intf_list, list)
758 mlx5_add_device(intf, priv);
759 mutex_unlock(&intf_mutex);
764 static void mlx5_unregister_device(struct mlx5_core_dev *dev)
766 struct mlx5_priv *priv = &dev->priv;
767 struct mlx5_interface *intf;
769 mutex_lock(&intf_mutex);
770 list_for_each_entry(intf, &intf_list, list)
771 mlx5_remove_device(intf, priv);
772 list_del(&priv->dev_list);
773 mutex_unlock(&intf_mutex);
776 int mlx5_register_interface(struct mlx5_interface *intf)
778 struct mlx5_priv *priv;
780 if (!intf->add || !intf->remove)
783 mutex_lock(&intf_mutex);
784 list_add_tail(&intf->list, &intf_list);
785 list_for_each_entry(priv, &dev_list, dev_list)
786 mlx5_add_device(intf, priv);
787 mutex_unlock(&intf_mutex);
791 EXPORT_SYMBOL(mlx5_register_interface);
793 void mlx5_unregister_interface(struct mlx5_interface *intf)
795 struct mlx5_priv *priv;
797 mutex_lock(&intf_mutex);
798 list_for_each_entry(priv, &dev_list, dev_list)
799 mlx5_remove_device(intf, priv);
800 list_del(&intf->list);
801 mutex_unlock(&intf_mutex);
803 EXPORT_SYMBOL(mlx5_unregister_interface);
805 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
807 struct mlx5_priv *priv = &mdev->priv;
808 struct mlx5_device_context *dev_ctx;
812 spin_lock_irqsave(&priv->ctx_lock, flags);
814 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
815 if ((dev_ctx->intf->protocol == protocol) &&
816 dev_ctx->intf->get_dev) {
817 result = dev_ctx->intf->get_dev(dev_ctx->context);
821 spin_unlock_irqrestore(&priv->ctx_lock, flags);
825 EXPORT_SYMBOL(mlx5_get_protocol_dev);
827 static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
829 struct pci_dev *pdev = dev->pdev;
832 pci_set_drvdata(dev->pdev, dev);
833 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
834 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
836 mutex_init(&priv->pgdir_mutex);
837 INIT_LIST_HEAD(&priv->pgdir_list);
838 spin_lock_init(&priv->mkey_lock);
840 priv->numa_node = NUMA_NO_NODE;
842 err = mlx5_pci_enable_device(dev);
844 device_printf((&pdev->dev)->bsddev, "ERR: ""Cannot enable PCI device, aborting\n");
848 err = request_bar(pdev);
850 device_printf((&pdev->dev)->bsddev, "ERR: ""error requesting BARs, aborting\n");
854 pci_set_master(pdev);
856 err = set_dma_caps(pdev);
858 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed setting DMA capabilities mask, aborting\n");
862 dev->iseg_base = pci_resource_start(dev->pdev, 0);
863 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
866 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed mapping initialization segment, aborting\n");
873 pci_clear_master(dev->pdev);
874 release_bar(dev->pdev);
876 mlx5_pci_disable_device(dev);
881 static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
884 pci_clear_master(dev->pdev);
885 release_bar(dev->pdev);
886 mlx5_pci_disable_device(dev);
889 static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
891 struct pci_dev *pdev = dev->pdev;
894 mutex_lock(&dev->intf_state_mutex);
895 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
896 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
901 device_printf((&pdev->dev)->bsddev, "INFO: ""firmware version: %d.%d.%d\n", fw_rev_maj(dev), fw_rev_min(dev), fw_rev_sub(dev));
904 * On load removing any previous indication of internal error,
907 dev->state = MLX5_DEVICE_STATE_UP;
909 err = mlx5_cmd_init(dev);
911 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed initializing command interface, aborting\n");
915 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
917 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""Firmware over %d MS in initializing state, aborting\n", FW_INIT_TIMEOUT_MILI);
918 goto err_cmd_cleanup;
921 mlx5_pagealloc_init(dev);
923 err = mlx5_core_enable_hca(dev);
925 device_printf((&pdev->dev)->bsddev, "ERR: ""enable hca failed\n");
926 goto err_pagealloc_cleanup;
929 err = mlx5_core_set_issi(dev);
931 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to set issi\n");
932 goto err_disable_hca;
935 err = mlx5_pagealloc_start(dev);
937 device_printf((&pdev->dev)->bsddev, "ERR: ""mlx5_pagealloc_start failed\n");
938 goto err_disable_hca;
941 err = mlx5_satisfy_startup_pages(dev, 1);
943 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to allocate boot pages\n");
944 goto err_pagealloc_stop;
947 err = set_hca_ctrl(dev);
949 device_printf((&pdev->dev)->bsddev, "ERR: ""set_hca_ctrl failed\n");
950 goto reclaim_boot_pages;
953 err = handle_hca_cap(dev);
955 device_printf((&pdev->dev)->bsddev, "ERR: ""handle_hca_cap failed\n");
956 goto reclaim_boot_pages;
959 err = handle_hca_cap_atomic(dev);
961 device_printf((&pdev->dev)->bsddev, "ERR: ""handle_hca_cap_atomic failed\n");
962 goto reclaim_boot_pages;
965 err = mlx5_satisfy_startup_pages(dev, 0);
967 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to allocate init pages\n");
968 goto reclaim_boot_pages;
971 err = mlx5_cmd_init_hca(dev);
973 device_printf((&pdev->dev)->bsddev, "ERR: ""init hca failed\n");
974 goto reclaim_boot_pages;
977 mlx5_start_health_poll(dev);
979 err = mlx5_query_hca_caps(dev);
981 device_printf((&pdev->dev)->bsddev, "ERR: ""query hca failed\n");
985 err = mlx5_query_board_id(dev);
987 device_printf((&pdev->dev)->bsddev, "ERR: ""query board id failed\n");
991 err = mlx5_enable_msix(dev);
993 device_printf((&pdev->dev)->bsddev, "ERR: ""enable msix failed\n");
997 err = mlx5_eq_init(dev);
999 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to initialize eq\n");
1003 err = mlx5_alloc_uuars(dev, &priv->uuari);
1005 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed allocating uar, aborting\n");
1006 goto err_eq_cleanup;
1009 err = mlx5_start_eqs(dev);
1011 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to start pages and async EQs\n");
1015 err = alloc_comp_eqs(dev);
1017 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to alloc completion EQs\n");
1021 if (map_bf_area(dev))
1022 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to map blue flame area\n");
1024 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
1026 mlx5_init_cq_table(dev);
1027 mlx5_init_qp_table(dev);
1028 mlx5_init_srq_table(dev);
1029 mlx5_init_mr_table(dev);
1031 err = mlx5_init_fs(dev);
1033 mlx5_core_err(dev, "flow steering init %d\n", err);
1034 goto err_init_tables;
1037 err = mlx5_register_device(dev);
1039 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1043 clear_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state);
1044 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1047 mutex_unlock(&dev->intf_state_mutex);
1051 mlx5_cleanup_fs(dev);
1053 mlx5_cleanup_mr_table(dev);
1054 mlx5_cleanup_srq_table(dev);
1055 mlx5_cleanup_qp_table(dev);
1056 mlx5_cleanup_cq_table(dev);
1063 mlx5_free_uuars(dev, &priv->uuari);
1066 mlx5_eq_cleanup(dev);
1069 mlx5_disable_msix(dev);
1072 mlx5_stop_health_poll(dev);
1073 if (mlx5_cmd_teardown_hca(dev)) {
1074 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""tear_down_hca failed, skip cleanup\n");
1079 mlx5_reclaim_startup_pages(dev);
1082 mlx5_pagealloc_stop(dev);
1085 mlx5_core_disable_hca(dev);
1087 err_pagealloc_cleanup:
1088 mlx5_pagealloc_cleanup(dev);
1091 mlx5_cmd_cleanup(dev);
1094 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1095 mutex_unlock(&dev->intf_state_mutex);
1100 static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
1104 mutex_lock(&dev->intf_state_mutex);
1105 if (test_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state)) {
1106 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n", __func__);
1110 mlx5_unregister_device(dev);
1112 mlx5_cleanup_fs(dev);
1113 mlx5_cleanup_mr_table(dev);
1114 mlx5_cleanup_srq_table(dev);
1115 mlx5_cleanup_qp_table(dev);
1116 mlx5_cleanup_cq_table(dev);
1118 mlx5_wait_for_reclaim_vfs_pages(dev);
1121 mlx5_free_uuars(dev, &priv->uuari);
1122 mlx5_eq_cleanup(dev);
1123 mlx5_disable_msix(dev);
1124 mlx5_stop_health_poll(dev);
1125 err = mlx5_cmd_teardown_hca(dev);
1127 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""tear_down_hca failed, skip cleanup\n");
1130 mlx5_pagealloc_stop(dev);
1131 mlx5_reclaim_startup_pages(dev);
1132 mlx5_core_disable_hca(dev);
1133 mlx5_pagealloc_cleanup(dev);
1134 mlx5_cmd_cleanup(dev);
1137 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1138 set_bit(MLX5_INTERFACE_STATE_DOWN, &dev->intf_state);
1139 mutex_unlock(&dev->intf_state_mutex);
1143 void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
1144 unsigned long param)
1146 struct mlx5_priv *priv = &dev->priv;
1147 struct mlx5_device_context *dev_ctx;
1148 unsigned long flags;
1150 spin_lock_irqsave(&priv->ctx_lock, flags);
1152 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
1153 if (dev_ctx->intf->event)
1154 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
1156 spin_unlock_irqrestore(&priv->ctx_lock, flags);
1159 struct mlx5_core_event_handler {
1160 void (*event)(struct mlx5_core_dev *dev,
1161 enum mlx5_dev_event event,
1166 static int init_one(struct pci_dev *pdev,
1167 const struct pci_device_id *id)
1169 struct mlx5_core_dev *dev;
1170 struct mlx5_priv *priv;
1173 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1176 priv->pci_dev_data = id->driver_data;
1178 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profiles)) {
1179 printf("mlx5_core: WARN: ""selected profile out of range, selecting default (%d)\n", MLX5_DEFAULT_PROF);
1180 prof_sel = MLX5_DEFAULT_PROF;
1182 dev->profile = &profiles[prof_sel];
1184 dev->event = mlx5_core_event;
1186 INIT_LIST_HEAD(&priv->ctx_list);
1187 spin_lock_init(&priv->ctx_lock);
1188 mutex_init(&dev->pci_status_mutex);
1189 mutex_init(&dev->intf_state_mutex);
1190 err = mlx5_pci_init(dev, priv);
1192 device_printf((&pdev->dev)->bsddev, "ERR: ""mlx5_pci_init failed %d\n", err);
1196 err = mlx5_health_init(dev);
1198 device_printf((&pdev->dev)->bsddev, "ERR: ""mlx5_health_init failed %d\n", err);
1202 err = mlx5_load_one(dev, priv);
1204 device_printf((&pdev->dev)->bsddev, "ERR: ""mlx5_register_device failed %d\n", err);
1212 mlx5_health_cleanup(dev);
1214 mlx5_pci_close(dev, priv);
1220 static void remove_one(struct pci_dev *pdev)
1222 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1223 struct mlx5_priv *priv = &dev->priv;
1225 if (mlx5_unload_one(dev, priv)) {
1226 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
1227 mlx5_health_cleanup(dev);
1231 mlx5_health_cleanup(dev);
1232 mlx5_pci_close(dev, priv);
1233 pci_set_drvdata(pdev, NULL);
1237 static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1238 pci_channel_state_t state)
1240 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1241 struct mlx5_priv *priv = &dev->priv;
1243 dev_info(&pdev->dev, "%s was called\n", __func__);
1244 mlx5_enter_error_state(dev);
1245 mlx5_unload_one(dev, priv);
1247 pci_save_state(pdev->dev.bsddev);
1248 mlx5_drain_health_wq(dev);
1249 mlx5_pci_disable_device(dev);
1252 return state == pci_channel_io_perm_failure ?
1253 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1256 static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1258 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1261 dev_info(&pdev->dev, "%s was called\n", __func__);
1263 err = mlx5_pci_enable_device(dev);
1265 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1267 return PCI_ERS_RESULT_DISCONNECT;
1269 pci_set_master(pdev);
1270 pci_set_powerstate(pdev->dev.bsddev, PCI_POWERSTATE_D0);
1271 pci_restore_state(pdev->dev.bsddev);
1273 return err ? PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_RECOVERED;
1276 void mlx5_disable_device(struct mlx5_core_dev *dev)
1278 mlx5_pci_err_detected(dev->pdev, 0);
1281 /* wait for the device to show vital signs. For now we check
1282 * that we can read the device ID and that the health buffer
1283 * shows a non zero value which is different than 0xffffffff
1285 static void wait_vital(struct pci_dev *pdev)
1287 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1288 struct mlx5_core_health *health = &dev->priv.health;
1289 const int niter = 100;
1294 /* Wait for firmware to be ready after reset */
1296 for (i = 0; i < niter; i++) {
1297 if (pci_read_config_word(pdev, 2, &did)) {
1298 dev_warn(&pdev->dev, "failed reading config word\n");
1301 if (did == pdev->device) {
1302 dev_info(&pdev->dev, "device ID correctly read after %d iterations\n", i);
1308 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__);
1310 for (i = 0; i < niter; i++) {
1311 count = ioread32be(health->health_counter);
1312 if (count && count != 0xffffffff) {
1313 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1320 dev_warn(&pdev->dev, "%s-%d: could not read device ID\n", __func__, __LINE__);
1323 static void mlx5_pci_resume(struct pci_dev *pdev)
1325 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1326 struct mlx5_priv *priv = &dev->priv;
1329 dev_info(&pdev->dev, "%s was called\n", __func__);
1331 pci_save_state(pdev->dev.bsddev);
1334 err = mlx5_load_one(dev, priv);
1336 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1339 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1342 static const struct pci_error_handlers mlx5_err_handler = {
1343 .error_detected = mlx5_pci_err_detected,
1344 .slot_reset = mlx5_pci_slot_reset,
1345 .resume = mlx5_pci_resume
1348 static void shutdown_one(struct pci_dev *pdev)
1350 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1351 struct mlx5_priv *priv = &dev->priv;
1353 set_bit(MLX5_INTERFACE_STATE_SHUTDOWN, &dev->intf_state);
1354 mlx5_unload_one(dev, priv);
1355 mlx5_pci_disable_device(dev);
1358 static const struct pci_device_id mlx5_core_pci_table[] = {
1359 { PCI_VDEVICE(MELLANOX, 4113) }, /* Connect-IB */
1360 { PCI_VDEVICE(MELLANOX, 4114) }, /* Connect-IB VF */
1361 { PCI_VDEVICE(MELLANOX, 4115) }, /* ConnectX-4 */
1362 { PCI_VDEVICE(MELLANOX, 4116) }, /* ConnectX-4 VF */
1363 { PCI_VDEVICE(MELLANOX, 4117) }, /* ConnectX-4LX */
1364 { PCI_VDEVICE(MELLANOX, 4118) }, /* ConnectX-4LX VF */
1365 { PCI_VDEVICE(MELLANOX, 4119) }, /* ConnectX-5 */
1366 { PCI_VDEVICE(MELLANOX, 4120) }, /* ConnectX-5 VF */
1367 { PCI_VDEVICE(MELLANOX, 4121) },
1368 { PCI_VDEVICE(MELLANOX, 4122) },
1369 { PCI_VDEVICE(MELLANOX, 4123) },
1370 { PCI_VDEVICE(MELLANOX, 4124) },
1371 { PCI_VDEVICE(MELLANOX, 4125) },
1372 { PCI_VDEVICE(MELLANOX, 4126) },
1373 { PCI_VDEVICE(MELLANOX, 4127) },
1374 { PCI_VDEVICE(MELLANOX, 4128) },
1375 { PCI_VDEVICE(MELLANOX, 4129) },
1376 { PCI_VDEVICE(MELLANOX, 4130) },
1377 { PCI_VDEVICE(MELLANOX, 4131) },
1378 { PCI_VDEVICE(MELLANOX, 4132) },
1379 { PCI_VDEVICE(MELLANOX, 4133) },
1380 { PCI_VDEVICE(MELLANOX, 4134) },
1381 { PCI_VDEVICE(MELLANOX, 4135) },
1382 { PCI_VDEVICE(MELLANOX, 4136) },
1383 { PCI_VDEVICE(MELLANOX, 4137) },
1384 { PCI_VDEVICE(MELLANOX, 4138) },
1385 { PCI_VDEVICE(MELLANOX, 4139) },
1386 { PCI_VDEVICE(MELLANOX, 4140) },
1387 { PCI_VDEVICE(MELLANOX, 4141) },
1388 { PCI_VDEVICE(MELLANOX, 4142) },
1389 { PCI_VDEVICE(MELLANOX, 4143) },
1390 { PCI_VDEVICE(MELLANOX, 4144) },
1394 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1396 static struct pci_driver mlx5_core_driver = {
1397 .name = DRIVER_NAME,
1398 .id_table = mlx5_core_pci_table,
1399 .shutdown = shutdown_one,
1401 .remove = remove_one,
1402 .err_handler = &mlx5_err_handler
1405 static int __init init(void)
1409 err = pci_register_driver(&mlx5_core_driver);
1420 static void __exit cleanup(void)
1422 pci_unregister_driver(&mlx5_core_driver);
1426 module_exit(cleanup);