2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <linux/kmod.h>
29 #include <linux/module.h>
30 #include <linux/errno.h>
31 #include <linux/pci.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/slab.h>
34 #include <linux/io-mapping.h>
35 #include <linux/interrupt.h>
36 #include <dev/mlx5/driver.h>
37 #include <dev/mlx5/cq.h>
38 #include <dev/mlx5/qp.h>
39 #include <dev/mlx5/srq.h>
40 #include <linux/delay.h>
41 #include <dev/mlx5/mlx5_ifc.h>
42 #include "mlx5_core.h"
44 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
45 MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
46 MODULE_LICENSE("Dual BSD/GPL");
47 #if (__FreeBSD_version >= 1100000)
48 MODULE_DEPEND(mlx5, linuxkpi, 1, 1, 1);
50 MODULE_VERSION(mlx5, 1);
52 int mlx5_core_debug_mask;
53 module_param_named(debug_mask, mlx5_core_debug_mask, int, 0644);
54 MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
56 #define MLX5_DEFAULT_PROF 2
57 static int prof_sel = MLX5_DEFAULT_PROF;
58 module_param_named(prof_sel, prof_sel, int, 0444);
59 MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
61 #define NUMA_NO_NODE -1
63 struct workqueue_struct *mlx5_core_wq;
64 static LIST_HEAD(intf_list);
65 static LIST_HEAD(dev_list);
66 static DEFINE_MUTEX(intf_mutex);
68 struct mlx5_device_context {
69 struct list_head list;
70 struct mlx5_interface *intf;
74 static struct mlx5_profile profiles[] = {
79 .mask = MLX5_PROF_MASK_QP_SIZE,
83 .mask = MLX5_PROF_MASK_QP_SIZE |
84 MLX5_PROF_MASK_MR_CACHE,
152 .mask = MLX5_PROF_MASK_QP_SIZE,
157 static int set_dma_caps(struct pci_dev *pdev)
161 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
163 device_printf((&pdev->dev)->bsddev, "WARN: ""Warning: couldn't set 64-bit PCI DMA mask\n");
164 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
166 device_printf((&pdev->dev)->bsddev, "ERR: ""Can't set PCI DMA mask, aborting\n");
171 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
173 device_printf((&pdev->dev)->bsddev, "WARN: ""Warning: couldn't set 64-bit consistent PCI DMA mask\n");
174 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
176 device_printf((&pdev->dev)->bsddev, "ERR: ""Can't set consistent PCI DMA mask, aborting\n");
181 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
185 static int request_bar(struct pci_dev *pdev)
189 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
190 device_printf((&pdev->dev)->bsddev, "ERR: ""Missing registers BAR, aborting\n");
194 err = pci_request_regions(pdev, DRIVER_NAME);
196 device_printf((&pdev->dev)->bsddev, "ERR: ""Couldn't get PCI resources, aborting\n");
201 static void release_bar(struct pci_dev *pdev)
203 pci_release_regions(pdev);
206 static int mlx5_enable_msix(struct mlx5_core_dev *dev)
208 struct mlx5_priv *priv = &dev->priv;
209 struct mlx5_eq_table *table = &priv->eq_table;
210 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
214 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
215 MLX5_EQ_VEC_COMP_BASE;
216 nvec = min_t(int, nvec, num_eqs);
217 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
220 priv->msix_arr = kzalloc(nvec * sizeof(*priv->msix_arr), GFP_KERNEL);
222 priv->irq_info = kzalloc(nvec * sizeof(*priv->irq_info), GFP_KERNEL);
224 for (i = 0; i < nvec; i++)
225 priv->msix_arr[i].entry = i;
227 nvec = pci_enable_msix_range(dev->pdev, priv->msix_arr,
228 MLX5_EQ_VEC_COMP_BASE + 1, nvec);
232 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
238 static void mlx5_disable_msix(struct mlx5_core_dev *dev)
240 struct mlx5_priv *priv = &dev->priv;
242 pci_disable_msix(dev->pdev);
243 kfree(priv->irq_info);
244 kfree(priv->msix_arr);
247 struct mlx5_reg_host_endianess {
253 #define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
256 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
257 MLX5_DEV_CAP_FLAG_DCT,
260 static u16 to_fw_pkey_sz(u32 size)
276 printf("mlx5_core: WARN: ""invalid pkey table size %d\n", size);
281 int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type,
282 enum mlx5_cap_mode cap_mode)
284 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
285 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
286 void *out, *hca_caps;
287 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
290 memset(in, 0, sizeof(in));
291 out = kzalloc(out_sz, GFP_KERNEL);
293 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
294 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
295 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
299 err = mlx5_cmd_status_to_err_v2(out);
302 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
303 cap_type, cap_mode, err);
307 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
310 case HCA_CAP_OPMOD_GET_MAX:
311 memcpy(dev->hca_caps_max[cap_type], hca_caps,
312 MLX5_UN_SZ_BYTES(hca_cap_union));
314 case HCA_CAP_OPMOD_GET_CUR:
315 memcpy(dev->hca_caps_cur[cap_type], hca_caps,
316 MLX5_UN_SZ_BYTES(hca_cap_union));
320 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
330 static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz)
332 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)];
335 memset(out, 0, sizeof(out));
337 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
338 err = mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
342 err = mlx5_cmd_status_to_err_v2(out);
347 static int handle_hca_cap(struct mlx5_core_dev *dev)
349 void *set_ctx = NULL;
350 struct mlx5_profile *prof = dev->profile;
352 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
355 set_ctx = kzalloc(set_sz, GFP_KERNEL);
357 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_MAX);
361 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL, HCA_CAP_OPMOD_GET_CUR);
365 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
367 memcpy(set_hca_cap, dev->hca_caps_cur[MLX5_CAP_GENERAL],
368 MLX5_ST_SZ_BYTES(cmd_hca_cap));
370 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
371 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
373 /* we limit the size of the pkey table to 128 entries for now */
374 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
377 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
378 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
381 /* disable cmdif checksum */
382 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
384 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
386 err = set_caps(dev, set_ctx, set_sz);
393 static int set_hca_ctrl(struct mlx5_core_dev *dev)
395 struct mlx5_reg_host_endianess he_in;
396 struct mlx5_reg_host_endianess he_out;
399 memset(&he_in, 0, sizeof(he_in));
400 he_in.he = MLX5_SET_HOST_ENDIANNESS;
401 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
402 &he_out, sizeof(he_out),
403 MLX5_REG_HOST_ENDIANNESS, 0, 1);
407 static int mlx5_core_enable_hca(struct mlx5_core_dev *dev)
409 u32 in[MLX5_ST_SZ_DW(enable_hca_in)];
410 u32 out[MLX5_ST_SZ_DW(enable_hca_out)];
412 memset(in, 0, sizeof(in));
413 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
414 memset(out, 0, sizeof(out));
415 return mlx5_cmd_exec_check_status(dev, in, sizeof(in),
419 static int mlx5_core_disable_hca(struct mlx5_core_dev *dev)
421 u32 in[MLX5_ST_SZ_DW(disable_hca_in)];
422 u32 out[MLX5_ST_SZ_DW(disable_hca_out)];
424 memset(in, 0, sizeof(in));
426 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
427 memset(out, 0, sizeof(out));
428 return mlx5_cmd_exec_check_status(dev, in, sizeof(in),
432 static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
434 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)];
435 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)];
436 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)];
437 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)];
441 memset(query_in, 0, sizeof(query_in));
442 memset(query_out, 0, sizeof(query_out));
444 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
446 err = mlx5_cmd_exec_check_status(dev, query_in, sizeof(query_in),
447 query_out, sizeof(query_out));
449 if (((struct mlx5_outbox_hdr *)query_out)->status ==
450 MLX5_CMD_STAT_BAD_OP_ERR) {
451 pr_debug("Only ISSI 0 is supported\n");
455 printf("mlx5_core: ERR: ""failed to query ISSI\n");
459 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
461 if (sup_issi & (1 << 1)) {
462 memset(set_in, 0, sizeof(set_in));
463 memset(set_out, 0, sizeof(set_out));
465 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
466 MLX5_SET(set_issi_in, set_in, current_issi, 1);
468 err = mlx5_cmd_exec_check_status(dev, set_in, sizeof(set_in),
469 set_out, sizeof(set_out));
471 printf("mlx5_core: ERR: ""failed to set ISSI=1\n");
478 } else if (sup_issi & (1 << 0)) {
486 int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn)
488 struct mlx5_eq_table *table = &dev->priv.eq_table;
492 spin_lock(&table->lock);
493 list_for_each_entry(eq, &table->comp_eqs_list, list) {
494 if (eq->index == vector) {
501 spin_unlock(&table->lock);
505 EXPORT_SYMBOL(mlx5_vector2eqn);
507 int mlx5_rename_eq(struct mlx5_core_dev *dev, int eq_ix, char *name)
509 struct mlx5_priv *priv = &dev->priv;
510 struct mlx5_eq_table *table = &priv->eq_table;
514 spin_lock(&table->lock);
515 list_for_each_entry(eq, &table->comp_eqs_list, list) {
516 if (eq->index == eq_ix) {
517 int irq_ix = eq_ix + MLX5_EQ_VEC_COMP_BASE;
519 snprintf(priv->irq_info[irq_ix].name, MLX5_MAX_IRQ_NAME,
520 "%s-%d", name, eq_ix);
526 spin_unlock(&table->lock);
531 static void free_comp_eqs(struct mlx5_core_dev *dev)
533 struct mlx5_eq_table *table = &dev->priv.eq_table;
534 struct mlx5_eq *eq, *n;
536 spin_lock(&table->lock);
537 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
539 spin_unlock(&table->lock);
540 if (mlx5_destroy_unmap_eq(dev, eq))
541 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
544 spin_lock(&table->lock);
546 spin_unlock(&table->lock);
549 static int alloc_comp_eqs(struct mlx5_core_dev *dev)
551 struct mlx5_eq_table *table = &dev->priv.eq_table;
552 char name[MLX5_MAX_IRQ_NAME];
559 INIT_LIST_HEAD(&table->comp_eqs_list);
560 ncomp_vec = table->num_comp_vectors;
561 nent = MLX5_COMP_EQ_SIZE;
562 for (i = 0; i < ncomp_vec; i++) {
563 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
565 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
566 err = mlx5_create_map_eq(dev, eq,
567 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
568 name, &dev->priv.uuari.uars[0]);
573 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
575 spin_lock(&table->lock);
576 list_add_tail(&eq->list, &table->comp_eqs_list);
577 spin_unlock(&table->lock);
587 static int map_bf_area(struct mlx5_core_dev *dev)
589 resource_size_t bf_start = pci_resource_start(dev->pdev, 0);
590 resource_size_t bf_len = pci_resource_len(dev->pdev, 0);
592 dev->priv.bf_mapping = io_mapping_create_wc(bf_start, bf_len);
594 return dev->priv.bf_mapping ? 0 : -ENOMEM;
597 static void unmap_bf_area(struct mlx5_core_dev *dev)
599 if (dev->priv.bf_mapping)
600 io_mapping_free(dev->priv.bf_mapping);
603 static inline int fw_initializing(struct mlx5_core_dev *dev)
605 return ioread32be(&dev->iseg->initializing) >> 31;
608 static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
610 u64 end = jiffies + msecs_to_jiffies(max_wait_mili);
613 while (fw_initializing(dev)) {
614 if (time_after(jiffies, end)) {
618 msleep(FW_INIT_WAIT_MS);
624 static int mlx5_dev_init(struct mlx5_core_dev *dev, struct pci_dev *pdev)
626 struct mlx5_priv *priv = &dev->priv;
630 pci_set_drvdata(dev->pdev, dev);
631 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
632 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
634 mutex_init(&priv->pgdir_mutex);
635 INIT_LIST_HEAD(&priv->pgdir_list);
636 spin_lock_init(&priv->mkey_lock);
638 priv->numa_node = NUMA_NO_NODE;
640 err = pci_enable_device(pdev);
642 device_printf((&pdev->dev)->bsddev, "ERR: ""Cannot enable PCI device, aborting\n");
646 err = request_bar(pdev);
648 device_printf((&pdev->dev)->bsddev, "ERR: ""error requesting BARs, aborting\n");
652 pci_set_master(pdev);
654 err = set_dma_caps(pdev);
656 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed setting DMA capabilities mask, aborting\n");
660 dev->iseg = ioremap(pci_resource_start(dev->pdev, 0),
664 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed mapping initialization segment, aborting\n");
667 device_printf((&pdev->dev)->bsddev, "INFO: ""firmware version: %d.%d.%d\n", fw_rev_maj(dev), fw_rev_min(dev), fw_rev_sub(dev));
669 err = mlx5_cmd_init(dev);
671 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed initializing command interface, aborting\n");
675 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
677 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""Firmware over %d MS in initializing state, aborting\n", FW_INIT_TIMEOUT_MILI);
678 goto err_cmd_cleanup;
681 mlx5_pagealloc_init(dev);
683 err = mlx5_core_enable_hca(dev);
685 device_printf((&pdev->dev)->bsddev, "ERR: ""enable hca failed\n");
686 goto err_pagealloc_cleanup;
689 err = mlx5_core_set_issi(dev);
691 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to set issi\n");
692 goto err_disable_hca;
695 err = mlx5_pagealloc_start(dev);
697 device_printf((&pdev->dev)->bsddev, "ERR: ""mlx5_pagealloc_start failed\n");
698 goto err_disable_hca;
701 err = mlx5_satisfy_startup_pages(dev, 1);
703 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to allocate boot pages\n");
704 goto err_pagealloc_stop;
707 err = set_hca_ctrl(dev);
709 device_printf((&pdev->dev)->bsddev, "ERR: ""set_hca_ctrl failed\n");
710 goto reclaim_boot_pages;
713 err = handle_hca_cap(dev);
715 device_printf((&pdev->dev)->bsddev, "ERR: ""handle_hca_cap failed\n");
716 goto reclaim_boot_pages;
719 err = mlx5_satisfy_startup_pages(dev, 0);
721 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to allocate init pages\n");
722 goto reclaim_boot_pages;
725 err = mlx5_cmd_init_hca(dev);
727 device_printf((&pdev->dev)->bsddev, "ERR: ""init hca failed\n");
728 goto reclaim_boot_pages;
731 mlx5_start_health_poll(dev);
733 err = mlx5_query_hca_caps(dev);
735 device_printf((&pdev->dev)->bsddev, "ERR: ""query hca failed\n");
739 err = mlx5_query_board_id(dev);
741 device_printf((&pdev->dev)->bsddev, "ERR: ""query board id failed\n");
745 err = mlx5_enable_msix(dev);
747 device_printf((&pdev->dev)->bsddev, "ERR: ""enable msix failed\n");
751 err = mlx5_eq_init(dev);
753 device_printf((&pdev->dev)->bsddev, "ERR: ""failed to initialize eq\n");
757 err = mlx5_alloc_uuars(dev, &priv->uuari);
759 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed allocating uar, aborting\n");
763 err = mlx5_start_eqs(dev);
765 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to start pages and async EQs\n");
769 err = alloc_comp_eqs(dev);
771 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to alloc completion EQs\n");
775 if (map_bf_area(dev))
776 device_printf((&pdev->dev)->bsddev, "ERR: ""Failed to map blue flame area\n");
778 MLX5_INIT_DOORBELL_LOCK(&priv->cq_uar_lock);
780 mlx5_init_cq_table(dev);
781 mlx5_init_qp_table(dev);
782 mlx5_init_srq_table(dev);
783 mlx5_init_mr_table(dev);
791 mlx5_free_uuars(dev, &priv->uuari);
794 mlx5_eq_cleanup(dev);
797 mlx5_disable_msix(dev);
800 mlx5_stop_health_poll(dev);
801 if (mlx5_cmd_teardown_hca(dev)) {
802 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""tear_down_hca failed, skip cleanup\n");
807 mlx5_reclaim_startup_pages(dev);
810 mlx5_pagealloc_stop(dev);
813 mlx5_core_disable_hca(dev);
815 err_pagealloc_cleanup:
816 mlx5_pagealloc_cleanup(dev);
818 mlx5_cmd_cleanup(dev);
824 pci_clear_master(dev->pdev);
825 release_bar(dev->pdev);
828 pci_disable_device(dev->pdev);
834 static void mlx5_dev_cleanup(struct mlx5_core_dev *dev)
836 struct mlx5_priv *priv = &dev->priv;
838 mlx5_cleanup_mr_table(dev);
839 mlx5_cleanup_srq_table(dev);
840 mlx5_cleanup_qp_table(dev);
841 mlx5_cleanup_cq_table(dev);
845 mlx5_free_uuars(dev, &priv->uuari);
846 mlx5_eq_cleanup(dev);
847 mlx5_disable_msix(dev);
848 mlx5_stop_health_poll(dev);
849 if (mlx5_cmd_teardown_hca(dev)) {
850 device_printf((&dev->pdev->dev)->bsddev, "ERR: ""tear_down_hca failed, skip cleanup\n");
853 mlx5_pagealloc_stop(dev);
854 mlx5_reclaim_startup_pages(dev);
855 mlx5_core_disable_hca(dev);
856 mlx5_pagealloc_cleanup(dev);
857 mlx5_cmd_cleanup(dev);
859 pci_clear_master(dev->pdev);
860 release_bar(dev->pdev);
861 pci_disable_device(dev->pdev);
864 static void mlx5_add_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
866 struct mlx5_device_context *dev_ctx;
867 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
869 dev_ctx = kmalloc(sizeof(*dev_ctx), GFP_KERNEL);
871 dev_ctx->intf = intf;
872 dev_ctx->context = intf->add(dev);
874 if (dev_ctx->context) {
875 spin_lock_irq(&priv->ctx_lock);
876 list_add_tail(&dev_ctx->list, &priv->ctx_list);
877 spin_unlock_irq(&priv->ctx_lock);
883 static void mlx5_remove_device(struct mlx5_interface *intf, struct mlx5_priv *priv)
885 struct mlx5_device_context *dev_ctx;
886 struct mlx5_core_dev *dev = container_of(priv, struct mlx5_core_dev, priv);
888 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
889 if (dev_ctx->intf == intf) {
890 spin_lock_irq(&priv->ctx_lock);
891 list_del(&dev_ctx->list);
892 spin_unlock_irq(&priv->ctx_lock);
894 intf->remove(dev, dev_ctx->context);
899 static int mlx5_register_device(struct mlx5_core_dev *dev)
901 struct mlx5_priv *priv = &dev->priv;
902 struct mlx5_interface *intf;
904 mutex_lock(&intf_mutex);
905 list_add_tail(&priv->dev_list, &dev_list);
906 list_for_each_entry(intf, &intf_list, list)
907 mlx5_add_device(intf, priv);
908 mutex_unlock(&intf_mutex);
912 static void mlx5_unregister_device(struct mlx5_core_dev *dev)
914 struct mlx5_priv *priv = &dev->priv;
915 struct mlx5_interface *intf;
917 mutex_lock(&intf_mutex);
918 list_for_each_entry(intf, &intf_list, list)
919 mlx5_remove_device(intf, priv);
920 list_del(&priv->dev_list);
921 mutex_unlock(&intf_mutex);
924 int mlx5_register_interface(struct mlx5_interface *intf)
926 struct mlx5_priv *priv;
928 if (!intf->add || !intf->remove)
931 mutex_lock(&intf_mutex);
932 list_add_tail(&intf->list, &intf_list);
933 list_for_each_entry(priv, &dev_list, dev_list)
934 mlx5_add_device(intf, priv);
935 mutex_unlock(&intf_mutex);
939 EXPORT_SYMBOL(mlx5_register_interface);
941 void mlx5_unregister_interface(struct mlx5_interface *intf)
943 struct mlx5_priv *priv;
945 mutex_lock(&intf_mutex);
946 list_for_each_entry(priv, &dev_list, dev_list)
947 mlx5_remove_device(intf, priv);
948 list_del(&intf->list);
949 mutex_unlock(&intf_mutex);
951 EXPORT_SYMBOL(mlx5_unregister_interface);
953 void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol)
955 struct mlx5_priv *priv = &mdev->priv;
956 struct mlx5_device_context *dev_ctx;
960 spin_lock_irqsave(&priv->ctx_lock, flags);
962 list_for_each_entry(dev_ctx, &mdev->priv.ctx_list, list)
963 if ((dev_ctx->intf->protocol == protocol) &&
964 dev_ctx->intf->get_dev) {
965 result = dev_ctx->intf->get_dev(dev_ctx->context);
969 spin_unlock_irqrestore(&priv->ctx_lock, flags);
973 EXPORT_SYMBOL(mlx5_get_protocol_dev);
975 static void mlx5_core_event(struct mlx5_core_dev *dev, enum mlx5_dev_event event,
978 struct mlx5_priv *priv = &dev->priv;
979 struct mlx5_device_context *dev_ctx;
982 spin_lock_irqsave(&priv->ctx_lock, flags);
984 list_for_each_entry(dev_ctx, &priv->ctx_list, list)
985 if (dev_ctx->intf->event)
986 dev_ctx->intf->event(dev, dev_ctx->context, event, param);
988 spin_unlock_irqrestore(&priv->ctx_lock, flags);
991 struct mlx5_core_event_handler {
992 void (*event)(struct mlx5_core_dev *dev,
993 enum mlx5_dev_event event,
998 static int init_one(struct pci_dev *pdev,
999 const struct pci_device_id *id)
1001 struct mlx5_core_dev *dev;
1002 struct mlx5_priv *priv;
1005 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
1008 if (prof_sel < 0 || prof_sel >= ARRAY_SIZE(profiles)) {
1009 printf("mlx5_core: WARN: ""selected profile out of range, selecting default (%d)\n", MLX5_DEFAULT_PROF);
1010 prof_sel = MLX5_DEFAULT_PROF;
1012 dev->profile = &profiles[prof_sel];
1013 dev->event = mlx5_core_event;
1015 INIT_LIST_HEAD(&priv->ctx_list);
1016 spin_lock_init(&priv->ctx_lock);
1017 err = mlx5_dev_init(dev, pdev);
1019 device_printf((&pdev->dev)->bsddev, "ERR: ""mlx5_dev_init failed %d\n", err);
1023 err = mlx5_register_device(dev);
1025 device_printf((&pdev->dev)->bsddev, "ERR: ""mlx5_register_device failed %d\n", err);
1033 mlx5_dev_cleanup(dev);
1039 static void remove_one(struct pci_dev *pdev)
1041 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1043 mlx5_unregister_device(dev);
1044 mlx5_dev_cleanup(dev);
1048 static const struct pci_device_id mlx5_core_pci_table[] = {
1049 { PCI_VDEVICE(MELLANOX, 4113) }, /* Connect-IB */
1050 { PCI_VDEVICE(MELLANOX, 4114) }, /* Connect-IB VF */
1051 { PCI_VDEVICE(MELLANOX, 4115) }, /* ConnectX-4 */
1052 { PCI_VDEVICE(MELLANOX, 4116) }, /* ConnectX-4 VF */
1053 { PCI_VDEVICE(MELLANOX, 4117) }, /* ConnectX-4LX */
1054 { PCI_VDEVICE(MELLANOX, 4118) }, /* ConnectX-4LX VF */
1055 { PCI_VDEVICE(MELLANOX, 4119) },
1056 { PCI_VDEVICE(MELLANOX, 4120) },
1057 { PCI_VDEVICE(MELLANOX, 4121) },
1058 { PCI_VDEVICE(MELLANOX, 4122) },
1059 { PCI_VDEVICE(MELLANOX, 4123) },
1060 { PCI_VDEVICE(MELLANOX, 4124) },
1061 { PCI_VDEVICE(MELLANOX, 4125) },
1062 { PCI_VDEVICE(MELLANOX, 4126) },
1063 { PCI_VDEVICE(MELLANOX, 4127) },
1064 { PCI_VDEVICE(MELLANOX, 4128) },
1065 { PCI_VDEVICE(MELLANOX, 4129) },
1066 { PCI_VDEVICE(MELLANOX, 4130) },
1067 { PCI_VDEVICE(MELLANOX, 4131) },
1068 { PCI_VDEVICE(MELLANOX, 4132) },
1069 { PCI_VDEVICE(MELLANOX, 4133) },
1070 { PCI_VDEVICE(MELLANOX, 4134) },
1071 { PCI_VDEVICE(MELLANOX, 4135) },
1072 { PCI_VDEVICE(MELLANOX, 4136) },
1073 { PCI_VDEVICE(MELLANOX, 4137) },
1074 { PCI_VDEVICE(MELLANOX, 4138) },
1075 { PCI_VDEVICE(MELLANOX, 4139) },
1076 { PCI_VDEVICE(MELLANOX, 4140) },
1077 { PCI_VDEVICE(MELLANOX, 4141) },
1078 { PCI_VDEVICE(MELLANOX, 4142) },
1079 { PCI_VDEVICE(MELLANOX, 4143) },
1080 { PCI_VDEVICE(MELLANOX, 4144) },
1084 MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1086 static struct pci_driver mlx5_core_driver = {
1087 .name = DRIVER_NAME,
1088 .id_table = mlx5_core_pci_table,
1090 .remove = remove_one
1093 static int __init init(void)
1097 mlx5_core_wq = create_singlethread_workqueue("mlx5_core_wq");
1098 if (!mlx5_core_wq) {
1104 err = pci_register_driver(&mlx5_core_driver);
1112 mlx5_health_cleanup();
1113 destroy_workqueue(mlx5_core_wq);
1118 static void __exit cleanup(void)
1120 pci_unregister_driver(&mlx5_core_driver);
1121 mlx5_health_cleanup();
1122 destroy_workqueue(mlx5_core_wq);
1126 module_exit(cleanup);