2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <linux/module.h>
29 #include <dev/mlx5/driver.h>
30 #include "mlx5_core.h"
32 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
33 int size_in, void *data_out, int size_out,
34 u16 reg_num, int arg, int write)
36 struct mlx5_access_reg_mbox_in *in = NULL;
37 struct mlx5_access_reg_mbox_out *out = NULL;
40 in = mlx5_vzalloc(sizeof(*in) + size_in);
44 out = mlx5_vzalloc(sizeof(*out) + size_out);
48 memcpy(in->data, data_in, size_in);
49 in->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ACCESS_REG);
50 in->hdr.opmod = cpu_to_be16(!write);
51 in->arg = cpu_to_be32(arg);
52 in->register_id = cpu_to_be16(reg_num);
53 err = mlx5_cmd_exec(dev, in, sizeof(*in) + size_in, out,
54 sizeof(*out) + size_out);
59 err = mlx5_cmd_status_to_err(&out->hdr);
62 memcpy(data_out, out->data, size_out);
70 EXPORT_SYMBOL_GPL(mlx5_core_access_reg);
73 struct mlx5_reg_pcap {
83 /* This function should be used after setting a port register only */
84 void mlx5_toggle_port_link(struct mlx5_core_dev *dev)
86 enum mlx5_port_status ps;
88 mlx5_query_port_admin_status(dev, &ps);
89 mlx5_set_port_status(dev, MLX5_PORT_DOWN);
90 if (ps == MLX5_PORT_UP)
91 mlx5_set_port_status(dev, MLX5_PORT_UP);
93 EXPORT_SYMBOL_GPL(mlx5_toggle_port_link);
95 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps)
97 struct mlx5_reg_pcap in;
98 struct mlx5_reg_pcap out;
101 memset(&in, 0, sizeof(in));
102 in.caps_127_96 = cpu_to_be32(caps);
103 in.port_num = port_num;
105 err = mlx5_core_access_reg(dev, &in, sizeof(in), &out,
106 sizeof(out), MLX5_REG_PCAP, 0, 1);
110 EXPORT_SYMBOL_GPL(mlx5_set_port_caps);
112 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
113 int ptys_size, int proto_mask)
115 u32 in[MLX5_ST_SZ_DW(ptys_reg)];
118 memset(in, 0, sizeof(in));
119 MLX5_SET(ptys_reg, in, local_port, 1);
120 MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
122 err = mlx5_core_access_reg(dev, in, sizeof(in), ptys,
123 ptys_size, MLX5_REG_PTYS, 0, 0);
127 EXPORT_SYMBOL_GPL(mlx5_query_port_ptys);
129 int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev,
130 u32 *proto_cap, int proto_mask)
132 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
135 err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask);
139 if (proto_mask == MLX5_PTYS_EN)
140 *proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
142 *proto_cap = MLX5_GET(ptys_reg, out, ib_proto_capability);
146 EXPORT_SYMBOL_GPL(mlx5_query_port_proto_cap);
148 int mlx5_query_port_autoneg(struct mlx5_core_dev *dev, int proto_mask,
149 u8 *an_disable_cap, u8 *an_disable_status)
151 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
154 err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask);
158 *an_disable_status = MLX5_GET(ptys_reg, out, an_disable_admin);
159 *an_disable_cap = MLX5_GET(ptys_reg, out, an_disable_cap);
163 EXPORT_SYMBOL_GPL(mlx5_query_port_autoneg);
165 int mlx5_set_port_autoneg(struct mlx5_core_dev *dev, bool disable,
166 u32 eth_proto_admin, int proto_mask)
168 u32 in[MLX5_ST_SZ_DW(ptys_reg)];
169 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
171 u8 an_disable_status;
174 err = mlx5_query_port_autoneg(dev, proto_mask, &an_disable_cap,
181 memset(in, 0, sizeof(in));
183 MLX5_SET(ptys_reg, in, local_port, 1);
184 MLX5_SET(ptys_reg, in, an_disable_admin, disable);
185 MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
186 if (proto_mask == MLX5_PTYS_EN)
187 MLX5_SET(ptys_reg, in, eth_proto_admin, eth_proto_admin);
189 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
190 sizeof(out), MLX5_REG_PTYS, 0, 1);
193 EXPORT_SYMBOL_GPL(mlx5_set_port_autoneg);
195 int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
196 u32 *proto_admin, int proto_mask)
198 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
201 err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask);
205 if (proto_mask == MLX5_PTYS_EN)
206 *proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
208 *proto_admin = MLX5_GET(ptys_reg, out, ib_proto_admin);
212 EXPORT_SYMBOL_GPL(mlx5_query_port_proto_admin);
214 int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin,
217 u32 in[MLX5_ST_SZ_DW(ptys_reg)];
218 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
221 memset(in, 0, sizeof(in));
223 MLX5_SET(ptys_reg, in, local_port, 1);
224 MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
225 if (proto_mask == MLX5_PTYS_EN)
226 MLX5_SET(ptys_reg, in, eth_proto_admin, proto_admin);
228 MLX5_SET(ptys_reg, in, ib_proto_admin, proto_admin);
230 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
231 sizeof(out), MLX5_REG_PTYS, 0, 1);
234 EXPORT_SYMBOL_GPL(mlx5_set_port_proto);
236 int mlx5_set_port_status(struct mlx5_core_dev *dev,
237 enum mlx5_port_status status)
239 u32 in[MLX5_ST_SZ_DW(paos_reg)];
240 u32 out[MLX5_ST_SZ_DW(paos_reg)];
243 memset(in, 0, sizeof(in));
245 MLX5_SET(paos_reg, in, local_port, 1);
247 MLX5_SET(paos_reg, in, admin_status, status);
248 MLX5_SET(paos_reg, in, ase, 1);
250 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
251 sizeof(out), MLX5_REG_PAOS, 0, 1);
255 int mlx5_query_port_status(struct mlx5_core_dev *dev, u8 *status)
257 u32 in[MLX5_ST_SZ_DW(paos_reg)];
258 u32 out[MLX5_ST_SZ_DW(paos_reg)];
261 memset(in, 0, sizeof(in));
263 MLX5_SET(paos_reg, in, local_port, 1);
265 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
266 sizeof(out), MLX5_REG_PAOS, 0, 0);
270 *status = MLX5_GET(paos_reg, out, oper_status);
274 int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
275 enum mlx5_port_status *status)
277 u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0};
278 u32 out[MLX5_ST_SZ_DW(paos_reg)];
281 MLX5_SET(paos_reg, in, local_port, 1);
282 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
283 sizeof(out), MLX5_REG_PAOS, 0, 0);
286 *status = MLX5_GET(paos_reg, out, admin_status);
289 EXPORT_SYMBOL_GPL(mlx5_query_port_admin_status);
291 static int mlx5_query_port_mtu(struct mlx5_core_dev *dev,
292 int *admin_mtu, int *max_mtu, int *oper_mtu)
294 u32 in[MLX5_ST_SZ_DW(pmtu_reg)];
295 u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
298 memset(in, 0, sizeof(in));
300 MLX5_SET(pmtu_reg, in, local_port, 1);
302 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
303 sizeof(out), MLX5_REG_PMTU, 0, 0);
308 *max_mtu = MLX5_GET(pmtu_reg, out, max_mtu);
310 *oper_mtu = MLX5_GET(pmtu_reg, out, oper_mtu);
312 *admin_mtu = MLX5_GET(pmtu_reg, out, admin_mtu);
317 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu)
319 u32 in[MLX5_ST_SZ_DW(pmtu_reg)];
320 u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
322 memset(in, 0, sizeof(in));
324 MLX5_SET(pmtu_reg, in, admin_mtu, mtu);
325 MLX5_SET(pmtu_reg, in, local_port, 1);
327 return mlx5_core_access_reg(dev, in, sizeof(in), out,
328 sizeof(out), MLX5_REG_PMTU, 0, 1);
330 EXPORT_SYMBOL_GPL(mlx5_set_port_mtu);
332 int mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu)
334 return mlx5_query_port_mtu(dev, NULL, max_mtu, NULL);
336 EXPORT_SYMBOL_GPL(mlx5_query_port_max_mtu);
338 int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 port,
339 u32 rx_pause, u32 tx_pause)
341 u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
342 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
344 memset(in, 0, sizeof(in));
345 memset(out, 0, sizeof(out));
347 MLX5_SET(pfcc_reg, in, local_port, port);
348 MLX5_SET(pfcc_reg, in, pptx, tx_pause);
349 MLX5_SET(pfcc_reg, in, pprx, rx_pause);
351 return mlx5_core_access_reg(dev, in, sizeof(in), out,
352 sizeof(out), MLX5_REG_PFCC, 0, 1);
355 int mlx5_query_port_pause(struct mlx5_core_dev *dev, u32 port,
356 u32 *rx_pause, u32 *tx_pause)
358 u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
359 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
362 memset(in, 0, sizeof(in));
363 memset(out, 0, sizeof(out));
365 MLX5_SET(pfcc_reg, in, local_port, port);
367 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
368 sizeof(out), MLX5_REG_PFCC, 0, 0);
372 *rx_pause = MLX5_GET(pfcc_reg, out, pprx);
373 *tx_pause = MLX5_GET(pfcc_reg, out, pptx);
378 int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx)
380 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
381 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
383 MLX5_SET(pfcc_reg, in, local_port, 1);
384 MLX5_SET(pfcc_reg, in, pfctx, pfc_en_tx);
385 MLX5_SET(pfcc_reg, in, pfcrx, pfc_en_rx);
386 MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_tx);
387 MLX5_SET_TO_ONES(pfcc_reg, in, prio_mask_rx);
389 return mlx5_core_access_reg(dev, in, sizeof(in), out,
390 sizeof(out), MLX5_REG_PFCC, 0, 1);
392 EXPORT_SYMBOL_GPL(mlx5_set_port_pfc);
394 int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx, u8 *pfc_en_rx)
396 u32 in[MLX5_ST_SZ_DW(pfcc_reg)] = {0};
397 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
400 MLX5_SET(pfcc_reg, in, local_port, 1);
401 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
402 sizeof(out), MLX5_REG_PFCC, 0, 0);
407 *pfc_en_tx = MLX5_GET(pfcc_reg, out, pfctx);
410 *pfc_en_rx = MLX5_GET(pfcc_reg, out, pfcrx);
414 EXPORT_SYMBOL_GPL(mlx5_query_port_pfc);
416 int mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu)
418 return mlx5_query_port_mtu(dev, NULL, NULL, oper_mtu);
420 EXPORT_SYMBOL_GPL(mlx5_query_port_oper_mtu);
422 u8 mlx5_is_wol_supported(struct mlx5_core_dev *dev)
424 u8 wol_supported = 0;
426 if (MLX5_CAP_GEN(dev, wol_s))
427 wol_supported |= MLX5_WOL_SECURED_MAGIC;
428 if (MLX5_CAP_GEN(dev, wol_g))
429 wol_supported |= MLX5_WOL_MAGIC;
430 if (MLX5_CAP_GEN(dev, wol_a))
431 wol_supported |= MLX5_WOL_ARP;
432 if (MLX5_CAP_GEN(dev, wol_b))
433 wol_supported |= MLX5_WOL_BROADCAST;
434 if (MLX5_CAP_GEN(dev, wol_m))
435 wol_supported |= MLX5_WOL_MULTICAST;
436 if (MLX5_CAP_GEN(dev, wol_u))
437 wol_supported |= MLX5_WOL_UNICAST;
438 if (MLX5_CAP_GEN(dev, wol_p))
439 wol_supported |= MLX5_WOL_PHY_ACTIVITY;
441 return wol_supported;
443 EXPORT_SYMBOL_GPL(mlx5_is_wol_supported);
445 int mlx5_set_wol(struct mlx5_core_dev *dev, u8 wol_mode)
447 u32 in[MLX5_ST_SZ_DW(set_wol_rol_in)];
448 u32 out[MLX5_ST_SZ_DW(set_wol_rol_out)];
450 memset(in, 0, sizeof(in));
451 memset(out, 0, sizeof(out));
453 MLX5_SET(set_wol_rol_in, in, opcode, MLX5_CMD_OP_SET_WOL_ROL);
454 MLX5_SET(set_wol_rol_in, in, wol_mode_valid, 1);
455 MLX5_SET(set_wol_rol_in, in, wol_mode, wol_mode);
457 return mlx5_cmd_exec_check_status(dev, in, sizeof(in),
460 EXPORT_SYMBOL_GPL(mlx5_set_wol);
462 int mlx5_query_dropless_mode(struct mlx5_core_dev *dev, u16 *timeout)
464 u32 in[MLX5_ST_SZ_DW(query_delay_drop_params_in)];
465 u32 out[MLX5_ST_SZ_DW(query_delay_drop_params_out)];
468 memset(in, 0, sizeof(in));
469 memset(out, 0, sizeof(out));
471 MLX5_SET(query_delay_drop_params_in, in, opcode,
472 MLX5_CMD_OP_QUERY_DELAY_DROP_PARAMS);
474 err = mlx5_cmd_exec_check_status(dev, in, sizeof(in), out, sizeof(out));
478 *timeout = MLX5_GET(query_delay_drop_params_out, out,
483 EXPORT_SYMBOL_GPL(mlx5_query_dropless_mode);
485 int mlx5_set_dropless_mode(struct mlx5_core_dev *dev, u16 timeout)
487 u32 in[MLX5_ST_SZ_DW(set_delay_drop_params_in)];
488 u32 out[MLX5_ST_SZ_DW(set_delay_drop_params_out)];
490 memset(in, 0, sizeof(in));
491 memset(out, 0, sizeof(out));
493 MLX5_SET(set_delay_drop_params_in, in, opcode,
494 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS);
495 MLX5_SET(set_delay_drop_params_in, in, delay_drop_timeout, timeout);
497 return mlx5_cmd_exec_check_status(dev, in, sizeof(in),
500 EXPORT_SYMBOL_GPL(mlx5_set_dropless_mode);
502 int mlx5_core_access_pvlc(struct mlx5_core_dev *dev,
503 struct mlx5_pvlc_reg *pvlc, int write)
505 int sz = MLX5_ST_SZ_BYTES(pvlc_reg);
506 u8 in[MLX5_ST_SZ_BYTES(pvlc_reg)];
507 u8 out[MLX5_ST_SZ_BYTES(pvlc_reg)];
510 memset(out, 0, sizeof(out));
511 memset(in, 0, sizeof(in));
513 MLX5_SET(pvlc_reg, in, local_port, pvlc->local_port);
515 MLX5_SET(pvlc_reg, in, vl_admin, pvlc->vl_admin);
517 err = mlx5_core_access_reg(dev, in, sz, out, sz, MLX5_REG_PVLC, 0,
523 pvlc->local_port = MLX5_GET(pvlc_reg, out, local_port);
524 pvlc->vl_hw_cap = MLX5_GET(pvlc_reg, out, vl_hw_cap);
525 pvlc->vl_admin = MLX5_GET(pvlc_reg, out, vl_admin);
526 pvlc->vl_operational = MLX5_GET(pvlc_reg, out, vl_operational);
531 EXPORT_SYMBOL_GPL(mlx5_core_access_pvlc);
533 int mlx5_core_access_ptys(struct mlx5_core_dev *dev,
534 struct mlx5_ptys_reg *ptys, int write)
536 int sz = MLX5_ST_SZ_BYTES(ptys_reg);
541 in = mlx5_vzalloc(sz);
545 out = mlx5_vzalloc(sz);
551 MLX5_SET(ptys_reg, in, local_port, ptys->local_port);
552 MLX5_SET(ptys_reg, in, proto_mask, ptys->proto_mask);
554 MLX5_SET(ptys_reg, in, eth_proto_capability,
555 ptys->eth_proto_cap);
556 MLX5_SET(ptys_reg, in, ib_link_width_capability,
557 ptys->ib_link_width_cap);
558 MLX5_SET(ptys_reg, in, ib_proto_capability,
560 MLX5_SET(ptys_reg, in, eth_proto_admin, ptys->eth_proto_admin);
561 MLX5_SET(ptys_reg, in, ib_link_width_admin,
562 ptys->ib_link_width_admin);
563 MLX5_SET(ptys_reg, in, ib_proto_admin, ptys->ib_proto_admin);
564 MLX5_SET(ptys_reg, in, eth_proto_oper, ptys->eth_proto_oper);
565 MLX5_SET(ptys_reg, in, ib_link_width_oper,
566 ptys->ib_link_width_oper);
567 MLX5_SET(ptys_reg, in, ib_proto_oper, ptys->ib_proto_oper);
568 MLX5_SET(ptys_reg, in, eth_proto_lp_advertise,
569 ptys->eth_proto_lp_advertise);
572 err = mlx5_core_access_reg(dev, in, sz, out, sz, MLX5_REG_PTYS, 0,
578 ptys->local_port = MLX5_GET(ptys_reg, out, local_port);
579 ptys->proto_mask = MLX5_GET(ptys_reg, out, proto_mask);
580 ptys->eth_proto_cap = MLX5_GET(ptys_reg, out,
581 eth_proto_capability);
582 ptys->ib_link_width_cap = MLX5_GET(ptys_reg, out,
583 ib_link_width_capability);
584 ptys->ib_proto_cap = MLX5_GET(ptys_reg, out,
585 ib_proto_capability);
586 ptys->eth_proto_admin = MLX5_GET(ptys_reg, out,
588 ptys->ib_link_width_admin = MLX5_GET(ptys_reg, out,
589 ib_link_width_admin);
590 ptys->ib_proto_admin = MLX5_GET(ptys_reg, out, ib_proto_admin);
591 ptys->eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
592 ptys->ib_link_width_oper = MLX5_GET(ptys_reg, out,
594 ptys->ib_proto_oper = MLX5_GET(ptys_reg, out, ib_proto_oper);
595 ptys->eth_proto_lp_advertise = MLX5_GET(ptys_reg, out,
596 eth_proto_lp_advertise);
604 EXPORT_SYMBOL_GPL(mlx5_core_access_ptys);
606 static int mtu_to_ib_mtu(int mtu)
615 printf("mlx5_core: WARN: ""invalid mtu\n");
620 int mlx5_core_access_pmtu(struct mlx5_core_dev *dev,
621 struct mlx5_pmtu_reg *pmtu, int write)
623 int sz = MLX5_ST_SZ_BYTES(pmtu_reg);
628 in = mlx5_vzalloc(sz);
632 out = mlx5_vzalloc(sz);
638 MLX5_SET(pmtu_reg, in, local_port, pmtu->local_port);
640 MLX5_SET(pmtu_reg, in, admin_mtu, pmtu->admin_mtu);
642 err = mlx5_core_access_reg(dev, in, sz, out, sz, MLX5_REG_PMTU, 0,
648 pmtu->local_port = MLX5_GET(pmtu_reg, out, local_port);
649 pmtu->max_mtu = mtu_to_ib_mtu(MLX5_GET(pmtu_reg, out,
651 pmtu->admin_mtu = mtu_to_ib_mtu(MLX5_GET(pmtu_reg, out,
653 pmtu->oper_mtu = mtu_to_ib_mtu(MLX5_GET(pmtu_reg, out,
662 EXPORT_SYMBOL_GPL(mlx5_core_access_pmtu);
664 int mlx5_query_module_num(struct mlx5_core_dev *dev, int *module_num)
666 u32 in[MLX5_ST_SZ_DW(pmlp_reg)];
667 u32 out[MLX5_ST_SZ_DW(pmlp_reg)];
671 memset(in, 0, sizeof(in));
673 MLX5_SET(pmlp_reg, in, local_port, 1);
675 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
676 sizeof(out), MLX5_REG_PMLP, 0, 0);
680 lane = MLX5_GET(pmlp_reg, out, lane0_module_mapping);
681 *module_num = lane & MLX5_EEPROM_IDENTIFIER_BYTE_MASK;
685 EXPORT_SYMBOL_GPL(mlx5_query_module_num);
687 int mlx5_query_eeprom(struct mlx5_core_dev *dev,
688 int i2c_addr, int page_num, int device_addr,
689 int size, int module_num, u32 *data, int *size_read)
691 u32 in[MLX5_ST_SZ_DW(mcia_reg)];
692 u32 out[MLX5_ST_SZ_DW(mcia_reg)];
693 u32 *ptr = (u32 *)MLX5_ADDR_OF(mcia_reg, out, dword_0);
697 memset(in, 0, sizeof(in));
698 size = min_t(int, size, MLX5_EEPROM_MAX_BYTES);
700 MLX5_SET(mcia_reg, in, l, 0);
701 MLX5_SET(mcia_reg, in, module, module_num);
702 MLX5_SET(mcia_reg, in, i2c_device_address, i2c_addr);
703 MLX5_SET(mcia_reg, in, page_number, page_num);
704 MLX5_SET(mcia_reg, in, device_address, device_addr);
705 MLX5_SET(mcia_reg, in, size, size);
707 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
708 sizeof(out), MLX5_REG_MCIA, 0, 0);
712 status = MLX5_GET(mcia_reg, out, status);
716 memcpy(data, ptr, size);
720 EXPORT_SYMBOL_GPL(mlx5_query_eeprom);
722 int mlx5_vxlan_udp_port_add(struct mlx5_core_dev *dev, u16 port)
724 u32 in[MLX5_ST_SZ_DW(add_vxlan_udp_dport_in)];
725 u32 out[MLX5_ST_SZ_DW(add_vxlan_udp_dport_out)];
728 memset(in, 0, sizeof(in));
729 memset(out, 0, sizeof(out));
731 MLX5_SET(add_vxlan_udp_dport_in, in, opcode,
732 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT);
733 MLX5_SET(add_vxlan_udp_dport_in, in, vxlan_udp_port, port);
735 err = mlx5_cmd_exec_check_status(dev, in, sizeof(in), out, sizeof(out));
737 mlx5_core_err(dev, "Failed %s, port %u, err - %d",
738 mlx5_command_str(MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT),
745 int mlx5_vxlan_udp_port_delete(struct mlx5_core_dev *dev, u16 port)
747 u32 in[MLX5_ST_SZ_DW(delete_vxlan_udp_dport_in)];
748 u32 out[MLX5_ST_SZ_DW(delete_vxlan_udp_dport_out)];
751 memset(in, 0, sizeof(in));
752 memset(out, 0, sizeof(out));
754 MLX5_SET(delete_vxlan_udp_dport_in, in, opcode,
755 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT);
756 MLX5_SET(delete_vxlan_udp_dport_in, in, vxlan_udp_port, port);
758 err = mlx5_cmd_exec_check_status(dev, in, sizeof(in), out, sizeof(out));
760 mlx5_core_err(dev, "Failed %s, port %u, err - %d",
761 mlx5_command_str(MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT),
768 int mlx5_query_wol(struct mlx5_core_dev *dev, u8 *wol_mode)
770 u32 in[MLX5_ST_SZ_DW(query_wol_rol_in)];
771 u32 out[MLX5_ST_SZ_DW(query_wol_rol_out)];
774 memset(in, 0, sizeof(in));
775 memset(out, 0, sizeof(out));
777 MLX5_SET(query_wol_rol_in, in, opcode, MLX5_CMD_OP_QUERY_WOL_ROL);
779 err = mlx5_cmd_exec_check_status(dev, in, sizeof(in), out, sizeof(out));
782 *wol_mode = MLX5_GET(query_wol_rol_out, out, wol_mode);
786 EXPORT_SYMBOL_GPL(mlx5_query_wol);
788 int mlx5_query_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
789 int priority, int *is_enable)
791 u32 in[MLX5_ST_SZ_DW(query_cong_status_in)];
792 u32 out[MLX5_ST_SZ_DW(query_cong_status_out)];
795 memset(in, 0, sizeof(in));
796 memset(out, 0, sizeof(out));
800 MLX5_SET(query_cong_status_in, in, opcode,
801 MLX5_CMD_OP_QUERY_CONG_STATUS);
802 MLX5_SET(query_cong_status_in, in, cong_protocol, protocol);
803 MLX5_SET(query_cong_status_in, in, priority, priority);
805 err = mlx5_cmd_exec_check_status(mdev, in, sizeof(in),
808 *is_enable = MLX5_GET(query_cong_status_out, out, enable);
812 int mlx5_modify_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
813 int priority, int enable)
815 u32 in[MLX5_ST_SZ_DW(modify_cong_status_in)];
816 u32 out[MLX5_ST_SZ_DW(modify_cong_status_out)];
818 memset(in, 0, sizeof(in));
819 memset(out, 0, sizeof(out));
821 MLX5_SET(modify_cong_status_in, in, opcode,
822 MLX5_CMD_OP_MODIFY_CONG_STATUS);
823 MLX5_SET(modify_cong_status_in, in, cong_protocol, protocol);
824 MLX5_SET(modify_cong_status_in, in, priority, priority);
825 MLX5_SET(modify_cong_status_in, in, enable, enable);
827 return mlx5_cmd_exec_check_status(mdev, in, sizeof(in),
831 int mlx5_query_port_cong_params(struct mlx5_core_dev *mdev, int protocol,
832 void *out, int out_size)
834 u32 in[MLX5_ST_SZ_DW(query_cong_params_in)];
836 memset(in, 0, sizeof(in));
838 MLX5_SET(query_cong_params_in, in, opcode,
839 MLX5_CMD_OP_QUERY_CONG_PARAMS);
840 MLX5_SET(query_cong_params_in, in, cong_protocol, protocol);
842 return mlx5_cmd_exec_check_status(mdev, in, sizeof(in),
846 int mlx5_modify_port_cong_params(struct mlx5_core_dev *mdev,
847 void *in, int in_size)
849 u32 out[MLX5_ST_SZ_DW(modify_cong_params_out)];
851 memset(out, 0, sizeof(out));
853 MLX5_SET(modify_cong_params_in, in, opcode,
854 MLX5_CMD_OP_MODIFY_CONG_PARAMS);
856 return mlx5_cmd_exec_check_status(mdev, in, in_size, out, sizeof(out));
859 int mlx5_query_port_cong_statistics(struct mlx5_core_dev *mdev, int clear,
860 void *out, int out_size)
862 u32 in[MLX5_ST_SZ_DW(query_cong_statistics_in)];
864 memset(in, 0, sizeof(in));
866 MLX5_SET(query_cong_statistics_in, in, opcode,
867 MLX5_CMD_OP_QUERY_CONG_STATISTICS);
868 MLX5_SET(query_cong_statistics_in, in, clear, clear);
870 return mlx5_cmd_exec_check_status(mdev, in, sizeof(in),
874 int mlx5_set_diagnostic_params(struct mlx5_core_dev *mdev, void *in,
877 u32 out[MLX5_ST_SZ_DW(set_diagnostic_params_out)];
879 memset(out, 0, sizeof(out));
881 MLX5_SET(set_diagnostic_params_in, in, opcode,
882 MLX5_CMD_OP_SET_DIAGNOSTICS);
884 return mlx5_cmd_exec_check_status(mdev, in, in_size, out, sizeof(out));
887 int mlx5_query_diagnostic_counters(struct mlx5_core_dev *mdev,
888 u8 num_of_samples, u16 sample_index,
889 void *out, int out_size)
891 u32 in[MLX5_ST_SZ_DW(query_diagnostic_counters_in)];
893 memset(in, 0, sizeof(in));
895 MLX5_SET(query_diagnostic_counters_in, in, opcode,
896 MLX5_CMD_OP_QUERY_DIAGNOSTICS);
897 MLX5_SET(query_diagnostic_counters_in, in, num_of_samples,
899 MLX5_SET(query_diagnostic_counters_in, in, sample_index, sample_index);
901 return mlx5_cmd_exec_check_status(mdev, in, sizeof(in), out, out_size);