2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <linux/module.h>
29 #include <dev/mlx5/driver.h>
30 #include "mlx5_core.h"
32 int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
33 int size_in, void *data_out, int size_out,
34 u16 reg_num, int arg, int write)
36 struct mlx5_access_reg_mbox_in *in = NULL;
37 struct mlx5_access_reg_mbox_out *out = NULL;
40 in = mlx5_vzalloc(sizeof(*in) + size_in);
44 out = mlx5_vzalloc(sizeof(*out) + size_out);
48 memcpy(in->data, data_in, size_in);
49 in->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_ACCESS_REG);
50 in->hdr.opmod = cpu_to_be16(!write);
51 in->arg = cpu_to_be32(arg);
52 in->register_id = cpu_to_be16(reg_num);
53 err = mlx5_cmd_exec(dev, in, sizeof(*in) + size_in, out,
54 sizeof(*out) + size_out);
59 err = mlx5_cmd_status_to_err(&out->hdr);
62 memcpy(data_out, out->data, size_out);
70 EXPORT_SYMBOL_GPL(mlx5_core_access_reg);
73 struct mlx5_reg_pcap {
83 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps)
85 struct mlx5_reg_pcap in;
86 struct mlx5_reg_pcap out;
89 memset(&in, 0, sizeof(in));
90 in.caps_127_96 = cpu_to_be32(caps);
91 in.port_num = port_num;
93 err = mlx5_core_access_reg(dev, &in, sizeof(in), &out,
94 sizeof(out), MLX5_REG_PCAP, 0, 1);
98 EXPORT_SYMBOL_GPL(mlx5_set_port_caps);
100 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
101 int ptys_size, int proto_mask)
103 u32 in[MLX5_ST_SZ_DW(ptys_reg)];
106 memset(in, 0, sizeof(in));
107 MLX5_SET(ptys_reg, in, local_port, 1);
108 MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
110 err = mlx5_core_access_reg(dev, in, sizeof(in), ptys,
111 ptys_size, MLX5_REG_PTYS, 0, 0);
115 EXPORT_SYMBOL_GPL(mlx5_query_port_ptys);
117 int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev,
118 u32 *proto_cap, int proto_mask)
120 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
123 err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask);
127 if (proto_mask == MLX5_PTYS_EN)
128 *proto_cap = MLX5_GET(ptys_reg, out, eth_proto_capability);
130 *proto_cap = MLX5_GET(ptys_reg, out, ib_proto_capability);
134 EXPORT_SYMBOL_GPL(mlx5_query_port_proto_cap);
136 int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev,
137 u32 *proto_admin, int proto_mask)
139 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
142 err = mlx5_query_port_ptys(dev, out, sizeof(out), proto_mask);
146 if (proto_mask == MLX5_PTYS_EN)
147 *proto_admin = MLX5_GET(ptys_reg, out, eth_proto_admin);
149 *proto_admin = MLX5_GET(ptys_reg, out, ib_proto_admin);
153 EXPORT_SYMBOL_GPL(mlx5_query_port_proto_admin);
155 int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin,
158 u32 in[MLX5_ST_SZ_DW(ptys_reg)];
159 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
162 memset(in, 0, sizeof(in));
164 MLX5_SET(ptys_reg, in, local_port, 1);
165 MLX5_SET(ptys_reg, in, proto_mask, proto_mask);
166 if (proto_mask == MLX5_PTYS_EN)
167 MLX5_SET(ptys_reg, in, eth_proto_admin, proto_admin);
169 MLX5_SET(ptys_reg, in, ib_proto_admin, proto_admin);
171 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
172 sizeof(out), MLX5_REG_PTYS, 0, 1);
175 EXPORT_SYMBOL_GPL(mlx5_set_port_proto);
177 int mlx5_set_port_status(struct mlx5_core_dev *dev,
178 enum mlx5_port_status status)
180 u32 in[MLX5_ST_SZ_DW(paos_reg)];
181 u32 out[MLX5_ST_SZ_DW(paos_reg)];
184 memset(in, 0, sizeof(in));
186 MLX5_SET(paos_reg, in, local_port, 1);
188 MLX5_SET(paos_reg, in, admin_status, status);
189 MLX5_SET(paos_reg, in, ase, 1);
191 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
192 sizeof(out), MLX5_REG_PAOS, 0, 1);
196 int mlx5_query_port_status(struct mlx5_core_dev *dev, u8 *status)
198 u32 in[MLX5_ST_SZ_DW(paos_reg)];
199 u32 out[MLX5_ST_SZ_DW(paos_reg)];
202 memset(in, 0, sizeof(in));
204 MLX5_SET(paos_reg, in, local_port, 1);
206 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
207 sizeof(out), MLX5_REG_PAOS, 0, 0);
211 *status = MLX5_GET(paos_reg, out, oper_status);
215 static int mlx5_query_port_mtu(struct mlx5_core_dev *dev,
216 int *admin_mtu, int *max_mtu, int *oper_mtu)
218 u32 in[MLX5_ST_SZ_DW(pmtu_reg)];
219 u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
222 memset(in, 0, sizeof(in));
224 MLX5_SET(pmtu_reg, in, local_port, 1);
226 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
227 sizeof(out), MLX5_REG_PMTU, 0, 0);
232 *max_mtu = MLX5_GET(pmtu_reg, out, max_mtu);
234 *oper_mtu = MLX5_GET(pmtu_reg, out, oper_mtu);
236 *admin_mtu = MLX5_GET(pmtu_reg, out, admin_mtu);
241 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu)
243 u32 in[MLX5_ST_SZ_DW(pmtu_reg)];
244 u32 out[MLX5_ST_SZ_DW(pmtu_reg)];
246 memset(in, 0, sizeof(in));
248 MLX5_SET(pmtu_reg, in, admin_mtu, mtu);
249 MLX5_SET(pmtu_reg, in, local_port, 1);
251 return mlx5_core_access_reg(dev, in, sizeof(in), out,
252 sizeof(out), MLX5_REG_PMTU, 0, 1);
254 EXPORT_SYMBOL_GPL(mlx5_set_port_mtu);
256 int mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu)
258 return mlx5_query_port_mtu(dev, NULL, max_mtu, NULL);
260 EXPORT_SYMBOL_GPL(mlx5_query_port_max_mtu);
262 int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 port,
263 u32 rx_pause, u32 tx_pause)
265 u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
266 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
268 memset(in, 0, sizeof(in));
269 memset(out, 0, sizeof(out));
271 MLX5_SET(pfcc_reg, in, local_port, port);
272 MLX5_SET(pfcc_reg, in, pptx, tx_pause);
273 MLX5_SET(pfcc_reg, in, pprx, rx_pause);
275 return mlx5_core_access_reg(dev, in, sizeof(in), out,
276 sizeof(out), MLX5_REG_PFCC, 0, 1);
279 int mlx5_query_port_pause(struct mlx5_core_dev *dev, u32 port,
280 u32 *rx_pause, u32 *tx_pause)
282 u32 in[MLX5_ST_SZ_DW(pfcc_reg)];
283 u32 out[MLX5_ST_SZ_DW(pfcc_reg)];
286 memset(in, 0, sizeof(in));
287 memset(out, 0, sizeof(out));
289 MLX5_SET(pfcc_reg, in, local_port, port);
291 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
292 sizeof(out), MLX5_REG_PFCC, 0, 0);
296 *rx_pause = MLX5_GET(pfcc_reg, out, pprx);
297 *tx_pause = MLX5_GET(pfcc_reg, out, pptx);
302 int mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu)
304 return mlx5_query_port_mtu(dev, NULL, NULL, oper_mtu);
306 EXPORT_SYMBOL_GPL(mlx5_query_port_oper_mtu);
308 u8 mlx5_is_wol_supported(struct mlx5_core_dev *dev)
310 u8 wol_supported = 0;
312 if (MLX5_CAP_GEN(dev, wol_s))
313 wol_supported |= MLX5_WOL_SECURED_MAGIC;
314 if (MLX5_CAP_GEN(dev, wol_g))
315 wol_supported |= MLX5_WOL_MAGIC;
316 if (MLX5_CAP_GEN(dev, wol_a))
317 wol_supported |= MLX5_WOL_ARP;
318 if (MLX5_CAP_GEN(dev, wol_b))
319 wol_supported |= MLX5_WOL_BROADCAST;
320 if (MLX5_CAP_GEN(dev, wol_m))
321 wol_supported |= MLX5_WOL_MULTICAST;
322 if (MLX5_CAP_GEN(dev, wol_u))
323 wol_supported |= MLX5_WOL_UNICAST;
324 if (MLX5_CAP_GEN(dev, wol_p))
325 wol_supported |= MLX5_WOL_PHY_ACTIVITY;
327 return wol_supported;
329 EXPORT_SYMBOL_GPL(mlx5_is_wol_supported);
331 int mlx5_set_wol(struct mlx5_core_dev *dev, u8 wol_mode)
333 u32 in[MLX5_ST_SZ_DW(set_wol_rol_in)];
334 u32 out[MLX5_ST_SZ_DW(set_wol_rol_out)];
336 memset(in, 0, sizeof(in));
337 memset(out, 0, sizeof(out));
339 MLX5_SET(set_wol_rol_in, in, opcode, MLX5_CMD_OP_SET_WOL_ROL);
340 MLX5_SET(set_wol_rol_in, in, wol_mode_valid, 1);
341 MLX5_SET(set_wol_rol_in, in, wol_mode, wol_mode);
343 return mlx5_cmd_exec_check_status(dev, in, sizeof(in),
346 EXPORT_SYMBOL_GPL(mlx5_set_wol);
348 int mlx5_core_access_pvlc(struct mlx5_core_dev *dev,
349 struct mlx5_pvlc_reg *pvlc, int write)
351 int sz = MLX5_ST_SZ_BYTES(pvlc_reg);
352 u8 in[MLX5_ST_SZ_BYTES(pvlc_reg)];
353 u8 out[MLX5_ST_SZ_BYTES(pvlc_reg)];
356 memset(out, 0, sizeof(out));
357 memset(in, 0, sizeof(in));
359 MLX5_SET(pvlc_reg, in, local_port, pvlc->local_port);
361 MLX5_SET(pvlc_reg, in, vl_admin, pvlc->vl_admin);
363 err = mlx5_core_access_reg(dev, in, sz, out, sz, MLX5_REG_PVLC, 0,
369 pvlc->local_port = MLX5_GET(pvlc_reg, out, local_port);
370 pvlc->vl_hw_cap = MLX5_GET(pvlc_reg, out, vl_hw_cap);
371 pvlc->vl_admin = MLX5_GET(pvlc_reg, out, vl_admin);
372 pvlc->vl_operational = MLX5_GET(pvlc_reg, out, vl_operational);
377 EXPORT_SYMBOL_GPL(mlx5_core_access_pvlc);
379 int mlx5_core_access_ptys(struct mlx5_core_dev *dev,
380 struct mlx5_ptys_reg *ptys, int write)
382 int sz = MLX5_ST_SZ_BYTES(ptys_reg);
387 in = mlx5_vzalloc(sz);
391 out = mlx5_vzalloc(sz);
397 MLX5_SET(ptys_reg, in, local_port, ptys->local_port);
398 MLX5_SET(ptys_reg, in, proto_mask, ptys->proto_mask);
400 MLX5_SET(ptys_reg, in, eth_proto_capability,
401 ptys->eth_proto_cap);
402 MLX5_SET(ptys_reg, in, ib_link_width_capability,
403 ptys->ib_link_width_cap);
404 MLX5_SET(ptys_reg, in, ib_proto_capability,
406 MLX5_SET(ptys_reg, in, eth_proto_admin, ptys->eth_proto_admin);
407 MLX5_SET(ptys_reg, in, ib_link_width_admin,
408 ptys->ib_link_width_admin);
409 MLX5_SET(ptys_reg, in, ib_proto_admin, ptys->ib_proto_admin);
410 MLX5_SET(ptys_reg, in, eth_proto_oper, ptys->eth_proto_oper);
411 MLX5_SET(ptys_reg, in, ib_link_width_oper,
412 ptys->ib_link_width_oper);
413 MLX5_SET(ptys_reg, in, ib_proto_oper, ptys->ib_proto_oper);
414 MLX5_SET(ptys_reg, in, eth_proto_lp_advertise,
415 ptys->eth_proto_lp_advertise);
418 err = mlx5_core_access_reg(dev, in, sz, out, sz, MLX5_REG_PTYS, 0,
424 ptys->local_port = MLX5_GET(ptys_reg, out, local_port);
425 ptys->proto_mask = MLX5_GET(ptys_reg, out, proto_mask);
426 ptys->eth_proto_cap = MLX5_GET(ptys_reg, out,
427 eth_proto_capability);
428 ptys->ib_link_width_cap = MLX5_GET(ptys_reg, out,
429 ib_link_width_capability);
430 ptys->ib_proto_cap = MLX5_GET(ptys_reg, out,
431 ib_proto_capability);
432 ptys->eth_proto_admin = MLX5_GET(ptys_reg, out,
434 ptys->ib_link_width_admin = MLX5_GET(ptys_reg, out,
435 ib_link_width_admin);
436 ptys->ib_proto_admin = MLX5_GET(ptys_reg, out, ib_proto_admin);
437 ptys->eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
438 ptys->ib_link_width_oper = MLX5_GET(ptys_reg, out,
440 ptys->ib_proto_oper = MLX5_GET(ptys_reg, out, ib_proto_oper);
441 ptys->eth_proto_lp_advertise = MLX5_GET(ptys_reg, out,
442 eth_proto_lp_advertise);
450 EXPORT_SYMBOL_GPL(mlx5_core_access_ptys);
452 static int mtu_to_ib_mtu(int mtu)
461 printf("mlx5_core: WARN: ""invalid mtu\n");
466 int mlx5_core_access_pmtu(struct mlx5_core_dev *dev,
467 struct mlx5_pmtu_reg *pmtu, int write)
469 int sz = MLX5_ST_SZ_BYTES(pmtu_reg);
474 in = mlx5_vzalloc(sz);
478 out = mlx5_vzalloc(sz);
484 MLX5_SET(pmtu_reg, in, local_port, pmtu->local_port);
486 MLX5_SET(pmtu_reg, in, admin_mtu, pmtu->admin_mtu);
488 err = mlx5_core_access_reg(dev, in, sz, out, sz, MLX5_REG_PMTU, 0,
494 pmtu->local_port = MLX5_GET(pmtu_reg, out, local_port);
495 pmtu->max_mtu = mtu_to_ib_mtu(MLX5_GET(pmtu_reg, out,
497 pmtu->admin_mtu = mtu_to_ib_mtu(MLX5_GET(pmtu_reg, out,
499 pmtu->oper_mtu = mtu_to_ib_mtu(MLX5_GET(pmtu_reg, out,
508 EXPORT_SYMBOL_GPL(mlx5_core_access_pmtu);
510 int mlx5_query_module_num(struct mlx5_core_dev *dev, int *module_num)
512 u32 in[MLX5_ST_SZ_DW(pmlp_reg)];
513 u32 out[MLX5_ST_SZ_DW(pmlp_reg)];
517 memset(in, 0, sizeof(in));
519 MLX5_SET(pmlp_reg, in, local_port, 1);
521 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
522 sizeof(out), MLX5_REG_PMLP, 0, 0);
526 lane = MLX5_GET(pmlp_reg, out, lane0_module_mapping);
527 *module_num = lane & MLX5_EEPROM_IDENTIFIER_BYTE_MASK;
531 EXPORT_SYMBOL_GPL(mlx5_query_module_num);
533 int mlx5_query_eeprom(struct mlx5_core_dev *dev,
534 int i2c_addr, int page_num, int device_addr,
535 int size, int module_num, u32 *data, int *size_read)
537 u32 in[MLX5_ST_SZ_DW(mcia_reg)];
538 u32 out[MLX5_ST_SZ_DW(mcia_reg)];
539 u32 *ptr = (u32 *)MLX5_ADDR_OF(mcia_reg, out, dword_0);
543 memset(in, 0, sizeof(in));
544 size = min_t(int, size, MLX5_EEPROM_MAX_BYTES);
546 MLX5_SET(mcia_reg, in, l, 0);
547 MLX5_SET(mcia_reg, in, module, module_num);
548 MLX5_SET(mcia_reg, in, i2c_device_address, i2c_addr);
549 MLX5_SET(mcia_reg, in, page_number, page_num);
550 MLX5_SET(mcia_reg, in, device_address, device_addr);
551 MLX5_SET(mcia_reg, in, size, size);
553 err = mlx5_core_access_reg(dev, in, sizeof(in), out,
554 sizeof(out), MLX5_REG_MCIA, 0, 0);
558 status = MLX5_GET(mcia_reg, out, status);
562 memcpy(data, ptr, size);
566 EXPORT_SYMBOL_GPL(mlx5_query_eeprom);
568 int mlx5_vxlan_udp_port_add(struct mlx5_core_dev *dev, u16 port)
570 u32 in[MLX5_ST_SZ_DW(add_vxlan_udp_dport_in)];
571 u32 out[MLX5_ST_SZ_DW(add_vxlan_udp_dport_out)];
574 memset(in, 0, sizeof(in));
575 memset(out, 0, sizeof(out));
577 MLX5_SET(add_vxlan_udp_dport_in, in, opcode,
578 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT);
579 MLX5_SET(add_vxlan_udp_dport_in, in, vxlan_udp_port, port);
581 err = mlx5_cmd_exec_check_status(dev, in, sizeof(in), out, sizeof(out));
583 mlx5_core_err(dev, "Failed %s, port %u, err - %d",
584 mlx5_command_str(MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT),
591 int mlx5_vxlan_udp_port_delete(struct mlx5_core_dev *dev, u16 port)
593 u32 in[MLX5_ST_SZ_DW(delete_vxlan_udp_dport_in)];
594 u32 out[MLX5_ST_SZ_DW(delete_vxlan_udp_dport_out)];
597 memset(in, 0, sizeof(in));
598 memset(out, 0, sizeof(out));
600 MLX5_SET(delete_vxlan_udp_dport_in, in, opcode,
601 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT);
602 MLX5_SET(delete_vxlan_udp_dport_in, in, vxlan_udp_port, port);
604 err = mlx5_cmd_exec_check_status(dev, in, sizeof(in), out, sizeof(out));
606 mlx5_core_err(dev, "Failed %s, port %u, err - %d",
607 mlx5_command_str(MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT),
614 int mlx5_query_wol(struct mlx5_core_dev *dev, u8 *wol_mode)
616 u32 in[MLX5_ST_SZ_DW(query_wol_rol_in)];
617 u32 out[MLX5_ST_SZ_DW(query_wol_rol_out)];
620 memset(in, 0, sizeof(in));
621 memset(out, 0, sizeof(out));
623 MLX5_SET(query_wol_rol_in, in, opcode, MLX5_CMD_OP_QUERY_WOL_ROL);
625 err = mlx5_cmd_exec_check_status(dev, in, sizeof(in), out, sizeof(out));
628 *wol_mode = MLX5_GET(query_wol_rol_out, out, wol_mode);
632 EXPORT_SYMBOL_GPL(mlx5_query_wol);
634 int mlx5_query_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
635 int priority, int *is_enable)
637 u32 in[MLX5_ST_SZ_DW(query_cong_status_in)];
638 u32 out[MLX5_ST_SZ_DW(query_cong_status_out)];
641 memset(in, 0, sizeof(in));
642 memset(out, 0, sizeof(out));
646 MLX5_SET(query_cong_status_in, in, opcode,
647 MLX5_CMD_OP_QUERY_CONG_STATUS);
648 MLX5_SET(query_cong_status_in, in, cong_protocol, protocol);
649 MLX5_SET(query_cong_status_in, in, priority, priority);
651 err = mlx5_cmd_exec_check_status(mdev, in, sizeof(in),
654 *is_enable = MLX5_GET(query_cong_status_out, out, enable);
658 int mlx5_modify_port_cong_status(struct mlx5_core_dev *mdev, int protocol,
659 int priority, int enable)
661 u32 in[MLX5_ST_SZ_DW(modify_cong_status_in)];
662 u32 out[MLX5_ST_SZ_DW(modify_cong_status_out)];
664 memset(in, 0, sizeof(in));
665 memset(out, 0, sizeof(out));
667 MLX5_SET(modify_cong_status_in, in, opcode,
668 MLX5_CMD_OP_MODIFY_CONG_STATUS);
669 MLX5_SET(modify_cong_status_in, in, cong_protocol, protocol);
670 MLX5_SET(modify_cong_status_in, in, priority, priority);
671 MLX5_SET(modify_cong_status_in, in, enable, enable);
673 return mlx5_cmd_exec_check_status(mdev, in, sizeof(in),
677 int mlx5_query_port_cong_params(struct mlx5_core_dev *mdev, int protocol,
678 void *out, int out_size)
680 u32 in[MLX5_ST_SZ_DW(query_cong_params_in)];
682 memset(in, 0, sizeof(in));
684 MLX5_SET(query_cong_params_in, in, opcode,
685 MLX5_CMD_OP_QUERY_CONG_PARAMS);
686 MLX5_SET(query_cong_params_in, in, cong_protocol, protocol);
688 return mlx5_cmd_exec_check_status(mdev, in, sizeof(in),
692 int mlx5_modify_port_cong_params(struct mlx5_core_dev *mdev,
693 void *in, int in_size)
695 u32 out[MLX5_ST_SZ_DW(modify_cong_params_out)];
697 memset(out, 0, sizeof(out));
699 MLX5_SET(modify_cong_params_in, in, opcode,
700 MLX5_CMD_OP_MODIFY_CONG_PARAMS);
702 return mlx5_cmd_exec_check_status(mdev, in, in_size, out, sizeof(out));
705 int mlx5_query_port_cong_statistics(struct mlx5_core_dev *mdev, int clear,
706 void *out, int out_size)
708 u32 in[MLX5_ST_SZ_DW(query_cong_statistics_in)];
710 memset(in, 0, sizeof(in));
712 MLX5_SET(query_cong_statistics_in, in, opcode,
713 MLX5_CMD_OP_QUERY_CONG_STATISTICS);
714 MLX5_SET(query_cong_statistics_in, in, clear, clear);
716 return mlx5_cmd_exec_check_status(mdev, in, sizeof(in),