2 * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/io-mapping.h>
31 #include <dev/mlx5/driver.h>
32 #include "mlx5_core.h"
34 int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn)
36 u32 in[MLX5_ST_SZ_DW(alloc_uar_in)] = {0};
37 u32 out[MLX5_ST_SZ_DW(alloc_uar_out)] = {0};
40 MLX5_SET(alloc_uar_in, in, opcode, MLX5_CMD_OP_ALLOC_UAR);
42 err = mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
46 *uarn = MLX5_GET(alloc_uar_out, out, uar);
50 EXPORT_SYMBOL(mlx5_cmd_alloc_uar);
52 int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn)
54 u32 in[MLX5_ST_SZ_DW(dealloc_uar_in)] = {0};
55 u32 out[MLX5_ST_SZ_DW(dealloc_uar_out)] = {0};
57 MLX5_SET(dealloc_uar_in, in, opcode, MLX5_CMD_OP_DEALLOC_UAR);
58 MLX5_SET(dealloc_uar_in, in, uar, uarn);
60 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
62 EXPORT_SYMBOL(mlx5_cmd_free_uar);
64 static int need_uuar_lock(int uuarn)
66 int tot_uuars = NUM_DRIVER_UARS * MLX5_BF_REGS_PER_PAGE;
68 if (uuarn == 0 || tot_uuars - NUM_LOW_LAT_UUARS)
74 int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari)
76 int tot_uuars = NUM_DRIVER_UARS * MLX5_BF_REGS_PER_PAGE;
82 uuari->num_uars = NUM_DRIVER_UARS;
83 uuari->num_low_latency_uuars = NUM_LOW_LAT_UUARS;
85 mutex_init(&uuari->lock);
86 uuari->uars = kcalloc(uuari->num_uars, sizeof(*uuari->uars), GFP_KERNEL);
88 uuari->bfs = kcalloc(tot_uuars, sizeof(*uuari->bfs), GFP_KERNEL);
90 uuari->bitmap = kcalloc(BITS_TO_LONGS(tot_uuars), sizeof(*uuari->bitmap),
93 uuari->count = kcalloc(tot_uuars, sizeof(*uuari->count), GFP_KERNEL);
95 for (i = 0; i < uuari->num_uars; i++) {
96 err = mlx5_cmd_alloc_uar(dev, &uuari->uars[i].index);
100 addr = pci_resource_start(dev->pdev, 0) +
101 ((phys_addr_t)(uuari->uars[i].index) << PAGE_SHIFT);
102 uuari->uars[i].map = ioremap(addr, PAGE_SIZE);
103 if (!uuari->uars[i].map) {
104 mlx5_cmd_free_uar(dev, uuari->uars[i].index);
108 mlx5_core_dbg(dev, "allocated uar index 0x%x, mmaped at %p\n",
109 uuari->uars[i].index, uuari->uars[i].map);
112 for (i = 0; i < tot_uuars; i++) {
115 bf->buf_size = (1 << MLX5_CAP_GEN(dev, log_bf_reg_size)) / 2;
116 bf->uar = &uuari->uars[i / MLX5_BF_REGS_PER_PAGE];
117 bf->regreg = uuari->uars[i / MLX5_BF_REGS_PER_PAGE].map;
118 bf->reg = NULL; /* Add WC support */
119 bf->offset = (i % MLX5_BF_REGS_PER_PAGE) *
120 (1 << MLX5_CAP_GEN(dev, log_bf_reg_size)) +
122 bf->need_lock = need_uuar_lock(i);
123 spin_lock_init(&bf->lock);
124 spin_lock_init(&bf->lock32);
131 for (i--; i >= 0; i--) {
132 iounmap(uuari->uars[i].map);
133 mlx5_cmd_free_uar(dev, uuari->uars[i].index);
137 kfree(uuari->bitmap);
145 int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari)
147 int i = uuari->num_uars;
149 for (i--; i >= 0; i--) {
150 iounmap(uuari->uars[i].map);
151 mlx5_cmd_free_uar(dev, uuari->uars[i].index);
155 kfree(uuari->bitmap);
162 int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar)
165 phys_addr_t uar_bar_start;
168 err = mlx5_cmd_alloc_uar(mdev, &uar->index);
170 mlx5_core_warn(mdev, "mlx5_cmd_alloc_uar() failed, %d\n", err);
174 uar_bar_start = pci_resource_start(mdev->pdev, 0);
175 pfn = (uar_bar_start >> PAGE_SHIFT) + uar->index;
176 uar->map = ioremap(pfn << PAGE_SHIFT, PAGE_SIZE);
178 mlx5_core_warn(mdev, "ioremap() failed, %d\n", err);
183 if (mdev->priv.bf_mapping)
184 uar->bf_map = io_mapping_map_wc(mdev->priv.bf_mapping,
185 uar->index << PAGE_SHIFT,
191 mlx5_cmd_free_uar(mdev, uar->index);
195 EXPORT_SYMBOL(mlx5_alloc_map_uar);
197 void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar)
199 io_mapping_unmap(uar->bf_map);
201 mlx5_cmd_free_uar(mdev, uar->index);
203 EXPORT_SYMBOL(mlx5_unmap_free_uar);