2 * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <linux/kmod.h>
32 #include <linux/page.h>
33 #include <linux/slab.h>
34 #include <linux/if_vlan.h>
35 #include <linux/if_ether.h>
36 #include <linux/vmalloc.h>
37 #include <linux/moduleparam.h>
38 #include <linux/delay.h>
39 #include <linux/netdevice.h>
40 #include <linux/etherdevice.h>
41 #include <linux/ktime.h>
42 #include <linux/net_dim.h>
44 #include <netinet/in_systm.h>
45 #include <netinet/in.h>
46 #include <netinet/if_ether.h>
47 #include <netinet/ip.h>
48 #include <netinet/ip6.h>
49 #include <netinet/tcp.h>
50 #include <netinet/tcp_lro.h>
51 #include <netinet/udp.h>
52 #include <net/ethernet.h>
53 #include <sys/buf_ring.h>
54 #include <sys/kthread.h>
59 #include <net/rss_config.h>
60 #include <netinet/in_rss.h>
63 #include <machine/bus.h>
65 #include <dev/mlx5/driver.h>
66 #include <dev/mlx5/qp.h>
67 #include <dev/mlx5/cq.h>
68 #include <dev/mlx5/port.h>
69 #include <dev/mlx5/vport.h>
70 #include <dev/mlx5/diagnostics.h>
72 #include <dev/mlx5/mlx5_core/wq.h>
73 #include <dev/mlx5/mlx5_core/transobj.h>
74 #include <dev/mlx5/mlx5_core/mlx5_core.h>
76 #define IEEE_8021QAZ_MAX_TCS 8
78 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x7
79 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
80 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xe
82 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x7
83 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
84 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xe
86 #define MLX5E_MAX_RX_SEGS 7
88 #ifndef MLX5E_MAX_RX_BYTES
89 #define MLX5E_MAX_RX_BYTES MCLBYTES
92 #if (MLX5E_MAX_RX_SEGS == 1)
93 /* FreeBSD HW LRO is limited by 16KB - the size of max mbuf */
94 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ MJUM16BYTES
96 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ \
97 MIN(65535, MLX5E_MAX_RX_SEGS * MLX5E_MAX_RX_BYTES)
99 #define MLX5E_DIM_DEFAULT_PROFILE 3
100 #define MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO 16
101 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
102 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
103 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
104 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
105 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
106 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
107 #define MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ 0x7
108 #define MLX5E_CACHELINE_SIZE CACHE_LINE_SIZE
109 #define MLX5E_HW2SW_MTU(hwmtu) \
110 ((hwmtu) - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN))
111 #define MLX5E_SW2HW_MTU(swmtu) \
112 ((swmtu) + (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN))
113 #define MLX5E_SW2MB_MTU(swmtu) \
114 (MLX5E_SW2HW_MTU(swmtu) + MLX5E_NET_IP_ALIGN)
115 #define MLX5E_MTU_MIN 72 /* Min MTU allowed by the kernel */
116 #define MLX5E_MTU_MAX MIN(ETHERMTU_JUMBO, MJUM16BYTES) /* Max MTU of Ethernet
119 #define MLX5E_BUDGET_MAX 8192 /* RX and TX */
120 #define MLX5E_RX_BUDGET_MAX 256
121 #define MLX5E_SQ_BF_BUDGET 16
122 #define MLX5E_SQ_TX_QUEUE_SIZE 4096 /* SQ drbr queue size */
124 #define MLX5E_MAX_TX_NUM_TC 8 /* units */
125 #define MLX5E_MAX_TX_HEADER 128 /* bytes */
126 #define MLX5E_MAX_TX_PAYLOAD_SIZE 65536 /* bytes */
127 #define MLX5E_MAX_TX_MBUF_SIZE 65536 /* bytes */
128 #define MLX5E_MAX_TX_MBUF_FRAGS \
129 ((MLX5_SEND_WQE_MAX_WQEBBS * MLX5_SEND_WQEBB_NUM_DS) - \
130 (MLX5E_MAX_TX_HEADER / MLX5_SEND_WQE_DS) - \
131 1 /* the maximum value of the DS counter is 0x3F and not 0x40 */) /* units */
132 #define MLX5E_MAX_TX_INLINE \
133 (MLX5E_MAX_TX_HEADER - sizeof(struct mlx5e_tx_wqe) + \
134 sizeof(((struct mlx5e_tx_wqe *)0)->eth.inline_hdr_start)) /* bytes */
136 #define MLX5E_100MB (100000)
137 #define MLX5E_1GB (1000000)
139 MALLOC_DECLARE(M_MLX5EN);
141 struct mlx5_core_dev;
144 typedef void (mlx5e_cq_comp_t)(struct mlx5_core_cq *);
146 #define MLX5E_STATS_COUNT(a,b,c,d) a
147 #define MLX5E_STATS_VAR(a,b,c,d) b;
148 #define MLX5E_STATS_DESC(a,b,c,d) c, d,
150 #define MLX5E_VPORT_STATS(m) \
152 m(+1, u64 rx_packets, "rx_packets", "Received packets") \
153 m(+1, u64 rx_bytes, "rx_bytes", "Received bytes") \
154 m(+1, u64 tx_packets, "tx_packets", "Transmitted packets") \
155 m(+1, u64 tx_bytes, "tx_bytes", "Transmitted bytes") \
156 m(+1, u64 rx_error_packets, "rx_error_packets", "Received error packets") \
157 m(+1, u64 rx_error_bytes, "rx_error_bytes", "Received error bytes") \
158 m(+1, u64 tx_error_packets, "tx_error_packets", "Transmitted error packets") \
159 m(+1, u64 tx_error_bytes, "tx_error_bytes", "Transmitted error bytes") \
160 m(+1, u64 rx_unicast_packets, "rx_unicast_packets", "Received unicast packets") \
161 m(+1, u64 rx_unicast_bytes, "rx_unicast_bytes", "Received unicast bytes") \
162 m(+1, u64 tx_unicast_packets, "tx_unicast_packets", "Transmitted unicast packets") \
163 m(+1, u64 tx_unicast_bytes, "tx_unicast_bytes", "Transmitted unicast bytes") \
164 m(+1, u64 rx_multicast_packets, "rx_multicast_packets", "Received multicast packets") \
165 m(+1, u64 rx_multicast_bytes, "rx_multicast_bytes", "Received multicast bytes") \
166 m(+1, u64 tx_multicast_packets, "tx_multicast_packets", "Transmitted multicast packets") \
167 m(+1, u64 tx_multicast_bytes, "tx_multicast_bytes", "Transmitted multicast bytes") \
168 m(+1, u64 rx_broadcast_packets, "rx_broadcast_packets", "Received broadcast packets") \
169 m(+1, u64 rx_broadcast_bytes, "rx_broadcast_bytes", "Received broadcast bytes") \
170 m(+1, u64 tx_broadcast_packets, "tx_broadcast_packets", "Transmitted broadcast packets") \
171 m(+1, u64 tx_broadcast_bytes, "tx_broadcast_bytes", "Transmitted broadcast bytes") \
172 m(+1, u64 rx_out_of_buffer, "rx_out_of_buffer", "Receive out of buffer, no recv wqes events") \
174 m(+1, u64 tso_packets, "tso_packets", "Transmitted TSO packets") \
175 m(+1, u64 tso_bytes, "tso_bytes", "Transmitted TSO bytes") \
176 m(+1, u64 lro_packets, "lro_packets", "Received LRO packets") \
177 m(+1, u64 lro_bytes, "lro_bytes", "Received LRO bytes") \
178 m(+1, u64 sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \
179 m(+1, u64 sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \
180 m(+1, u64 rx_csum_good, "rx_csum_good", "Received checksum valid packets") \
181 m(+1, u64 rx_csum_none, "rx_csum_none", "Received no checksum packets") \
182 m(+1, u64 tx_csum_offload, "tx_csum_offload", "Transmit checksum offload packets") \
183 m(+1, u64 tx_queue_dropped, "tx_queue_dropped", "Transmit queue dropped") \
184 m(+1, u64 tx_defragged, "tx_defragged", "Transmit queue defragged") \
185 m(+1, u64 rx_wqe_err, "rx_wqe_err", "Receive WQE errors") \
186 m(+1, u64 tx_jumbo_packets, "tx_jumbo_packets", "TX packets greater than 1518 octets")
188 #define MLX5E_VPORT_STATS_NUM (0 MLX5E_VPORT_STATS(MLX5E_STATS_COUNT))
190 struct mlx5e_vport_stats {
191 struct sysctl_ctx_list ctx;
193 MLX5E_VPORT_STATS(MLX5E_STATS_VAR)
194 u32 rx_out_of_buffer_prev;
197 #define MLX5E_PPORT_IEEE802_3_STATS(m) \
198 m(+1, u64 frames_tx, "frames_tx", "Frames transmitted") \
199 m(+1, u64 frames_rx, "frames_rx", "Frames received") \
200 m(+1, u64 check_seq_err, "check_seq_err", "Sequence errors") \
201 m(+1, u64 alignment_err, "alignment_err", "Alignment errors") \
202 m(+1, u64 octets_tx, "octets_tx", "Bytes transmitted") \
203 m(+1, u64 octets_received, "octets_received", "Bytes received") \
204 m(+1, u64 multicast_xmitted, "multicast_xmitted", "Multicast transmitted") \
205 m(+1, u64 broadcast_xmitted, "broadcast_xmitted", "Broadcast transmitted") \
206 m(+1, u64 multicast_rx, "multicast_rx", "Multicast received") \
207 m(+1, u64 broadcast_rx, "broadcast_rx", "Broadcast received") \
208 m(+1, u64 in_range_len_errors, "in_range_len_errors", "In range length errors") \
209 m(+1, u64 out_of_range_len, "out_of_range_len", "Out of range length errors") \
210 m(+1, u64 too_long_errors, "too_long_errors", "Too long errors") \
211 m(+1, u64 symbol_err, "symbol_err", "Symbol errors") \
212 m(+1, u64 mac_control_tx, "mac_control_tx", "MAC control transmitted") \
213 m(+1, u64 mac_control_rx, "mac_control_rx", "MAC control received") \
214 m(+1, u64 unsupported_op_rx, "unsupported_op_rx", "Unsupported operation received") \
215 m(+1, u64 pause_ctrl_rx, "pause_ctrl_rx", "Pause control received") \
216 m(+1, u64 pause_ctrl_tx, "pause_ctrl_tx", "Pause control transmitted")
218 #define MLX5E_PPORT_RFC2819_STATS(m) \
219 m(+1, u64 drop_events, "drop_events", "Dropped events") \
220 m(+1, u64 octets, "octets", "Octets") \
221 m(+1, u64 pkts, "pkts", "Packets") \
222 m(+1, u64 broadcast_pkts, "broadcast_pkts", "Broadcast packets") \
223 m(+1, u64 multicast_pkts, "multicast_pkts", "Multicast packets") \
224 m(+1, u64 crc_align_errors, "crc_align_errors", "CRC alignment errors") \
225 m(+1, u64 undersize_pkts, "undersize_pkts", "Undersized packets") \
226 m(+1, u64 oversize_pkts, "oversize_pkts", "Oversized packets") \
227 m(+1, u64 fragments, "fragments", "Fragments") \
228 m(+1, u64 jabbers, "jabbers", "Jabbers") \
229 m(+1, u64 collisions, "collisions", "Collisions")
231 #define MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \
232 m(+1, u64 p64octets, "p64octets", "Bytes") \
233 m(+1, u64 p65to127octets, "p65to127octets", "Bytes") \
234 m(+1, u64 p128to255octets, "p128to255octets", "Bytes") \
235 m(+1, u64 p256to511octets, "p256to511octets", "Bytes") \
236 m(+1, u64 p512to1023octets, "p512to1023octets", "Bytes") \
237 m(+1, u64 p1024to1518octets, "p1024to1518octets", "Bytes") \
238 m(+1, u64 p1519to2047octets, "p1519to2047octets", "Bytes") \
239 m(+1, u64 p2048to4095octets, "p2048to4095octets", "Bytes") \
240 m(+1, u64 p4096to8191octets, "p4096to8191octets", "Bytes") \
241 m(+1, u64 p8192to10239octets, "p8192to10239octets", "Bytes")
243 #define MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \
244 m(+1, u64 in_octets, "in_octets", "In octets") \
245 m(+1, u64 in_ucast_pkts, "in_ucast_pkts", "In unicast packets") \
246 m(+1, u64 in_discards, "in_discards", "In discards") \
247 m(+1, u64 in_errors, "in_errors", "In errors") \
248 m(+1, u64 in_unknown_protos, "in_unknown_protos", "In unknown protocols") \
249 m(+1, u64 out_octets, "out_octets", "Out octets") \
250 m(+1, u64 out_ucast_pkts, "out_ucast_pkts", "Out unicast packets") \
251 m(+1, u64 out_discards, "out_discards", "Out discards") \
252 m(+1, u64 out_errors, "out_errors", "Out errors") \
253 m(+1, u64 in_multicast_pkts, "in_multicast_pkts", "In multicast packets") \
254 m(+1, u64 in_broadcast_pkts, "in_broadcast_pkts", "In broadcast packets") \
255 m(+1, u64 out_multicast_pkts, "out_multicast_pkts", "Out multicast packets") \
256 m(+1, u64 out_broadcast_pkts, "out_broadcast_pkts", "Out broadcast packets")
258 #define MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(m) \
259 m(+1, u64 port_transmit_wait_high, "port_transmit_wait_high", "Port transmit wait high") \
260 m(+1, u64 ecn_marked, "ecn_marked", "ECN marked") \
261 m(+1, u64 no_buffer_discard_mc, "no_buffer_discard_mc", "No buffer discard mc") \
262 m(+1, u64 rx_ebp, "rx_ebp", "RX EBP") \
263 m(+1, u64 tx_ebp, "tx_ebp", "TX EBP") \
264 m(+1, u64 rx_buffer_almost_full, "rx_buffer_almost_full", "RX buffer almost full") \
265 m(+1, u64 rx_buffer_full, "rx_buffer_full", "RX buffer full") \
266 m(+1, u64 rx_icrc_encapsulated, "rx_icrc_encapsulated", "RX ICRC encapsulated") \
267 m(+1, u64 ex_reserved_0, "ex_reserved_0", "Reserved") \
268 m(+1, u64 ex_reserved_1, "ex_reserved_1", "Reserved") \
269 m(+1, u64 tx_stat_p64octets, "tx_stat_p64octets", "Bytes") \
270 m(+1, u64 tx_stat_p65to127octets, "tx_stat_p65to127octets", "Bytes") \
271 m(+1, u64 tx_stat_p128to255octets, "tx_stat_p128to255octets", "Bytes") \
272 m(+1, u64 tx_stat_p256to511octets, "tx_stat_p256to511octets", "Bytes") \
273 m(+1, u64 tx_stat_p512to1023octets, "tx_stat_p512to1023octets", "Bytes") \
274 m(+1, u64 tx_stat_p1024to1518octets, "tx_stat_p1024to1518octets", "Bytes") \
275 m(+1, u64 tx_stat_p1519to2047octets, "tx_stat_p1519to2047octets", "Bytes") \
276 m(+1, u64 tx_stat_p2048to4095octets, "tx_stat_p2048to4095octets", "Bytes") \
277 m(+1, u64 tx_stat_p4096to8191octets, "tx_stat_p4096to8191octets", "Bytes") \
278 m(+1, u64 tx_stat_p8192to10239octets, "tx_stat_p8192to10239octets", "Bytes")
280 #define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \
281 m(+1, u64 time_since_last_clear, "time_since_last_clear", \
282 "Time since the last counters clear event (msec)") \
283 m(+1, u64 symbol_errors, "symbol_errors", "Symbol errors") \
284 m(+1, u64 sync_headers_errors, "sync_headers_errors", "Sync header error counter") \
285 m(+1, u64 bip_errors_lane0, "edpl_bip_errors_lane0", \
286 "Indicates the number of PRBS errors on lane 0") \
287 m(+1, u64 bip_errors_lane1, "edpl_bip_errors_lane1", \
288 "Indicates the number of PRBS errors on lane 1") \
289 m(+1, u64 bip_errors_lane2, "edpl_bip_errors_lane2", \
290 "Indicates the number of PRBS errors on lane 2") \
291 m(+1, u64 bip_errors_lane3, "edpl_bip_errors_lane3", \
292 "Indicates the number of PRBS errors on lane 3") \
293 m(+1, u64 fc_corrected_blocks_lane0, "fc_corrected_blocks_lane0", \
294 "FEC correctable block counter lane 0") \
295 m(+1, u64 fc_corrected_blocks_lane1, "fc_corrected_blocks_lane1", \
296 "FEC correctable block counter lane 1") \
297 m(+1, u64 fc_corrected_blocks_lane2, "fc_corrected_blocks_lane2", \
298 "FEC correctable block counter lane 2") \
299 m(+1, u64 fc_corrected_blocks_lane3, "fc_corrected_blocks_lane3", \
300 "FEC correctable block counter lane 3") \
301 m(+1, u64 rs_corrected_blocks, "rs_corrected_blocks", \
302 "FEC correcable block counter") \
303 m(+1, u64 rs_uncorrectable_blocks, "rs_uncorrectable_blocks", \
304 "FEC uncorrecable block counter") \
305 m(+1, u64 rs_no_errors_blocks, "rs_no_errors_blocks", \
306 "The number of RS-FEC blocks received that had no errors") \
307 m(+1, u64 rs_single_error_blocks, "rs_single_error_blocks", \
308 "The number of corrected RS-FEC blocks received that had" \
309 "exactly 1 error symbol") \
310 m(+1, u64 rs_corrected_symbols_total, "rs_corrected_symbols_total", \
311 "Port FEC corrected symbol counter") \
312 m(+1, u64 rs_corrected_symbols_lane0, "rs_corrected_symbols_lane0", \
313 "FEC corrected symbol counter lane 0") \
314 m(+1, u64 rs_corrected_symbols_lane1, "rs_corrected_symbols_lane1", \
315 "FEC corrected symbol counter lane 1") \
316 m(+1, u64 rs_corrected_symbols_lane2, "rs_corrected_symbols_lane2", \
317 "FEC corrected symbol counter lane 2") \
318 m(+1, u64 rs_corrected_symbols_lane3, "rs_corrected_symbols_lane3", \
319 "FEC corrected symbol counter lane 3")
321 /* Per priority statistics for PFC */
322 #define MLX5E_PPORT_PER_PRIO_STATS_SUB(m,n,p) \
323 m(n, p, +1, u64, rx_octets, "rx_octets", "Received octets") \
324 m(n, p, +1, u64, reserved_0, "reserved_0", "Reserved") \
325 m(n, p, +1, u64, reserved_1, "reserved_1", "Reserved") \
326 m(n, p, +1, u64, reserved_2, "reserved_2", "Reserved") \
327 m(n, p, +1, u64, rx_frames, "rx_frames", "Received frames") \
328 m(n, p, +1, u64, tx_octets, "tx_octets", "Transmitted octets") \
329 m(n, p, +1, u64, reserved_3, "reserved_3", "Reserved") \
330 m(n, p, +1, u64, reserved_4, "reserved_4", "Reserved") \
331 m(n, p, +1, u64, reserved_5, "reserved_5", "Reserved") \
332 m(n, p, +1, u64, tx_frames, "tx_frames", "Transmitted frames") \
333 m(n, p, +1, u64, rx_pause, "rx_pause", "Received pause frames") \
334 m(n, p, +1, u64, rx_pause_duration, "rx_pause_duration", \
335 "Received pause duration") \
336 m(n, p, +1, u64, tx_pause, "tx_pause", "Transmitted pause frames") \
337 m(n, p, +1, u64, tx_pause_duration, "tx_pause_duration", \
338 "Transmitted pause duration") \
339 m(n, p, +1, u64, rx_pause_transition, "rx_pause_transition", \
340 "Received pause transitions") \
341 m(n, p, +1, u64, rx_discards, "rx_discards", "Discarded received frames") \
342 m(n, p, +1, u64, device_stall_minor_watermark, \
343 "device_stall_minor_watermark", "Device stall minor watermark") \
344 m(n, p, +1, u64, device_stall_critical_watermark, \
345 "device_stall_critical_watermark", "Device stall critical watermark")
347 #define MLX5E_PPORT_PER_PRIO_STATS_PREFIX(m,p,c,t,f,s,d) \
348 m(c, t pri_##p##_##f, "prio" #p "_" s, "Priority " #p " - " d)
350 #define MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO 8
352 #define MLX5E_PPORT_PER_PRIO_STATS(m) \
353 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,0) \
354 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,1) \
355 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,2) \
356 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,3) \
357 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,4) \
358 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,5) \
359 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,6) \
360 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,7)
363 * Make sure to update mlx5e_update_pport_counters()
364 * when adding a new MLX5E_PPORT_STATS block
366 #define MLX5E_PPORT_STATS(m) \
367 MLX5E_PPORT_PER_PRIO_STATS(m) \
368 MLX5E_PPORT_IEEE802_3_STATS(m) \
369 MLX5E_PPORT_RFC2819_STATS(m)
371 #define MLX5E_PORT_STATS_DEBUG(m) \
372 MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \
373 MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \
374 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \
375 MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(m)
377 #define MLX5E_PPORT_IEEE802_3_STATS_NUM \
378 (0 MLX5E_PPORT_IEEE802_3_STATS(MLX5E_STATS_COUNT))
379 #define MLX5E_PPORT_RFC2819_STATS_NUM \
380 (0 MLX5E_PPORT_RFC2819_STATS(MLX5E_STATS_COUNT))
381 #define MLX5E_PPORT_STATS_NUM \
382 (0 MLX5E_PPORT_STATS(MLX5E_STATS_COUNT))
384 #define MLX5E_PPORT_PER_PRIO_STATS_NUM \
385 (0 MLX5E_PPORT_PER_PRIO_STATS(MLX5E_STATS_COUNT))
386 #define MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM \
387 (0 MLX5E_PPORT_RFC2819_STATS_DEBUG(MLX5E_STATS_COUNT))
388 #define MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM \
389 (0 MLX5E_PPORT_RFC2863_STATS_DEBUG(MLX5E_STATS_COUNT))
390 #define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM \
391 (0 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(MLX5E_STATS_COUNT))
392 #define MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM \
393 (0 MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG(MLX5E_STATS_COUNT))
394 #define MLX5E_PORT_STATS_DEBUG_NUM \
395 (0 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_COUNT))
397 struct mlx5e_pport_stats {
398 struct sysctl_ctx_list ctx;
400 MLX5E_PPORT_STATS(MLX5E_STATS_VAR)
403 struct mlx5e_port_stats_debug {
404 struct sysctl_ctx_list ctx;
406 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_VAR)
409 #define MLX5E_RQ_STATS(m) \
410 m(+1, u64 packets, "packets", "Received packets") \
411 m(+1, u64 bytes, "bytes", "Received bytes") \
412 m(+1, u64 csum_none, "csum_none", "Received packets") \
413 m(+1, u64 lro_packets, "lro_packets", "Received LRO packets") \
414 m(+1, u64 lro_bytes, "lro_bytes", "Received LRO bytes") \
415 m(+1, u64 sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \
416 m(+1, u64 sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \
417 m(+1, u64 wqe_err, "wqe_err", "Received packets")
419 #define MLX5E_RQ_STATS_NUM (0 MLX5E_RQ_STATS(MLX5E_STATS_COUNT))
421 struct mlx5e_rq_stats {
422 struct sysctl_ctx_list ctx;
424 MLX5E_RQ_STATS(MLX5E_STATS_VAR)
427 #define MLX5E_SQ_STATS(m) \
428 m(+1, u64 packets, "packets", "Transmitted packets") \
429 m(+1, u64 bytes, "bytes", "Transmitted bytes") \
430 m(+1, u64 tso_packets, "tso_packets", "Transmitted packets") \
431 m(+1, u64 tso_bytes, "tso_bytes", "Transmitted bytes") \
432 m(+1, u64 csum_offload_none, "csum_offload_none", "Transmitted packets") \
433 m(+1, u64 defragged, "defragged", "Transmitted packets") \
434 m(+1, u64 dropped, "dropped", "Transmitted packets") \
435 m(+1, u64 nop, "nop", "Transmitted packets")
437 #define MLX5E_SQ_STATS_NUM (0 MLX5E_SQ_STATS(MLX5E_STATS_COUNT))
439 struct mlx5e_sq_stats {
440 struct sysctl_ctx_list ctx;
442 MLX5E_SQ_STATS(MLX5E_STATS_VAR)
446 struct mlx5e_vport_stats vport;
447 struct mlx5e_pport_stats pport;
448 struct mlx5e_port_stats_debug port_stats_debug;
451 struct mlx5e_rq_param {
452 u32 rqc [MLX5_ST_SZ_DW(rqc)];
453 struct mlx5_wq_param wq;
456 struct mlx5e_sq_param {
457 u32 sqc [MLX5_ST_SZ_DW(sqc)];
458 struct mlx5_wq_param wq;
461 struct mlx5e_cq_param {
462 u32 cqc [MLX5_ST_SZ_DW(cqc)];
463 struct mlx5_wq_param wq;
466 struct mlx5e_params {
470 u8 default_vlan_prio;
472 u8 rx_cq_moderation_mode;
473 u8 tx_cq_moderation_mode;
474 u16 rx_cq_moderation_usec;
475 u16 rx_cq_moderation_pkts;
476 u16 tx_cq_moderation_usec;
477 u16 tx_cq_moderation_pkts;
482 u16 rx_hash_log_tbl_sz;
483 u32 tx_pauseframe_control __aligned(4);
484 u32 rx_pauseframe_control __aligned(4);
485 u32 tx_priority_flow_control __aligned(4);
486 u32 rx_priority_flow_control __aligned(4);
488 u8 tx_min_inline_mode;
492 #define MLX5E_PARAMS(m) \
493 m(+1, u64 tx_queue_size_max, "tx_queue_size_max", "Max send queue size") \
494 m(+1, u64 rx_queue_size_max, "rx_queue_size_max", "Max receive queue size") \
495 m(+1, u64 tx_queue_size, "tx_queue_size", "Default send queue size") \
496 m(+1, u64 rx_queue_size, "rx_queue_size", "Default receive queue size") \
497 m(+1, u64 channels, "channels", "Default number of channels") \
498 m(+1, u64 channels_rsss, "channels_rsss", "Default channels receive side scaling stride") \
499 m(+1, u64 coalesce_usecs_max, "coalesce_usecs_max", "Maximum usecs for joining packets") \
500 m(+1, u64 coalesce_pkts_max, "coalesce_pkts_max", "Maximum packets to join") \
501 m(+1, u64 rx_coalesce_usecs, "rx_coalesce_usecs", "Limit in usec for joining rx packets") \
502 m(+1, u64 rx_coalesce_pkts, "rx_coalesce_pkts", "Maximum number of rx packets to join") \
503 m(+1, u64 rx_coalesce_mode, "rx_coalesce_mode", "0: EQE fixed mode 1: CQE fixed mode 2: EQE auto mode 3: CQE auto mode") \
504 m(+1, u64 tx_coalesce_usecs, "tx_coalesce_usecs", "Limit in usec for joining tx packets") \
505 m(+1, u64 tx_coalesce_pkts, "tx_coalesce_pkts", "Maximum number of tx packets to join") \
506 m(+1, u64 tx_coalesce_mode, "tx_coalesce_mode", "0: EQE mode 1: CQE mode") \
507 m(+1, u64 tx_completion_fact, "tx_completion_fact", "1..MAX: Completion event ratio") \
508 m(+1, u64 tx_completion_fact_max, "tx_completion_fact_max", "Maximum completion event ratio") \
509 m(+1, u64 hw_lro, "hw_lro", "set to enable hw_lro") \
510 m(+1, u64 cqe_zipping, "cqe_zipping", "0 : CQE zipping disabled") \
511 m(+1, u64 modify_tx_dma, "modify_tx_dma", "0: Enable TX 1: Disable TX") \
512 m(+1, u64 modify_rx_dma, "modify_rx_dma", "0: Enable RX 1: Disable RX") \
513 m(+1, u64 diag_pci_enable, "diag_pci_enable", "0: Disabled 1: Enabled") \
514 m(+1, u64 diag_general_enable, "diag_general_enable", "0: Disabled 1: Enabled") \
515 m(+1, u64 hw_mtu, "hw_mtu", "Current hardware MTU value") \
516 m(+1, u64 mc_local_lb, "mc_local_lb", "0: Local multicast loopback enabled 1: Disabled") \
517 m(+1, u64 uc_local_lb, "uc_local_lb", "0: Local unicast loopback enabled 1: Disabled")
520 #define MLX5E_PARAMS_NUM (0 MLX5E_PARAMS(MLX5E_STATS_COUNT))
522 struct mlx5e_params_ethtool {
524 MLX5E_PARAMS(MLX5E_STATS_VAR)
525 u64 max_bw_value[IEEE_8021QAZ_MAX_TCS];
526 u8 max_bw_share[IEEE_8021QAZ_MAX_TCS];
527 u8 prio_tc[IEEE_8021QAZ_MAX_TCS];
528 u8 dscp2prio[MLX5_MAX_SUPPORTED_DSCP];
532 /* EEPROM Standards for plug in modules */
533 #ifndef MLX5E_ETH_MODULE_SFF_8472
534 #define MLX5E_ETH_MODULE_SFF_8472 0x1
535 #define MLX5E_ETH_MODULE_SFF_8472_LEN 128
538 #ifndef MLX5E_ETH_MODULE_SFF_8636
539 #define MLX5E_ETH_MODULE_SFF_8636 0x2
540 #define MLX5E_ETH_MODULE_SFF_8636_LEN 256
543 #ifndef MLX5E_ETH_MODULE_SFF_8436
544 #define MLX5E_ETH_MODULE_SFF_8436 0x3
545 #define MLX5E_ETH_MODULE_SFF_8436_LEN 256
548 /* EEPROM I2C Addresses */
549 #define MLX5E_I2C_ADDR_LOW 0x50
550 #define MLX5E_I2C_ADDR_HIGH 0x51
552 #define MLX5E_EEPROM_LOW_PAGE 0x0
553 #define MLX5E_EEPROM_HIGH_PAGE 0x3
555 #define MLX5E_EEPROM_HIGH_PAGE_OFFSET 128
556 #define MLX5E_EEPROM_PAGE_LENGTH 256
558 #define MLX5E_EEPROM_INFO_BYTES 0x3
561 /* data path - accessed per cqe */
564 /* data path - accessed per HW polling */
565 struct mlx5_core_cq mcq;
568 struct mlx5e_priv *priv;
569 struct mlx5_wq_ctrl wq_ctrl;
570 } __aligned(MLX5E_CACHELINE_SIZE);
572 struct mlx5e_rq_mbuf {
573 bus_dmamap_t dma_map;
580 struct mlx5_wq_ll wq;
582 bus_dma_tag_t dma_tag;
585 struct mlx5e_rq_mbuf *mbuf;
587 struct mlx5e_rq_stats stats;
590 volatile int enabled;
593 /* Dynamic Interrupt Moderation */
597 struct mlx5_wq_ctrl wq_ctrl;
599 struct mlx5e_channel *channel;
600 struct callout watchdog;
601 } __aligned(MLX5E_CACHELINE_SIZE);
603 struct mlx5e_sq_mbuf {
604 bus_dmamap_t dma_map;
615 struct mlx5e_snd_tag {
616 struct m_snd_tag m_snd_tag; /* send tag */
617 u32 type; /* tag type */
623 bus_dma_tag_t dma_tag;
624 struct mtx comp_lock;
626 /* dirtied @completion */
630 u16 pc __aligned(MLX5E_CACHELINE_SIZE);
632 u16 cev_counter; /* completion event counter */
633 u16 cev_factor; /* completion event factor */
634 u16 cev_next_state; /* next completion event state */
635 #define MLX5E_CEV_STATE_INITIAL 0 /* timer not started */
636 #define MLX5E_CEV_STATE_SEND_NOPS 1 /* send NOPs */
637 #define MLX5E_CEV_STATE_HOLD_NOPS 2 /* don't send NOPs yet */
638 u16 running; /* set if SQ is running */
639 struct callout cev_callout;
644 struct mlx5e_sq_stats stats;
648 /* pointers to per packet info: write@xmit, read@completion */
649 struct mlx5e_sq_mbuf *mbuf;
653 struct mlx5_wq_cyc wq;
662 #define MLX5E_INSERT_VLAN 1
663 #define MLX5E_INSERT_NON_VLAN 2
666 struct mlx5_wq_ctrl wq_ctrl;
667 struct mlx5e_priv *priv;
669 } __aligned(MLX5E_CACHELINE_SIZE);
672 mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
677 return ((sq->wq.sz_m1 & (cc - pc)) >= n || cc == pc);
681 mlx5e_sq_queue_level(struct mlx5e_sq *sq)
692 return (((sq->wq.sz_m1 & (pc - cc)) *
693 IF_SND_QUEUE_LEVEL_MAX) / sq->wq.sz_m1);
696 struct mlx5e_channel {
699 struct mlx5e_snd_tag tag;
700 struct mlx5e_sq sq[MLX5E_MAX_TX_NUM_TC];
705 struct mlx5e_priv *priv;
708 } __aligned(MLX5E_CACHELINE_SIZE);
710 enum mlx5e_traffic_types {
715 MLX5E_TT_IPV4_IPSEC_AH,
716 MLX5E_TT_IPV6_IPSEC_AH,
717 MLX5E_TT_IPV4_IPSEC_ESP,
718 MLX5E_TT_IPV6_IPSEC_ESP,
726 MLX5E_RQT_SPREADING = 0,
727 MLX5E_RQT_DEFAULT_RQ = 1,
731 struct mlx5_flow_rule;
733 struct mlx5e_eth_addr_info {
734 u8 addr [ETH_ALEN + 2];
736 /* flow table rule per traffic type */
737 struct mlx5_flow_rule *ft_rule[MLX5E_NUM_TT];
740 #define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE)
742 struct mlx5e_eth_addr_hash_node;
744 struct mlx5e_eth_addr_hash_head {
745 struct mlx5e_eth_addr_hash_node *lh_first;
748 struct mlx5e_eth_addr_db {
749 struct mlx5e_eth_addr_hash_head if_uc[MLX5E_ETH_ADDR_HASH_SIZE];
750 struct mlx5e_eth_addr_hash_head if_mc[MLX5E_ETH_ADDR_HASH_SIZE];
751 struct mlx5e_eth_addr_info broadcast;
752 struct mlx5e_eth_addr_info allmulti;
753 struct mlx5e_eth_addr_info promisc;
754 bool broadcast_enabled;
755 bool allmulti_enabled;
756 bool promisc_enabled;
760 MLX5E_STATE_ASYNC_EVENTS_ENABLE,
765 MLX5_BW_NO_LIMIT = 0,
766 MLX5_100_MBPS_UNIT = 3,
770 struct mlx5e_vlan_db {
771 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
772 struct mlx5_flow_rule *active_vlans_ft_rule[VLAN_N_VID];
773 struct mlx5_flow_rule *untagged_ft_rule;
774 struct mlx5_flow_rule *any_cvlan_ft_rule;
775 struct mlx5_flow_rule *any_svlan_ft_rule;
776 bool filter_disabled;
779 struct mlx5e_flow_table {
781 struct mlx5_flow_table *t;
782 struct mlx5_flow_group **g;
785 struct mlx5e_flow_tables {
786 struct mlx5_flow_namespace *ns;
787 struct mlx5e_flow_table vlan;
788 struct mlx5e_flow_table main;
789 struct mlx5e_flow_table inner_rss;
796 #define MLX5E_TSTMP_PREC 10
798 struct mlx5e_clbr_point {
801 uint64_t clbr_hw_prev;
802 uint64_t clbr_hw_curr;
807 struct mlx5_core_dev *mdev; /* must be first */
809 /* priv data path fields - start */
810 int order_base_2_num_channels;
811 int queue_mapping_channel_mask;
813 int default_vlan_prio;
814 /* priv data path fields - end */
818 #define PRIV_LOCK(priv) sx_xlock(&(priv)->state_lock)
819 #define PRIV_UNLOCK(priv) sx_xunlock(&(priv)->state_lock)
820 #define PRIV_LOCKED(priv) sx_xlocked(&(priv)->state_lock)
821 struct sx state_lock; /* Protects Interface state */
822 struct mlx5_uar cq_uar;
825 struct mlx5_core_mr mr;
826 volatile unsigned int channel_refs;
828 u32 tisn[MLX5E_MAX_TX_NUM_TC];
830 u32 tirn[MLX5E_NUM_TT];
832 struct mlx5e_flow_tables fts;
833 struct mlx5e_eth_addr_db eth_addr;
834 struct mlx5e_vlan_db vlan;
836 struct mlx5e_params params;
837 struct mlx5e_params_ethtool params_ethtool;
838 union mlx5_core_pci_diagnostics params_pci;
839 union mlx5_core_general_diagnostics params_general;
840 struct mtx async_events_mtx; /* sync hw events */
841 struct work_struct update_stats_work;
842 struct work_struct update_carrier_work;
843 struct work_struct set_rx_mode_work;
844 MLX5_DECLARE_DOORBELL_LOCK(doorbell_lock)
847 struct sysctl_ctx_list sysctl_ctx;
848 struct sysctl_oid *sysctl_ifnet;
849 struct sysctl_oid *sysctl_hw;
851 struct mlx5e_stats stats;
854 struct workqueue_struct *wq;
856 eventhandler_tag vlan_detach;
857 eventhandler_tag vlan_attach;
858 struct ifmedia media;
859 int media_status_last;
860 int media_active_last;
862 struct callout watchdog;
864 struct mlx5e_rl_priv_data rl;
867 struct callout tstmp_clbr;
870 struct mlx5e_clbr_point clbr_points[2];
873 struct mlx5e_channel channel[];
876 #define MLX5E_NET_IP_ALIGN 2
878 struct mlx5e_tx_wqe {
879 struct mlx5_wqe_ctrl_seg ctrl;
880 struct mlx5_wqe_eth_seg eth;
883 struct mlx5e_rx_wqe {
884 struct mlx5_wqe_srq_next_seg next;
885 struct mlx5_wqe_data_seg data[];
888 /* the size of the structure above must be power of two */
889 CTASSERT(powerof2(sizeof(struct mlx5e_rx_wqe)));
891 struct mlx5e_eeprom {
903 #define MLX5E_FLD_MAX(typ, fld) ((1ULL << __mlx5_bit_sz(typ, fld)) - 1ULL)
905 int mlx5e_xmit(struct ifnet *, struct mbuf *);
907 int mlx5e_open_locked(struct ifnet *);
908 int mlx5e_close_locked(struct ifnet *);
910 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, int event);
911 void mlx5e_rx_cq_comp(struct mlx5_core_cq *);
912 void mlx5e_tx_cq_comp(struct mlx5_core_cq *);
913 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
915 void mlx5e_dim_work(struct work_struct *);
916 void mlx5e_dim_build_cq_param(struct mlx5e_priv *, struct mlx5e_cq_param *);
918 int mlx5e_open_flow_table(struct mlx5e_priv *priv);
919 void mlx5e_close_flow_table(struct mlx5e_priv *priv);
920 void mlx5e_set_rx_mode_core(struct mlx5e_priv *priv);
921 void mlx5e_set_rx_mode_work(struct work_struct *work);
923 void mlx5e_vlan_rx_add_vid(void *, struct ifnet *, u16);
924 void mlx5e_vlan_rx_kill_vid(void *, struct ifnet *, u16);
925 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
926 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
927 int mlx5e_add_all_vlan_rules(struct mlx5e_priv *priv);
928 void mlx5e_del_all_vlan_rules(struct mlx5e_priv *priv);
931 mlx5e_tx_notify_hw(struct mlx5e_sq *sq, u32 *wqe, int bf_sz)
933 u16 ofst = MLX5_BF_OFFSET + sq->bf_offset;
935 /* ensure wqe is visible to device before updating doorbell record */
938 *sq->wq.db = cpu_to_be32(sq->pc);
941 * Ensure the doorbell record is visible to device before ringing
947 __iowrite64_copy(sq->uar.bf_map + ofst, wqe, bf_sz);
949 /* flush the write-combining mapped buffer */
953 mlx5_write64(wqe, sq->uar.map + ofst,
954 MLX5_GET_DOORBELL_LOCK(&sq->priv->doorbell_lock));
957 sq->bf_offset ^= sq->bf_buf_size;
961 mlx5e_cq_arm(struct mlx5e_cq *cq, spinlock_t *dblock)
963 struct mlx5_core_cq *mcq;
966 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, dblock, cq->wq.cc);
970 mlx5e_ref_channel(struct mlx5e_priv *priv)
973 KASSERT(priv->channel_refs < INT_MAX,
974 ("Channel refs will overflow"));
975 atomic_fetchadd_int(&priv->channel_refs, 1);
979 mlx5e_unref_channel(struct mlx5e_priv *priv)
982 KASSERT(priv->channel_refs > 0,
983 ("Channel refs is not greater than zero"));
984 atomic_fetchadd_int(&priv->channel_refs, -1);
987 extern const struct ethtool_ops mlx5e_ethtool_ops;
988 void mlx5e_create_ethtool(struct mlx5e_priv *);
989 void mlx5e_create_stats(struct sysctl_ctx_list *,
990 struct sysctl_oid_list *, const char *,
991 const char **, unsigned, u64 *);
992 void mlx5e_send_nop(struct mlx5e_sq *, u32);
993 void mlx5e_sq_cev_timeout(void *);
994 int mlx5e_refresh_channel_params(struct mlx5e_priv *);
995 int mlx5e_open_cq(struct mlx5e_priv *, struct mlx5e_cq_param *,
996 struct mlx5e_cq *, mlx5e_cq_comp_t *, int eq_ix);
997 void mlx5e_close_cq(struct mlx5e_cq *);
998 void mlx5e_free_sq_db(struct mlx5e_sq *);
999 int mlx5e_alloc_sq_db(struct mlx5e_sq *);
1000 int mlx5e_enable_sq(struct mlx5e_sq *, struct mlx5e_sq_param *, int tis_num);
1001 int mlx5e_modify_sq(struct mlx5e_sq *, int curr_state, int next_state);
1002 void mlx5e_disable_sq(struct mlx5e_sq *);
1003 void mlx5e_drain_sq(struct mlx5e_sq *);
1004 void mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value);
1005 void mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value);
1006 void mlx5e_resume_sq(struct mlx5e_sq *sq);
1007 void mlx5e_update_sq_inline(struct mlx5e_sq *sq);
1008 void mlx5e_refresh_sq_inline(struct mlx5e_priv *priv);
1010 #endif /* _MLX5_EN_H_ */