2 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <linux/kmod.h>
32 #include <linux/page.h>
33 #include <linux/slab.h>
34 #include <linux/if_vlan.h>
35 #include <linux/if_ether.h>
36 #include <linux/vmalloc.h>
37 #include <linux/moduleparam.h>
38 #include <linux/delay.h>
39 #include <linux/netdevice.h>
40 #include <linux/etherdevice.h>
42 #include <netinet/in_systm.h>
43 #include <netinet/in.h>
44 #include <netinet/if_ether.h>
45 #include <netinet/ip.h>
46 #include <netinet/ip6.h>
47 #include <netinet/tcp.h>
48 #include <netinet/tcp_lro.h>
49 #include <netinet/udp.h>
50 #include <net/ethernet.h>
51 #include <sys/buf_ring.h>
52 #include <sys/kthread.h>
57 #include <net/rss_config.h>
58 #include <netinet/in_rss.h>
61 #include <machine/bus.h>
63 #include <dev/mlx5/driver.h>
64 #include <dev/mlx5/qp.h>
65 #include <dev/mlx5/cq.h>
66 #include <dev/mlx5/port.h>
67 #include <dev/mlx5/vport.h>
68 #include <dev/mlx5/diagnostics.h>
70 #include <dev/mlx5/mlx5_core/wq.h>
71 #include <dev/mlx5/mlx5_core/transobj.h>
72 #include <dev/mlx5/mlx5_core/mlx5_core.h>
74 #define IEEE_8021QAZ_MAX_TCS 8
76 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x7
77 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
78 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xe
80 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x7
81 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
82 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xe
84 #define MLX5E_MAX_RX_SEGS 7
86 #ifndef MLX5E_MAX_RX_BYTES
87 #define MLX5E_MAX_RX_BYTES MCLBYTES
90 #if (MLX5E_MAX_RX_SEGS == 1)
91 /* FreeBSD HW LRO is limited by 16KB - the size of max mbuf */
92 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ MJUM16BYTES
94 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ \
95 MIN(65535, MLX5E_MAX_RX_SEGS * MLX5E_MAX_RX_BYTES)
97 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
98 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
99 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
100 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
101 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
102 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
103 #define MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ 0x7
104 #define MLX5E_CACHELINE_SIZE CACHE_LINE_SIZE
105 #define MLX5E_HW2SW_MTU(hwmtu) \
106 ((hwmtu) - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN))
107 #define MLX5E_SW2HW_MTU(swmtu) \
108 ((swmtu) + (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN))
109 #define MLX5E_SW2MB_MTU(swmtu) \
110 (MLX5E_SW2HW_MTU(swmtu) + MLX5E_NET_IP_ALIGN)
111 #define MLX5E_MTU_MIN 72 /* Min MTU allowed by the kernel */
112 #define MLX5E_MTU_MAX MIN(ETHERMTU_JUMBO, MJUM16BYTES) /* Max MTU of Ethernet
115 #define MLX5E_BUDGET_MAX 8192 /* RX and TX */
116 #define MLX5E_RX_BUDGET_MAX 256
117 #define MLX5E_SQ_BF_BUDGET 16
118 #define MLX5E_SQ_TX_QUEUE_SIZE 4096 /* SQ drbr queue size */
120 #define MLX5E_MAX_TX_NUM_TC 8 /* units */
121 #define MLX5E_MAX_TX_HEADER 128 /* bytes */
122 #define MLX5E_MAX_TX_PAYLOAD_SIZE 65536 /* bytes */
123 #define MLX5E_MAX_TX_MBUF_SIZE 65536 /* bytes */
124 #define MLX5E_MAX_TX_MBUF_FRAGS \
125 ((MLX5_SEND_WQE_MAX_WQEBBS * MLX5_SEND_WQEBB_NUM_DS) - \
126 (MLX5E_MAX_TX_HEADER / MLX5_SEND_WQE_DS) - \
127 1 /* the maximum value of the DS counter is 0x3F and not 0x40 */) /* units */
128 #define MLX5E_MAX_TX_INLINE \
129 (MLX5E_MAX_TX_HEADER - sizeof(struct mlx5e_tx_wqe) + \
130 sizeof(((struct mlx5e_tx_wqe *)0)->eth.inline_hdr_start)) /* bytes */
132 #define MLX5E_100MB (100000)
133 #define MLX5E_1GB (1000000)
135 MALLOC_DECLARE(M_MLX5EN);
137 struct mlx5_core_dev;
140 typedef void (mlx5e_cq_comp_t)(struct mlx5_core_cq *);
142 #define MLX5E_STATS_COUNT(a,b,c,d) a
143 #define MLX5E_STATS_VAR(a,b,c,d) b;
144 #define MLX5E_STATS_DESC(a,b,c,d) c, d,
146 #define MLX5E_VPORT_STATS(m) \
148 m(+1, u64 rx_packets, "rx_packets", "Received packets") \
149 m(+1, u64 rx_bytes, "rx_bytes", "Received bytes") \
150 m(+1, u64 tx_packets, "tx_packets", "Transmitted packets") \
151 m(+1, u64 tx_bytes, "tx_bytes", "Transmitted bytes") \
152 m(+1, u64 rx_error_packets, "rx_error_packets", "Received error packets") \
153 m(+1, u64 rx_error_bytes, "rx_error_bytes", "Received error bytes") \
154 m(+1, u64 tx_error_packets, "tx_error_packets", "Transmitted error packets") \
155 m(+1, u64 tx_error_bytes, "tx_error_bytes", "Transmitted error bytes") \
156 m(+1, u64 rx_unicast_packets, "rx_unicast_packets", "Received unicast packets") \
157 m(+1, u64 rx_unicast_bytes, "rx_unicast_bytes", "Received unicast bytes") \
158 m(+1, u64 tx_unicast_packets, "tx_unicast_packets", "Transmitted unicast packets") \
159 m(+1, u64 tx_unicast_bytes, "tx_unicast_bytes", "Transmitted unicast bytes") \
160 m(+1, u64 rx_multicast_packets, "rx_multicast_packets", "Received multicast packets") \
161 m(+1, u64 rx_multicast_bytes, "rx_multicast_bytes", "Received multicast bytes") \
162 m(+1, u64 tx_multicast_packets, "tx_multicast_packets", "Transmitted multicast packets") \
163 m(+1, u64 tx_multicast_bytes, "tx_multicast_bytes", "Transmitted multicast bytes") \
164 m(+1, u64 rx_broadcast_packets, "rx_broadcast_packets", "Received broadcast packets") \
165 m(+1, u64 rx_broadcast_bytes, "rx_broadcast_bytes", "Received broadcast bytes") \
166 m(+1, u64 tx_broadcast_packets, "tx_broadcast_packets", "Transmitted broadcast packets") \
167 m(+1, u64 tx_broadcast_bytes, "tx_broadcast_bytes", "Transmitted broadcast bytes") \
168 m(+1, u64 rx_out_of_buffer, "rx_out_of_buffer", "Receive out of buffer, no recv wqes events") \
170 m(+1, u64 tso_packets, "tso_packets", "Transmitted TSO packets") \
171 m(+1, u64 tso_bytes, "tso_bytes", "Transmitted TSO bytes") \
172 m(+1, u64 lro_packets, "lro_packets", "Received LRO packets") \
173 m(+1, u64 lro_bytes, "lro_bytes", "Received LRO bytes") \
174 m(+1, u64 sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \
175 m(+1, u64 sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \
176 m(+1, u64 rx_csum_good, "rx_csum_good", "Received checksum valid packets") \
177 m(+1, u64 rx_csum_none, "rx_csum_none", "Received no checksum packets") \
178 m(+1, u64 tx_csum_offload, "tx_csum_offload", "Transmit checksum offload packets") \
179 m(+1, u64 tx_queue_dropped, "tx_queue_dropped", "Transmit queue dropped") \
180 m(+1, u64 tx_defragged, "tx_defragged", "Transmit queue defragged") \
181 m(+1, u64 rx_wqe_err, "rx_wqe_err", "Receive WQE errors") \
182 m(+1, u64 tx_jumbo_packets, "tx_jumbo_packets", "TX packets greater than 1518 octets")
184 #define MLX5E_VPORT_STATS_NUM (0 MLX5E_VPORT_STATS(MLX5E_STATS_COUNT))
186 struct mlx5e_vport_stats {
187 struct sysctl_ctx_list ctx;
189 MLX5E_VPORT_STATS(MLX5E_STATS_VAR)
190 u32 rx_out_of_buffer_prev;
193 #define MLX5E_PPORT_IEEE802_3_STATS(m) \
194 m(+1, u64 frames_tx, "frames_tx", "Frames transmitted") \
195 m(+1, u64 frames_rx, "frames_rx", "Frames received") \
196 m(+1, u64 check_seq_err, "check_seq_err", "Sequence errors") \
197 m(+1, u64 alignment_err, "alignment_err", "Alignment errors") \
198 m(+1, u64 octets_tx, "octets_tx", "Bytes transmitted") \
199 m(+1, u64 octets_received, "octets_received", "Bytes received") \
200 m(+1, u64 multicast_xmitted, "multicast_xmitted", "Multicast transmitted") \
201 m(+1, u64 broadcast_xmitted, "broadcast_xmitted", "Broadcast transmitted") \
202 m(+1, u64 multicast_rx, "multicast_rx", "Multicast received") \
203 m(+1, u64 broadcast_rx, "broadcast_rx", "Broadcast received") \
204 m(+1, u64 in_range_len_errors, "in_range_len_errors", "In range length errors") \
205 m(+1, u64 out_of_range_len, "out_of_range_len", "Out of range length errors") \
206 m(+1, u64 too_long_errors, "too_long_errors", "Too long errors") \
207 m(+1, u64 symbol_err, "symbol_err", "Symbol errors") \
208 m(+1, u64 mac_control_tx, "mac_control_tx", "MAC control transmitted") \
209 m(+1, u64 mac_control_rx, "mac_control_rx", "MAC control received") \
210 m(+1, u64 unsupported_op_rx, "unsupported_op_rx", "Unsupported operation received") \
211 m(+1, u64 pause_ctrl_rx, "pause_ctrl_rx", "Pause control received") \
212 m(+1, u64 pause_ctrl_tx, "pause_ctrl_tx", "Pause control transmitted")
214 #define MLX5E_PPORT_RFC2819_STATS(m) \
215 m(+1, u64 drop_events, "drop_events", "Dropped events") \
216 m(+1, u64 octets, "octets", "Octets") \
217 m(+1, u64 pkts, "pkts", "Packets") \
218 m(+1, u64 broadcast_pkts, "broadcast_pkts", "Broadcast packets") \
219 m(+1, u64 multicast_pkts, "multicast_pkts", "Multicast packets") \
220 m(+1, u64 crc_align_errors, "crc_align_errors", "CRC alignment errors") \
221 m(+1, u64 undersize_pkts, "undersize_pkts", "Undersized packets") \
222 m(+1, u64 oversize_pkts, "oversize_pkts", "Oversized packets") \
223 m(+1, u64 fragments, "fragments", "Fragments") \
224 m(+1, u64 jabbers, "jabbers", "Jabbers") \
225 m(+1, u64 collisions, "collisions", "Collisions")
227 #define MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \
228 m(+1, u64 p64octets, "p64octets", "Bytes") \
229 m(+1, u64 p65to127octets, "p65to127octets", "Bytes") \
230 m(+1, u64 p128to255octets, "p128to255octets", "Bytes") \
231 m(+1, u64 p256to511octets, "p256to511octets", "Bytes") \
232 m(+1, u64 p512to1023octets, "p512to1023octets", "Bytes") \
233 m(+1, u64 p1024to1518octets, "p1024to1518octets", "Bytes") \
234 m(+1, u64 p1519to2047octets, "p1519to2047octets", "Bytes") \
235 m(+1, u64 p2048to4095octets, "p2048to4095octets", "Bytes") \
236 m(+1, u64 p4096to8191octets, "p4096to8191octets", "Bytes") \
237 m(+1, u64 p8192to10239octets, "p8192to10239octets", "Bytes")
239 #define MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \
240 m(+1, u64 in_octets, "in_octets", "In octets") \
241 m(+1, u64 in_ucast_pkts, "in_ucast_pkts", "In unicast packets") \
242 m(+1, u64 in_discards, "in_discards", "In discards") \
243 m(+1, u64 in_errors, "in_errors", "In errors") \
244 m(+1, u64 in_unknown_protos, "in_unknown_protos", "In unknown protocols") \
245 m(+1, u64 out_octets, "out_octets", "Out octets") \
246 m(+1, u64 out_ucast_pkts, "out_ucast_pkts", "Out unicast packets") \
247 m(+1, u64 out_discards, "out_discards", "Out discards") \
248 m(+1, u64 out_errors, "out_errors", "Out errors") \
249 m(+1, u64 in_multicast_pkts, "in_multicast_pkts", "In multicast packets") \
250 m(+1, u64 in_broadcast_pkts, "in_broadcast_pkts", "In broadcast packets") \
251 m(+1, u64 out_multicast_pkts, "out_multicast_pkts", "Out multicast packets") \
252 m(+1, u64 out_broadcast_pkts, "out_broadcast_pkts", "Out broadcast packets")
254 #define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \
255 m(+1, u64 time_since_last_clear, "time_since_last_clear", \
256 "Time since the last counters clear event (msec)") \
257 m(+1, u64 symbol_errors, "symbol_errors", "Symbol errors") \
258 m(+1, u64 sync_headers_errors, "sync_headers_errors", "Sync header error counter") \
259 m(+1, u64 bip_errors_lane0, "edpl_bip_errors_lane0", \
260 "Indicates the number of PRBS errors on lane 0") \
261 m(+1, u64 bip_errors_lane1, "edpl_bip_errors_lane1", \
262 "Indicates the number of PRBS errors on lane 1") \
263 m(+1, u64 bip_errors_lane2, "edpl_bip_errors_lane2", \
264 "Indicates the number of PRBS errors on lane 2") \
265 m(+1, u64 bip_errors_lane3, "edpl_bip_errors_lane3", \
266 "Indicates the number of PRBS errors on lane 3") \
267 m(+1, u64 fc_corrected_blocks_lane0, "fc_corrected_blocks_lane0", \
268 "FEC correctable block counter lane 0") \
269 m(+1, u64 fc_corrected_blocks_lane1, "fc_corrected_blocks_lane1", \
270 "FEC correctable block counter lane 1") \
271 m(+1, u64 fc_corrected_blocks_lane2, "fc_corrected_blocks_lane2", \
272 "FEC correctable block counter lane 2") \
273 m(+1, u64 fc_corrected_blocks_lane3, "fc_corrected_blocks_lane3", \
274 "FEC correctable block counter lane 3") \
275 m(+1, u64 rs_corrected_blocks, "rs_corrected_blocks", \
276 "FEC correcable block counter") \
277 m(+1, u64 rs_uncorrectable_blocks, "rs_uncorrectable_blocks", \
278 "FEC uncorrecable block counter") \
279 m(+1, u64 rs_no_errors_blocks, "rs_no_errors_blocks", \
280 "The number of RS-FEC blocks received that had no errors") \
281 m(+1, u64 rs_single_error_blocks, "rs_single_error_blocks", \
282 "The number of corrected RS-FEC blocks received that had" \
283 "exactly 1 error symbol") \
284 m(+1, u64 rs_corrected_symbols_total, "rs_corrected_symbols_total", \
285 "Port FEC corrected symbol counter") \
286 m(+1, u64 rs_corrected_symbols_lane0, "rs_corrected_symbols_lane0", \
287 "FEC corrected symbol counter lane 0") \
288 m(+1, u64 rs_corrected_symbols_lane1, "rs_corrected_symbols_lane1", \
289 "FEC corrected symbol counter lane 1") \
290 m(+1, u64 rs_corrected_symbols_lane2, "rs_corrected_symbols_lane2", \
291 "FEC corrected symbol counter lane 2") \
292 m(+1, u64 rs_corrected_symbols_lane3, "rs_corrected_symbols_lane3", \
293 "FEC corrected symbol counter lane 3")
295 /* Per priority statistics for PFC */
296 #define MLX5E_PPORT_PER_PRIO_STATS_SUB(m,n,p) \
297 m(n, p, +1, u64, rx_octets, "rx_octets", "Received octets") \
298 m(n, p, +1, u64, reserved_0, "reserved_0", "Reserved") \
299 m(n, p, +1, u64, reserved_1, "reserved_1", "Reserved") \
300 m(n, p, +1, u64, reserved_2, "reserved_2", "Reserved") \
301 m(n, p, +1, u64, rx_frames, "rx_frames", "Received frames") \
302 m(n, p, +1, u64, tx_octets, "tx_octets", "Transmitted octets") \
303 m(n, p, +1, u64, reserved_3, "reserved_3", "Reserved") \
304 m(n, p, +1, u64, reserved_4, "reserved_4", "Reserved") \
305 m(n, p, +1, u64, reserved_5, "reserved_5", "Reserved") \
306 m(n, p, +1, u64, tx_frames, "tx_frames", "Transmitted frames") \
307 m(n, p, +1, u64, rx_pause, "rx_pause", "Received pause frames") \
308 m(n, p, +1, u64, rx_pause_duration, "rx_pause_duration", \
309 "Received pause duration") \
310 m(n, p, +1, u64, tx_pause, "tx_pause", "Transmitted pause frames") \
311 m(n, p, +1, u64, tx_pause_duration, "tx_pause_duration", \
312 "Transmitted pause duration") \
313 m(n, p, +1, u64, rx_pause_transition, "rx_pause_transition", \
314 "Received pause transitions") \
315 m(n, p, +1, u64, rx_discards, "rx_discards", "Discarded received frames") \
316 m(n, p, +1, u64, device_stall_minor_watermark, \
317 "device_stall_minor_watermark", "Device stall minor watermark") \
318 m(n, p, +1, u64, device_stall_critical_watermark, \
319 "device_stall_critical_watermark", "Device stall critical watermark")
321 #define MLX5E_PPORT_PER_PRIO_STATS_PREFIX(m,p,c,t,f,s,d) \
322 m(c, t pri_##p##_##f, "prio" #p "_" s, "Priority " #p " - " d)
324 #define MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO 8
326 #define MLX5E_PPORT_PER_PRIO_STATS(m) \
327 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,0) \
328 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,1) \
329 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,2) \
330 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,3) \
331 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,4) \
332 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,5) \
333 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,6) \
334 MLX5E_PPORT_PER_PRIO_STATS_SUB(MLX5E_PPORT_PER_PRIO_STATS_PREFIX,m,7)
337 * Make sure to update mlx5e_update_pport_counters()
338 * when adding a new MLX5E_PPORT_STATS block
340 #define MLX5E_PPORT_STATS(m) \
341 MLX5E_PPORT_PER_PRIO_STATS(m) \
342 MLX5E_PPORT_IEEE802_3_STATS(m) \
343 MLX5E_PPORT_RFC2819_STATS(m)
345 #define MLX5E_PORT_STATS_DEBUG(m) \
346 MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \
347 MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \
348 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m)
350 #define MLX5E_PPORT_IEEE802_3_STATS_NUM \
351 (0 MLX5E_PPORT_IEEE802_3_STATS(MLX5E_STATS_COUNT))
352 #define MLX5E_PPORT_RFC2819_STATS_NUM \
353 (0 MLX5E_PPORT_RFC2819_STATS(MLX5E_STATS_COUNT))
354 #define MLX5E_PPORT_STATS_NUM \
355 (0 MLX5E_PPORT_STATS(MLX5E_STATS_COUNT))
357 #define MLX5E_PPORT_PER_PRIO_STATS_NUM \
358 (0 MLX5E_PPORT_PER_PRIO_STATS(MLX5E_STATS_COUNT))
359 #define MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM \
360 (0 MLX5E_PPORT_RFC2819_STATS_DEBUG(MLX5E_STATS_COUNT))
361 #define MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM \
362 (0 MLX5E_PPORT_RFC2863_STATS_DEBUG(MLX5E_STATS_COUNT))
363 #define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM \
364 (0 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(MLX5E_STATS_COUNT))
365 #define MLX5E_PORT_STATS_DEBUG_NUM \
366 (0 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_COUNT))
368 struct mlx5e_pport_stats {
369 struct sysctl_ctx_list ctx;
371 MLX5E_PPORT_STATS(MLX5E_STATS_VAR)
374 struct mlx5e_port_stats_debug {
375 struct sysctl_ctx_list ctx;
377 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_VAR)
380 #define MLX5E_RQ_STATS(m) \
381 m(+1, u64 packets, "packets", "Received packets") \
382 m(+1, u64 csum_none, "csum_none", "Received packets") \
383 m(+1, u64 lro_packets, "lro_packets", "Received packets") \
384 m(+1, u64 lro_bytes, "lro_bytes", "Received packets") \
385 m(+1, u64 sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \
386 m(+1, u64 sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \
387 m(+1, u64 wqe_err, "wqe_err", "Received packets")
389 #define MLX5E_RQ_STATS_NUM (0 MLX5E_RQ_STATS(MLX5E_STATS_COUNT))
391 struct mlx5e_rq_stats {
392 struct sysctl_ctx_list ctx;
394 MLX5E_RQ_STATS(MLX5E_STATS_VAR)
397 #define MLX5E_SQ_STATS(m) \
398 m(+1, u64 packets, "packets", "Transmitted packets") \
399 m(+1, u64 tso_packets, "tso_packets", "Transmitted packets") \
400 m(+1, u64 tso_bytes, "tso_bytes", "Transmitted bytes") \
401 m(+1, u64 csum_offload_none, "csum_offload_none", "Transmitted packets") \
402 m(+1, u64 defragged, "defragged", "Transmitted packets") \
403 m(+1, u64 dropped, "dropped", "Transmitted packets") \
404 m(+1, u64 nop, "nop", "Transmitted packets")
406 #define MLX5E_SQ_STATS_NUM (0 MLX5E_SQ_STATS(MLX5E_STATS_COUNT))
408 struct mlx5e_sq_stats {
409 struct sysctl_ctx_list ctx;
411 MLX5E_SQ_STATS(MLX5E_STATS_VAR)
415 struct mlx5e_vport_stats vport;
416 struct mlx5e_pport_stats pport;
417 struct mlx5e_port_stats_debug port_stats_debug;
420 struct mlx5e_rq_param {
421 u32 rqc [MLX5_ST_SZ_DW(rqc)];
422 struct mlx5_wq_param wq;
425 struct mlx5e_sq_param {
426 u32 sqc [MLX5_ST_SZ_DW(sqc)];
427 struct mlx5_wq_param wq;
430 struct mlx5e_cq_param {
431 u32 cqc [MLX5_ST_SZ_DW(cqc)];
432 struct mlx5_wq_param wq;
435 struct mlx5e_params {
439 u8 default_vlan_prio;
441 u8 rx_cq_moderation_mode;
442 u8 tx_cq_moderation_mode;
443 u16 rx_cq_moderation_usec;
444 u16 rx_cq_moderation_pkts;
445 u16 tx_cq_moderation_usec;
446 u16 tx_cq_moderation_pkts;
451 u16 rx_hash_log_tbl_sz;
452 u32 tx_pauseframe_control __aligned(4);
453 u32 rx_pauseframe_control __aligned(4);
454 u32 tx_priority_flow_control __aligned(4);
455 u32 rx_priority_flow_control __aligned(4);
457 u8 tx_min_inline_mode;
461 #define MLX5E_PARAMS(m) \
462 m(+1, u64 tx_queue_size_max, "tx_queue_size_max", "Max send queue size") \
463 m(+1, u64 rx_queue_size_max, "rx_queue_size_max", "Max receive queue size") \
464 m(+1, u64 tx_queue_size, "tx_queue_size", "Default send queue size") \
465 m(+1, u64 rx_queue_size, "rx_queue_size", "Default receive queue size") \
466 m(+1, u64 channels, "channels", "Default number of channels") \
467 m(+1, u64 channels_rsss, "channels_rsss", "Default channels receive side scaling stride") \
468 m(+1, u64 coalesce_usecs_max, "coalesce_usecs_max", "Maximum usecs for joining packets") \
469 m(+1, u64 coalesce_pkts_max, "coalesce_pkts_max", "Maximum packets to join") \
470 m(+1, u64 rx_coalesce_usecs, "rx_coalesce_usecs", "Limit in usec for joining rx packets") \
471 m(+1, u64 rx_coalesce_pkts, "rx_coalesce_pkts", "Maximum number of rx packets to join") \
472 m(+1, u64 rx_coalesce_mode, "rx_coalesce_mode", "0: EQE mode 1: CQE mode") \
473 m(+1, u64 tx_coalesce_usecs, "tx_coalesce_usecs", "Limit in usec for joining tx packets") \
474 m(+1, u64 tx_coalesce_pkts, "tx_coalesce_pkts", "Maximum number of tx packets to join") \
475 m(+1, u64 tx_coalesce_mode, "tx_coalesce_mode", "0: EQE mode 1: CQE mode") \
476 m(+1, u64 tx_completion_fact, "tx_completion_fact", "1..MAX: Completion event ratio") \
477 m(+1, u64 tx_completion_fact_max, "tx_completion_fact_max", "Maximum completion event ratio") \
478 m(+1, u64 hw_lro, "hw_lro", "set to enable hw_lro") \
479 m(+1, u64 cqe_zipping, "cqe_zipping", "0 : CQE zipping disabled") \
480 m(+1, u64 modify_tx_dma, "modify_tx_dma", "0: Enable TX 1: Disable TX") \
481 m(+1, u64 modify_rx_dma, "modify_rx_dma", "0: Enable RX 1: Disable RX") \
482 m(+1, u64 diag_pci_enable, "diag_pci_enable", "0: Disabled 1: Enabled") \
483 m(+1, u64 diag_general_enable, "diag_general_enable", "0: Disabled 1: Enabled") \
484 m(+1, u64 hw_mtu, "hw_mtu", "Current hardware MTU value") \
485 m(+1, u64 mc_local_lb, "mc_local_lb", "0: Local multicast loopback enabled 1: Disabled") \
486 m(+1, u64 uc_local_lb, "uc_local_lb", "0: Local unicast loopback enabled 1: Disabled")
489 #define MLX5E_PARAMS_NUM (0 MLX5E_PARAMS(MLX5E_STATS_COUNT))
491 struct mlx5e_params_ethtool {
493 MLX5E_PARAMS(MLX5E_STATS_VAR)
494 u64 max_bw_value[IEEE_8021QAZ_MAX_TCS];
495 u8 max_bw_share[IEEE_8021QAZ_MAX_TCS];
496 u8 prio_tc[IEEE_8021QAZ_MAX_TCS];
497 u8 dscp2prio[MLX5_MAX_SUPPORTED_DSCP];
501 /* EEPROM Standards for plug in modules */
502 #ifndef MLX5E_ETH_MODULE_SFF_8472
503 #define MLX5E_ETH_MODULE_SFF_8472 0x1
504 #define MLX5E_ETH_MODULE_SFF_8472_LEN 128
507 #ifndef MLX5E_ETH_MODULE_SFF_8636
508 #define MLX5E_ETH_MODULE_SFF_8636 0x2
509 #define MLX5E_ETH_MODULE_SFF_8636_LEN 256
512 #ifndef MLX5E_ETH_MODULE_SFF_8436
513 #define MLX5E_ETH_MODULE_SFF_8436 0x3
514 #define MLX5E_ETH_MODULE_SFF_8436_LEN 256
517 /* EEPROM I2C Addresses */
518 #define MLX5E_I2C_ADDR_LOW 0x50
519 #define MLX5E_I2C_ADDR_HIGH 0x51
521 #define MLX5E_EEPROM_LOW_PAGE 0x0
522 #define MLX5E_EEPROM_HIGH_PAGE 0x3
524 #define MLX5E_EEPROM_HIGH_PAGE_OFFSET 128
525 #define MLX5E_EEPROM_PAGE_LENGTH 256
527 #define MLX5E_EEPROM_INFO_BYTES 0x3
530 /* data path - accessed per cqe */
533 /* data path - accessed per HW polling */
534 struct mlx5_core_cq mcq;
537 struct mlx5e_priv *priv;
538 struct mlx5_wq_ctrl wq_ctrl;
539 } __aligned(MLX5E_CACHELINE_SIZE);
541 struct mlx5e_rq_mbuf {
542 bus_dmamap_t dma_map;
549 struct mlx5_wq_ll wq;
551 bus_dma_tag_t dma_tag;
554 struct mlx5e_rq_mbuf *mbuf;
556 struct mlx5e_rq_stats stats;
559 volatile int enabled;
563 struct mlx5_wq_ctrl wq_ctrl;
565 struct mlx5e_channel *channel;
566 struct callout watchdog;
567 } __aligned(MLX5E_CACHELINE_SIZE);
569 struct mlx5e_sq_mbuf {
570 bus_dmamap_t dma_map;
584 bus_dma_tag_t dma_tag;
585 struct mtx comp_lock;
587 /* dirtied @completion */
591 u16 pc __aligned(MLX5E_CACHELINE_SIZE);
593 u16 cev_counter; /* completion event counter */
594 u16 cev_factor; /* completion event factor */
595 u16 cev_next_state; /* next completion event state */
596 #define MLX5E_CEV_STATE_INITIAL 0 /* timer not started */
597 #define MLX5E_CEV_STATE_SEND_NOPS 1 /* send NOPs */
598 #define MLX5E_CEV_STATE_HOLD_NOPS 2 /* don't send NOPs yet */
599 u16 stopped; /* set if SQ is stopped */
600 struct callout cev_callout;
605 struct mlx5e_sq_stats stats;
609 /* pointers to per packet info: write@xmit, read@completion */
610 struct mlx5e_sq_mbuf *mbuf;
614 struct mlx5_wq_cyc wq;
623 #define MLX5E_INSERT_VLAN 1
624 #define MLX5E_INSERT_NON_VLAN 2
627 struct mlx5_wq_ctrl wq_ctrl;
628 struct mlx5e_priv *priv;
630 } __aligned(MLX5E_CACHELINE_SIZE);
633 mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
638 return ((sq->wq.sz_m1 & (cc - pc)) >= n || cc == pc);
641 struct mlx5e_channel {
644 struct mlx5e_sq sq[MLX5E_MAX_TX_NUM_TC];
650 struct mlx5e_priv *priv;
653 } __aligned(MLX5E_CACHELINE_SIZE);
655 enum mlx5e_traffic_types {
660 MLX5E_TT_IPV4_IPSEC_AH,
661 MLX5E_TT_IPV6_IPSEC_AH,
662 MLX5E_TT_IPV4_IPSEC_ESP,
663 MLX5E_TT_IPV6_IPSEC_ESP,
671 MLX5E_RQT_SPREADING = 0,
672 MLX5E_RQT_DEFAULT_RQ = 1,
676 struct mlx5_flow_rule;
678 struct mlx5e_eth_addr_info {
679 u8 addr [ETH_ALEN + 2];
681 /* flow table rule per traffic type */
682 struct mlx5_flow_rule *ft_rule[MLX5E_NUM_TT];
685 #define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE)
687 struct mlx5e_eth_addr_hash_node;
689 struct mlx5e_eth_addr_hash_head {
690 struct mlx5e_eth_addr_hash_node *lh_first;
693 struct mlx5e_eth_addr_db {
694 struct mlx5e_eth_addr_hash_head if_uc[MLX5E_ETH_ADDR_HASH_SIZE];
695 struct mlx5e_eth_addr_hash_head if_mc[MLX5E_ETH_ADDR_HASH_SIZE];
696 struct mlx5e_eth_addr_info broadcast;
697 struct mlx5e_eth_addr_info allmulti;
698 struct mlx5e_eth_addr_info promisc;
699 bool broadcast_enabled;
700 bool allmulti_enabled;
701 bool promisc_enabled;
705 MLX5E_STATE_ASYNC_EVENTS_ENABLE,
710 MLX5_BW_NO_LIMIT = 0,
711 MLX5_100_MBPS_UNIT = 3,
715 struct mlx5e_vlan_db {
716 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
717 struct mlx5_flow_rule *active_vlans_ft_rule[VLAN_N_VID];
718 struct mlx5_flow_rule *untagged_ft_rule;
719 struct mlx5_flow_rule *any_cvlan_ft_rule;
720 struct mlx5_flow_rule *any_svlan_ft_rule;
721 bool filter_disabled;
724 struct mlx5e_flow_table {
726 struct mlx5_flow_table *t;
727 struct mlx5_flow_group **g;
730 struct mlx5e_flow_tables {
731 struct mlx5_flow_namespace *ns;
732 struct mlx5e_flow_table vlan;
733 struct mlx5e_flow_table main;
734 struct mlx5e_flow_table inner_rss;
741 #define MLX5E_TSTMP_PREC 10
743 struct mlx5e_clbr_point {
746 uint64_t clbr_hw_prev;
747 uint64_t clbr_hw_curr;
752 struct mlx5_core_dev *mdev; /* must be first */
754 /* priv data path fields - start */
755 int order_base_2_num_channels;
756 int queue_mapping_channel_mask;
758 int default_vlan_prio;
759 /* priv data path fields - end */
763 #define PRIV_LOCK(priv) sx_xlock(&(priv)->state_lock)
764 #define PRIV_UNLOCK(priv) sx_xunlock(&(priv)->state_lock)
765 #define PRIV_LOCKED(priv) sx_xlocked(&(priv)->state_lock)
766 struct sx state_lock; /* Protects Interface state */
767 struct mlx5_uar cq_uar;
770 struct mlx5_core_mr mr;
772 struct mlx5e_channel *volatile *channel;
773 u32 tisn[MLX5E_MAX_TX_NUM_TC];
775 u32 tirn[MLX5E_NUM_TT];
777 struct mlx5e_flow_tables fts;
778 struct mlx5e_eth_addr_db eth_addr;
779 struct mlx5e_vlan_db vlan;
781 struct mlx5e_params params;
782 struct mlx5e_params_ethtool params_ethtool;
783 union mlx5_core_pci_diagnostics params_pci;
784 union mlx5_core_general_diagnostics params_general;
785 struct mtx async_events_mtx; /* sync hw events */
786 struct work_struct update_stats_work;
787 struct work_struct update_carrier_work;
788 struct work_struct set_rx_mode_work;
789 MLX5_DECLARE_DOORBELL_LOCK(doorbell_lock)
792 struct sysctl_ctx_list sysctl_ctx;
793 struct sysctl_oid *sysctl_ifnet;
794 struct sysctl_oid *sysctl_hw;
796 struct mlx5e_stats stats;
799 struct workqueue_struct *wq;
801 eventhandler_tag vlan_detach;
802 eventhandler_tag vlan_attach;
803 struct ifmedia media;
804 int media_status_last;
805 int media_active_last;
807 struct callout watchdog;
809 struct mlx5e_rl_priv_data rl;
812 struct callout tstmp_clbr;
815 struct mlx5e_clbr_point clbr_points[2];
819 #define MLX5E_NET_IP_ALIGN 2
821 struct mlx5e_tx_wqe {
822 struct mlx5_wqe_ctrl_seg ctrl;
823 struct mlx5_wqe_eth_seg eth;
826 struct mlx5e_rx_wqe {
827 struct mlx5_wqe_srq_next_seg next;
828 struct mlx5_wqe_data_seg data[];
831 /* the size of the structure above must be power of two */
832 CTASSERT(powerof2(sizeof(struct mlx5e_rx_wqe)));
834 struct mlx5e_eeprom {
846 #define MLX5E_FLD_MAX(typ, fld) ((1ULL << __mlx5_bit_sz(typ, fld)) - 1ULL)
848 int mlx5e_xmit(struct ifnet *, struct mbuf *);
850 int mlx5e_open_locked(struct ifnet *);
851 int mlx5e_close_locked(struct ifnet *);
853 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, int event);
854 void mlx5e_rx_cq_comp(struct mlx5_core_cq *);
855 void mlx5e_tx_cq_comp(struct mlx5_core_cq *);
856 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
858 int mlx5e_open_flow_table(struct mlx5e_priv *priv);
859 void mlx5e_close_flow_table(struct mlx5e_priv *priv);
860 void mlx5e_set_rx_mode_core(struct mlx5e_priv *priv);
861 void mlx5e_set_rx_mode_work(struct work_struct *work);
863 void mlx5e_vlan_rx_add_vid(void *, struct ifnet *, u16);
864 void mlx5e_vlan_rx_kill_vid(void *, struct ifnet *, u16);
865 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
866 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
867 int mlx5e_add_all_vlan_rules(struct mlx5e_priv *priv);
868 void mlx5e_del_all_vlan_rules(struct mlx5e_priv *priv);
871 mlx5e_tx_notify_hw(struct mlx5e_sq *sq, u32 *wqe, int bf_sz)
873 u16 ofst = MLX5_BF_OFFSET + sq->bf_offset;
875 /* ensure wqe is visible to device before updating doorbell record */
878 *sq->wq.db = cpu_to_be32(sq->pc);
881 * Ensure the doorbell record is visible to device before ringing
887 __iowrite64_copy(sq->uar.bf_map + ofst, wqe, bf_sz);
889 /* flush the write-combining mapped buffer */
893 mlx5_write64(wqe, sq->uar.map + ofst,
894 MLX5_GET_DOORBELL_LOCK(&sq->priv->doorbell_lock));
897 sq->bf_offset ^= sq->bf_buf_size;
901 mlx5e_cq_arm(struct mlx5e_cq *cq, spinlock_t *dblock)
903 struct mlx5_core_cq *mcq;
906 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, dblock, cq->wq.cc);
909 extern const struct ethtool_ops mlx5e_ethtool_ops;
910 void mlx5e_create_ethtool(struct mlx5e_priv *);
911 void mlx5e_create_stats(struct sysctl_ctx_list *,
912 struct sysctl_oid_list *, const char *,
913 const char **, unsigned, u64 *);
914 void mlx5e_send_nop(struct mlx5e_sq *, u32);
915 void mlx5e_sq_cev_timeout(void *);
916 int mlx5e_refresh_channel_params(struct mlx5e_priv *);
917 int mlx5e_open_cq(struct mlx5e_priv *, struct mlx5e_cq_param *,
918 struct mlx5e_cq *, mlx5e_cq_comp_t *, int eq_ix);
919 void mlx5e_close_cq(struct mlx5e_cq *);
920 void mlx5e_free_sq_db(struct mlx5e_sq *);
921 int mlx5e_alloc_sq_db(struct mlx5e_sq *);
922 int mlx5e_enable_sq(struct mlx5e_sq *, struct mlx5e_sq_param *, int tis_num);
923 int mlx5e_modify_sq(struct mlx5e_sq *, int curr_state, int next_state);
924 void mlx5e_disable_sq(struct mlx5e_sq *);
925 void mlx5e_drain_sq(struct mlx5e_sq *);
926 void mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value);
927 void mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value);
928 void mlx5e_resume_sq(struct mlx5e_sq *sq);
929 void mlx5e_update_sq_inline(struct mlx5e_sq *sq);
930 void mlx5e_refresh_sq_inline(struct mlx5e_priv *priv);
932 #endif /* _MLX5_EN_H_ */