2 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <linux/kmod.h>
32 #include <linux/page.h>
33 #include <linux/slab.h>
34 #include <linux/if_vlan.h>
35 #include <linux/if_ether.h>
36 #include <linux/vmalloc.h>
37 #include <linux/moduleparam.h>
38 #include <linux/delay.h>
39 #include <linux/netdevice.h>
40 #include <linux/etherdevice.h>
42 #include <netinet/in_systm.h>
43 #include <netinet/in.h>
44 #include <netinet/if_ether.h>
45 #include <netinet/ip.h>
46 #include <netinet/ip6.h>
47 #include <netinet/tcp.h>
48 #include <netinet/tcp_lro.h>
49 #include <netinet/udp.h>
50 #include <net/ethernet.h>
51 #include <sys/buf_ring.h>
56 #include <net/rss_config.h>
57 #include <netinet/in_rss.h>
60 #include <machine/bus.h>
62 #include <dev/mlx5/driver.h>
63 #include <dev/mlx5/qp.h>
64 #include <dev/mlx5/cq.h>
65 #include <dev/mlx5/port.h>
66 #include <dev/mlx5/vport.h>
67 #include <dev/mlx5/diagnostics.h>
69 #include <dev/mlx5/mlx5_core/wq.h>
70 #include <dev/mlx5/mlx5_core/transobj.h>
71 #include <dev/mlx5/mlx5_core/mlx5_core.h>
73 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x7
74 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
75 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xe
77 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x7
78 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
79 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xe
81 /* freeBSD HW LRO is limited by 16KB - the size of max mbuf */
82 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ MJUM16BYTES
83 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
84 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
85 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
86 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
87 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
88 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
89 #define MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ 0x7
90 #define MLX5E_CACHELINE_SIZE CACHE_LINE_SIZE
91 #define MLX5E_HW2SW_MTU(hwmtu) \
92 ((hwmtu) - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN))
93 #define MLX5E_SW2HW_MTU(swmtu) \
94 ((swmtu) + (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN))
95 #define MLX5E_SW2MB_MTU(swmtu) \
96 (MLX5E_SW2HW_MTU(swmtu) + MLX5E_NET_IP_ALIGN)
97 #define MLX5E_MTU_MIN 72 /* Min MTU allowed by the kernel */
98 #define MLX5E_MTU_MAX MIN(ETHERMTU_JUMBO, MJUM16BYTES) /* Max MTU of Ethernet
101 #define MLX5E_BUDGET_MAX 8192 /* RX and TX */
102 #define MLX5E_RX_BUDGET_MAX 256
103 #define MLX5E_SQ_BF_BUDGET 16
104 #define MLX5E_SQ_TX_QUEUE_SIZE 4096 /* SQ drbr queue size */
106 #define MLX5E_MAX_TX_NUM_TC 8 /* units */
107 #define MLX5E_MAX_TX_HEADER 128 /* bytes */
108 #define MLX5E_MAX_TX_PAYLOAD_SIZE 65536 /* bytes */
109 #define MLX5E_MAX_TX_MBUF_SIZE 65536 /* bytes */
110 #define MLX5E_MAX_TX_MBUF_FRAGS \
111 ((MLX5_SEND_WQE_MAX_WQEBBS * MLX5_SEND_WQEBB_NUM_DS) - \
112 (MLX5E_MAX_TX_HEADER / MLX5_SEND_WQE_DS)) /* units */
113 #define MLX5E_MAX_TX_INLINE \
114 (MLX5E_MAX_TX_HEADER - sizeof(struct mlx5e_tx_wqe) + \
115 sizeof(((struct mlx5e_tx_wqe *)0)->eth.inline_hdr_start)) /* bytes */
117 MALLOC_DECLARE(M_MLX5EN);
119 struct mlx5_core_dev;
122 typedef void (mlx5e_cq_comp_t)(struct mlx5_core_cq *);
124 #define MLX5E_STATS_COUNT(a,b,c,d) a
125 #define MLX5E_STATS_VAR(a,b,c,d) b;
126 #define MLX5E_STATS_DESC(a,b,c,d) c, d,
128 #define MLX5E_VPORT_STATS(m) \
130 m(+1, u64 rx_packets, "rx_packets", "Received packets") \
131 m(+1, u64 rx_bytes, "rx_bytes", "Received bytes") \
132 m(+1, u64 tx_packets, "tx_packets", "Transmitted packets") \
133 m(+1, u64 tx_bytes, "tx_bytes", "Transmitted bytes") \
134 m(+1, u64 rx_error_packets, "rx_error_packets", "Received error packets") \
135 m(+1, u64 rx_error_bytes, "rx_error_bytes", "Received error bytes") \
136 m(+1, u64 tx_error_packets, "tx_error_packets", "Transmitted error packets") \
137 m(+1, u64 tx_error_bytes, "tx_error_bytes", "Transmitted error bytes") \
138 m(+1, u64 rx_unicast_packets, "rx_unicast_packets", "Received unicast packets") \
139 m(+1, u64 rx_unicast_bytes, "rx_unicast_bytes", "Received unicast bytes") \
140 m(+1, u64 tx_unicast_packets, "tx_unicast_packets", "Transmitted unicast packets") \
141 m(+1, u64 tx_unicast_bytes, "tx_unicast_bytes", "Transmitted unicast bytes") \
142 m(+1, u64 rx_multicast_packets, "rx_multicast_packets", "Received multicast packets") \
143 m(+1, u64 rx_multicast_bytes, "rx_multicast_bytes", "Received multicast bytes") \
144 m(+1, u64 tx_multicast_packets, "tx_multicast_packets", "Transmitted multicast packets") \
145 m(+1, u64 tx_multicast_bytes, "tx_multicast_bytes", "Transmitted multicast bytes") \
146 m(+1, u64 rx_broadcast_packets, "rx_broadcast_packets", "Received broadcast packets") \
147 m(+1, u64 rx_broadcast_bytes, "rx_broadcast_bytes", "Received broadcast bytes") \
148 m(+1, u64 tx_broadcast_packets, "tx_broadcast_packets", "Transmitted broadcast packets") \
149 m(+1, u64 tx_broadcast_bytes, "tx_broadcast_bytes", "Transmitted broadcast bytes") \
150 m(+1, u64 rx_out_of_buffer, "rx_out_of_buffer", "Receive out of buffer, no recv wqes events") \
152 m(+1, u64 tso_packets, "tso_packets", "Transmitted TSO packets") \
153 m(+1, u64 tso_bytes, "tso_bytes", "Transmitted TSO bytes") \
154 m(+1, u64 lro_packets, "lro_packets", "Received LRO packets") \
155 m(+1, u64 lro_bytes, "lro_bytes", "Received LRO bytes") \
156 m(+1, u64 sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \
157 m(+1, u64 sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \
158 m(+1, u64 rx_csum_good, "rx_csum_good", "Received checksum valid packets") \
159 m(+1, u64 rx_csum_none, "rx_csum_none", "Received no checksum packets") \
160 m(+1, u64 tx_csum_offload, "tx_csum_offload", "Transmit checksum offload packets") \
161 m(+1, u64 tx_queue_dropped, "tx_queue_dropped", "Transmit queue dropped") \
162 m(+1, u64 tx_defragged, "tx_defragged", "Transmit queue defragged") \
163 m(+1, u64 rx_wqe_err, "rx_wqe_err", "Receive WQE errors")
165 #define MLX5E_VPORT_STATS_NUM (0 MLX5E_VPORT_STATS(MLX5E_STATS_COUNT))
167 struct mlx5e_vport_stats {
168 struct sysctl_ctx_list ctx;
170 MLX5E_VPORT_STATS(MLX5E_STATS_VAR)
171 u32 rx_out_of_buffer_prev;
174 #define MLX5E_PPORT_IEEE802_3_STATS(m) \
175 m(+1, u64 frames_tx, "frames_tx", "Frames transmitted") \
176 m(+1, u64 frames_rx, "frames_rx", "Frames received") \
177 m(+1, u64 check_seq_err, "check_seq_err", "Sequence errors") \
178 m(+1, u64 alignment_err, "alignment_err", "Alignment errors") \
179 m(+1, u64 octets_tx, "octets_tx", "Bytes transmitted") \
180 m(+1, u64 octets_received, "octets_received", "Bytes received") \
181 m(+1, u64 multicast_xmitted, "multicast_xmitted", "Multicast transmitted") \
182 m(+1, u64 broadcast_xmitted, "broadcast_xmitted", "Broadcast transmitted") \
183 m(+1, u64 multicast_rx, "multicast_rx", "Multicast received") \
184 m(+1, u64 broadcast_rx, "broadcast_rx", "Broadcast received") \
185 m(+1, u64 in_range_len_errors, "in_range_len_errors", "In range length errors") \
186 m(+1, u64 out_of_range_len, "out_of_range_len", "Out of range length errors") \
187 m(+1, u64 too_long_errors, "too_long_errors", "Too long errors") \
188 m(+1, u64 symbol_err, "symbol_err", "Symbol errors") \
189 m(+1, u64 mac_control_tx, "mac_control_tx", "MAC control transmitted") \
190 m(+1, u64 mac_control_rx, "mac_control_rx", "MAC control received") \
191 m(+1, u64 unsupported_op_rx, "unsupported_op_rx", "Unsupported operation received") \
192 m(+1, u64 pause_ctrl_rx, "pause_ctrl_rx", "Pause control received") \
193 m(+1, u64 pause_ctrl_tx, "pause_ctrl_tx", "Pause control transmitted")
195 #define MLX5E_PPORT_RFC2819_STATS(m) \
196 m(+1, u64 drop_events, "drop_events", "Dropped events") \
197 m(+1, u64 octets, "octets", "Octets") \
198 m(+1, u64 pkts, "pkts", "Packets") \
199 m(+1, u64 broadcast_pkts, "broadcast_pkts", "Broadcast packets") \
200 m(+1, u64 multicast_pkts, "multicast_pkts", "Multicast packets") \
201 m(+1, u64 crc_align_errors, "crc_align_errors", "CRC alignment errors") \
202 m(+1, u64 undersize_pkts, "undersize_pkts", "Undersized packets") \
203 m(+1, u64 oversize_pkts, "oversize_pkts", "Oversized packets") \
204 m(+1, u64 fragments, "fragments", "Fragments") \
205 m(+1, u64 jabbers, "jabbers", "Jabbers") \
206 m(+1, u64 collisions, "collisions", "Collisions")
208 #define MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \
209 m(+1, u64 p64octets, "p64octets", "Bytes") \
210 m(+1, u64 p65to127octets, "p65to127octets", "Bytes") \
211 m(+1, u64 p128to255octets, "p128to255octets", "Bytes") \
212 m(+1, u64 p256to511octets, "p256to511octets", "Bytes") \
213 m(+1, u64 p512to1023octets, "p512to1023octets", "Bytes") \
214 m(+1, u64 p1024to1518octets, "p1024to1518octets", "Bytes") \
215 m(+1, u64 p1519to2047octets, "p1519to2047octets", "Bytes") \
216 m(+1, u64 p2048to4095octets, "p2048to4095octets", "Bytes") \
217 m(+1, u64 p4096to8191octets, "p4096to8191octets", "Bytes") \
218 m(+1, u64 p8192to10239octets, "p8192to10239octets", "Bytes")
220 #define MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \
221 m(+1, u64 in_octets, "in_octets", "In octets") \
222 m(+1, u64 in_ucast_pkts, "in_ucast_pkts", "In unicast packets") \
223 m(+1, u64 in_discards, "in_discards", "In discards") \
224 m(+1, u64 in_errors, "in_errors", "In errors") \
225 m(+1, u64 in_unknown_protos, "in_unknown_protos", "In unknown protocols") \
226 m(+1, u64 out_octets, "out_octets", "Out octets") \
227 m(+1, u64 out_ucast_pkts, "out_ucast_pkts", "Out unicast packets") \
228 m(+1, u64 out_discards, "out_discards", "Out discards") \
229 m(+1, u64 out_errors, "out_errors", "Out errors") \
230 m(+1, u64 in_multicast_pkts, "in_multicast_pkts", "In multicast packets") \
231 m(+1, u64 in_broadcast_pkts, "in_broadcast_pkts", "In broadcast packets") \
232 m(+1, u64 out_multicast_pkts, "out_multicast_pkts", "Out multicast packets") \
233 m(+1, u64 out_broadcast_pkts, "out_broadcast_pkts", "Out broadcast packets")
235 #define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \
236 m(+1, u64 time_since_last_clear, "time_since_last_clear", \
237 "Time since the last counters clear event (msec)") \
238 m(+1, u64 symbol_errors, "symbol_errors", "Symbol errors") \
239 m(+1, u64 sync_headers_errors, "sync_headers_errors", "Sync header error counter") \
240 m(+1, u64 bip_errors_lane0, "edpl_bip_errors_lane0", \
241 "Indicates the number of PRBS errors on lane 0") \
242 m(+1, u64 bip_errors_lane1, "edpl_bip_errors_lane1", \
243 "Indicates the number of PRBS errors on lane 1") \
244 m(+1, u64 bip_errors_lane2, "edpl_bip_errors_lane2", \
245 "Indicates the number of PRBS errors on lane 2") \
246 m(+1, u64 bip_errors_lane3, "edpl_bip_errors_lane3", \
247 "Indicates the number of PRBS errors on lane 3") \
248 m(+1, u64 fc_corrected_blocks_lane0, "fc_corrected_blocks_lane0", \
249 "FEC correctable block counter lane 0") \
250 m(+1, u64 fc_corrected_blocks_lane1, "fc_corrected_blocks_lane1", \
251 "FEC correctable block counter lane 1") \
252 m(+1, u64 fc_corrected_blocks_lane2, "fc_corrected_blocks_lane2", \
253 "FEC correctable block counter lane 2") \
254 m(+1, u64 fc_corrected_blocks_lane3, "fc_corrected_blocks_lane3", \
255 "FEC correctable block counter lane 3") \
256 m(+1, u64 rs_corrected_blocks, "rs_corrected_blocks", \
257 "FEC correcable block counter") \
258 m(+1, u64 rs_uncorrectable_blocks, "rs_uncorrectable_blocks", \
259 "FEC uncorrecable block counter") \
260 m(+1, u64 rs_no_errors_blocks, "rs_no_errors_blocks", \
261 "The number of RS-FEC blocks received that had no errors") \
262 m(+1, u64 rs_single_error_blocks, "rs_single_error_blocks", \
263 "The number of corrected RS-FEC blocks received that had" \
264 "exactly 1 error symbol") \
265 m(+1, u64 rs_corrected_symbols_total, "rs_corrected_symbols_total", \
266 "Port FEC corrected symbol counter") \
267 m(+1, u64 rs_corrected_symbols_lane0, "rs_corrected_symbols_lane0", \
268 "FEC corrected symbol counter lane 0") \
269 m(+1, u64 rs_corrected_symbols_lane1, "rs_corrected_symbols_lane1", \
270 "FEC corrected symbol counter lane 1") \
271 m(+1, u64 rs_corrected_symbols_lane2, "rs_corrected_symbols_lane2", \
272 "FEC corrected symbol counter lane 2") \
273 m(+1, u64 rs_corrected_symbols_lane3, "rs_corrected_symbols_lane3", \
274 "FEC corrected symbol counter lane 3") \
277 * Make sure to update mlx5e_update_pport_counters()
278 * when adding a new MLX5E_PPORT_STATS block
280 #define MLX5E_PPORT_STATS(m) \
281 MLX5E_PPORT_IEEE802_3_STATS(m) \
282 MLX5E_PPORT_RFC2819_STATS(m)
284 #define MLX5E_PORT_STATS_DEBUG(m) \
285 MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \
286 MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \
287 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m)
289 #define MLX5E_PPORT_IEEE802_3_STATS_NUM \
290 (0 MLX5E_PPORT_IEEE802_3_STATS(MLX5E_STATS_COUNT))
291 #define MLX5E_PPORT_RFC2819_STATS_NUM \
292 (0 MLX5E_PPORT_RFC2819_STATS(MLX5E_STATS_COUNT))
293 #define MLX5E_PPORT_STATS_NUM \
294 (0 MLX5E_PPORT_STATS(MLX5E_STATS_COUNT))
296 #define MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM \
297 (0 MLX5E_PPORT_RFC2819_STATS_DEBUG(MLX5E_STATS_COUNT))
298 #define MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM \
299 (0 MLX5E_PPORT_RFC2863_STATS_DEBUG(MLX5E_STATS_COUNT))
300 #define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM \
301 (0 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(MLX5E_STATS_COUNT))
302 #define MLX5E_PORT_STATS_DEBUG_NUM \
303 (0 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_COUNT))
305 struct mlx5e_pport_stats {
306 struct sysctl_ctx_list ctx;
308 MLX5E_PPORT_STATS(MLX5E_STATS_VAR)
311 struct mlx5e_port_stats_debug {
312 struct sysctl_ctx_list ctx;
314 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_VAR)
317 #define MLX5E_RQ_STATS(m) \
318 m(+1, u64 packets, "packets", "Received packets") \
319 m(+1, u64 csum_none, "csum_none", "Received packets") \
320 m(+1, u64 lro_packets, "lro_packets", "Received packets") \
321 m(+1, u64 lro_bytes, "lro_bytes", "Received packets") \
322 m(+1, u64 sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \
323 m(+1, u64 sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \
324 m(+1, u64 wqe_err, "wqe_err", "Received packets")
326 #define MLX5E_RQ_STATS_NUM (0 MLX5E_RQ_STATS(MLX5E_STATS_COUNT))
328 struct mlx5e_rq_stats {
329 struct sysctl_ctx_list ctx;
331 MLX5E_RQ_STATS(MLX5E_STATS_VAR)
334 #define MLX5E_SQ_STATS(m) \
335 m(+1, u64 packets, "packets", "Transmitted packets") \
336 m(+1, u64 tso_packets, "tso_packets", "Transmitted packets") \
337 m(+1, u64 tso_bytes, "tso_bytes", "Transmitted bytes") \
338 m(+1, u64 csum_offload_none, "csum_offload_none", "Transmitted packets") \
339 m(+1, u64 defragged, "defragged", "Transmitted packets") \
340 m(+1, u64 dropped, "dropped", "Transmitted packets") \
341 m(+1, u64 nop, "nop", "Transmitted packets")
343 #define MLX5E_SQ_STATS_NUM (0 MLX5E_SQ_STATS(MLX5E_STATS_COUNT))
345 struct mlx5e_sq_stats {
346 struct sysctl_ctx_list ctx;
348 MLX5E_SQ_STATS(MLX5E_STATS_VAR)
352 struct mlx5e_vport_stats vport;
353 struct mlx5e_pport_stats pport;
354 struct mlx5e_port_stats_debug port_stats_debug;
357 struct mlx5e_rq_param {
358 u32 rqc [MLX5_ST_SZ_DW(rqc)];
359 struct mlx5_wq_param wq;
362 struct mlx5e_sq_param {
363 u32 sqc [MLX5_ST_SZ_DW(sqc)];
364 struct mlx5_wq_param wq;
367 struct mlx5e_cq_param {
368 u32 cqc [MLX5_ST_SZ_DW(cqc)];
369 struct mlx5_wq_param wq;
372 struct mlx5e_params {
376 u8 default_vlan_prio;
378 u8 rx_cq_moderation_mode;
379 u8 tx_cq_moderation_mode;
380 u16 rx_cq_moderation_usec;
381 u16 rx_cq_moderation_pkts;
382 u16 tx_cq_moderation_usec;
383 u16 tx_cq_moderation_pkts;
388 u16 rx_hash_log_tbl_sz;
389 u32 tx_pauseframe_control;
390 u32 rx_pauseframe_control;
393 #define MLX5E_PARAMS(m) \
394 m(+1, u64 tx_queue_size_max, "tx_queue_size_max", "Max send queue size") \
395 m(+1, u64 rx_queue_size_max, "rx_queue_size_max", "Max receive queue size") \
396 m(+1, u64 tx_queue_size, "tx_queue_size", "Default send queue size") \
397 m(+1, u64 rx_queue_size, "rx_queue_size", "Default receive queue size") \
398 m(+1, u64 channels, "channels", "Default number of channels") \
399 m(+1, u64 coalesce_usecs_max, "coalesce_usecs_max", "Maximum usecs for joining packets") \
400 m(+1, u64 coalesce_pkts_max, "coalesce_pkts_max", "Maximum packets to join") \
401 m(+1, u64 rx_coalesce_usecs, "rx_coalesce_usecs", "Limit in usec for joining rx packets") \
402 m(+1, u64 rx_coalesce_pkts, "rx_coalesce_pkts", "Maximum number of rx packets to join") \
403 m(+1, u64 rx_coalesce_mode, "rx_coalesce_mode", "0: EQE mode 1: CQE mode") \
404 m(+1, u64 tx_coalesce_usecs, "tx_coalesce_usecs", "Limit in usec for joining tx packets") \
405 m(+1, u64 tx_coalesce_pkts, "tx_coalesce_pkts", "Maximum number of tx packets to join") \
406 m(+1, u64 tx_coalesce_mode, "tx_coalesce_mode", "0: EQE mode 1: CQE mode") \
407 m(+1, u64 tx_bufring_disable, "tx_bufring_disable", "0: Enable bufring 1: Disable bufring") \
408 m(+1, u64 tx_completion_fact, "tx_completion_fact", "1..MAX: Completion event ratio") \
409 m(+1, u64 tx_completion_fact_max, "tx_completion_fact_max", "Maximum completion event ratio") \
410 m(+1, u64 hw_lro, "hw_lro", "set to enable hw_lro") \
411 m(+1, u64 cqe_zipping, "cqe_zipping", "0 : CQE zipping disabled") \
412 m(+1, u64 modify_tx_dma, "modify_tx_dma", "0: Enable TX 1: Disable TX") \
413 m(+1, u64 modify_rx_dma, "modify_rx_dma", "0: Enable RX 1: Disable RX") \
414 m(+1, u64 diag_pci_enable, "diag_pci_enable", "0: Disabled 1: Enabled") \
415 m(+1, u64 diag_general_enable, "diag_general_enable", "0: Disabled 1: Enabled") \
416 m(+1, u64 hw_mtu, "hw_mtu", "Current hardware MTU value") \
417 m(+1, u64 mc_local_lb, "mc_local_lb", "0: Local multicast loopback enabled 1: Disabled") \
418 m(+1, u64 uc_local_lb, "uc_local_lb", "0: Local unicast loopback enabled 1: Disabled")
420 #define MLX5E_PARAMS_NUM (0 MLX5E_PARAMS(MLX5E_STATS_COUNT))
422 struct mlx5e_params_ethtool {
424 MLX5E_PARAMS(MLX5E_STATS_VAR)
427 /* EEPROM Standards for plug in modules */
428 #ifndef MLX5E_ETH_MODULE_SFF_8472
429 #define MLX5E_ETH_MODULE_SFF_8472 0x1
430 #define MLX5E_ETH_MODULE_SFF_8472_LEN 128
433 #ifndef MLX5E_ETH_MODULE_SFF_8636
434 #define MLX5E_ETH_MODULE_SFF_8636 0x2
435 #define MLX5E_ETH_MODULE_SFF_8636_LEN 256
438 #ifndef MLX5E_ETH_MODULE_SFF_8436
439 #define MLX5E_ETH_MODULE_SFF_8436 0x3
440 #define MLX5E_ETH_MODULE_SFF_8436_LEN 256
443 /* EEPROM I2C Addresses */
444 #define MLX5E_I2C_ADDR_LOW 0x50
445 #define MLX5E_I2C_ADDR_HIGH 0x51
447 #define MLX5E_EEPROM_LOW_PAGE 0x0
448 #define MLX5E_EEPROM_HIGH_PAGE 0x3
450 #define MLX5E_EEPROM_HIGH_PAGE_OFFSET 128
451 #define MLX5E_EEPROM_PAGE_LENGTH 256
453 #define MLX5E_EEPROM_INFO_BYTES 0x3
456 /* data path - accessed per cqe */
459 /* data path - accessed per HW polling */
460 struct mlx5_core_cq mcq;
463 struct mlx5e_priv *priv;
464 struct mlx5_wq_ctrl wq_ctrl;
465 } __aligned(MLX5E_CACHELINE_SIZE);
467 struct mlx5e_rq_mbuf {
468 bus_dmamap_t dma_map;
475 struct mlx5_wq_ll wq;
477 bus_dma_tag_t dma_tag;
479 struct mlx5e_rq_mbuf *mbuf;
481 struct mlx5e_rq_stats stats;
484 volatile int enabled;
488 struct mlx5_wq_ctrl wq_ctrl;
490 struct mlx5e_channel *channel;
491 struct callout watchdog;
492 } __aligned(MLX5E_CACHELINE_SIZE);
494 struct mlx5e_sq_mbuf {
495 bus_dmamap_t dma_map;
509 bus_dma_tag_t dma_tag;
510 struct mtx comp_lock;
512 /* dirtied @completion */
516 u16 pc __aligned(MLX5E_CACHELINE_SIZE);
518 u16 cev_counter; /* completion event counter */
519 u16 cev_factor; /* completion event factor */
520 u16 cev_next_state; /* next completion event state */
521 #define MLX5E_CEV_STATE_INITIAL 0 /* timer not started */
522 #define MLX5E_CEV_STATE_SEND_NOPS 1 /* send NOPs */
523 #define MLX5E_CEV_STATE_HOLD_NOPS 2 /* don't send NOPs yet */
524 u16 stopped; /* set if SQ is stopped */
525 struct callout cev_callout;
530 struct mlx5e_sq_stats stats;
534 struct taskqueue *sq_tq;
536 /* pointers to per packet info: write@xmit, read@completion */
537 struct mlx5e_sq_mbuf *mbuf;
541 struct mlx5_wq_cyc wq;
549 struct mlx5_wq_ctrl wq_ctrl;
550 struct mlx5e_priv *priv;
552 unsigned int queue_state;
553 } __aligned(MLX5E_CACHELINE_SIZE);
556 mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
561 return ((sq->wq.sz_m1 & (cc - pc)) >= n || cc == pc);
564 struct mlx5e_channel {
567 struct mlx5e_sq sq[MLX5E_MAX_TX_NUM_TC];
573 struct mlx5e_priv *priv;
576 } __aligned(MLX5E_CACHELINE_SIZE);
578 enum mlx5e_traffic_types {
583 MLX5E_TT_IPV4_IPSEC_AH,
584 MLX5E_TT_IPV6_IPSEC_AH,
585 MLX5E_TT_IPV4_IPSEC_ESP,
586 MLX5E_TT_IPV6_IPSEC_ESP,
594 MLX5E_RQT_SPREADING = 0,
595 MLX5E_RQT_DEFAULT_RQ = 1,
599 struct mlx5_flow_rule;
601 struct mlx5e_eth_addr_info {
602 u8 addr [ETH_ALEN + 2];
604 /* flow table rule per traffic type */
605 struct mlx5_flow_rule *ft_rule[MLX5E_NUM_TT];
608 #define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE)
610 struct mlx5e_eth_addr_hash_node;
612 struct mlx5e_eth_addr_hash_head {
613 struct mlx5e_eth_addr_hash_node *lh_first;
616 struct mlx5e_eth_addr_db {
617 struct mlx5e_eth_addr_hash_head if_uc[MLX5E_ETH_ADDR_HASH_SIZE];
618 struct mlx5e_eth_addr_hash_head if_mc[MLX5E_ETH_ADDR_HASH_SIZE];
619 struct mlx5e_eth_addr_info broadcast;
620 struct mlx5e_eth_addr_info allmulti;
621 struct mlx5e_eth_addr_info promisc;
622 bool broadcast_enabled;
623 bool allmulti_enabled;
624 bool promisc_enabled;
628 MLX5E_STATE_ASYNC_EVENTS_ENABLE,
632 struct mlx5e_vlan_db {
633 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
634 struct mlx5_flow_rule *active_vlans_ft_rule[VLAN_N_VID];
635 struct mlx5_flow_rule *untagged_ft_rule;
636 struct mlx5_flow_rule *any_cvlan_ft_rule;
637 struct mlx5_flow_rule *any_svlan_ft_rule;
638 bool filter_disabled;
641 struct mlx5e_flow_table {
643 struct mlx5_flow_table *t;
644 struct mlx5_flow_group **g;
647 struct mlx5e_flow_tables {
648 struct mlx5_flow_namespace *ns;
649 struct mlx5e_flow_table vlan;
650 struct mlx5e_flow_table main;
651 struct mlx5e_flow_table inner_rss;
655 struct mlx5_core_dev *mdev; /* must be first */
657 /* priv data path fields - start */
658 int order_base_2_num_channels;
659 int queue_mapping_channel_mask;
661 int default_vlan_prio;
662 /* priv data path fields - end */
666 #define PRIV_LOCK(priv) sx_xlock(&(priv)->state_lock)
667 #define PRIV_UNLOCK(priv) sx_xunlock(&(priv)->state_lock)
668 #define PRIV_LOCKED(priv) sx_xlocked(&(priv)->state_lock)
669 struct sx state_lock; /* Protects Interface state */
670 struct mlx5_uar cq_uar;
673 struct mlx5_core_mr mr;
675 struct mlx5e_channel *volatile *channel;
676 u32 tisn[MLX5E_MAX_TX_NUM_TC];
678 u32 tirn[MLX5E_NUM_TT];
680 struct mlx5e_flow_tables fts;
681 struct mlx5e_eth_addr_db eth_addr;
682 struct mlx5e_vlan_db vlan;
684 struct mlx5e_params params;
685 struct mlx5e_params_ethtool params_ethtool;
686 union mlx5_core_pci_diagnostics params_pci;
687 union mlx5_core_general_diagnostics params_general;
688 struct mtx async_events_mtx; /* sync hw events */
689 struct work_struct update_stats_work;
690 struct work_struct update_carrier_work;
691 struct work_struct set_rx_mode_work;
692 MLX5_DECLARE_DOORBELL_LOCK(doorbell_lock)
695 struct sysctl_ctx_list sysctl_ctx;
696 struct sysctl_oid *sysctl_ifnet;
697 struct sysctl_oid *sysctl_hw;
699 struct mlx5e_stats stats;
702 eventhandler_tag vlan_detach;
703 eventhandler_tag vlan_attach;
704 struct ifmedia media;
705 int media_status_last;
706 int media_active_last;
708 struct callout watchdog;
711 #define MLX5E_NET_IP_ALIGN 2
713 struct mlx5e_tx_wqe {
714 struct mlx5_wqe_ctrl_seg ctrl;
715 struct mlx5_wqe_eth_seg eth;
718 struct mlx5e_rx_wqe {
719 struct mlx5_wqe_srq_next_seg next;
720 struct mlx5_wqe_data_seg data;
723 struct mlx5e_eeprom {
735 #define MLX5E_FLD_MAX(typ, fld) ((1ULL << __mlx5_bit_sz(typ, fld)) - 1ULL)
737 int mlx5e_xmit(struct ifnet *, struct mbuf *);
739 int mlx5e_open_locked(struct ifnet *);
740 int mlx5e_close_locked(struct ifnet *);
742 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, int event);
743 void mlx5e_rx_cq_comp(struct mlx5_core_cq *);
744 void mlx5e_tx_cq_comp(struct mlx5_core_cq *);
745 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
746 void mlx5e_tx_que(void *context, int pending);
748 int mlx5e_open_flow_table(struct mlx5e_priv *priv);
749 void mlx5e_close_flow_table(struct mlx5e_priv *priv);
750 void mlx5e_set_rx_mode_core(struct mlx5e_priv *priv);
751 void mlx5e_set_rx_mode_work(struct work_struct *work);
753 void mlx5e_vlan_rx_add_vid(void *, struct ifnet *, u16);
754 void mlx5e_vlan_rx_kill_vid(void *, struct ifnet *, u16);
755 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
756 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
757 int mlx5e_add_all_vlan_rules(struct mlx5e_priv *priv);
758 void mlx5e_del_all_vlan_rules(struct mlx5e_priv *priv);
761 mlx5e_tx_notify_hw(struct mlx5e_sq *sq, u32 *wqe, int bf_sz)
763 u16 ofst = MLX5_BF_OFFSET + sq->bf_offset;
765 /* ensure wqe is visible to device before updating doorbell record */
768 *sq->wq.db = cpu_to_be32(sq->pc);
771 * Ensure the doorbell record is visible to device before ringing
777 __iowrite64_copy(sq->uar.bf_map + ofst, wqe, bf_sz);
779 /* flush the write-combining mapped buffer */
783 mlx5_write64(wqe, sq->uar.map + ofst,
784 MLX5_GET_DOORBELL_LOCK(&sq->priv->doorbell_lock));
787 sq->bf_offset ^= sq->bf_buf_size;
791 mlx5e_cq_arm(struct mlx5e_cq *cq, spinlock_t *dblock)
793 struct mlx5_core_cq *mcq;
796 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, dblock, cq->wq.cc);
799 extern const struct ethtool_ops mlx5e_ethtool_ops;
800 void mlx5e_create_ethtool(struct mlx5e_priv *);
801 void mlx5e_create_stats(struct sysctl_ctx_list *,
802 struct sysctl_oid_list *, const char *,
803 const char **, unsigned, u64 *);
804 void mlx5e_send_nop(struct mlx5e_sq *, u32);
805 void mlx5e_sq_cev_timeout(void *);
806 int mlx5e_refresh_channel_params(struct mlx5e_priv *);
807 int mlx5e_open_cq(struct mlx5e_priv *, struct mlx5e_cq_param *,
808 struct mlx5e_cq *, mlx5e_cq_comp_t *, int eq_ix);
809 void mlx5e_close_cq(struct mlx5e_cq *);
810 void mlx5e_free_sq_db(struct mlx5e_sq *);
811 int mlx5e_alloc_sq_db(struct mlx5e_sq *);
812 int mlx5e_enable_sq(struct mlx5e_sq *, struct mlx5e_sq_param *, int tis_num);
813 int mlx5e_modify_sq(struct mlx5e_sq *, int curr_state, int next_state);
814 void mlx5e_disable_sq(struct mlx5e_sq *);
815 void mlx5e_drain_sq(struct mlx5e_sq *);
816 void mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value);
817 void mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value);
818 void mlx5e_resume_sq(struct mlx5e_sq *sq);
820 #endif /* _MLX5_EN_H_ */