2 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <linux/kmod.h>
32 #include <linux/page.h>
33 #include <linux/slab.h>
34 #include <linux/if_vlan.h>
35 #include <linux/if_ether.h>
36 #include <linux/vmalloc.h>
37 #include <linux/moduleparam.h>
38 #include <linux/delay.h>
39 #include <linux/netdevice.h>
40 #include <linux/etherdevice.h>
42 #include <netinet/in_systm.h>
43 #include <netinet/in.h>
44 #include <netinet/if_ether.h>
45 #include <netinet/ip.h>
46 #include <netinet/ip6.h>
47 #include <netinet/tcp.h>
48 #include <netinet/tcp_lro.h>
49 #include <netinet/udp.h>
50 #include <net/ethernet.h>
51 #include <sys/buf_ring.h>
56 #include <net/rss_config.h>
57 #include <netinet/in_rss.h>
60 #include <machine/bus.h>
62 #include <dev/mlx5/driver.h>
63 #include <dev/mlx5/qp.h>
64 #include <dev/mlx5/cq.h>
65 #include <dev/mlx5/vport.h>
67 #include <dev/mlx5/mlx5_core/wq.h>
68 #include <dev/mlx5/mlx5_core/transobj.h>
69 #include <dev/mlx5/mlx5_core/mlx5_core.h>
71 #define MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE 0x7
72 #define MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE 0xa
73 #define MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE 0xd
75 #define MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE 0x7
76 #define MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE 0xa
77 #define MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE 0xd
79 /* freeBSD HW LRO is limited by 16KB - the size of max mbuf */
80 #define MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ MJUM16BYTES
81 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC 0x10
82 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE 0x3
83 #define MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS 0x20
84 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC 0x10
85 #define MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS 0x20
86 #define MLX5E_PARAMS_DEFAULT_MIN_RX_WQES 0x80
87 #define MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ 0x7
88 #define MLX5E_CACHELINE_SIZE CACHE_LINE_SIZE
89 #define MLX5E_HW2SW_MTU(hwmtu) \
90 ((hwmtu) - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN))
91 #define MLX5E_SW2HW_MTU(swmtu) \
92 ((swmtu) + (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN))
93 #define MLX5E_SW2MB_MTU(swmtu) \
94 (MLX5E_SW2HW_MTU(swmtu) + MLX5E_NET_IP_ALIGN)
95 #define MLX5E_MTU_MIN 72 /* Min MTU allowed by the kernel */
96 #define MLX5E_MTU_MAX MIN(ETHERMTU_JUMBO, MJUM16BYTES) /* Max MTU of Ethernet
99 #define MLX5E_BUDGET_MAX 8192 /* RX and TX */
100 #define MLX5E_RX_BUDGET_MAX 256
101 #define MLX5E_SQ_BF_BUDGET 16
102 #define MLX5E_SQ_TX_QUEUE_SIZE 4096 /* SQ drbr queue size */
104 #define MLX5E_MAX_TX_NUM_TC 8 /* units */
105 #define MLX5E_MAX_TX_HEADER 128 /* bytes */
106 #define MLX5E_MAX_TX_PAYLOAD_SIZE 65536 /* bytes */
107 #define MLX5E_MAX_TX_MBUF_SIZE 65536 /* bytes */
108 #define MLX5E_MAX_TX_MBUF_FRAGS \
109 ((MLX5_SEND_WQE_MAX_WQEBBS * MLX5_SEND_WQEBB_NUM_DS) - \
110 (MLX5E_MAX_TX_HEADER / MLX5_SEND_WQE_DS)) /* units */
111 #define MLX5E_MAX_TX_INLINE \
112 (MLX5E_MAX_TX_HEADER - sizeof(struct mlx5e_tx_wqe) + \
113 sizeof(((struct mlx5e_tx_wqe *)0)->eth.inline_hdr_start)) /* bytes */
115 MALLOC_DECLARE(M_MLX5EN);
117 struct mlx5_core_dev;
120 typedef void (mlx5e_cq_comp_t)(struct mlx5_core_cq *);
122 #define MLX5E_STATS_COUNT(a,b,c,d) a
123 #define MLX5E_STATS_VAR(a,b,c,d) b;
124 #define MLX5E_STATS_DESC(a,b,c,d) c, d,
126 #define MLX5E_VPORT_STATS(m) \
128 m(+1, u64 rx_packets, "rx_packets", "Received packets") \
129 m(+1, u64 rx_bytes, "rx_bytes", "Received bytes") \
130 m(+1, u64 tx_packets, "tx_packets", "Transmitted packets") \
131 m(+1, u64 tx_bytes, "tx_bytes", "Transmitted bytes") \
132 m(+1, u64 rx_error_packets, "rx_error_packets", "Received error packets") \
133 m(+1, u64 rx_error_bytes, "rx_error_bytes", "Received error bytes") \
134 m(+1, u64 tx_error_packets, "tx_error_packets", "Transmitted error packets") \
135 m(+1, u64 tx_error_bytes, "tx_error_bytes", "Transmitted error bytes") \
136 m(+1, u64 rx_unicast_packets, "rx_unicast_packets", "Received unicast packets") \
137 m(+1, u64 rx_unicast_bytes, "rx_unicast_bytes", "Received unicast bytes") \
138 m(+1, u64 tx_unicast_packets, "tx_unicast_packets", "Transmitted unicast packets") \
139 m(+1, u64 tx_unicast_bytes, "tx_unicast_bytes", "Transmitted unicast bytes") \
140 m(+1, u64 rx_multicast_packets, "rx_multicast_packets", "Received multicast packets") \
141 m(+1, u64 rx_multicast_bytes, "rx_multicast_bytes", "Received multicast bytes") \
142 m(+1, u64 tx_multicast_packets, "tx_multicast_packets", "Transmitted multicast packets") \
143 m(+1, u64 tx_multicast_bytes, "tx_multicast_bytes", "Transmitted multicast bytes") \
144 m(+1, u64 rx_broadcast_packets, "rx_broadcast_packets", "Received broadcast packets") \
145 m(+1, u64 rx_broadcast_bytes, "rx_broadcast_bytes", "Received broadcast bytes") \
146 m(+1, u64 tx_broadcast_packets, "tx_broadcast_packets", "Transmitted broadcast packets") \
147 m(+1, u64 tx_broadcast_bytes, "tx_broadcast_bytes", "Transmitted broadcast bytes") \
148 m(+1, u64 rx_out_of_buffer, "rx_out_of_buffer", "Receive out of buffer, no recv wqes events") \
150 m(+1, u64 tso_packets, "tso_packets", "Transmitted TSO packets") \
151 m(+1, u64 tso_bytes, "tso_bytes", "Transmitted TSO bytes") \
152 m(+1, u64 lro_packets, "lro_packets", "Received LRO packets") \
153 m(+1, u64 lro_bytes, "lro_bytes", "Received LRO bytes") \
154 m(+1, u64 sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \
155 m(+1, u64 sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \
156 m(+1, u64 rx_csum_good, "rx_csum_good", "Received checksum valid packets") \
157 m(+1, u64 rx_csum_none, "rx_csum_none", "Received no checksum packets") \
158 m(+1, u64 tx_csum_offload, "tx_csum_offload", "Transmit checksum offload packets") \
159 m(+1, u64 tx_queue_dropped, "tx_queue_dropped", "Transmit queue dropped") \
160 m(+1, u64 tx_defragged, "tx_defragged", "Transmit queue defragged") \
161 m(+1, u64 rx_wqe_err, "rx_wqe_err", "Receive WQE errors")
163 #define MLX5E_VPORT_STATS_NUM (0 MLX5E_VPORT_STATS(MLX5E_STATS_COUNT))
165 struct mlx5e_vport_stats {
166 struct sysctl_ctx_list ctx;
168 MLX5E_VPORT_STATS(MLX5E_STATS_VAR)
169 u32 rx_out_of_buffer_prev;
172 #define MLX5E_PPORT_IEEE802_3_STATS(m) \
173 m(+1, u64 frames_tx, "frames_tx", "Frames transmitted") \
174 m(+1, u64 frames_rx, "frames_rx", "Frames received") \
175 m(+1, u64 check_seq_err, "check_seq_err", "Sequence errors") \
176 m(+1, u64 alignment_err, "alignment_err", "Alignment errors") \
177 m(+1, u64 octets_tx, "octets_tx", "Bytes transmitted") \
178 m(+1, u64 octets_received, "octets_received", "Bytes received") \
179 m(+1, u64 multicast_xmitted, "multicast_xmitted", "Multicast transmitted") \
180 m(+1, u64 broadcast_xmitted, "broadcast_xmitted", "Broadcast transmitted") \
181 m(+1, u64 multicast_rx, "multicast_rx", "Multicast received") \
182 m(+1, u64 broadcast_rx, "broadcast_rx", "Broadcast received") \
183 m(+1, u64 in_range_len_errors, "in_range_len_errors", "In range length errors") \
184 m(+1, u64 out_of_range_len, "out_of_range_len", "Out of range length errors") \
185 m(+1, u64 too_long_errors, "too_long_errors", "Too long errors") \
186 m(+1, u64 symbol_err, "symbol_err", "Symbol errors") \
187 m(+1, u64 mac_control_tx, "mac_control_tx", "MAC control transmitted") \
188 m(+1, u64 mac_control_rx, "mac_control_rx", "MAC control received") \
189 m(+1, u64 unsupported_op_rx, "unsupported_op_rx", "Unsupported operation received") \
190 m(+1, u64 pause_ctrl_rx, "pause_ctrl_rx", "Pause control received") \
191 m(+1, u64 pause_ctrl_tx, "pause_ctrl_tx", "Pause control transmitted")
193 #define MLX5E_PPORT_RFC2819_STATS(m) \
194 m(+1, u64 drop_events, "drop_events", "Dropped events") \
195 m(+1, u64 octets, "octets", "Octets") \
196 m(+1, u64 pkts, "pkts", "Packets") \
197 m(+1, u64 broadcast_pkts, "broadcast_pkts", "Broadcast packets") \
198 m(+1, u64 multicast_pkts, "multicast_pkts", "Multicast packets") \
199 m(+1, u64 crc_align_errors, "crc_align_errors", "CRC alignment errors") \
200 m(+1, u64 undersize_pkts, "undersize_pkts", "Undersized packets") \
201 m(+1, u64 oversize_pkts, "oversize_pkts", "Oversized packets") \
202 m(+1, u64 fragments, "fragments", "Fragments") \
203 m(+1, u64 jabbers, "jabbers", "Jabbers") \
204 m(+1, u64 collisions, "collisions", "Collisions")
206 #define MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \
207 m(+1, u64 p64octets, "p64octets", "Bytes") \
208 m(+1, u64 p65to127octets, "p65to127octets", "Bytes") \
209 m(+1, u64 p128to255octets, "p128to255octets", "Bytes") \
210 m(+1, u64 p256to511octets, "p256to511octets", "Bytes") \
211 m(+1, u64 p512to1023octets, "p512to1023octets", "Bytes") \
212 m(+1, u64 p1024to1518octets, "p1024to1518octets", "Bytes") \
213 m(+1, u64 p1519to2047octets, "p1519to2047octets", "Bytes") \
214 m(+1, u64 p2048to4095octets, "p2048to4095octets", "Bytes") \
215 m(+1, u64 p4096to8191octets, "p4096to8191octets", "Bytes") \
216 m(+1, u64 p8192to10239octets, "p8192to10239octets", "Bytes")
218 #define MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \
219 m(+1, u64 in_octets, "in_octets", "In octets") \
220 m(+1, u64 in_ucast_pkts, "in_ucast_pkts", "In unicast packets") \
221 m(+1, u64 in_discards, "in_discards", "In discards") \
222 m(+1, u64 in_errors, "in_errors", "In errors") \
223 m(+1, u64 in_unknown_protos, "in_unknown_protos", "In unknown protocols") \
224 m(+1, u64 out_octets, "out_octets", "Out octets") \
225 m(+1, u64 out_ucast_pkts, "out_ucast_pkts", "Out unicast packets") \
226 m(+1, u64 out_discards, "out_discards", "Out discards") \
227 m(+1, u64 out_errors, "out_errors", "Out errors") \
228 m(+1, u64 in_multicast_pkts, "in_multicast_pkts", "In multicast packets") \
229 m(+1, u64 in_broadcast_pkts, "in_broadcast_pkts", "In broadcast packets") \
230 m(+1, u64 out_multicast_pkts, "out_multicast_pkts", "Out multicast packets") \
231 m(+1, u64 out_broadcast_pkts, "out_broadcast_pkts", "Out broadcast packets")
233 #define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m) \
234 m(+1, u64 time_since_last_clear, "time_since_last_clear", \
235 "Time since the last counters clear event (msec)") \
236 m(+1, u64 symbol_errors, "symbol_errors", "Symbol errors") \
237 m(+1, u64 sync_headers_errors, "sync_headers_errors", "Sync header error counter") \
238 m(+1, u64 bip_errors_lane0, "edpl_bip_errors_lane0", \
239 "Indicates the number of PRBS errors on lane 0") \
240 m(+1, u64 bip_errors_lane1, "edpl_bip_errors_lane1", \
241 "Indicates the number of PRBS errors on lane 1") \
242 m(+1, u64 bip_errors_lane2, "edpl_bip_errors_lane2", \
243 "Indicates the number of PRBS errors on lane 2") \
244 m(+1, u64 bip_errors_lane3, "edpl_bip_errors_lane3", \
245 "Indicates the number of PRBS errors on lane 3") \
246 m(+1, u64 fc_corrected_blocks_lane0, "fc_corrected_blocks_lane0", \
247 "FEC correctable block counter lane 0") \
248 m(+1, u64 fc_corrected_blocks_lane1, "fc_corrected_blocks_lane1", \
249 "FEC correctable block counter lane 1") \
250 m(+1, u64 fc_corrected_blocks_lane2, "fc_corrected_blocks_lane2", \
251 "FEC correctable block counter lane 2") \
252 m(+1, u64 fc_corrected_blocks_lane3, "fc_corrected_blocks_lane3", \
253 "FEC correctable block counter lane 3") \
254 m(+1, u64 rs_corrected_blocks, "rs_corrected_blocks", \
255 "FEC correcable block counter") \
256 m(+1, u64 rs_uncorrectable_blocks, "rs_uncorrectable_blocks", \
257 "FEC uncorrecable block counter") \
258 m(+1, u64 rs_no_errors_blocks, "rs_no_errors_blocks", \
259 "The number of RS-FEC blocks received that had no errors") \
260 m(+1, u64 rs_single_error_blocks, "rs_single_error_blocks", \
261 "The number of corrected RS-FEC blocks received that had" \
262 "exactly 1 error symbol") \
263 m(+1, u64 rs_corrected_symbols_total, "rs_corrected_symbols_total", \
264 "Port FEC corrected symbol counter") \
265 m(+1, u64 rs_corrected_symbols_lane0, "rs_corrected_symbols_lane0", \
266 "FEC corrected symbol counter lane 0") \
267 m(+1, u64 rs_corrected_symbols_lane1, "rs_corrected_symbols_lane1", \
268 "FEC corrected symbol counter lane 1") \
269 m(+1, u64 rs_corrected_symbols_lane2, "rs_corrected_symbols_lane2", \
270 "FEC corrected symbol counter lane 2") \
271 m(+1, u64 rs_corrected_symbols_lane3, "rs_corrected_symbols_lane3", \
272 "FEC corrected symbol counter lane 3") \
275 * Make sure to update mlx5e_update_pport_counters()
276 * when adding a new MLX5E_PPORT_STATS block
278 #define MLX5E_PPORT_STATS(m) \
279 MLX5E_PPORT_IEEE802_3_STATS(m) \
280 MLX5E_PPORT_RFC2819_STATS(m)
282 #define MLX5E_PORT_STATS_DEBUG(m) \
283 MLX5E_PPORT_RFC2819_STATS_DEBUG(m) \
284 MLX5E_PPORT_RFC2863_STATS_DEBUG(m) \
285 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(m)
287 #define MLX5E_PPORT_IEEE802_3_STATS_NUM \
288 (0 MLX5E_PPORT_IEEE802_3_STATS(MLX5E_STATS_COUNT))
289 #define MLX5E_PPORT_RFC2819_STATS_NUM \
290 (0 MLX5E_PPORT_RFC2819_STATS(MLX5E_STATS_COUNT))
291 #define MLX5E_PPORT_STATS_NUM \
292 (0 MLX5E_PPORT_STATS(MLX5E_STATS_COUNT))
294 #define MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM \
295 (0 MLX5E_PPORT_RFC2819_STATS_DEBUG(MLX5E_STATS_COUNT))
296 #define MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM \
297 (0 MLX5E_PPORT_RFC2863_STATS_DEBUG(MLX5E_STATS_COUNT))
298 #define MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM \
299 (0 MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG(MLX5E_STATS_COUNT))
300 #define MLX5E_PORT_STATS_DEBUG_NUM \
301 (0 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_COUNT))
303 struct mlx5e_pport_stats {
304 struct sysctl_ctx_list ctx;
306 MLX5E_PPORT_STATS(MLX5E_STATS_VAR)
309 struct mlx5e_port_stats_debug {
310 struct sysctl_ctx_list ctx;
312 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_VAR)
315 #define MLX5E_RQ_STATS(m) \
316 m(+1, u64 packets, "packets", "Received packets") \
317 m(+1, u64 csum_none, "csum_none", "Received packets") \
318 m(+1, u64 lro_packets, "lro_packets", "Received packets") \
319 m(+1, u64 lro_bytes, "lro_bytes", "Received packets") \
320 m(+1, u64 sw_lro_queued, "sw_lro_queued", "Packets queued for SW LRO") \
321 m(+1, u64 sw_lro_flushed, "sw_lro_flushed", "Packets flushed from SW LRO") \
322 m(+1, u64 wqe_err, "wqe_err", "Received packets")
324 #define MLX5E_RQ_STATS_NUM (0 MLX5E_RQ_STATS(MLX5E_STATS_COUNT))
326 struct mlx5e_rq_stats {
327 struct sysctl_ctx_list ctx;
329 MLX5E_RQ_STATS(MLX5E_STATS_VAR)
332 #define MLX5E_SQ_STATS(m) \
333 m(+1, u64 packets, "packets", "Transmitted packets") \
334 m(+1, u64 tso_packets, "tso_packets", "Transmitted packets") \
335 m(+1, u64 tso_bytes, "tso_bytes", "Transmitted bytes") \
336 m(+1, u64 csum_offload_none, "csum_offload_none", "Transmitted packets") \
337 m(+1, u64 defragged, "defragged", "Transmitted packets") \
338 m(+1, u64 dropped, "dropped", "Transmitted packets") \
339 m(+1, u64 nop, "nop", "Transmitted packets")
341 #define MLX5E_SQ_STATS_NUM (0 MLX5E_SQ_STATS(MLX5E_STATS_COUNT))
343 struct mlx5e_sq_stats {
344 struct sysctl_ctx_list ctx;
346 MLX5E_SQ_STATS(MLX5E_STATS_VAR)
350 struct mlx5e_vport_stats vport;
351 struct mlx5e_pport_stats pport;
352 struct mlx5e_port_stats_debug port_stats_debug;
355 struct mlx5e_params {
359 u8 default_vlan_prio;
361 u8 rx_cq_moderation_mode;
362 u8 tx_cq_moderation_mode;
363 u16 rx_cq_moderation_usec;
364 u16 rx_cq_moderation_pkts;
365 u16 tx_cq_moderation_usec;
366 u16 tx_cq_moderation_pkts;
371 u16 rx_hash_log_tbl_sz;
372 u32 tx_pauseframe_control;
373 u32 rx_pauseframe_control;
376 #define MLX5E_PARAMS(m) \
377 m(+1, u64 tx_queue_size_max, "tx_queue_size_max", "Max send queue size") \
378 m(+1, u64 rx_queue_size_max, "rx_queue_size_max", "Max receive queue size") \
379 m(+1, u64 tx_queue_size, "tx_queue_size", "Default send queue size") \
380 m(+1, u64 rx_queue_size, "rx_queue_size", "Default receive queue size") \
381 m(+1, u64 channels, "channels", "Default number of channels") \
382 m(+1, u64 coalesce_usecs_max, "coalesce_usecs_max", "Maximum usecs for joining packets") \
383 m(+1, u64 coalesce_pkts_max, "coalesce_pkts_max", "Maximum packets to join") \
384 m(+1, u64 rx_coalesce_usecs, "rx_coalesce_usecs", "Limit in usec for joining rx packets") \
385 m(+1, u64 rx_coalesce_pkts, "rx_coalesce_pkts", "Maximum number of rx packets to join") \
386 m(+1, u64 rx_coalesce_mode, "rx_coalesce_mode", "0: EQE mode 1: CQE mode") \
387 m(+1, u64 tx_coalesce_usecs, "tx_coalesce_usecs", "Limit in usec for joining tx packets") \
388 m(+1, u64 tx_coalesce_pkts, "tx_coalesce_pkts", "Maximum number of tx packets to join") \
389 m(+1, u64 tx_coalesce_mode, "tx_coalesce_mode", "0: EQE mode 1: CQE mode") \
390 m(+1, u64 tx_completion_fact, "tx_completion_fact", "1..MAX: Completion event ratio") \
391 m(+1, u64 tx_completion_fact_max, "tx_completion_fact_max", "Maximum completion event ratio") \
392 m(+1, u64 hw_lro, "hw_lro", "set to enable hw_lro") \
393 m(+1, u64 cqe_zipping, "cqe_zipping", "0 : CQE zipping disabled")
395 #define MLX5E_PARAMS_NUM (0 MLX5E_PARAMS(MLX5E_STATS_COUNT))
397 struct mlx5e_params_ethtool {
399 MLX5E_PARAMS(MLX5E_STATS_VAR)
402 /* EEPROM Standards for plug in modules */
403 #ifndef MLX5E_ETH_MODULE_SFF_8472
404 #define MLX5E_ETH_MODULE_SFF_8472 0x1
405 #define MLX5E_ETH_MODULE_SFF_8472_LEN 128
408 #ifndef MLX5E_ETH_MODULE_SFF_8636
409 #define MLX5E_ETH_MODULE_SFF_8636 0x2
410 #define MLX5E_ETH_MODULE_SFF_8636_LEN 256
413 #ifndef MLX5E_ETH_MODULE_SFF_8436
414 #define MLX5E_ETH_MODULE_SFF_8436 0x3
415 #define MLX5E_ETH_MODULE_SFF_8436_LEN 256
418 /* EEPROM I2C Addresses */
419 #define MLX5E_I2C_ADDR_LOW 0x50
420 #define MLX5E_I2C_ADDR_HIGH 0x51
422 #define MLX5E_EEPROM_LOW_PAGE 0x0
423 #define MLX5E_EEPROM_HIGH_PAGE 0x3
425 #define MLX5E_EEPROM_HIGH_PAGE_OFFSET 128
426 #define MLX5E_EEPROM_PAGE_LENGTH 256
428 #define MLX5E_EEPROM_INFO_BYTES 0x3
431 /* data path - accessed per cqe */
434 /* data path - accessed per HW polling */
435 struct mlx5_core_cq mcq;
436 struct mlx5e_channel *channel;
439 struct mlx5_wq_ctrl wq_ctrl;
440 } __aligned(MLX5E_CACHELINE_SIZE);
442 struct mlx5e_rq_mbuf {
443 bus_dmamap_t dma_map;
450 struct mlx5_wq_ll wq;
452 bus_dma_tag_t dma_tag;
454 struct mlx5e_rq_mbuf *mbuf;
457 struct mlx5e_rq_stats stats;
460 volatile int enabled;
464 struct mlx5_wq_ctrl wq_ctrl;
466 struct mlx5e_channel *channel;
467 } __aligned(MLX5E_CACHELINE_SIZE);
469 struct mlx5e_sq_mbuf {
470 bus_dmamap_t dma_map;
484 bus_dma_tag_t dma_tag;
485 struct mtx comp_lock;
487 /* dirtied @completion */
491 u16 pc __aligned(MLX5E_CACHELINE_SIZE);
493 u16 cev_counter; /* completion event counter */
494 u16 cev_factor; /* completion event factor */
495 u32 cev_next_state; /* next completion event state */
496 #define MLX5E_CEV_STATE_INITIAL 0 /* timer not started */
497 #define MLX5E_CEV_STATE_SEND_NOPS 1 /* send NOPs */
498 #define MLX5E_CEV_STATE_HOLD_NOPS 2 /* don't send NOPs yet */
499 struct callout cev_callout;
504 struct mlx5e_sq_stats stats;
508 struct taskqueue *sq_tq;
510 /* pointers to per packet info: write@xmit, read@completion */
511 struct mlx5e_sq_mbuf *mbuf;
515 struct mlx5_wq_cyc wq;
516 void __iomem *uar_map;
517 void __iomem *uar_bf_map;
524 struct mlx5_wq_ctrl wq_ctrl;
526 struct mlx5e_channel *channel;
528 unsigned int queue_state;
529 } __aligned(MLX5E_CACHELINE_SIZE);
532 mlx5e_sq_has_room_for(struct mlx5e_sq *sq, u16 n)
534 return ((sq->wq.sz_m1 & (sq->cc - sq->pc)) >= n ||
538 struct mlx5e_channel {
541 struct mlx5e_sq sq[MLX5E_MAX_TX_NUM_TC];
548 struct mlx5e_priv *priv;
551 } __aligned(MLX5E_CACHELINE_SIZE);
553 enum mlx5e_traffic_types {
558 MLX5E_TT_IPV4_IPSEC_AH,
559 MLX5E_TT_IPV6_IPSEC_AH,
560 MLX5E_TT_IPV4_IPSEC_ESP,
561 MLX5E_TT_IPV6_IPSEC_ESP,
569 MLX5E_RQT_SPREADING = 0,
570 MLX5E_RQT_DEFAULT_RQ = 1,
574 struct mlx5e_eth_addr_info {
575 u8 addr [ETH_ALEN + 2];
577 u32 ft_ix[MLX5E_NUM_TT]; /* flow table index per traffic type */
580 #define MLX5E_ETH_ADDR_HASH_SIZE (1 << BITS_PER_BYTE)
582 struct mlx5e_eth_addr_hash_node;
584 struct mlx5e_eth_addr_hash_head {
585 struct mlx5e_eth_addr_hash_node *lh_first;
588 struct mlx5e_eth_addr_db {
589 struct mlx5e_eth_addr_hash_head if_uc[MLX5E_ETH_ADDR_HASH_SIZE];
590 struct mlx5e_eth_addr_hash_head if_mc[MLX5E_ETH_ADDR_HASH_SIZE];
591 struct mlx5e_eth_addr_info broadcast;
592 struct mlx5e_eth_addr_info allmulti;
593 struct mlx5e_eth_addr_info promisc;
594 bool broadcast_enabled;
595 bool allmulti_enabled;
596 bool promisc_enabled;
600 MLX5E_STATE_ASYNC_EVENTS_ENABLE,
604 struct mlx5e_vlan_db {
605 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
606 u32 active_vlans_ft_ix[VLAN_N_VID];
607 u32 untagged_rule_ft_ix;
608 u32 any_vlan_rule_ft_ix;
609 bool filter_disabled;
612 struct mlx5e_flow_table {
618 /* priv data path fields - start */
619 int order_base_2_num_channels;
620 int queue_mapping_channel_mask;
622 int default_vlan_prio;
623 /* priv data path fields - end */
627 #define PRIV_LOCK(priv) sx_xlock(&(priv)->state_lock)
628 #define PRIV_UNLOCK(priv) sx_xunlock(&(priv)->state_lock)
629 #define PRIV_LOCKED(priv) sx_xlocked(&(priv)->state_lock)
630 struct sx state_lock; /* Protects Interface state */
631 struct mlx5_uar cq_uar;
634 struct mlx5_core_mr mr;
636 struct mlx5e_channel *volatile *channel;
637 u32 tisn[MLX5E_MAX_TX_NUM_TC];
639 u32 tirn[MLX5E_NUM_TT];
641 struct mlx5e_flow_table ft;
642 struct mlx5e_eth_addr_db eth_addr;
643 struct mlx5e_vlan_db vlan;
645 struct mlx5e_params params;
646 struct mlx5e_params_ethtool params_ethtool;
647 struct mtx async_events_mtx; /* sync hw events */
648 struct work_struct update_stats_work;
649 struct work_struct update_carrier_work;
650 struct work_struct set_rx_mode_work;
652 struct mlx5_core_dev *mdev;
654 struct sysctl_ctx_list sysctl_ctx;
655 struct sysctl_oid *sysctl_ifnet;
656 struct sysctl_oid *sysctl_hw;
658 struct mlx5e_stats stats;
661 eventhandler_tag vlan_detach;
662 eventhandler_tag vlan_attach;
663 struct ifmedia media;
664 int media_status_last;
665 int media_active_last;
667 struct callout watchdog;
670 #define MLX5E_NET_IP_ALIGN 2
672 struct mlx5e_tx_wqe {
673 struct mlx5_wqe_ctrl_seg ctrl;
674 struct mlx5_wqe_eth_seg eth;
677 struct mlx5e_rx_wqe {
678 struct mlx5_wqe_srq_next_seg next;
679 struct mlx5_wqe_data_seg data;
682 struct mlx5e_eeprom {
694 enum mlx5e_link_mode {
695 MLX5E_1000BASE_CX_SGMII = 0,
696 MLX5E_1000BASE_KX = 1,
697 MLX5E_10GBASE_CX4 = 2,
698 MLX5E_10GBASE_KX4 = 3,
699 MLX5E_10GBASE_KR = 4,
700 MLX5E_20GBASE_KR2 = 5,
701 MLX5E_40GBASE_CR4 = 6,
702 MLX5E_40GBASE_KR4 = 7,
703 MLX5E_56GBASE_R4 = 8,
704 MLX5E_10GBASE_CR = 12,
705 MLX5E_10GBASE_SR = 13,
706 MLX5E_10GBASE_LR = 14,
707 MLX5E_40GBASE_SR4 = 15,
708 MLX5E_40GBASE_LR4 = 16,
709 MLX5E_100GBASE_CR4 = 20,
710 MLX5E_100GBASE_SR4 = 21,
711 MLX5E_100GBASE_KR4 = 22,
712 MLX5E_100GBASE_LR4 = 23,
713 MLX5E_100BASE_TX = 24,
714 MLX5E_100BASE_T = 25,
715 MLX5E_10GBASE_T = 26,
716 MLX5E_25GBASE_CR = 27,
717 MLX5E_25GBASE_KR = 28,
718 MLX5E_25GBASE_SR = 29,
719 MLX5E_50GBASE_CR2 = 30,
720 MLX5E_50GBASE_KR2 = 31,
721 MLX5E_LINK_MODES_NUMBER,
724 #define MLX5E_PROT_MASK(link_mode) (1 << (link_mode))
725 #define MLX5E_FLD_MAX(typ, fld) ((1ULL << __mlx5_bit_sz(typ, fld)) - 1ULL)
727 int mlx5e_xmit(struct ifnet *, struct mbuf *);
729 int mlx5e_open_locked(struct ifnet *);
730 int mlx5e_close_locked(struct ifnet *);
732 void mlx5e_cq_error_event(struct mlx5_core_cq *mcq, int event);
733 void mlx5e_rx_cq_comp(struct mlx5_core_cq *);
734 void mlx5e_tx_cq_comp(struct mlx5_core_cq *);
735 struct mlx5_cqe64 *mlx5e_get_cqe(struct mlx5e_cq *cq);
736 void mlx5e_tx_que(void *context, int pending);
738 int mlx5e_open_flow_table(struct mlx5e_priv *priv);
739 void mlx5e_close_flow_table(struct mlx5e_priv *priv);
740 void mlx5e_set_rx_mode_core(struct mlx5e_priv *priv);
741 void mlx5e_set_rx_mode_work(struct work_struct *work);
743 void mlx5e_vlan_rx_add_vid(void *, struct ifnet *, u16);
744 void mlx5e_vlan_rx_kill_vid(void *, struct ifnet *, u16);
745 void mlx5e_enable_vlan_filter(struct mlx5e_priv *priv);
746 void mlx5e_disable_vlan_filter(struct mlx5e_priv *priv);
747 int mlx5e_add_all_vlan_rules(struct mlx5e_priv *priv);
748 void mlx5e_del_all_vlan_rules(struct mlx5e_priv *priv);
751 mlx5e_tx_notify_hw(struct mlx5e_sq *sq, u32 *wqe, int bf_sz)
753 u16 ofst = MLX5_BF_OFFSET + sq->bf_offset;
755 /* ensure wqe is visible to device before updating doorbell record */
758 *sq->wq.db = cpu_to_be32(sq->pc);
761 * Ensure the doorbell record is visible to device before ringing
767 __iowrite64_copy(sq->uar_bf_map + ofst, wqe, bf_sz);
769 /* flush the write-combining mapped buffer */
773 mlx5_write64(wqe, sq->uar_map + ofst, NULL);
776 sq->bf_offset ^= sq->bf_buf_size;
780 mlx5e_cq_arm(struct mlx5e_cq *cq)
782 struct mlx5_core_cq *mcq;
785 mlx5_cq_arm(mcq, MLX5_CQ_DB_REQ_NOT, mcq->uar->map, NULL, cq->wq.cc);
788 extern const struct ethtool_ops mlx5e_ethtool_ops;
789 void mlx5e_create_ethtool(struct mlx5e_priv *);
790 void mlx5e_create_stats(struct sysctl_ctx_list *,
791 struct sysctl_oid_list *, const char *,
792 const char **, unsigned, u64 *);
793 void mlx5e_send_nop(struct mlx5e_sq *, u32);
794 void mlx5e_sq_cev_timeout(void *);
795 int mlx5e_refresh_channel_params(struct mlx5e_priv *);
797 #endif /* _MLX5_EN_H_ */