2 * Copyright (c) 2015-2021 Mellanox Technologies. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include "opt_ratelimit.h"
29 #include <dev/mlx5/mlx5_en/en.h>
30 #include <dev/mlx5/mlx5_en/port_buffer.h>
33 mlx5e_create_stats(struct sysctl_ctx_list *ctx,
34 struct sysctl_oid_list *parent, const char *buffer,
35 const char **desc, unsigned num, u64 * arg)
37 struct sysctl_oid *node;
42 node = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO,
43 buffer, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics");
46 for (x = 0; x != num; x++) {
47 SYSCTL_ADD_UQUAD(ctx, SYSCTL_CHILDREN(node), OID_AUTO,
48 desc[2 * x], CTLFLAG_RD, arg + x, desc[2 * x + 1]);
53 mlx5e_create_counter_stats(struct sysctl_ctx_list *ctx,
54 struct sysctl_oid_list *parent, const char *buffer,
55 const char **desc, unsigned num, counter_u64_t *arg)
57 struct sysctl_oid *node;
62 node = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO,
63 buffer, CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Statistics");
66 for (x = 0; x != num; x++) {
67 SYSCTL_ADD_COUNTER_U64(ctx, SYSCTL_CHILDREN(node), OID_AUTO,
68 desc[2 * x], CTLFLAG_RD, arg + x, desc[2 * x + 1]);
73 mlx5e_ethtool_sync_tx_completion_fact(struct mlx5e_priv *priv)
76 * Limit the maximum distance between completion events to
77 * half of the currently set TX queue size.
79 * The maximum number of queue entries a single IP packet can
80 * consume is given by MLX5_SEND_WQE_MAX_WQEBBS.
82 * The worst case max value is then given as below:
84 uint64_t max = priv->params_ethtool.tx_queue_size /
85 (2 * MLX5_SEND_WQE_MAX_WQEBBS);
88 * Update the maximum completion factor value in case the
89 * tx_queue_size field changed. Ensure we don't overflow
96 priv->params_ethtool.tx_completion_fact_max = max;
99 * Verify that the current TX completion factor is within the
102 if (priv->params_ethtool.tx_completion_fact < 1)
103 priv->params_ethtool.tx_completion_fact = 1;
104 else if (priv->params_ethtool.tx_completion_fact > max)
105 priv->params_ethtool.tx_completion_fact = max;
109 mlx5e_getmaxrate(struct mlx5e_priv *priv)
111 struct mlx5_core_dev *mdev = priv->mdev;
112 u8 max_bw_unit[IEEE_8021QAZ_MAX_TCS];
113 u8 max_bw_value[IEEE_8021QAZ_MAX_TCS];
118 err = -mlx5_query_port_tc_rate_limit(mdev, max_bw_value, max_bw_unit);
122 for (i = 0; i <= mlx5_max_tc(mdev); i++) {
123 switch (max_bw_unit[i]) {
124 case MLX5_100_MBPS_UNIT:
125 priv->params_ethtool.max_bw_value[i] = max_bw_value[i] * MLX5E_100MB;
128 priv->params_ethtool.max_bw_value[i] = max_bw_value[i] * MLX5E_1GB;
130 case MLX5_BW_NO_LIMIT:
131 priv->params_ethtool.max_bw_value[i] = 0;
134 priv->params_ethtool.max_bw_value[i] = -1;
135 WARN_ONCE(true, "non-supported BW unit");
145 mlx5e_get_max_alloc(struct mlx5e_priv *priv)
147 struct mlx5_core_dev *mdev = priv->mdev;
152 err = -mlx5_query_port_tc_bw_alloc(mdev, priv->params_ethtool.max_bw_share);
154 /* set default value */
155 for (x = 0; x != IEEE_8021QAZ_MAX_TCS; x++) {
156 priv->params_ethtool.max_bw_share[x] =
157 100 / IEEE_8021QAZ_MAX_TCS;
159 err = -mlx5_set_port_tc_bw_alloc(mdev,
160 priv->params_ethtool.max_bw_share);
168 mlx5e_get_dscp(struct mlx5e_priv *priv)
170 struct mlx5_core_dev *mdev = priv->mdev;
173 if (MLX5_CAP_GEN(mdev, qcam_reg) == 0 ||
174 MLX5_CAP_QCAM_REG(mdev, qpts) == 0 ||
175 MLX5_CAP_QCAM_REG(mdev, qpdpm) == 0)
179 err = -mlx5_query_dscp2prio(mdev, priv->params_ethtool.dscp2prio);
183 err = -mlx5_query_trust_state(mdev, &priv->params_ethtool.trust_state);
192 mlx5e_tc_get_parameters(struct mlx5e_priv *priv,
193 u64 *new_bw_value, u8 *max_bw_value, u8 *max_bw_unit)
195 const u64 upper_limit_mbps = 255 * MLX5E_100MB;
196 const u64 upper_limit_gbps = 255 * MLX5E_1GB;
200 memset(max_bw_value, 0, IEEE_8021QAZ_MAX_TCS);
201 memset(max_bw_unit, 0, IEEE_8021QAZ_MAX_TCS);
203 for (i = 0; i <= mlx5_max_tc(priv->mdev); i++) {
204 temp = (new_bw_value != NULL) ?
205 new_bw_value[i] : priv->params_ethtool.max_bw_value[i];
208 max_bw_unit[i] = MLX5_BW_NO_LIMIT;
209 } else if (temp > upper_limit_gbps) {
210 max_bw_unit[i] = MLX5_BW_NO_LIMIT;
211 } else if (temp <= upper_limit_mbps) {
212 max_bw_value[i] = howmany(temp, MLX5E_100MB);
213 max_bw_unit[i] = MLX5_100_MBPS_UNIT;
215 max_bw_value[i] = howmany(temp, MLX5E_1GB);
216 max_bw_unit[i] = MLX5_GBPS_UNIT;
222 mlx5e_tc_maxrate_handler(SYSCTL_HANDLER_ARGS)
224 struct mlx5e_priv *priv = arg1;
225 struct mlx5_core_dev *mdev = priv->mdev;
226 u8 max_bw_unit[IEEE_8021QAZ_MAX_TCS];
227 u8 max_bw_value[IEEE_8021QAZ_MAX_TCS];
228 u64 new_bw_value[IEEE_8021QAZ_MAX_TCS];
229 u8 max_rates = mlx5_max_tc(mdev) + 1;
234 err = SYSCTL_OUT(req, priv->params_ethtool.max_bw_value,
235 sizeof(priv->params_ethtool.max_bw_value[0]) * max_rates);
236 if (err || !req->newptr)
238 err = SYSCTL_IN(req, new_bw_value,
239 sizeof(new_bw_value[0]) * max_rates);
243 /* range check input value */
244 for (x = 0; x != max_rates; x++) {
245 if (new_bw_value[x] % MLX5E_100MB) {
251 mlx5e_tc_get_parameters(priv, new_bw_value, max_bw_value, max_bw_unit);
253 err = -mlx5_modify_port_tc_rate_limit(mdev, max_bw_value, max_bw_unit);
257 memcpy(priv->params_ethtool.max_bw_value, new_bw_value,
258 sizeof(priv->params_ethtool.max_bw_value));
265 mlx5e_tc_rate_share_handler(SYSCTL_HANDLER_ARGS)
267 struct mlx5e_priv *priv = arg1;
268 struct mlx5_core_dev *mdev = priv->mdev;
269 u8 max_bw_share[IEEE_8021QAZ_MAX_TCS];
270 u8 max_rates = mlx5_max_tc(mdev) + 1;
276 err = SYSCTL_OUT(req, priv->params_ethtool.max_bw_share, max_rates);
277 if (err || !req->newptr)
279 err = SYSCTL_IN(req, max_bw_share, max_rates);
283 /* range check input value */
284 for (sum = i = 0; i != max_rates; i++) {
285 if (max_bw_share[i] < 1 || max_bw_share[i] > 100) {
289 sum += max_bw_share[i];
292 /* sum of values should be as close to 100 as possible */
293 if (sum < (100 - max_rates + 1) || sum > 100) {
298 err = -mlx5_set_port_tc_bw_alloc(mdev, max_bw_share);
302 memcpy(priv->params_ethtool.max_bw_share, max_bw_share,
303 sizeof(priv->params_ethtool.max_bw_share));
310 mlx5e_get_prio_tc(struct mlx5e_priv *priv)
312 struct mlx5_core_dev *mdev = priv->mdev;
317 if (!MLX5_CAP_GEN(priv->mdev, ets)) {
322 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
323 err = -mlx5_query_port_prio_tc(mdev, i, priv->params_ethtool.prio_tc + i);
332 mlx5e_prio_to_tc_handler(SYSCTL_HANDLER_ARGS)
334 struct mlx5e_priv *priv = arg1;
335 struct mlx5_core_dev *mdev = priv->mdev;
336 uint8_t temp[MLX5E_MAX_PRIORITY];
341 err = SYSCTL_OUT(req, priv->params_ethtool.prio_tc, MLX5E_MAX_PRIORITY);
342 if (err || !req->newptr)
344 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
348 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
349 if (temp[i] > mlx5_max_tc(mdev)) {
355 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
356 if (temp[i] == priv->params_ethtool.prio_tc[i])
358 err = -mlx5_set_port_prio_tc(mdev, i, temp[i]);
361 /* update cached value */
362 priv->params_ethtool.prio_tc[i] = temp[i];
370 mlx5e_fec_update(struct mlx5e_priv *priv)
372 struct mlx5_core_dev *mdev = priv->mdev;
373 u32 in[MLX5_ST_SZ_DW(pplm_reg)] = {};
374 const int sz = MLX5_ST_SZ_BYTES(pplm_reg);
377 if (!MLX5_CAP_GEN(mdev, pcam_reg))
380 if (!MLX5_CAP_PCAM_REG(mdev, pplm))
383 MLX5_SET(pplm_reg, in, local_port, 1);
385 err = -mlx5_core_access_reg(mdev, in, sz, in, sz, MLX5_REG_PPLM, 0, 0);
389 /* get 10x..25x mask */
390 priv->params_ethtool.fec_mask_10x_25x[0] =
391 MLX5_GET(pplm_reg, in, fec_override_admin_10g_40g);
392 priv->params_ethtool.fec_mask_10x_25x[1] =
393 MLX5_GET(pplm_reg, in, fec_override_admin_25g) &
394 MLX5_GET(pplm_reg, in, fec_override_admin_50g);
395 priv->params_ethtool.fec_mask_10x_25x[2] =
396 MLX5_GET(pplm_reg, in, fec_override_admin_56g);
397 priv->params_ethtool.fec_mask_10x_25x[3] =
398 MLX5_GET(pplm_reg, in, fec_override_admin_100g);
400 /* get 10x..25x available bits */
401 priv->params_ethtool.fec_avail_10x_25x[0] =
402 MLX5_GET(pplm_reg, in, fec_override_cap_10g_40g);
403 priv->params_ethtool.fec_avail_10x_25x[1] =
404 MLX5_GET(pplm_reg, in, fec_override_cap_25g) &
405 MLX5_GET(pplm_reg, in, fec_override_cap_50g);
406 priv->params_ethtool.fec_avail_10x_25x[2] =
407 MLX5_GET(pplm_reg, in, fec_override_cap_56g);
408 priv->params_ethtool.fec_avail_10x_25x[3] =
409 MLX5_GET(pplm_reg, in, fec_override_cap_100g);
412 priv->params_ethtool.fec_mask_50x[0] =
413 MLX5_GET(pplm_reg, in, fec_override_admin_50g_1x);
414 priv->params_ethtool.fec_mask_50x[1] =
415 MLX5_GET(pplm_reg, in, fec_override_admin_100g_2x);
416 priv->params_ethtool.fec_mask_50x[2] =
417 MLX5_GET(pplm_reg, in, fec_override_admin_200g_4x);
418 priv->params_ethtool.fec_mask_50x[3] =
419 MLX5_GET(pplm_reg, in, fec_override_admin_400g_8x);
421 /* get 50x available bits */
422 priv->params_ethtool.fec_avail_50x[0] =
423 MLX5_GET(pplm_reg, in, fec_override_cap_50g_1x);
424 priv->params_ethtool.fec_avail_50x[1] =
425 MLX5_GET(pplm_reg, in, fec_override_cap_100g_2x);
426 priv->params_ethtool.fec_avail_50x[2] =
427 MLX5_GET(pplm_reg, in, fec_override_cap_200g_4x);
428 priv->params_ethtool.fec_avail_50x[3] =
429 MLX5_GET(pplm_reg, in, fec_override_cap_400g_8x);
431 /* get current FEC mask */
432 priv->params_ethtool.fec_mode_active =
433 MLX5_GET(pplm_reg, in, fec_mode_active);
439 mlx5e_fec_mask_10x_25x_handler(SYSCTL_HANDLER_ARGS)
441 struct mlx5e_priv *priv = arg1;
442 struct mlx5_core_dev *mdev = priv->mdev;
443 u32 out[MLX5_ST_SZ_DW(pplm_reg)] = {};
444 u32 in[MLX5_ST_SZ_DW(pplm_reg)] = {};
445 const int sz = MLX5_ST_SZ_BYTES(pplm_reg);
446 u8 fec_mask_10x_25x[MLX5E_MAX_FEC_10X_25X];
447 u8 fec_cap_changed = 0;
452 err = SYSCTL_OUT(req, priv->params_ethtool.fec_mask_10x_25x,
453 sizeof(priv->params_ethtool.fec_mask_10x_25x));
454 if (err || !req->newptr)
457 err = SYSCTL_IN(req, fec_mask_10x_25x,
458 sizeof(fec_mask_10x_25x));
462 if (!MLX5_CAP_GEN(mdev, pcam_reg)) {
467 if (!MLX5_CAP_PCAM_REG(mdev, pplm)) {
472 MLX5_SET(pplm_reg, in, local_port, 1);
474 err = -mlx5_core_access_reg(mdev, in, sz, in, sz, MLX5_REG_PPLM, 0, 0);
478 /* range check input value */
479 for (x = 0; x != MLX5E_MAX_FEC_10X_25X; x++) {
480 /* check only one bit is set, if any */
481 if (fec_mask_10x_25x[x] & (fec_mask_10x_25x[x] - 1)) {
485 /* check a supported bit is set, if any */
486 if (fec_mask_10x_25x[x] &
487 ~priv->params_ethtool.fec_avail_10x_25x[x]) {
491 fec_cap_changed |= (fec_mask_10x_25x[x] ^
492 priv->params_ethtool.fec_mask_10x_25x[x]);
495 /* check for no changes */
496 if (fec_cap_changed == 0)
499 memset(in, 0, sizeof(in));
501 MLX5_SET(pplm_reg, in, local_port, 1);
504 MLX5_SET(pplm_reg, in, fec_override_admin_10g_40g, fec_mask_10x_25x[0]);
505 MLX5_SET(pplm_reg, in, fec_override_admin_25g, fec_mask_10x_25x[1]);
506 MLX5_SET(pplm_reg, in, fec_override_admin_50g, fec_mask_10x_25x[1]);
507 MLX5_SET(pplm_reg, in, fec_override_admin_56g, fec_mask_10x_25x[2]);
508 MLX5_SET(pplm_reg, in, fec_override_admin_100g, fec_mask_10x_25x[3]);
510 /* preserve other values */
511 MLX5_SET(pplm_reg, in, fec_override_admin_50g_1x, priv->params_ethtool.fec_mask_50x[0]);
512 MLX5_SET(pplm_reg, in, fec_override_admin_100g_2x, priv->params_ethtool.fec_mask_50x[1]);
513 MLX5_SET(pplm_reg, in, fec_override_admin_200g_4x, priv->params_ethtool.fec_mask_50x[2]);
514 MLX5_SET(pplm_reg, in, fec_override_admin_400g_8x, priv->params_ethtool.fec_mask_50x[3]);
516 /* send new value to the firmware */
517 err = -mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPLM, 0, 1);
521 memcpy(priv->params_ethtool.fec_mask_10x_25x, fec_mask_10x_25x,
522 sizeof(priv->params_ethtool.fec_mask_10x_25x));
524 mlx5_toggle_port_link(priv->mdev);
531 mlx5e_fec_avail_10x_25x_handler(SYSCTL_HANDLER_ARGS)
533 struct mlx5e_priv *priv = arg1;
537 err = SYSCTL_OUT(req, priv->params_ethtool.fec_avail_10x_25x,
538 sizeof(priv->params_ethtool.fec_avail_10x_25x));
544 mlx5e_fec_mask_50x_handler(SYSCTL_HANDLER_ARGS)
546 struct mlx5e_priv *priv = arg1;
547 struct mlx5_core_dev *mdev = priv->mdev;
548 u32 out[MLX5_ST_SZ_DW(pplm_reg)] = {};
549 u32 in[MLX5_ST_SZ_DW(pplm_reg)] = {};
550 const int sz = MLX5_ST_SZ_BYTES(pplm_reg);
551 u16 fec_mask_50x[MLX5E_MAX_FEC_50X];
552 u16 fec_cap_changed = 0;
557 err = SYSCTL_OUT(req, priv->params_ethtool.fec_mask_50x,
558 sizeof(priv->params_ethtool.fec_mask_50x));
559 if (err || !req->newptr)
562 err = SYSCTL_IN(req, fec_mask_50x,
563 sizeof(fec_mask_50x));
567 if (!MLX5_CAP_GEN(mdev, pcam_reg)) {
572 if (!MLX5_CAP_PCAM_REG(mdev, pplm)) {
577 MLX5_SET(pplm_reg, in, local_port, 1);
579 err = -mlx5_core_access_reg(mdev, in, sz, in, sz, MLX5_REG_PPLM, 0, 0);
583 /* range check input value */
584 for (x = 0; x != MLX5E_MAX_FEC_50X; x++) {
585 /* check only one bit is set, if any */
586 if (fec_mask_50x[x] & (fec_mask_50x[x] - 1)) {
590 /* check a supported bit is set, if any */
591 if (fec_mask_50x[x] &
592 ~priv->params_ethtool.fec_avail_50x[x]) {
596 fec_cap_changed |= (fec_mask_50x[x] ^
597 priv->params_ethtool.fec_mask_50x[x]);
600 /* check for no changes */
601 if (fec_cap_changed == 0)
604 memset(in, 0, sizeof(in));
606 MLX5_SET(pplm_reg, in, local_port, 1);
609 MLX5_SET(pplm_reg, in, fec_override_admin_50g_1x, fec_mask_50x[0]);
610 MLX5_SET(pplm_reg, in, fec_override_admin_100g_2x, fec_mask_50x[1]);
611 MLX5_SET(pplm_reg, in, fec_override_admin_200g_4x, fec_mask_50x[2]);
612 MLX5_SET(pplm_reg, in, fec_override_admin_400g_8x, fec_mask_50x[3]);
614 /* preserve other values */
615 MLX5_SET(pplm_reg, in, fec_override_admin_10g_40g, priv->params_ethtool.fec_mask_10x_25x[0]);
616 MLX5_SET(pplm_reg, in, fec_override_admin_25g, priv->params_ethtool.fec_mask_10x_25x[1]);
617 MLX5_SET(pplm_reg, in, fec_override_admin_50g, priv->params_ethtool.fec_mask_10x_25x[1]);
618 MLX5_SET(pplm_reg, in, fec_override_admin_56g, priv->params_ethtool.fec_mask_10x_25x[2]);
619 MLX5_SET(pplm_reg, in, fec_override_admin_100g, priv->params_ethtool.fec_mask_10x_25x[3]);
621 /* send new value to the firmware */
622 err = -mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPLM, 0, 1);
626 memcpy(priv->params_ethtool.fec_mask_50x, fec_mask_50x,
627 sizeof(priv->params_ethtool.fec_mask_50x));
629 mlx5_toggle_port_link(priv->mdev);
636 mlx5e_fec_avail_50x_handler(SYSCTL_HANDLER_ARGS)
638 struct mlx5e_priv *priv = arg1;
642 err = SYSCTL_OUT(req, priv->params_ethtool.fec_avail_50x,
643 sizeof(priv->params_ethtool.fec_avail_50x));
649 mlx5e_trust_state_handler(SYSCTL_HANDLER_ARGS)
651 struct mlx5e_priv *priv = arg1;
652 struct mlx5_core_dev *mdev = priv->mdev;
657 result = priv->params_ethtool.trust_state;
658 err = sysctl_handle_8(oidp, &result, 0, req);
659 if (err || !req->newptr ||
660 result == priv->params_ethtool.trust_state)
664 case MLX5_QPTS_TRUST_PCP:
665 case MLX5_QPTS_TRUST_DSCP:
667 case MLX5_QPTS_TRUST_BOTH:
668 if (!MLX5_CAP_QCAM_FEATURE(mdev, qpts_trust_both)) {
678 err = -mlx5_set_trust_state(mdev, result);
682 priv->params_ethtool.trust_state = result;
684 /* update inline mode */
685 mlx5e_refresh_sq_inline(priv);
687 mlx5e_rl_refresh_sq_inline(&priv->rl);
695 mlx5e_dscp_prio_handler(SYSCTL_HANDLER_ARGS)
697 struct mlx5e_priv *priv = arg1;
698 int prio_index = arg2;
699 struct mlx5_core_dev *mdev = priv->mdev;
700 uint8_t dscp2prio[MLX5_MAX_SUPPORTED_DSCP];
705 err = SYSCTL_OUT(req, priv->params_ethtool.dscp2prio + prio_index,
706 sizeof(priv->params_ethtool.dscp2prio) / 8);
707 if (err || !req->newptr)
710 memcpy(dscp2prio, priv->params_ethtool.dscp2prio, sizeof(dscp2prio));
711 err = SYSCTL_IN(req, dscp2prio + prio_index, sizeof(dscp2prio) / 8);
714 for (x = 0; x != MLX5_MAX_SUPPORTED_DSCP; x++) {
715 if (dscp2prio[x] > 7) {
720 err = -mlx5_set_dscp2prio(mdev, dscp2prio);
724 /* update local array */
725 memcpy(priv->params_ethtool.dscp2prio, dscp2prio,
726 sizeof(priv->params_ethtool.dscp2prio));
733 mlx5e_update_buf_lossy(struct mlx5e_priv *priv)
737 PRIV_ASSERT_LOCKED(priv);
738 bzero(&pfc, sizeof(pfc));
739 pfc.pfc_en = priv->params.rx_priority_flow_control;
740 return (-mlx5e_port_manual_buffer_config(priv, MLX5E_PORT_BUFFER_PFC,
741 priv->params_ethtool.hw_mtu, &pfc, NULL, NULL));
745 mlx5e_buf_size_handler(SYSCTL_HANDLER_ARGS)
747 struct mlx5e_priv *priv;
748 u32 buf_size[MLX5E_MAX_BUFFER];
749 struct mlx5e_port_buffer port_buffer;
754 error = -mlx5e_port_query_buffer(priv, &port_buffer);
757 for (i = 0; i < nitems(buf_size); i++)
758 buf_size[i] = port_buffer.buffer[i].size;
759 error = SYSCTL_OUT(req, buf_size, sizeof(buf_size));
760 if (error != 0 || req->newptr == NULL)
762 error = SYSCTL_IN(req, buf_size, sizeof(buf_size));
765 error = -mlx5e_port_manual_buffer_config(priv, MLX5E_PORT_BUFFER_SIZE,
766 priv->params_ethtool.hw_mtu, NULL, buf_size, NULL);
773 mlx5e_buf_prio_handler(SYSCTL_HANDLER_ARGS)
775 struct mlx5e_priv *priv;
776 struct mlx5_core_dev *mdev;
777 u8 buffer[MLX5E_MAX_BUFFER];
783 error = -mlx5e_port_query_priority2buffer(mdev, buffer);
786 error = SYSCTL_OUT(req, buffer, MLX5E_MAX_BUFFER);
787 if (error != 0 || req->newptr == NULL)
789 error = SYSCTL_IN(req, buffer, MLX5E_MAX_BUFFER);
792 error = -mlx5e_port_manual_buffer_config(priv,
793 MLX5E_PORT_BUFFER_PRIO2BUFFER,
794 priv->params_ethtool.hw_mtu, NULL, NULL, buffer);
796 error = mlx5e_update_buf_lossy(priv);
803 mlx5e_cable_length_handler(SYSCTL_HANDLER_ARGS)
805 struct mlx5e_priv *priv;
811 cable_len = priv->dcbx.cable_len;
812 error = sysctl_handle_int(oidp, &cable_len, 0, req);
813 if (error == 0 && req->newptr != NULL &&
814 cable_len != priv->dcbx.cable_len) {
815 error = -mlx5e_port_manual_buffer_config(priv,
816 MLX5E_PORT_BUFFER_CABLE_LEN, priv->params_ethtool.hw_mtu,
819 priv->dcbx.cable_len = cable_len;
826 mlx5e_hw_temperature_handler(SYSCTL_HANDLER_ARGS)
828 struct mlx5e_priv *priv = arg1;
832 err = SYSCTL_OUT(req, priv->params_ethtool.hw_val_temp,
833 sizeof(priv->params_ethtool.hw_val_temp[0]) *
834 priv->params_ethtool.hw_num_temp);
835 if (err == 0 && req->newptr != NULL)
842 mlx5e_hw_temperature_update(struct mlx5e_priv *priv)
847 if (priv->params_ethtool.hw_num_temp == 0) {
848 u32 out_cap[MLX5_ST_SZ_DW(mtcap)] = {};
849 const int sz_cap = MLX5_ST_SZ_BYTES(mtcap);
852 err = -mlx5_core_access_reg(priv->mdev, NULL, 0, out_cap, sz_cap,
853 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTCAP, 0, 0);
856 value = MLX5_GET(mtcap, out_cap, sensor_count);
859 if (value > MLX5_MAX_TEMPERATURE)
860 value = MLX5_MAX_TEMPERATURE;
861 /* update number of temperature sensors */
862 priv->params_ethtool.hw_num_temp = value;
865 for (x = 0; x != priv->params_ethtool.hw_num_temp; x++) {
866 u32 out_sensor[MLX5_ST_SZ_DW(mtmp_reg)] = {};
867 const int sz_sensor = MLX5_ST_SZ_BYTES(mtmp_reg);
869 MLX5_SET(mtmp_reg, out_sensor, sensor_index, x);
871 err = -mlx5_core_access_reg(priv->mdev, out_sensor, sz_sensor,
872 out_sensor, sz_sensor,
873 MLX5_ACCESS_REG_SUMMARY_CTRL_ID_MTMP, 0, 0);
876 /* convert from 0.125 celsius to millicelsius */
877 priv->params_ethtool.hw_val_temp[x] =
878 (s16)MLX5_GET(mtmp_reg, out_sensor, temperature) * 125;
884 #define MLX5_PARAM_OFFSET(n) \
885 __offsetof(struct mlx5e_priv, params_ethtool.n)
888 mlx5e_ethtool_handler(SYSCTL_HANDLER_ARGS)
890 struct mlx5e_priv *priv = arg1;
897 value = priv->params_ethtool.arg[arg2];
899 error = sysctl_handle_64(oidp, &value, 0, req);
900 if (error || req->newptr == NULL ||
901 value == priv->params_ethtool.arg[arg2])
904 /* assign new value */
905 priv->params_ethtool.arg[arg2] = value;
909 /* check if device is gone */
914 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
915 mode_modify = MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify);
917 switch (MLX5_PARAM_OFFSET(arg[arg2])) {
918 case MLX5_PARAM_OFFSET(rx_coalesce_usecs):
919 /* import RX coal time */
920 if (priv->params_ethtool.rx_coalesce_usecs < 1)
921 priv->params_ethtool.rx_coalesce_usecs = 0;
922 else if (priv->params_ethtool.rx_coalesce_usecs >
923 MLX5E_FLD_MAX(cqc, cq_period)) {
924 priv->params_ethtool.rx_coalesce_usecs =
925 MLX5E_FLD_MAX(cqc, cq_period);
927 priv->params.rx_cq_moderation_usec =
928 priv->params_ethtool.rx_coalesce_usecs;
930 /* check to avoid down and up the network interface */
932 error = mlx5e_refresh_channel_params(priv);
935 case MLX5_PARAM_OFFSET(rx_coalesce_pkts):
936 /* import RX coal pkts */
937 if (priv->params_ethtool.rx_coalesce_pkts < 1)
938 priv->params_ethtool.rx_coalesce_pkts = 0;
939 else if (priv->params_ethtool.rx_coalesce_pkts >
940 MLX5E_FLD_MAX(cqc, cq_max_count)) {
941 priv->params_ethtool.rx_coalesce_pkts =
942 MLX5E_FLD_MAX(cqc, cq_max_count);
944 priv->params.rx_cq_moderation_pkts =
945 priv->params_ethtool.rx_coalesce_pkts;
947 /* check to avoid down and up the network interface */
949 error = mlx5e_refresh_channel_params(priv);
952 case MLX5_PARAM_OFFSET(tx_coalesce_usecs):
953 /* import TX coal time */
954 if (priv->params_ethtool.tx_coalesce_usecs < 1)
955 priv->params_ethtool.tx_coalesce_usecs = 0;
956 else if (priv->params_ethtool.tx_coalesce_usecs >
957 MLX5E_FLD_MAX(cqc, cq_period)) {
958 priv->params_ethtool.tx_coalesce_usecs =
959 MLX5E_FLD_MAX(cqc, cq_period);
961 priv->params.tx_cq_moderation_usec =
962 priv->params_ethtool.tx_coalesce_usecs;
964 /* check to avoid down and up the network interface */
966 error = mlx5e_refresh_channel_params(priv);
969 case MLX5_PARAM_OFFSET(tx_coalesce_pkts):
970 /* import TX coal pkts */
971 if (priv->params_ethtool.tx_coalesce_pkts < 1)
972 priv->params_ethtool.tx_coalesce_pkts = 0;
973 else if (priv->params_ethtool.tx_coalesce_pkts >
974 MLX5E_FLD_MAX(cqc, cq_max_count)) {
975 priv->params_ethtool.tx_coalesce_pkts =
976 MLX5E_FLD_MAX(cqc, cq_max_count);
978 priv->params.tx_cq_moderation_pkts =
979 priv->params_ethtool.tx_coalesce_pkts;
981 /* check to avoid down and up the network interface */
983 error = mlx5e_refresh_channel_params(priv);
986 case MLX5_PARAM_OFFSET(tx_queue_size):
987 /* network interface must be down */
989 mlx5e_close_locked(priv->ifp);
991 /* import TX queue size */
992 if (priv->params_ethtool.tx_queue_size <
993 (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE)) {
994 priv->params_ethtool.tx_queue_size =
995 (1 << MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE);
996 } else if (priv->params_ethtool.tx_queue_size >
997 priv->params_ethtool.tx_queue_size_max) {
998 priv->params_ethtool.tx_queue_size =
999 priv->params_ethtool.tx_queue_size_max;
1001 /* store actual TX queue size */
1002 priv->params.log_sq_size =
1003 order_base_2(priv->params_ethtool.tx_queue_size);
1004 priv->params_ethtool.tx_queue_size =
1005 1 << priv->params.log_sq_size;
1007 /* verify TX completion factor */
1008 mlx5e_ethtool_sync_tx_completion_fact(priv);
1010 /* restart network interface, if any */
1012 mlx5e_open_locked(priv->ifp);
1015 case MLX5_PARAM_OFFSET(rx_queue_size):
1016 /* network interface must be down */
1018 mlx5e_close_locked(priv->ifp);
1020 /* import RX queue size */
1021 if (priv->params_ethtool.rx_queue_size <
1022 (1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE)) {
1023 priv->params_ethtool.rx_queue_size =
1024 (1 << MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE);
1025 } else if (priv->params_ethtool.rx_queue_size >
1026 priv->params_ethtool.rx_queue_size_max) {
1027 priv->params_ethtool.rx_queue_size =
1028 priv->params_ethtool.rx_queue_size_max;
1030 /* store actual RX queue size */
1031 priv->params.log_rq_size =
1032 order_base_2(priv->params_ethtool.rx_queue_size);
1033 priv->params_ethtool.rx_queue_size =
1034 1 << priv->params.log_rq_size;
1036 /* restart network interface, if any */
1038 mlx5e_open_locked(priv->ifp);
1041 case MLX5_PARAM_OFFSET(channels_rsss):
1042 /* network interface must be down */
1044 mlx5e_close_locked(priv->ifp);
1046 /* import number of channels */
1047 if (priv->params_ethtool.channels_rsss < 1)
1048 priv->params_ethtool.channels_rsss = 1;
1049 else if (priv->params_ethtool.channels_rsss > 128)
1050 priv->params_ethtool.channels_rsss = 128;
1052 priv->params.channels_rsss = priv->params_ethtool.channels_rsss;
1054 /* restart network interface, if any */
1056 mlx5e_open_locked(priv->ifp);
1059 case MLX5_PARAM_OFFSET(channels):
1060 /* network interface must be down */
1062 mlx5e_close_locked(priv->ifp);
1064 /* import number of channels */
1065 if (priv->params_ethtool.channels < 1)
1066 priv->params_ethtool.channels = 1;
1067 else if (priv->params_ethtool.channels >
1068 (u64) priv->mdev->priv.eq_table.num_comp_vectors) {
1069 priv->params_ethtool.channels =
1070 (u64) priv->mdev->priv.eq_table.num_comp_vectors;
1072 priv->params.num_channels = priv->params_ethtool.channels;
1074 /* restart network interface, if any */
1076 mlx5e_open_locked(priv->ifp);
1079 case MLX5_PARAM_OFFSET(rx_coalesce_mode):
1080 /* network interface must be down */
1081 if (was_opened != 0 && mode_modify == 0)
1082 mlx5e_close_locked(priv->ifp);
1084 /* import RX coalesce mode */
1085 if (priv->params_ethtool.rx_coalesce_mode > 3)
1086 priv->params_ethtool.rx_coalesce_mode = 3;
1087 priv->params.rx_cq_moderation_mode =
1088 priv->params_ethtool.rx_coalesce_mode;
1090 /* restart network interface, if any */
1091 if (was_opened != 0) {
1092 if (mode_modify == 0)
1093 mlx5e_open_locked(priv->ifp);
1095 error = mlx5e_refresh_channel_params(priv);
1099 case MLX5_PARAM_OFFSET(tx_coalesce_mode):
1100 /* network interface must be down */
1101 if (was_opened != 0 && mode_modify == 0)
1102 mlx5e_close_locked(priv->ifp);
1104 /* import TX coalesce mode */
1105 if (priv->params_ethtool.tx_coalesce_mode != 0)
1106 priv->params_ethtool.tx_coalesce_mode = 1;
1107 priv->params.tx_cq_moderation_mode =
1108 priv->params_ethtool.tx_coalesce_mode;
1110 /* restart network interface, if any */
1111 if (was_opened != 0) {
1112 if (mode_modify == 0)
1113 mlx5e_open_locked(priv->ifp);
1115 error = mlx5e_refresh_channel_params(priv);
1119 case MLX5_PARAM_OFFSET(hw_lro):
1120 /* network interface must be down */
1122 mlx5e_close_locked(priv->ifp);
1124 /* import HW LRO mode */
1125 if (priv->params_ethtool.hw_lro != 0 &&
1126 MLX5_CAP_ETH(priv->mdev, lro_cap)) {
1127 priv->params_ethtool.hw_lro = 1;
1128 /* check if feature should actually be enabled */
1129 if (if_getcapenable(priv->ifp) & IFCAP_LRO) {
1130 priv->params.hw_lro_en = true;
1132 priv->params.hw_lro_en = false;
1134 mlx5_en_warn(priv->ifp, "To enable HW LRO "
1135 "please also enable LRO via ifconfig(8).\n");
1138 /* return an error if HW does not support this feature */
1139 if (priv->params_ethtool.hw_lro != 0)
1141 priv->params.hw_lro_en = false;
1142 priv->params_ethtool.hw_lro = 0;
1144 /* restart network interface, if any */
1146 mlx5e_open_locked(priv->ifp);
1149 case MLX5_PARAM_OFFSET(cqe_zipping):
1150 /* network interface must be down */
1152 mlx5e_close_locked(priv->ifp);
1154 /* import CQE zipping mode */
1155 if (priv->params_ethtool.cqe_zipping &&
1156 MLX5_CAP_GEN(priv->mdev, cqe_compression)) {
1157 priv->params.cqe_zipping_en = true;
1158 priv->params_ethtool.cqe_zipping = 1;
1160 priv->params.cqe_zipping_en = false;
1161 priv->params_ethtool.cqe_zipping = 0;
1163 /* restart network interface, if any */
1165 mlx5e_open_locked(priv->ifp);
1168 case MLX5_PARAM_OFFSET(tx_completion_fact):
1169 /* network interface must be down */
1171 mlx5e_close_locked(priv->ifp);
1173 /* verify parameter */
1174 mlx5e_ethtool_sync_tx_completion_fact(priv);
1176 /* restart network interface, if any */
1178 mlx5e_open_locked(priv->ifp);
1181 case MLX5_PARAM_OFFSET(modify_tx_dma):
1182 /* check if network interface is opened */
1184 priv->params_ethtool.modify_tx_dma =
1185 priv->params_ethtool.modify_tx_dma ? 1 : 0;
1186 /* modify tx according to value */
1187 mlx5e_modify_tx_dma(priv, value != 0);
1189 /* if closed force enable tx */
1190 priv->params_ethtool.modify_tx_dma = 0;
1194 case MLX5_PARAM_OFFSET(modify_rx_dma):
1195 /* check if network interface is opened */
1197 priv->params_ethtool.modify_rx_dma =
1198 priv->params_ethtool.modify_rx_dma ? 1 : 0;
1199 /* modify rx according to value */
1200 mlx5e_modify_rx_dma(priv, value != 0);
1202 /* if closed force enable rx */
1203 priv->params_ethtool.modify_rx_dma = 0;
1207 case MLX5_PARAM_OFFSET(diag_pci_enable):
1208 priv->params_ethtool.diag_pci_enable =
1209 priv->params_ethtool.diag_pci_enable ? 1 : 0;
1211 error = -mlx5_core_set_diagnostics_full(priv->mdev,
1212 priv->params_ethtool.diag_pci_enable,
1213 priv->params_ethtool.diag_general_enable);
1216 case MLX5_PARAM_OFFSET(diag_general_enable):
1217 priv->params_ethtool.diag_general_enable =
1218 priv->params_ethtool.diag_general_enable ? 1 : 0;
1220 error = -mlx5_core_set_diagnostics_full(priv->mdev,
1221 priv->params_ethtool.diag_pci_enable,
1222 priv->params_ethtool.diag_general_enable);
1225 case MLX5_PARAM_OFFSET(mc_local_lb):
1226 /* check if mlx5ib is managing this feature */
1227 if (MLX5_CAP_GEN(priv->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) {
1232 priv->params_ethtool.mc_local_lb =
1233 priv->params_ethtool.mc_local_lb ? 1 : 0;
1235 if (MLX5_CAP_GEN(priv->mdev, disable_local_lb_mc)) {
1236 error = mlx5_nic_vport_modify_local_lb(priv->mdev,
1237 MLX5_LOCAL_MC_LB, priv->params_ethtool.mc_local_lb);
1243 case MLX5_PARAM_OFFSET(uc_local_lb):
1244 /* check if mlx5ib is managing this feature */
1245 if (MLX5_CAP_GEN(priv->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) {
1250 priv->params_ethtool.uc_local_lb =
1251 priv->params_ethtool.uc_local_lb ? 1 : 0;
1253 if (MLX5_CAP_GEN(priv->mdev, disable_local_lb_uc)) {
1254 error = mlx5_nic_vport_modify_local_lb(priv->mdev,
1255 MLX5_LOCAL_UC_LB, priv->params_ethtool.uc_local_lb);
1261 case MLX5_PARAM_OFFSET(irq_cpu_base):
1262 case MLX5_PARAM_OFFSET(irq_cpu_stride):
1264 /* network interface must toggled */
1265 mlx5e_close_locked(priv->ifp);
1266 mlx5e_open_locked(priv->ifp);
1278 static const char *mlx5e_params_desc[] = {
1279 MLX5E_PARAMS(MLX5E_STATS_DESC)
1282 static const char *mlx5e_port_stats_debug_desc[] = {
1283 MLX5E_PORT_STATS_DEBUG(MLX5E_STATS_DESC)
1287 mlx5e_ethtool_debug_channel_info(SYSCTL_HANDLER_ARGS)
1289 struct mlx5e_priv *priv;
1291 struct mlx5e_channel *c;
1292 struct mlx5e_sq *sq;
1293 struct mlx5e_rq *rq;
1298 error = sysctl_wire_old_buffer(req, 0);
1301 if (sbuf_new_for_sysctl(&sb, NULL, 1024, req) == NULL)
1303 sbuf_clear_flags(&sb, SBUF_INCLUDENUL);
1306 opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
1308 sbuf_printf(&sb, "pages irq %d\n",
1309 priv->mdev->priv.msix_arr[MLX5_EQ_VEC_PAGES].vector);
1310 sbuf_printf(&sb, "command irq %d\n",
1311 priv->mdev->priv.msix_arr[MLX5_EQ_VEC_CMD].vector);
1312 sbuf_printf(&sb, "async irq %d\n",
1313 priv->mdev->priv.msix_arr[MLX5_EQ_VEC_ASYNC].vector);
1315 for (i = 0; i != priv->params.num_channels; i++) {
1316 int eqn_not_used = -1;
1317 int irqn = MLX5_EQ_VEC_COMP_BASE;
1319 if (mlx5_vector2eqn(priv->mdev, i, &eqn_not_used, &irqn) != 0)
1322 c = opened ? &priv->channel[i] : NULL;
1323 rq = opened ? &c->rq : NULL;
1324 sbuf_printf(&sb, "channel %d rq %d cq %d irq %d\n", i,
1325 opened ? rq->rqn : -1,
1326 opened ? rq->cq.mcq.cqn : -1,
1327 priv->mdev->priv.msix_arr[irqn].vector);
1329 for (tc = 0; tc != priv->num_tc; tc++) {
1330 sq = opened ? &c->sq[tc] : NULL;
1331 sbuf_printf(&sb, "channel %d tc %d sq %d cq %d irq %d\n",
1333 opened ? sq->sqn : -1,
1334 opened ? sq->cq.mcq.cqn : -1,
1335 priv->mdev->priv.msix_arr[irqn].vector);
1339 error = sbuf_finish(&sb);
1345 mlx5e_ethtool_debug_stats(SYSCTL_HANDLER_ARGS)
1347 struct mlx5e_priv *priv = arg1;
1352 if (priv->gone != 0) {
1356 sys_debug = priv->sysctl_debug;
1357 error = sysctl_handle_int(oidp, &sys_debug, 0, req);
1358 if (error != 0 || !req->newptr)
1360 sys_debug = sys_debug ? 1 : 0;
1361 if (sys_debug == priv->sysctl_debug)
1364 if ((priv->sysctl_debug = sys_debug)) {
1365 mlx5e_create_stats(&priv->stats.port_stats_debug.ctx,
1366 SYSCTL_CHILDREN(priv->sysctl_ifnet), "debug_stats",
1367 mlx5e_port_stats_debug_desc, MLX5E_PORT_STATS_DEBUG_NUM,
1368 priv->stats.port_stats_debug.arg);
1369 SYSCTL_ADD_PROC(&priv->stats.port_stats_debug.ctx,
1370 SYSCTL_CHILDREN(priv->sysctl_ifnet), OID_AUTO,
1372 CTLFLAG_RD | CTLFLAG_MPSAFE | CTLTYPE_STRING, priv, 0,
1373 mlx5e_ethtool_debug_channel_info, "S", "");
1375 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
1383 mlx5e_create_diagnostics(struct mlx5e_priv *priv)
1385 struct mlx5_core_diagnostics_entry entry;
1386 struct sysctl_ctx_list *ctx;
1387 struct sysctl_oid *node;
1390 /* sysctl context we are using */
1391 ctx = &priv->sysctl_ctx;
1393 /* create root node */
1394 node = SYSCTL_ADD_NODE(ctx,
1395 SYSCTL_CHILDREN(priv->sysctl_ifnet), OID_AUTO,
1396 "diagnostics", CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Diagnostics");
1400 /* create PCI diagnostics */
1401 for (x = 0; x != MLX5_CORE_PCI_DIAGNOSTICS_NUM; x++) {
1402 entry = mlx5_core_pci_diagnostics_table[x];
1403 if (mlx5_core_supports_diagnostics(priv->mdev, entry.counter_id) == 0)
1405 SYSCTL_ADD_UQUAD(ctx, SYSCTL_CHILDREN(node), OID_AUTO,
1406 entry.desc, CTLFLAG_RD, priv->params_pci.array + x,
1407 "PCI diagnostics counter");
1410 /* create general diagnostics */
1411 for (x = 0; x != MLX5_CORE_GENERAL_DIAGNOSTICS_NUM; x++) {
1412 entry = mlx5_core_general_diagnostics_table[x];
1413 if (mlx5_core_supports_diagnostics(priv->mdev, entry.counter_id) == 0)
1415 SYSCTL_ADD_UQUAD(ctx, SYSCTL_CHILDREN(node), OID_AUTO,
1416 entry.desc, CTLFLAG_RD, priv->params_general.array + x,
1417 "General diagnostics counter");
1422 mlx5e_create_ethtool(struct mlx5e_priv *priv)
1424 struct sysctl_oid *fec_node;
1425 struct sysctl_oid *qos_node;
1426 struct sysctl_oid *node;
1427 const char *pnameunit;
1428 struct mlx5e_port_buffer port_buffer;
1432 /* set some defaults */
1433 priv->params_ethtool.irq_cpu_base = -1; /* disabled */
1434 priv->params_ethtool.irq_cpu_stride = 1;
1435 priv->params_ethtool.tx_queue_size_max = 1 << MLX5E_PARAMS_MAXIMUM_LOG_SQ_SIZE;
1436 priv->params_ethtool.rx_queue_size_max = 1 << MLX5E_PARAMS_MAXIMUM_LOG_RQ_SIZE;
1437 priv->params_ethtool.tx_queue_size = 1 << priv->params.log_sq_size;
1438 priv->params_ethtool.rx_queue_size = 1 << priv->params.log_rq_size;
1439 priv->params_ethtool.channels = priv->params.num_channels;
1440 priv->params_ethtool.channels_rsss = priv->params.channels_rsss;
1441 priv->params_ethtool.coalesce_pkts_max = MLX5E_FLD_MAX(cqc, cq_max_count);
1442 priv->params_ethtool.coalesce_usecs_max = MLX5E_FLD_MAX(cqc, cq_period);
1443 priv->params_ethtool.rx_coalesce_mode = priv->params.rx_cq_moderation_mode;
1444 priv->params_ethtool.rx_coalesce_usecs = priv->params.rx_cq_moderation_usec;
1445 priv->params_ethtool.rx_coalesce_pkts = priv->params.rx_cq_moderation_pkts;
1446 priv->params_ethtool.tx_coalesce_mode = priv->params.tx_cq_moderation_mode;
1447 priv->params_ethtool.tx_coalesce_usecs = priv->params.tx_cq_moderation_usec;
1448 priv->params_ethtool.tx_coalesce_pkts = priv->params.tx_cq_moderation_pkts;
1449 priv->params_ethtool.hw_lro = priv->params.hw_lro_en;
1450 priv->params_ethtool.cqe_zipping = priv->params.cqe_zipping_en;
1451 mlx5e_ethtool_sync_tx_completion_fact(priv);
1453 /* get default values for local loopback, if any */
1454 if (MLX5_CAP_GEN(priv->mdev, disable_local_lb_mc) ||
1455 MLX5_CAP_GEN(priv->mdev, disable_local_lb_uc)) {
1459 err = mlx5_nic_vport_query_local_lb(priv->mdev, MLX5_LOCAL_MC_LB, &val);
1461 priv->params_ethtool.mc_local_lb = val;
1463 err = mlx5_nic_vport_query_local_lb(priv->mdev, MLX5_LOCAL_UC_LB, &val);
1465 priv->params_ethtool.uc_local_lb = val;
1468 /* create root node */
1469 node = SYSCTL_ADD_NODE(&priv->sysctl_ctx,
1470 SYSCTL_CHILDREN(priv->sysctl_ifnet), OID_AUTO,
1471 "conf", CTLFLAG_RW | CTLFLAG_MPSAFE, NULL, "Configuration");
1474 for (x = 0; x != MLX5E_PARAMS_NUM; x++) {
1475 /* check for read-only parameter */
1476 if (strstr(mlx5e_params_desc[2 * x], "_max") != NULL ||
1477 strstr(mlx5e_params_desc[2 * x], "_mtu") != NULL) {
1478 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(node), OID_AUTO,
1479 mlx5e_params_desc[2 * x], CTLTYPE_U64 | CTLFLAG_RD |
1480 CTLFLAG_MPSAFE, priv, x, &mlx5e_ethtool_handler, "QU",
1481 mlx5e_params_desc[2 * x + 1]);
1482 } else if (strcmp(mlx5e_params_desc[2 * x], "hw_lro") == 0) {
1483 /* read-only, but tunable parameters */
1484 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(node), OID_AUTO,
1485 mlx5e_params_desc[2 * x], CTLTYPE_U64 | CTLFLAG_RDTUN |
1486 CTLFLAG_MPSAFE, priv, x, &mlx5e_ethtool_handler, "QU",
1487 mlx5e_params_desc[2 * x + 1]);
1490 * NOTE: In FreeBSD-11 and newer the
1491 * CTLFLAG_RWTUN flag will take care of
1492 * loading default sysctl value from the
1493 * kernel environment, if any:
1495 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(node), OID_AUTO,
1496 mlx5e_params_desc[2 * x], CTLTYPE_U64 | CTLFLAG_RWTUN |
1497 CTLFLAG_MPSAFE, priv, x, &mlx5e_ethtool_handler, "QU",
1498 mlx5e_params_desc[2 * x + 1]);
1502 /* create fec node */
1503 fec_node = SYSCTL_ADD_NODE(&priv->sysctl_ctx,
1504 SYSCTL_CHILDREN(node), OID_AUTO,
1505 "fec", CTLFLAG_RW | CTLFLAG_MPSAFE, NULL,
1506 "Forward Error Correction");
1507 if (fec_node == NULL)
1510 if (mlx5e_fec_update(priv) == 0) {
1511 SYSCTL_ADD_U32(&priv->sysctl_ctx, SYSCTL_CHILDREN(fec_node), OID_AUTO,
1512 "mode_active", CTLFLAG_RD | CTLFLAG_MPSAFE,
1513 &priv->params_ethtool.fec_mode_active, 0,
1514 "Current FEC mode bit, if any.");
1516 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(fec_node), OID_AUTO,
1517 "mask_10x_25x", CTLTYPE_U8 | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
1518 priv, 0, &mlx5e_fec_mask_10x_25x_handler, "CU",
1519 "Set FEC masks for 10G_40G, 25G_50G, 56G, 100G respectivly. "
1525 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(fec_node), OID_AUTO,
1526 "avail_10x_25x", CTLTYPE_U8 | CTLFLAG_RD | CTLFLAG_MPSAFE,
1527 priv, 0, &mlx5e_fec_avail_10x_25x_handler, "CU",
1528 "Get available FEC bits for 10G_40G, 25G_50G, 56G, 100G respectivly. "
1534 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(fec_node), OID_AUTO,
1535 "mask_50x", CTLTYPE_U16 | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
1536 priv, 0, &mlx5e_fec_mask_50x_handler, "SU",
1537 "Set FEC masks for 50G 1x, 100G 2x, 200G 4x, 400G 8x respectivly. "
1542 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(fec_node), OID_AUTO,
1543 "avail_50x", CTLTYPE_U16 | CTLFLAG_RD | CTLFLAG_MPSAFE,
1544 priv, 0, &mlx5e_fec_avail_50x_handler, "SU",
1545 "Get available FEC bits for 50G 1x, 100G 2x, 200G 4x, 400G 8x respectivly. "
1551 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(node), OID_AUTO,
1552 "debug_stats", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, priv,
1553 0, &mlx5e_ethtool_debug_stats, "I", "Extended debug statistics");
1555 pnameunit = device_get_nameunit(priv->mdev->pdev->dev.bsddev);
1557 SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(node),
1558 OID_AUTO, "device_name", CTLFLAG_RD,
1559 __DECONST(void *, pnameunit), 0,
1562 /* Diagnostics support */
1563 mlx5e_create_diagnostics(priv);
1565 /* create qos node */
1566 qos_node = SYSCTL_ADD_NODE(&priv->sysctl_ctx,
1567 SYSCTL_CHILDREN(node), OID_AUTO,
1568 "qos", CTLFLAG_RW | CTLFLAG_MPSAFE, NULL,
1569 "Quality Of Service configuration");
1570 if (qos_node == NULL)
1573 /* Priority rate limit support */
1574 if (mlx5e_getmaxrate(priv) == 0) {
1575 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(qos_node),
1576 OID_AUTO, "tc_max_rate", CTLTYPE_U64 | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
1577 priv, 0, mlx5e_tc_maxrate_handler, "QU",
1578 "Max rate for priority, specified in kilobits, where kilo=1000, "
1579 "max_rate must be divisible by 100000");
1582 /* Bandwidth limiting by ratio */
1583 if (mlx5e_get_max_alloc(priv) == 0) {
1584 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(qos_node),
1585 OID_AUTO, "tc_rate_share", CTLTYPE_U8 | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
1586 priv, 0, mlx5e_tc_rate_share_handler, "QU",
1587 "Specify bandwidth ratio from 1 to 100 "
1588 "for the available traffic classes");
1591 /* Priority to traffic class mapping */
1592 if (mlx5e_get_prio_tc(priv) == 0) {
1593 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(qos_node),
1594 OID_AUTO, "prio_0_7_tc", CTLTYPE_U8 | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
1595 priv, 0, mlx5e_prio_to_tc_handler, "CU",
1596 "Set traffic class 0 to 7 for priority 0 to 7 inclusivly");
1600 if (mlx5e_get_dscp(priv) == 0) {
1601 for (i = 0; i != MLX5_MAX_SUPPORTED_DSCP; i += 8) {
1603 snprintf(name, sizeof(name), "dscp_%d_%d_prio", i, i + 7);
1604 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(qos_node),
1605 OID_AUTO, name, CTLTYPE_U8 | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
1606 priv, i, mlx5e_dscp_prio_handler, "CU",
1607 "Set DSCP to priority mapping, 0..7");
1609 #define A "Set trust state, 1:PCP 2:DSCP"
1611 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(qos_node),
1612 OID_AUTO, "trust_state", CTLTYPE_U8 | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
1613 priv, 0, mlx5e_trust_state_handler, "CU",
1614 MLX5_CAP_QCAM_FEATURE(priv->mdev, qpts_trust_both) ?
1620 if (mlx5e_port_query_buffer(priv, &port_buffer) == 0) {
1621 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(qos_node),
1622 OID_AUTO, "buffers_size",
1623 CTLTYPE_U32 | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
1624 priv, 0, mlx5e_buf_size_handler, "IU",
1625 "Set buffers sizes");
1626 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(qos_node),
1627 OID_AUTO, "buffers_prio",
1628 CTLTYPE_U8 | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
1629 priv, 0, mlx5e_buf_prio_handler, "CU",
1630 "Set prio to buffers mapping");
1631 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(qos_node),
1632 OID_AUTO, "cable_length",
1633 CTLTYPE_UINT | CTLFLAG_RWTUN | CTLFLAG_MPSAFE,
1634 priv, 0, mlx5e_cable_length_handler, "IU",
1635 "Set cable length in meters for xoff threshold calculation");
1638 if (mlx5e_hw_temperature_update(priv) == 0) {
1639 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1640 OID_AUTO, "hw_temperature",
1641 CTLTYPE_S32 | CTLFLAG_RD | CTLFLAG_MPSAFE,
1642 priv, 0, mlx5e_hw_temperature_handler, "I",
1643 "HW temperature in millicelsius");