2 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <linux/list.h>
31 #include <dev/mlx5/flow_table.h>
47 MLX5E_ACTION_NONE = 0,
52 struct mlx5e_eth_addr_hash_node {
53 LIST_ENTRY(mlx5e_eth_addr_hash_node) hlist;
55 struct mlx5e_eth_addr_info ai;
59 mlx5e_hash_eth_addr(const u8 * addr)
65 mlx5e_add_eth_addr_to_hash(struct mlx5e_eth_addr_hash_head *hash,
68 struct mlx5e_eth_addr_hash_node *hn;
69 int ix = mlx5e_hash_eth_addr(addr);
71 LIST_FOREACH(hn, &hash[ix], hlist) {
72 if (bcmp(hn->ai.addr, addr, ETHER_ADDR_LEN) == 0) {
73 if (hn->action == MLX5E_ACTION_DEL)
74 hn->action = MLX5E_ACTION_NONE;
79 hn = malloc(sizeof(*hn), M_MLX5EN, M_NOWAIT | M_ZERO);
83 ether_addr_copy(hn->ai.addr, addr);
84 hn->action = MLX5E_ACTION_ADD;
86 LIST_INSERT_HEAD(&hash[ix], hn, hlist);
90 mlx5e_del_eth_addr_from_hash(struct mlx5e_eth_addr_hash_node *hn)
92 LIST_REMOVE(hn, hlist);
97 mlx5e_del_eth_addr_from_flow_table(struct mlx5e_priv *priv,
98 struct mlx5e_eth_addr_info *ai)
100 void *ft = priv->ft.main;
102 if (ai->tt_vec & (1 << MLX5E_TT_IPV6_TCP))
103 mlx5_del_flow_table_entry(ft, ai->ft_ix[MLX5E_TT_IPV6_TCP]);
105 if (ai->tt_vec & (1 << MLX5E_TT_IPV4_TCP))
106 mlx5_del_flow_table_entry(ft, ai->ft_ix[MLX5E_TT_IPV4_TCP]);
108 if (ai->tt_vec & (1 << MLX5E_TT_IPV6_UDP))
109 mlx5_del_flow_table_entry(ft, ai->ft_ix[MLX5E_TT_IPV6_UDP]);
111 if (ai->tt_vec & (1 << MLX5E_TT_IPV4_UDP))
112 mlx5_del_flow_table_entry(ft, ai->ft_ix[MLX5E_TT_IPV4_UDP]);
114 if (ai->tt_vec & (1 << MLX5E_TT_IPV6))
115 mlx5_del_flow_table_entry(ft, ai->ft_ix[MLX5E_TT_IPV6]);
117 if (ai->tt_vec & (1 << MLX5E_TT_IPV4))
118 mlx5_del_flow_table_entry(ft, ai->ft_ix[MLX5E_TT_IPV4]);
120 if (ai->tt_vec & (1 << MLX5E_TT_ANY))
121 mlx5_del_flow_table_entry(ft, ai->ft_ix[MLX5E_TT_ANY]);
125 mlx5e_get_eth_addr_type(const u8 * addr)
127 if (ETHER_IS_MULTICAST(addr) == 0)
130 if ((addr[0] == 0x01) &&
134 return (MLX5E_MC_IPV4);
136 if ((addr[0] == 0x33) &&
138 return (MLX5E_MC_IPV6);
140 return (MLX5E_MC_OTHER);
144 mlx5e_get_tt_vec(struct mlx5e_eth_addr_info *ai, int type)
150 case MLX5E_FULLMATCH:
151 eth_addr_type = mlx5e_get_eth_addr_type(ai->addr);
152 switch (eth_addr_type) {
155 (1 << MLX5E_TT_IPV4_TCP) |
156 (1 << MLX5E_TT_IPV6_TCP) |
157 (1 << MLX5E_TT_IPV4_UDP) |
158 (1 << MLX5E_TT_IPV6_UDP) |
159 (1 << MLX5E_TT_IPV4) |
160 (1 << MLX5E_TT_IPV6) |
161 (1 << MLX5E_TT_ANY) |
167 (1 << MLX5E_TT_IPV4_UDP) |
168 (1 << MLX5E_TT_IPV4) |
174 (1 << MLX5E_TT_IPV6_UDP) |
175 (1 << MLX5E_TT_IPV6) |
181 (1 << MLX5E_TT_ANY) |
189 (1 << MLX5E_TT_IPV4_UDP) |
190 (1 << MLX5E_TT_IPV6_UDP) |
191 (1 << MLX5E_TT_IPV4) |
192 (1 << MLX5E_TT_IPV6) |
193 (1 << MLX5E_TT_ANY) |
197 default: /* MLX5E_PROMISC */
199 (1 << MLX5E_TT_IPV4_TCP) |
200 (1 << MLX5E_TT_IPV6_TCP) |
201 (1 << MLX5E_TT_IPV4_UDP) |
202 (1 << MLX5E_TT_IPV6_UDP) |
203 (1 << MLX5E_TT_IPV4) |
204 (1 << MLX5E_TT_IPV6) |
205 (1 << MLX5E_TT_ANY) |
214 mlx5e_add_eth_addr_rule_sub(struct mlx5e_priv *priv,
215 struct mlx5e_eth_addr_info *ai, int type,
216 void *flow_context, void *match_criteria)
218 u8 match_criteria_enable = 0;
222 u8 *match_criteria_dmac;
223 void *ft = priv->ft.main;
224 u32 *tirn = priv->tirn;
228 match_value = MLX5_ADDR_OF(flow_context, flow_context, match_value);
229 dmac = MLX5_ADDR_OF(fte_match_param, match_value,
230 outer_headers.dmac_47_16);
231 match_criteria_dmac = MLX5_ADDR_OF(fte_match_param, match_criteria,
232 outer_headers.dmac_47_16);
233 dest = MLX5_ADDR_OF(flow_context, flow_context, destination);
235 MLX5_SET(flow_context, flow_context, action,
236 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST);
237 MLX5_SET(flow_context, flow_context, destination_list_size, 1);
238 MLX5_SET(dest_format_struct, dest, destination_type,
239 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR);
242 case MLX5E_FULLMATCH:
243 match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
244 memset(match_criteria_dmac, 0xff, ETH_ALEN);
245 ether_addr_copy(dmac, ai->addr);
249 match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
250 match_criteria_dmac[0] = 0x01;
260 tt_vec = mlx5e_get_tt_vec(ai, type);
262 if (tt_vec & (1 << MLX5E_TT_ANY)) {
263 MLX5_SET(dest_format_struct, dest, destination_id,
265 err = mlx5_add_flow_table_entry(ft, match_criteria_enable,
266 match_criteria, flow_context, &ai->ft_ix[MLX5E_TT_ANY]);
268 mlx5e_del_eth_addr_from_flow_table(priv, ai);
271 ai->tt_vec |= (1 << MLX5E_TT_ANY);
273 match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
274 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
275 outer_headers.ethertype);
277 if (tt_vec & (1 << MLX5E_TT_IPV4)) {
278 MLX5_SET(fte_match_param, match_value, outer_headers.ethertype,
280 MLX5_SET(dest_format_struct, dest, destination_id,
281 tirn[MLX5E_TT_IPV4]);
282 err = mlx5_add_flow_table_entry(ft, match_criteria_enable,
283 match_criteria, flow_context, &ai->ft_ix[MLX5E_TT_IPV4]);
285 mlx5e_del_eth_addr_from_flow_table(priv, ai);
288 ai->tt_vec |= (1 << MLX5E_TT_IPV4);
290 if (tt_vec & (1 << MLX5E_TT_IPV6)) {
291 MLX5_SET(fte_match_param, match_value, outer_headers.ethertype,
293 MLX5_SET(dest_format_struct, dest, destination_id,
294 tirn[MLX5E_TT_IPV6]);
295 err = mlx5_add_flow_table_entry(ft, match_criteria_enable,
296 match_criteria, flow_context, &ai->ft_ix[MLX5E_TT_IPV6]);
298 mlx5e_del_eth_addr_from_flow_table(priv, ai);
301 ai->tt_vec |= (1 << MLX5E_TT_IPV6);
303 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
304 outer_headers.ip_protocol);
305 MLX5_SET(fte_match_param, match_value, outer_headers.ip_protocol,
308 if (tt_vec & (1 << MLX5E_TT_IPV4_UDP)) {
309 MLX5_SET(fte_match_param, match_value, outer_headers.ethertype,
311 MLX5_SET(dest_format_struct, dest, destination_id,
312 tirn[MLX5E_TT_IPV4_UDP]);
313 err = mlx5_add_flow_table_entry(ft, match_criteria_enable,
314 match_criteria, flow_context, &ai->ft_ix[MLX5E_TT_IPV4_UDP]);
316 mlx5e_del_eth_addr_from_flow_table(priv, ai);
319 ai->tt_vec |= (1 << MLX5E_TT_IPV4_UDP);
321 if (tt_vec & (1 << MLX5E_TT_IPV6_UDP)) {
322 MLX5_SET(fte_match_param, match_value, outer_headers.ethertype,
324 MLX5_SET(dest_format_struct, dest, destination_id,
325 tirn[MLX5E_TT_IPV6_UDP]);
326 err = mlx5_add_flow_table_entry(ft, match_criteria_enable,
327 match_criteria, flow_context, &ai->ft_ix[MLX5E_TT_IPV6_UDP]);
329 mlx5e_del_eth_addr_from_flow_table(priv, ai);
332 ai->tt_vec |= (1 << MLX5E_TT_IPV6_UDP);
334 MLX5_SET(fte_match_param, match_value, outer_headers.ip_protocol,
337 if (tt_vec & (1 << MLX5E_TT_IPV4_TCP)) {
338 MLX5_SET(fte_match_param, match_value, outer_headers.ethertype,
340 MLX5_SET(dest_format_struct, dest, destination_id,
341 tirn[MLX5E_TT_IPV4_TCP]);
342 err = mlx5_add_flow_table_entry(ft, match_criteria_enable,
343 match_criteria, flow_context, &ai->ft_ix[MLX5E_TT_IPV4_TCP]);
345 mlx5e_del_eth_addr_from_flow_table(priv, ai);
348 ai->tt_vec |= (1 << MLX5E_TT_IPV4_TCP);
350 if (tt_vec & (1 << MLX5E_TT_IPV6_TCP)) {
351 MLX5_SET(fte_match_param, match_value, outer_headers.ethertype,
353 MLX5_SET(dest_format_struct, dest, destination_id,
354 tirn[MLX5E_TT_IPV6_TCP]);
355 err = mlx5_add_flow_table_entry(ft, match_criteria_enable,
356 match_criteria, flow_context, &ai->ft_ix[MLX5E_TT_IPV6_TCP]);
358 mlx5e_del_eth_addr_from_flow_table(priv, ai);
361 ai->tt_vec |= (1 << MLX5E_TT_IPV6_TCP);
367 mlx5e_add_eth_addr_rule(struct mlx5e_priv *priv,
368 struct mlx5e_eth_addr_info *ai, int type)
374 flow_context = mlx5_vzalloc(MLX5_ST_SZ_BYTES(flow_context) +
375 MLX5_ST_SZ_BYTES(dest_format_struct));
376 match_criteria = mlx5_vzalloc(MLX5_ST_SZ_BYTES(fte_match_param));
377 if (!flow_context || !match_criteria) {
378 if_printf(priv->ifp, "%s: alloc failed\n", __func__);
380 goto add_eth_addr_rule_out;
382 err = mlx5e_add_eth_addr_rule_sub(priv, ai, type, flow_context,
385 if_printf(priv->ifp, "%s: failed\n", __func__);
387 add_eth_addr_rule_out:
388 kvfree(match_criteria);
389 kvfree(flow_context);
393 static int mlx5e_vport_context_update_vlans(struct mlx5e_priv *priv)
395 struct ifnet *ifp = priv->ifp;
404 for_each_set_bit(vlan, priv->vlan.active_vlans, VLAN_N_VID)
407 max_list_size = 1 << MLX5_CAP_GEN(priv->mdev, log_max_vlan_list);
409 if (list_size > max_list_size) {
411 "ifnet vlans list size (%d) > (%d) max vport list size, some vlans will be dropped\n",
412 list_size, max_list_size);
413 list_size = max_list_size;
416 vlans = kcalloc(list_size, sizeof(*vlans), GFP_KERNEL);
421 for_each_set_bit(vlan, priv->vlan.active_vlans, VLAN_N_VID) {
427 err = mlx5_modify_nic_vport_vlans(priv->mdev, vlans, list_size);
429 if_printf(ifp, "Failed to modify vport vlans list err(%d)\n",
436 enum mlx5e_vlan_rule_type {
437 MLX5E_VLAN_RULE_TYPE_UNTAGGED,
438 MLX5E_VLAN_RULE_TYPE_ANY_VID,
439 MLX5E_VLAN_RULE_TYPE_MATCH_VID,
443 mlx5e_add_vlan_rule(struct mlx5e_priv *priv,
444 enum mlx5e_vlan_rule_type rule_type, u16 vid)
446 u8 match_criteria_enable = 0;
454 flow_context = mlx5_vzalloc(MLX5_ST_SZ_BYTES(flow_context) +
455 MLX5_ST_SZ_BYTES(dest_format_struct));
456 match_criteria = mlx5_vzalloc(MLX5_ST_SZ_BYTES(fte_match_param));
457 if (!flow_context || !match_criteria) {
458 if_printf(priv->ifp, "%s: alloc failed\n", __func__);
460 goto add_vlan_rule_out;
462 match_value = MLX5_ADDR_OF(flow_context, flow_context, match_value);
463 dest = MLX5_ADDR_OF(flow_context, flow_context, destination);
465 MLX5_SET(flow_context, flow_context, action,
466 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST);
467 MLX5_SET(flow_context, flow_context, destination_list_size, 1);
468 MLX5_SET(dest_format_struct, dest, destination_type,
469 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE);
470 MLX5_SET(dest_format_struct, dest, destination_id,
471 mlx5_get_flow_table_id(priv->ft.main));
473 match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
474 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
475 outer_headers.cvlan_tag);
478 case MLX5E_VLAN_RULE_TYPE_UNTAGGED:
479 ft_ix = &priv->vlan.untagged_rule_ft_ix;
481 case MLX5E_VLAN_RULE_TYPE_ANY_VID:
482 ft_ix = &priv->vlan.any_vlan_rule_ft_ix;
483 MLX5_SET(fte_match_param, match_value, outer_headers.cvlan_tag,
486 default: /* MLX5E_VLAN_RULE_TYPE_MATCH_VID */
487 ft_ix = &priv->vlan.active_vlans_ft_ix[vid];
488 MLX5_SET(fte_match_param, match_value, outer_headers.cvlan_tag,
490 MLX5_SET_TO_ONES(fte_match_param, match_criteria,
491 outer_headers.first_vid);
492 MLX5_SET(fte_match_param, match_value, outer_headers.first_vid,
494 mlx5e_vport_context_update_vlans(priv);
498 err = mlx5_add_flow_table_entry(priv->ft.vlan, match_criteria_enable,
499 match_criteria, flow_context, ft_ix);
501 if_printf(priv->ifp, "%s: failed\n", __func__);
504 kvfree(match_criteria);
505 kvfree(flow_context);
510 mlx5e_del_vlan_rule(struct mlx5e_priv *priv,
511 enum mlx5e_vlan_rule_type rule_type, u16 vid)
514 case MLX5E_VLAN_RULE_TYPE_UNTAGGED:
515 mlx5_del_flow_table_entry(priv->ft.vlan,
516 priv->vlan.untagged_rule_ft_ix);
518 case MLX5E_VLAN_RULE_TYPE_ANY_VID:
519 mlx5_del_flow_table_entry(priv->ft.vlan,
520 priv->vlan.any_vlan_rule_ft_ix);
522 case MLX5E_VLAN_RULE_TYPE_MATCH_VID:
523 mlx5_del_flow_table_entry(priv->ft.vlan,
524 priv->vlan.active_vlans_ft_ix[vid]);
525 mlx5e_vport_context_update_vlans(priv);
531 mlx5e_enable_vlan_filter(struct mlx5e_priv *priv)
533 if (priv->vlan.filter_disabled) {
534 priv->vlan.filter_disabled = false;
535 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
536 mlx5e_del_vlan_rule(priv, MLX5E_VLAN_RULE_TYPE_ANY_VID,
542 mlx5e_disable_vlan_filter(struct mlx5e_priv *priv)
544 if (!priv->vlan.filter_disabled) {
545 priv->vlan.filter_disabled = true;
546 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
547 mlx5e_add_vlan_rule(priv, MLX5E_VLAN_RULE_TYPE_ANY_VID,
553 mlx5e_vlan_rx_add_vid(void *arg, struct ifnet *ifp, u16 vid)
555 struct mlx5e_priv *priv = arg;
557 if (ifp != priv->ifp)
561 set_bit(vid, priv->vlan.active_vlans);
562 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
563 mlx5e_add_vlan_rule(priv, MLX5E_VLAN_RULE_TYPE_MATCH_VID, vid);
568 mlx5e_vlan_rx_kill_vid(void *arg, struct ifnet *ifp, u16 vid)
570 struct mlx5e_priv *priv = arg;
572 if (ifp != priv->ifp)
576 clear_bit(vid, priv->vlan.active_vlans);
577 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
578 mlx5e_del_vlan_rule(priv, MLX5E_VLAN_RULE_TYPE_MATCH_VID, vid);
583 mlx5e_add_all_vlan_rules(struct mlx5e_priv *priv)
588 for_each_set_bit(vid, priv->vlan.active_vlans, VLAN_N_VID) {
589 err = mlx5e_add_vlan_rule(priv, MLX5E_VLAN_RULE_TYPE_MATCH_VID,
595 err = mlx5e_add_vlan_rule(priv, MLX5E_VLAN_RULE_TYPE_UNTAGGED, 0);
599 if (priv->vlan.filter_disabled) {
600 err = mlx5e_add_vlan_rule(priv, MLX5E_VLAN_RULE_TYPE_ANY_VID,
609 mlx5e_del_all_vlan_rules(struct mlx5e_priv *priv)
613 if (priv->vlan.filter_disabled)
614 mlx5e_del_vlan_rule(priv, MLX5E_VLAN_RULE_TYPE_ANY_VID, 0);
616 mlx5e_del_vlan_rule(priv, MLX5E_VLAN_RULE_TYPE_UNTAGGED, 0);
618 for_each_set_bit(vid, priv->vlan.active_vlans, VLAN_N_VID)
619 mlx5e_del_vlan_rule(priv, MLX5E_VLAN_RULE_TYPE_MATCH_VID, vid);
622 #define mlx5e_for_each_hash_node(hn, tmp, hash, i) \
623 for (i = 0; i < MLX5E_ETH_ADDR_HASH_SIZE; i++) \
624 LIST_FOREACH_SAFE(hn, &(hash)[i], hlist, tmp)
627 mlx5e_execute_action(struct mlx5e_priv *priv,
628 struct mlx5e_eth_addr_hash_node *hn)
630 switch (hn->action) {
631 case MLX5E_ACTION_ADD:
632 mlx5e_add_eth_addr_rule(priv, &hn->ai, MLX5E_FULLMATCH);
633 hn->action = MLX5E_ACTION_NONE;
636 case MLX5E_ACTION_DEL:
637 mlx5e_del_eth_addr_from_flow_table(priv, &hn->ai);
638 mlx5e_del_eth_addr_from_hash(hn);
647 mlx5e_sync_ifp_addr(struct mlx5e_priv *priv)
649 struct ifnet *ifp = priv->ifp;
651 struct ifmultiaddr *ifma;
653 /* XXX adding this entry might not be needed */
654 mlx5e_add_eth_addr_to_hash(priv->eth_addr.if_uc,
655 LLADDR((struct sockaddr_dl *)(ifp->if_addr->ifa_addr)));
658 TAILQ_FOREACH(ifa, &ifp->if_addrhead, ifa_link) {
659 if (ifa->ifa_addr->sa_family != AF_LINK)
661 mlx5e_add_eth_addr_to_hash(priv->eth_addr.if_uc,
662 LLADDR((struct sockaddr_dl *)ifa->ifa_addr));
664 if_addr_runlock(ifp);
667 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
668 if (ifma->ifma_addr->sa_family != AF_LINK)
670 mlx5e_add_eth_addr_to_hash(priv->eth_addr.if_mc,
671 LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
673 if_maddr_runlock(ifp);
676 static void mlx5e_fill_addr_array(struct mlx5e_priv *priv, int list_type,
677 u8 addr_array[][ETH_ALEN], int size)
679 bool is_uc = (list_type == MLX5_NIC_VPORT_LIST_TYPE_UC);
680 struct ifnet *ifp = priv->ifp;
681 struct mlx5e_eth_addr_hash_node *hn;
682 struct mlx5e_eth_addr_hash_head *addr_list;
683 struct mlx5e_eth_addr_hash_node *tmp;
687 addr_list = is_uc ? priv->eth_addr.if_uc : priv->eth_addr.if_mc;
689 if (is_uc) /* Make sure our own address is pushed first */
690 ether_addr_copy(addr_array[i++], IF_LLADDR(ifp));
691 else if (priv->eth_addr.broadcast_enabled)
692 ether_addr_copy(addr_array[i++], ifp->if_broadcastaddr);
694 mlx5e_for_each_hash_node(hn, tmp, addr_list, hi) {
695 if (ether_addr_equal(IF_LLADDR(ifp), hn->ai.addr))
699 ether_addr_copy(addr_array[i++], hn->ai.addr);
703 static void mlx5e_vport_context_update_addr_list(struct mlx5e_priv *priv,
706 bool is_uc = (list_type == MLX5_NIC_VPORT_LIST_TYPE_UC);
707 struct mlx5e_eth_addr_hash_node *hn;
708 u8 (*addr_array)[ETH_ALEN] = NULL;
709 struct mlx5e_eth_addr_hash_head *addr_list;
710 struct mlx5e_eth_addr_hash_node *tmp;
716 size = is_uc ? 0 : (priv->eth_addr.broadcast_enabled ? 1 : 0);
718 1 << MLX5_CAP_GEN(priv->mdev, log_max_current_uc_list) :
719 1 << MLX5_CAP_GEN(priv->mdev, log_max_current_mc_list);
721 addr_list = is_uc ? priv->eth_addr.if_uc : priv->eth_addr.if_mc;
722 mlx5e_for_each_hash_node(hn, tmp, addr_list, hi)
725 if (size > max_size) {
727 "ifp %s list size (%d) > (%d) max vport list size, some addresses will be dropped\n",
728 is_uc ? "UC" : "MC", size, max_size);
733 addr_array = kcalloc(size, ETH_ALEN, GFP_KERNEL);
738 mlx5e_fill_addr_array(priv, list_type, addr_array, size);
741 err = mlx5_modify_nic_vport_mac_list(priv->mdev, list_type, addr_array, size);
745 "Failed to modify vport %s list err(%d)\n",
746 is_uc ? "UC" : "MC", err);
750 static void mlx5e_vport_context_update(struct mlx5e_priv *priv)
752 struct mlx5e_eth_addr_db *ea = &priv->eth_addr;
754 mlx5e_vport_context_update_addr_list(priv, MLX5_NIC_VPORT_LIST_TYPE_UC);
755 mlx5e_vport_context_update_addr_list(priv, MLX5_NIC_VPORT_LIST_TYPE_MC);
756 mlx5_modify_nic_vport_promisc(priv->mdev, 0,
757 ea->allmulti_enabled,
758 ea->promisc_enabled);
762 mlx5e_apply_ifp_addr(struct mlx5e_priv *priv)
764 struct mlx5e_eth_addr_hash_node *hn;
765 struct mlx5e_eth_addr_hash_node *tmp;
768 mlx5e_for_each_hash_node(hn, tmp, priv->eth_addr.if_uc, i)
769 mlx5e_execute_action(priv, hn);
771 mlx5e_for_each_hash_node(hn, tmp, priv->eth_addr.if_mc, i)
772 mlx5e_execute_action(priv, hn);
776 mlx5e_handle_ifp_addr(struct mlx5e_priv *priv)
778 struct mlx5e_eth_addr_hash_node *hn;
779 struct mlx5e_eth_addr_hash_node *tmp;
782 mlx5e_for_each_hash_node(hn, tmp, priv->eth_addr.if_uc, i)
783 hn->action = MLX5E_ACTION_DEL;
784 mlx5e_for_each_hash_node(hn, tmp, priv->eth_addr.if_mc, i)
785 hn->action = MLX5E_ACTION_DEL;
787 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
788 mlx5e_sync_ifp_addr(priv);
790 mlx5e_apply_ifp_addr(priv);
794 mlx5e_set_rx_mode_core(struct mlx5e_priv *priv)
796 struct mlx5e_eth_addr_db *ea = &priv->eth_addr;
797 struct ifnet *ndev = priv->ifp;
799 bool rx_mode_enable = test_bit(MLX5E_STATE_OPENED, &priv->state);
800 bool promisc_enabled = rx_mode_enable && (ndev->if_flags & IFF_PROMISC);
801 bool allmulti_enabled = rx_mode_enable && (ndev->if_flags & IFF_ALLMULTI);
802 bool broadcast_enabled = rx_mode_enable;
804 bool enable_promisc = !ea->promisc_enabled && promisc_enabled;
805 bool disable_promisc = ea->promisc_enabled && !promisc_enabled;
806 bool enable_allmulti = !ea->allmulti_enabled && allmulti_enabled;
807 bool disable_allmulti = ea->allmulti_enabled && !allmulti_enabled;
808 bool enable_broadcast = !ea->broadcast_enabled && broadcast_enabled;
809 bool disable_broadcast = ea->broadcast_enabled && !broadcast_enabled;
811 /* update broadcast address */
812 ether_addr_copy(priv->eth_addr.broadcast.addr,
813 priv->ifp->if_broadcastaddr);
816 mlx5e_add_eth_addr_rule(priv, &ea->promisc, MLX5E_PROMISC);
818 mlx5e_add_eth_addr_rule(priv, &ea->allmulti, MLX5E_ALLMULTI);
819 if (enable_broadcast)
820 mlx5e_add_eth_addr_rule(priv, &ea->broadcast, MLX5E_FULLMATCH);
822 mlx5e_handle_ifp_addr(priv);
824 if (disable_broadcast)
825 mlx5e_del_eth_addr_from_flow_table(priv, &ea->broadcast);
826 if (disable_allmulti)
827 mlx5e_del_eth_addr_from_flow_table(priv, &ea->allmulti);
829 mlx5e_del_eth_addr_from_flow_table(priv, &ea->promisc);
831 ea->promisc_enabled = promisc_enabled;
832 ea->allmulti_enabled = allmulti_enabled;
833 ea->broadcast_enabled = broadcast_enabled;
835 mlx5e_vport_context_update(priv);
839 mlx5e_set_rx_mode_work(struct work_struct *work)
841 struct mlx5e_priv *priv =
842 container_of(work, struct mlx5e_priv, set_rx_mode_work);
845 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
846 mlx5e_set_rx_mode_core(priv);
851 mlx5e_create_main_flow_table(struct mlx5e_priv *priv)
853 struct mlx5_flow_table_group *g;
856 g = malloc(9 * sizeof(*g), M_MLX5EN, M_WAITOK | M_ZERO);
859 g[0].match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
860 MLX5_SET_TO_ONES(fte_match_param, g[0].match_criteria,
861 outer_headers.ethertype);
862 MLX5_SET_TO_ONES(fte_match_param, g[0].match_criteria,
863 outer_headers.ip_protocol);
866 g[1].match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
867 MLX5_SET_TO_ONES(fte_match_param, g[1].match_criteria,
868 outer_headers.ethertype);
873 g[3].match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
874 dmac = MLX5_ADDR_OF(fte_match_param, g[3].match_criteria,
875 outer_headers.dmac_47_16);
876 memset(dmac, 0xff, ETH_ALEN);
877 MLX5_SET_TO_ONES(fte_match_param, g[3].match_criteria,
878 outer_headers.ethertype);
879 MLX5_SET_TO_ONES(fte_match_param, g[3].match_criteria,
880 outer_headers.ip_protocol);
883 g[4].match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
884 dmac = MLX5_ADDR_OF(fte_match_param, g[4].match_criteria,
885 outer_headers.dmac_47_16);
886 memset(dmac, 0xff, ETH_ALEN);
887 MLX5_SET_TO_ONES(fte_match_param, g[4].match_criteria,
888 outer_headers.ethertype);
891 g[5].match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
892 dmac = MLX5_ADDR_OF(fte_match_param, g[5].match_criteria,
893 outer_headers.dmac_47_16);
894 memset(dmac, 0xff, ETH_ALEN);
897 g[6].match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
898 dmac = MLX5_ADDR_OF(fte_match_param, g[6].match_criteria,
899 outer_headers.dmac_47_16);
901 MLX5_SET_TO_ONES(fte_match_param, g[6].match_criteria,
902 outer_headers.ethertype);
903 MLX5_SET_TO_ONES(fte_match_param, g[6].match_criteria,
904 outer_headers.ip_protocol);
907 g[7].match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
908 dmac = MLX5_ADDR_OF(fte_match_param, g[7].match_criteria,
909 outer_headers.dmac_47_16);
911 MLX5_SET_TO_ONES(fte_match_param, g[7].match_criteria,
912 outer_headers.ethertype);
915 g[8].match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
916 dmac = MLX5_ADDR_OF(fte_match_param, g[8].match_criteria,
917 outer_headers.dmac_47_16);
919 priv->ft.main = mlx5_create_flow_table(priv->mdev, 1,
920 MLX5_FLOW_TABLE_TYPE_NIC_RCV,
924 return (priv->ft.main ? 0 : -ENOMEM);
928 mlx5e_destroy_main_flow_table(struct mlx5e_priv *priv)
930 mlx5_destroy_flow_table(priv->ft.main);
931 priv->ft.main = NULL;
935 mlx5e_create_vlan_flow_table(struct mlx5e_priv *priv)
937 struct mlx5_flow_table_group *g;
939 g = malloc(2 * sizeof(*g), M_MLX5EN, M_WAITOK | M_ZERO);
942 g[0].match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
943 MLX5_SET_TO_ONES(fte_match_param, g[0].match_criteria,
944 outer_headers.cvlan_tag);
945 MLX5_SET_TO_ONES(fte_match_param, g[0].match_criteria,
946 outer_headers.first_vid);
948 /* untagged + any vlan id */
950 g[1].match_criteria_enable = MLX5_MATCH_OUTER_HEADERS;
951 MLX5_SET_TO_ONES(fte_match_param, g[1].match_criteria,
952 outer_headers.cvlan_tag);
954 priv->ft.vlan = mlx5_create_flow_table(priv->mdev, 0,
955 MLX5_FLOW_TABLE_TYPE_NIC_RCV,
959 return (priv->ft.vlan ? 0 : -ENOMEM);
963 mlx5e_destroy_vlan_flow_table(struct mlx5e_priv *priv)
965 mlx5_destroy_flow_table(priv->ft.vlan);
966 priv->ft.vlan = NULL;
970 mlx5e_open_flow_table(struct mlx5e_priv *priv)
974 err = mlx5e_create_main_flow_table(priv);
978 err = mlx5e_create_vlan_flow_table(priv);
980 goto err_destroy_main_flow_table;
984 err_destroy_main_flow_table:
985 mlx5e_destroy_main_flow_table(priv);
991 mlx5e_close_flow_table(struct mlx5e_priv *priv)
993 mlx5e_destroy_vlan_flow_table(priv);
994 mlx5e_destroy_main_flow_table(priv);