2 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <linux/list.h>
31 #include <dev/mlx5/fs.h>
32 #include <dev/mlx5/mpfs.h>
34 #define MLX5_SET_CFG(p, f, v) MLX5_SET(create_flow_group_in, p, f, v)
50 MLX5E_ACTION_NONE = 0,
55 struct mlx5e_eth_addr_hash_node {
56 LIST_ENTRY(mlx5e_eth_addr_hash_node) hlist;
59 struct mlx5e_eth_addr_info ai;
63 mlx5e_hash_eth_addr(const u8 * addr)
69 mlx5e_add_eth_addr_to_hash(struct mlx5e_eth_addr_hash_head *hash,
70 struct mlx5e_eth_addr_hash_node *hn_new)
72 struct mlx5e_eth_addr_hash_node *hn;
73 u32 ix = mlx5e_hash_eth_addr(hn_new->ai.addr);
75 LIST_FOREACH(hn, &hash[ix], hlist) {
76 if (bcmp(hn->ai.addr, hn_new->ai.addr, ETHER_ADDR_LEN) == 0) {
77 if (hn->action == MLX5E_ACTION_DEL)
78 hn->action = MLX5E_ACTION_NONE;
79 free(hn_new, M_MLX5EN);
83 LIST_INSERT_HEAD(&hash[ix], hn_new, hlist);
88 mlx5e_del_eth_addr_from_hash(struct mlx5e_eth_addr_hash_node *hn)
90 LIST_REMOVE(hn, hlist);
95 mlx5e_del_eth_addr_from_flow_table(struct mlx5e_priv *priv,
96 struct mlx5e_eth_addr_info *ai)
98 if (ai->tt_vec & (1 << MLX5E_TT_IPV6_IPSEC_ESP))
99 mlx5_del_flow_rule(ai->ft_rule[MLX5E_TT_IPV6_IPSEC_ESP]);
101 if (ai->tt_vec & (1 << MLX5E_TT_IPV4_IPSEC_ESP))
102 mlx5_del_flow_rule(ai->ft_rule[MLX5E_TT_IPV4_IPSEC_ESP]);
104 if (ai->tt_vec & (1 << MLX5E_TT_IPV6_IPSEC_AH))
105 mlx5_del_flow_rule(ai->ft_rule[MLX5E_TT_IPV6_IPSEC_AH]);
107 if (ai->tt_vec & (1 << MLX5E_TT_IPV4_IPSEC_AH))
108 mlx5_del_flow_rule(ai->ft_rule[MLX5E_TT_IPV4_IPSEC_AH]);
110 if (ai->tt_vec & (1 << MLX5E_TT_IPV6_TCP))
111 mlx5_del_flow_rule(ai->ft_rule[MLX5E_TT_IPV6_TCP]);
113 if (ai->tt_vec & (1 << MLX5E_TT_IPV4_TCP))
114 mlx5_del_flow_rule(ai->ft_rule[MLX5E_TT_IPV4_TCP]);
116 if (ai->tt_vec & (1 << MLX5E_TT_IPV6_UDP))
117 mlx5_del_flow_rule(ai->ft_rule[MLX5E_TT_IPV6_UDP]);
119 if (ai->tt_vec & (1 << MLX5E_TT_IPV4_UDP))
120 mlx5_del_flow_rule(ai->ft_rule[MLX5E_TT_IPV4_UDP]);
122 if (ai->tt_vec & (1 << MLX5E_TT_IPV6))
123 mlx5_del_flow_rule(ai->ft_rule[MLX5E_TT_IPV6]);
125 if (ai->tt_vec & (1 << MLX5E_TT_IPV4))
126 mlx5_del_flow_rule(ai->ft_rule[MLX5E_TT_IPV4]);
128 if (ai->tt_vec & (1 << MLX5E_TT_ANY))
129 mlx5_del_flow_rule(ai->ft_rule[MLX5E_TT_ANY]);
131 /* ensure the rules are not freed again */
136 mlx5e_get_eth_addr_type(const u8 * addr)
138 if (ETHER_IS_MULTICAST(addr) == 0)
141 if ((addr[0] == 0x01) &&
145 return (MLX5E_MC_IPV4);
147 if ((addr[0] == 0x33) &&
149 return (MLX5E_MC_IPV6);
151 return (MLX5E_MC_OTHER);
155 mlx5e_get_tt_vec(struct mlx5e_eth_addr_info *ai, int type)
161 case MLX5E_FULLMATCH:
162 eth_addr_type = mlx5e_get_eth_addr_type(ai->addr);
163 switch (eth_addr_type) {
166 (1 << MLX5E_TT_IPV4_TCP) |
167 (1 << MLX5E_TT_IPV6_TCP) |
168 (1 << MLX5E_TT_IPV4_UDP) |
169 (1 << MLX5E_TT_IPV6_UDP) |
170 (1 << MLX5E_TT_IPV4) |
171 (1 << MLX5E_TT_IPV6) |
172 (1 << MLX5E_TT_ANY) |
178 (1 << MLX5E_TT_IPV4_UDP) |
179 (1 << MLX5E_TT_IPV4) |
185 (1 << MLX5E_TT_IPV6_UDP) |
186 (1 << MLX5E_TT_IPV6) |
192 (1 << MLX5E_TT_ANY) |
200 (1 << MLX5E_TT_IPV4_UDP) |
201 (1 << MLX5E_TT_IPV6_UDP) |
202 (1 << MLX5E_TT_IPV4) |
203 (1 << MLX5E_TT_IPV6) |
204 (1 << MLX5E_TT_ANY) |
208 default: /* MLX5E_PROMISC */
210 (1 << MLX5E_TT_IPV4_TCP) |
211 (1 << MLX5E_TT_IPV6_TCP) |
212 (1 << MLX5E_TT_IPV4_UDP) |
213 (1 << MLX5E_TT_IPV6_UDP) |
214 (1 << MLX5E_TT_IPV4) |
215 (1 << MLX5E_TT_IPV6) |
216 (1 << MLX5E_TT_ANY) |
225 mlx5e_add_eth_addr_rule_sub(struct mlx5e_priv *priv,
226 struct mlx5e_eth_addr_info *ai, int type,
229 struct mlx5_flow_destination dest = {};
231 struct mlx5_flow_rule **rule_p;
232 struct mlx5_flow_table *ft = priv->fts.main.t;
233 u8 *mc_dmac = MLX5_ADDR_OF(fte_match_param, mc,
234 outer_headers.dmac_47_16);
235 u8 *mv_dmac = MLX5_ADDR_OF(fte_match_param, mv,
236 outer_headers.dmac_47_16);
237 u32 *tirn = priv->tirn;
241 dest.type = MLX5_FLOW_DESTINATION_TYPE_TIR;
244 case MLX5E_FULLMATCH:
245 mc_enable = MLX5_MATCH_OUTER_HEADERS;
246 memset(mc_dmac, 0xff, ETH_ALEN);
247 ether_addr_copy(mv_dmac, ai->addr);
251 mc_enable = MLX5_MATCH_OUTER_HEADERS;
262 tt_vec = mlx5e_get_tt_vec(ai, type);
264 if (tt_vec & BIT(MLX5E_TT_ANY)) {
265 rule_p = &ai->ft_rule[MLX5E_TT_ANY];
266 dest.tir_num = tirn[MLX5E_TT_ANY];
267 *rule_p = mlx5_add_flow_rule(ft, mc_enable, mc, mv,
268 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST,
269 MLX5_FS_ETH_FLOW_TAG, &dest);
270 if (IS_ERR_OR_NULL(*rule_p))
272 ai->tt_vec |= BIT(MLX5E_TT_ANY);
275 mc_enable = MLX5_MATCH_OUTER_HEADERS;
276 MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.ethertype);
278 if (tt_vec & BIT(MLX5E_TT_IPV4)) {
279 rule_p = &ai->ft_rule[MLX5E_TT_IPV4];
280 dest.tir_num = tirn[MLX5E_TT_IPV4];
281 MLX5_SET(fte_match_param, mv, outer_headers.ethertype,
283 *rule_p = mlx5_add_flow_rule(ft, mc_enable, mc, mv,
284 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST,
285 MLX5_FS_ETH_FLOW_TAG, &dest);
286 if (IS_ERR_OR_NULL(*rule_p))
288 ai->tt_vec |= BIT(MLX5E_TT_IPV4);
291 if (tt_vec & BIT(MLX5E_TT_IPV6)) {
292 rule_p = &ai->ft_rule[MLX5E_TT_IPV6];
293 dest.tir_num = tirn[MLX5E_TT_IPV6];
294 MLX5_SET(fte_match_param, mv, outer_headers.ethertype,
296 *rule_p = mlx5_add_flow_rule(ft, mc_enable, mc, mv,
297 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST,
298 MLX5_FS_ETH_FLOW_TAG, &dest);
299 if (IS_ERR_OR_NULL(*rule_p))
301 ai->tt_vec |= BIT(MLX5E_TT_IPV6);
304 MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.ip_protocol);
305 MLX5_SET(fte_match_param, mv, outer_headers.ip_protocol, IPPROTO_UDP);
307 if (tt_vec & BIT(MLX5E_TT_IPV4_UDP)) {
308 rule_p = &ai->ft_rule[MLX5E_TT_IPV4_UDP];
309 dest.tir_num = tirn[MLX5E_TT_IPV4_UDP];
310 MLX5_SET(fte_match_param, mv, outer_headers.ethertype,
312 *rule_p = mlx5_add_flow_rule(ft, mc_enable, mc, mv,
313 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST,
314 MLX5_FS_ETH_FLOW_TAG, &dest);
315 if (IS_ERR_OR_NULL(*rule_p))
317 ai->tt_vec |= BIT(MLX5E_TT_IPV4_UDP);
320 if (tt_vec & BIT(MLX5E_TT_IPV6_UDP)) {
321 rule_p = &ai->ft_rule[MLX5E_TT_IPV6_UDP];
322 dest.tir_num = tirn[MLX5E_TT_IPV6_UDP];
323 MLX5_SET(fte_match_param, mv, outer_headers.ethertype,
325 *rule_p = mlx5_add_flow_rule(ft, mc_enable, mc, mv,
326 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST,
327 MLX5_FS_ETH_FLOW_TAG, &dest);
328 if (IS_ERR_OR_NULL(*rule_p))
330 ai->tt_vec |= BIT(MLX5E_TT_IPV6_UDP);
333 MLX5_SET(fte_match_param, mv, outer_headers.ip_protocol, IPPROTO_TCP);
335 if (tt_vec & BIT(MLX5E_TT_IPV4_TCP)) {
336 rule_p = &ai->ft_rule[MLX5E_TT_IPV4_TCP];
337 dest.tir_num = tirn[MLX5E_TT_IPV4_TCP];
338 MLX5_SET(fte_match_param, mv, outer_headers.ethertype,
340 *rule_p = mlx5_add_flow_rule(ft, mc_enable, mc, mv,
341 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST,
342 MLX5_FS_ETH_FLOW_TAG, &dest);
343 if (IS_ERR_OR_NULL(*rule_p))
345 ai->tt_vec |= BIT(MLX5E_TT_IPV4_TCP);
348 if (tt_vec & BIT(MLX5E_TT_IPV6_TCP)) {
349 rule_p = &ai->ft_rule[MLX5E_TT_IPV6_TCP];
350 dest.tir_num = tirn[MLX5E_TT_IPV6_TCP];
351 MLX5_SET(fte_match_param, mv, outer_headers.ethertype,
353 *rule_p = mlx5_add_flow_rule(ft, mc_enable, mc, mv,
354 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST,
355 MLX5_FS_ETH_FLOW_TAG, &dest);
356 if (IS_ERR_OR_NULL(*rule_p))
359 ai->tt_vec |= BIT(MLX5E_TT_IPV6_TCP);
362 MLX5_SET(fte_match_param, mv, outer_headers.ip_protocol, IPPROTO_AH);
364 if (tt_vec & BIT(MLX5E_TT_IPV4_IPSEC_AH)) {
365 rule_p = &ai->ft_rule[MLX5E_TT_IPV4_IPSEC_AH];
366 dest.tir_num = tirn[MLX5E_TT_IPV4_IPSEC_AH];
367 MLX5_SET(fte_match_param, mv, outer_headers.ethertype,
369 *rule_p = mlx5_add_flow_rule(ft, mc_enable, mc, mv,
370 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST,
371 MLX5_FS_ETH_FLOW_TAG, &dest);
372 if (IS_ERR_OR_NULL(*rule_p))
374 ai->tt_vec |= BIT(MLX5E_TT_IPV4_IPSEC_AH);
377 if (tt_vec & BIT(MLX5E_TT_IPV6_IPSEC_AH)) {
378 rule_p = &ai->ft_rule[MLX5E_TT_IPV6_IPSEC_AH];
379 dest.tir_num = tirn[MLX5E_TT_IPV6_IPSEC_AH];
380 MLX5_SET(fte_match_param, mv, outer_headers.ethertype,
382 *rule_p = mlx5_add_flow_rule(ft, mc_enable, mc, mv,
383 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST,
384 MLX5_FS_ETH_FLOW_TAG, &dest);
385 if (IS_ERR_OR_NULL(*rule_p))
387 ai->tt_vec |= BIT(MLX5E_TT_IPV6_IPSEC_AH);
390 MLX5_SET(fte_match_param, mv, outer_headers.ip_protocol, IPPROTO_ESP);
392 if (tt_vec & BIT(MLX5E_TT_IPV4_IPSEC_ESP)) {
393 rule_p = &ai->ft_rule[MLX5E_TT_IPV4_IPSEC_ESP];
394 dest.tir_num = tirn[MLX5E_TT_IPV4_IPSEC_ESP];
395 MLX5_SET(fte_match_param, mv, outer_headers.ethertype,
397 *rule_p = mlx5_add_flow_rule(ft, mc_enable, mc, mv,
398 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST,
399 MLX5_FS_ETH_FLOW_TAG, &dest);
400 if (IS_ERR_OR_NULL(*rule_p))
402 ai->tt_vec |= BIT(MLX5E_TT_IPV4_IPSEC_ESP);
405 if (tt_vec & BIT(MLX5E_TT_IPV6_IPSEC_ESP)) {
406 rule_p = &ai->ft_rule[MLX5E_TT_IPV6_IPSEC_ESP];
407 dest.tir_num = tirn[MLX5E_TT_IPV6_IPSEC_ESP];
408 MLX5_SET(fte_match_param, mv, outer_headers.ethertype,
410 *rule_p = mlx5_add_flow_rule(ft, mc_enable, mc, mv,
411 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST,
412 MLX5_FS_ETH_FLOW_TAG, &dest);
413 if (IS_ERR_OR_NULL(*rule_p))
415 ai->tt_vec |= BIT(MLX5E_TT_IPV6_IPSEC_ESP);
421 err = PTR_ERR(*rule_p);
423 mlx5e_del_eth_addr_from_flow_table(priv, ai);
429 mlx5e_add_eth_addr_rule(struct mlx5e_priv *priv,
430 struct mlx5e_eth_addr_info *ai, int type)
436 match_value = mlx5_vzalloc(MLX5_ST_SZ_BYTES(fte_match_param));
437 match_criteria = mlx5_vzalloc(MLX5_ST_SZ_BYTES(fte_match_param));
438 if (!match_value || !match_criteria) {
439 mlx5_en_err(priv->ifp, "alloc failed\n");
441 goto add_eth_addr_rule_out;
443 err = mlx5e_add_eth_addr_rule_sub(priv, ai, type, match_criteria,
446 add_eth_addr_rule_out:
447 kvfree(match_criteria);
453 static int mlx5e_vport_context_update_vlans(struct mlx5e_priv *priv)
455 struct ifnet *ifp = priv->ifp;
464 for_each_set_bit(vlan, priv->vlan.active_vlans, VLAN_N_VID)
467 max_list_size = 1 << MLX5_CAP_GEN(priv->mdev, log_max_vlan_list);
469 if (list_size > max_list_size) {
471 "ifnet vlans list size (%d) > (%d) max vport list size, some vlans will be dropped\n",
472 list_size, max_list_size);
473 list_size = max_list_size;
476 vlans = kcalloc(list_size, sizeof(*vlans), GFP_KERNEL);
481 for_each_set_bit(vlan, priv->vlan.active_vlans, VLAN_N_VID) {
487 err = mlx5_modify_nic_vport_vlans(priv->mdev, vlans, list_size);
489 mlx5_en_err(ifp, "Failed to modify vport vlans list err(%d)\n",
496 enum mlx5e_vlan_rule_type {
497 MLX5E_VLAN_RULE_TYPE_UNTAGGED,
498 MLX5E_VLAN_RULE_TYPE_ANY_CTAG_VID,
499 MLX5E_VLAN_RULE_TYPE_ANY_STAG_VID,
500 MLX5E_VLAN_RULE_TYPE_MATCH_VID,
504 mlx5e_add_vlan_rule_sub(struct mlx5e_priv *priv,
505 enum mlx5e_vlan_rule_type rule_type, u16 vid,
508 struct mlx5_flow_table *ft = priv->fts.vlan.t;
509 struct mlx5_flow_destination dest = {};
511 struct mlx5_flow_rule **rule_p;
514 dest.type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
515 dest.ft = priv->fts.main.t;
517 mc_enable = MLX5_MATCH_OUTER_HEADERS;
520 case MLX5E_VLAN_RULE_TYPE_UNTAGGED:
521 rule_p = &priv->vlan.untagged_ft_rule;
522 MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.cvlan_tag);
524 case MLX5E_VLAN_RULE_TYPE_ANY_CTAG_VID:
525 rule_p = &priv->vlan.any_cvlan_ft_rule;
526 MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.cvlan_tag);
527 MLX5_SET(fte_match_param, mv, outer_headers.cvlan_tag, 1);
529 case MLX5E_VLAN_RULE_TYPE_ANY_STAG_VID:
530 rule_p = &priv->vlan.any_svlan_ft_rule;
531 MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.svlan_tag);
532 MLX5_SET(fte_match_param, mv, outer_headers.svlan_tag, 1);
534 default: /* MLX5E_VLAN_RULE_TYPE_MATCH_VID */
535 rule_p = &priv->vlan.active_vlans_ft_rule[vid];
536 MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.cvlan_tag);
537 MLX5_SET(fte_match_param, mv, outer_headers.cvlan_tag, 1);
538 MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.first_vid);
539 MLX5_SET(fte_match_param, mv, outer_headers.first_vid, vid);
540 mlx5e_vport_context_update_vlans(priv);
544 *rule_p = mlx5_add_flow_rule(ft, mc_enable, mc, mv,
545 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST,
546 MLX5_FS_ETH_FLOW_TAG,
549 if (IS_ERR(*rule_p)) {
550 err = PTR_ERR(*rule_p);
552 mlx5_en_err(priv->ifp, "add rule failed\n");
559 mlx5e_add_vlan_rule(struct mlx5e_priv *priv,
560 enum mlx5e_vlan_rule_type rule_type, u16 vid)
566 match_value = mlx5_vzalloc(MLX5_ST_SZ_BYTES(fte_match_param));
567 match_criteria = mlx5_vzalloc(MLX5_ST_SZ_BYTES(fte_match_param));
568 if (!match_value || !match_criteria) {
569 mlx5_en_err(priv->ifp, "alloc failed\n");
571 goto add_vlan_rule_out;
574 err = mlx5e_add_vlan_rule_sub(priv, rule_type, vid, match_criteria,
578 kvfree(match_criteria);
585 mlx5e_del_vlan_rule(struct mlx5e_priv *priv,
586 enum mlx5e_vlan_rule_type rule_type, u16 vid)
589 case MLX5E_VLAN_RULE_TYPE_UNTAGGED:
590 if (priv->vlan.untagged_ft_rule) {
591 mlx5_del_flow_rule(priv->vlan.untagged_ft_rule);
592 priv->vlan.untagged_ft_rule = NULL;
595 case MLX5E_VLAN_RULE_TYPE_ANY_CTAG_VID:
596 if (priv->vlan.any_cvlan_ft_rule) {
597 mlx5_del_flow_rule(priv->vlan.any_cvlan_ft_rule);
598 priv->vlan.any_cvlan_ft_rule = NULL;
601 case MLX5E_VLAN_RULE_TYPE_ANY_STAG_VID:
602 if (priv->vlan.any_svlan_ft_rule) {
603 mlx5_del_flow_rule(priv->vlan.any_svlan_ft_rule);
604 priv->vlan.any_svlan_ft_rule = NULL;
607 case MLX5E_VLAN_RULE_TYPE_MATCH_VID:
608 if (priv->vlan.active_vlans_ft_rule[vid]) {
609 mlx5_del_flow_rule(priv->vlan.active_vlans_ft_rule[vid]);
610 priv->vlan.active_vlans_ft_rule[vid] = NULL;
612 mlx5e_vport_context_update_vlans(priv);
620 mlx5e_del_any_vid_rules(struct mlx5e_priv *priv)
622 mlx5e_del_vlan_rule(priv, MLX5E_VLAN_RULE_TYPE_ANY_CTAG_VID, 0);
623 mlx5e_del_vlan_rule(priv, MLX5E_VLAN_RULE_TYPE_ANY_STAG_VID, 0);
627 mlx5e_add_any_vid_rules(struct mlx5e_priv *priv)
631 err = mlx5e_add_vlan_rule(priv, MLX5E_VLAN_RULE_TYPE_ANY_CTAG_VID, 0);
635 err = mlx5e_add_vlan_rule(priv, MLX5E_VLAN_RULE_TYPE_ANY_STAG_VID, 0);
637 mlx5e_del_vlan_rule(priv, MLX5E_VLAN_RULE_TYPE_ANY_CTAG_VID, 0);
643 mlx5e_enable_vlan_filter(struct mlx5e_priv *priv)
645 if (priv->vlan.filter_disabled) {
646 priv->vlan.filter_disabled = false;
647 if (priv->ifp->if_flags & IFF_PROMISC)
649 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
650 mlx5e_del_any_vid_rules(priv);
655 mlx5e_disable_vlan_filter(struct mlx5e_priv *priv)
657 if (!priv->vlan.filter_disabled) {
658 priv->vlan.filter_disabled = true;
659 if (priv->ifp->if_flags & IFF_PROMISC)
661 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
662 mlx5e_add_any_vid_rules(priv);
667 mlx5e_vlan_rx_add_vid(void *arg, struct ifnet *ifp, u16 vid)
669 struct mlx5e_priv *priv = arg;
671 if (ifp != priv->ifp)
675 if (!test_and_set_bit(vid, priv->vlan.active_vlans) &&
676 test_bit(MLX5E_STATE_OPENED, &priv->state))
677 mlx5e_add_vlan_rule(priv, MLX5E_VLAN_RULE_TYPE_MATCH_VID, vid);
682 mlx5e_vlan_rx_kill_vid(void *arg, struct ifnet *ifp, u16 vid)
684 struct mlx5e_priv *priv = arg;
686 if (ifp != priv->ifp)
690 clear_bit(vid, priv->vlan.active_vlans);
691 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
692 mlx5e_del_vlan_rule(priv, MLX5E_VLAN_RULE_TYPE_MATCH_VID, vid);
697 mlx5e_add_all_vlan_rules(struct mlx5e_priv *priv)
702 set_bit(0, priv->vlan.active_vlans);
703 for_each_set_bit(i, priv->vlan.active_vlans, VLAN_N_VID) {
704 err = mlx5e_add_vlan_rule(priv, MLX5E_VLAN_RULE_TYPE_MATCH_VID,
710 err = mlx5e_add_vlan_rule(priv, MLX5E_VLAN_RULE_TYPE_UNTAGGED, 0);
714 if (priv->vlan.filter_disabled) {
715 err = mlx5e_add_any_vid_rules(priv);
721 mlx5e_del_all_vlan_rules(priv);
726 mlx5e_del_all_vlan_rules(struct mlx5e_priv *priv)
730 if (priv->vlan.filter_disabled)
731 mlx5e_del_any_vid_rules(priv);
733 mlx5e_del_vlan_rule(priv, MLX5E_VLAN_RULE_TYPE_UNTAGGED, 0);
735 for_each_set_bit(i, priv->vlan.active_vlans, VLAN_N_VID)
736 mlx5e_del_vlan_rule(priv, MLX5E_VLAN_RULE_TYPE_MATCH_VID, i);
737 clear_bit(0, priv->vlan.active_vlans);
740 #define mlx5e_for_each_hash_node(hn, tmp, hash, i) \
741 for (i = 0; i < MLX5E_ETH_ADDR_HASH_SIZE; i++) \
742 LIST_FOREACH_SAFE(hn, &(hash)[i], hlist, tmp)
745 mlx5e_execute_action(struct mlx5e_priv *priv,
746 struct mlx5e_eth_addr_hash_node *hn)
748 switch (hn->action) {
749 case MLX5E_ACTION_ADD:
750 mlx5e_add_eth_addr_rule(priv, &hn->ai, MLX5E_FULLMATCH);
751 hn->action = MLX5E_ACTION_NONE;
754 case MLX5E_ACTION_DEL:
755 mlx5e_del_eth_addr_from_flow_table(priv, &hn->ai);
756 if (hn->mpfs_index != -1U)
757 mlx5_mpfs_del_mac(priv->mdev, hn->mpfs_index);
758 mlx5e_del_eth_addr_from_hash(hn);
766 static struct mlx5e_eth_addr_hash_node *
767 mlx5e_move_hn(struct mlx5e_eth_addr_hash_head *fh, struct mlx5e_eth_addr_hash_head *uh)
769 struct mlx5e_eth_addr_hash_node *hn;
773 LIST_REMOVE(hn, hlist);
774 LIST_INSERT_HEAD(uh, hn, hlist);
779 static struct mlx5e_eth_addr_hash_node *
780 mlx5e_remove_hn(struct mlx5e_eth_addr_hash_head *fh)
782 struct mlx5e_eth_addr_hash_node *hn;
786 LIST_REMOVE(hn, hlist);
790 struct mlx5e_copy_addr_ctx {
791 struct mlx5e_eth_addr_hash_head *free;
792 struct mlx5e_eth_addr_hash_head *fill;
797 mlx5e_copy_addr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
799 struct mlx5e_copy_addr_ctx *ctx = arg;
800 struct mlx5e_eth_addr_hash_node *hn;
802 hn = mlx5e_move_hn(ctx->free, ctx->fill);
804 ctx->success = false;
807 ether_addr_copy(hn->ai.addr, LLADDR(sdl));
813 mlx5e_sync_ifp_addr(struct mlx5e_priv *priv)
815 struct mlx5e_copy_addr_ctx ctx;
816 struct mlx5e_eth_addr_hash_head head_free;
817 struct mlx5e_eth_addr_hash_head head_uc;
818 struct mlx5e_eth_addr_hash_head head_mc;
819 struct mlx5e_eth_addr_hash_node *hn;
820 struct ifnet *ifp = priv->ifp;
824 PRIV_ASSERT_LOCKED(priv);
827 LIST_INIT(&head_free);
830 num = 1 + if_lladdr_count(ifp) + if_llmaddr_count(ifp);
832 /* allocate place holders */
833 for (x = 0; x != num; x++) {
834 hn = malloc(sizeof(*hn), M_MLX5EN, M_WAITOK | M_ZERO);
835 hn->action = MLX5E_ACTION_ADD;
836 hn->mpfs_index = -1U;
837 LIST_INSERT_HEAD(&head_free, hn, hlist);
840 hn = mlx5e_move_hn(&head_free, &head_uc);
843 ether_addr_copy(hn->ai.addr,
844 LLADDR((struct sockaddr_dl *)(ifp->if_addr->ifa_addr)));
846 ctx.free = &head_free;
849 if_foreach_lladdr(ifp, mlx5e_copy_addr, &ctx);
850 if (ctx.success == false)
854 if_foreach_llmaddr(ifp, mlx5e_copy_addr, &ctx);
855 if (ctx.success == false)
858 /* insert L2 unicast addresses into hash list */
860 while ((hn = mlx5e_remove_hn(&head_uc)) != NULL) {
861 if (mlx5e_add_eth_addr_to_hash(priv->eth_addr.if_uc, hn) == 0)
863 if (hn->mpfs_index == -1U)
864 mlx5_mpfs_add_mac(priv->mdev, &hn->mpfs_index, hn->ai.addr);
867 /* insert L2 multicast addresses into hash list */
869 while ((hn = mlx5e_remove_hn(&head_mc)) != NULL) {
870 if (mlx5e_add_eth_addr_to_hash(priv->eth_addr.if_mc, hn) == 0)
875 while ((hn = mlx5e_remove_hn(&head_uc)) != NULL)
877 while ((hn = mlx5e_remove_hn(&head_mc)) != NULL)
879 while ((hn = mlx5e_remove_hn(&head_free)) != NULL)
882 if (ctx.success == false)
886 static void mlx5e_fill_addr_array(struct mlx5e_priv *priv, int list_type,
887 u8 addr_array[][ETH_ALEN], int size)
889 bool is_uc = (list_type == MLX5_NIC_VPORT_LIST_TYPE_UC);
890 struct ifnet *ifp = priv->ifp;
891 struct mlx5e_eth_addr_hash_node *hn;
892 struct mlx5e_eth_addr_hash_head *addr_list;
893 struct mlx5e_eth_addr_hash_node *tmp;
897 addr_list = is_uc ? priv->eth_addr.if_uc : priv->eth_addr.if_mc;
899 if (is_uc) /* Make sure our own address is pushed first */
900 ether_addr_copy(addr_array[i++], IF_LLADDR(ifp));
901 else if (priv->eth_addr.broadcast_enabled)
902 ether_addr_copy(addr_array[i++], ifp->if_broadcastaddr);
904 mlx5e_for_each_hash_node(hn, tmp, addr_list, hi) {
905 if (ether_addr_equal(IF_LLADDR(ifp), hn->ai.addr))
909 ether_addr_copy(addr_array[i++], hn->ai.addr);
913 static void mlx5e_vport_context_update_addr_list(struct mlx5e_priv *priv,
916 bool is_uc = (list_type == MLX5_NIC_VPORT_LIST_TYPE_UC);
917 struct mlx5e_eth_addr_hash_node *hn;
918 u8 (*addr_array)[ETH_ALEN] = NULL;
919 struct mlx5e_eth_addr_hash_head *addr_list;
920 struct mlx5e_eth_addr_hash_node *tmp;
926 size = is_uc ? 0 : (priv->eth_addr.broadcast_enabled ? 1 : 0);
928 1 << MLX5_CAP_GEN(priv->mdev, log_max_current_uc_list) :
929 1 << MLX5_CAP_GEN(priv->mdev, log_max_current_mc_list);
931 addr_list = is_uc ? priv->eth_addr.if_uc : priv->eth_addr.if_mc;
932 mlx5e_for_each_hash_node(hn, tmp, addr_list, hi)
935 if (size > max_size) {
936 mlx5_en_err(priv->ifp,
937 "ifp %s list size (%d) > (%d) max vport list size, some addresses will be dropped\n",
938 is_uc ? "UC" : "MC", size, max_size);
943 addr_array = kcalloc(size, ETH_ALEN, GFP_KERNEL);
948 mlx5e_fill_addr_array(priv, list_type, addr_array, size);
951 err = mlx5_modify_nic_vport_mac_list(priv->mdev, list_type, addr_array, size);
954 mlx5_en_err(priv->ifp,
955 "Failed to modify vport %s list err(%d)\n",
956 is_uc ? "UC" : "MC", err);
960 static void mlx5e_vport_context_update(struct mlx5e_priv *priv)
962 struct mlx5e_eth_addr_db *ea = &priv->eth_addr;
964 mlx5e_vport_context_update_addr_list(priv, MLX5_NIC_VPORT_LIST_TYPE_UC);
965 mlx5e_vport_context_update_addr_list(priv, MLX5_NIC_VPORT_LIST_TYPE_MC);
966 mlx5_modify_nic_vport_promisc(priv->mdev, 0,
967 ea->allmulti_enabled,
968 ea->promisc_enabled);
972 mlx5e_apply_ifp_addr(struct mlx5e_priv *priv)
974 struct mlx5e_eth_addr_hash_node *hn;
975 struct mlx5e_eth_addr_hash_node *tmp;
978 mlx5e_for_each_hash_node(hn, tmp, priv->eth_addr.if_uc, i)
979 mlx5e_execute_action(priv, hn);
981 mlx5e_for_each_hash_node(hn, tmp, priv->eth_addr.if_mc, i)
982 mlx5e_execute_action(priv, hn);
986 mlx5e_handle_ifp_addr(struct mlx5e_priv *priv)
988 struct mlx5e_eth_addr_hash_node *hn;
989 struct mlx5e_eth_addr_hash_node *tmp;
992 mlx5e_for_each_hash_node(hn, tmp, priv->eth_addr.if_uc, i)
993 hn->action = MLX5E_ACTION_DEL;
994 mlx5e_for_each_hash_node(hn, tmp, priv->eth_addr.if_mc, i)
995 hn->action = MLX5E_ACTION_DEL;
997 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
998 mlx5e_sync_ifp_addr(priv);
1000 mlx5e_apply_ifp_addr(priv);
1004 mlx5e_set_rx_mode_core(struct mlx5e_priv *priv)
1006 struct mlx5e_eth_addr_db *ea = &priv->eth_addr;
1007 struct ifnet *ndev = priv->ifp;
1009 bool rx_mode_enable = test_bit(MLX5E_STATE_OPENED, &priv->state);
1010 bool promisc_enabled = rx_mode_enable && (ndev->if_flags & IFF_PROMISC);
1011 bool allmulti_enabled = rx_mode_enable && (ndev->if_flags & IFF_ALLMULTI);
1012 bool broadcast_enabled = rx_mode_enable;
1014 bool enable_promisc = !ea->promisc_enabled && promisc_enabled;
1015 bool disable_promisc = ea->promisc_enabled && !promisc_enabled;
1016 bool enable_allmulti = !ea->allmulti_enabled && allmulti_enabled;
1017 bool disable_allmulti = ea->allmulti_enabled && !allmulti_enabled;
1018 bool enable_broadcast = !ea->broadcast_enabled && broadcast_enabled;
1019 bool disable_broadcast = ea->broadcast_enabled && !broadcast_enabled;
1021 /* update broadcast address */
1022 ether_addr_copy(priv->eth_addr.broadcast.addr,
1023 priv->ifp->if_broadcastaddr);
1025 if (enable_promisc) {
1026 mlx5e_add_eth_addr_rule(priv, &ea->promisc, MLX5E_PROMISC);
1027 if (!priv->vlan.filter_disabled)
1028 mlx5e_add_any_vid_rules(priv);
1030 if (enable_allmulti)
1031 mlx5e_add_eth_addr_rule(priv, &ea->allmulti, MLX5E_ALLMULTI);
1032 if (enable_broadcast)
1033 mlx5e_add_eth_addr_rule(priv, &ea->broadcast, MLX5E_FULLMATCH);
1035 mlx5e_handle_ifp_addr(priv);
1037 if (disable_broadcast)
1038 mlx5e_del_eth_addr_from_flow_table(priv, &ea->broadcast);
1039 if (disable_allmulti)
1040 mlx5e_del_eth_addr_from_flow_table(priv, &ea->allmulti);
1041 if (disable_promisc) {
1042 if (!priv->vlan.filter_disabled)
1043 mlx5e_del_any_vid_rules(priv);
1044 mlx5e_del_eth_addr_from_flow_table(priv, &ea->promisc);
1047 ea->promisc_enabled = promisc_enabled;
1048 ea->allmulti_enabled = allmulti_enabled;
1049 ea->broadcast_enabled = broadcast_enabled;
1051 mlx5e_vport_context_update(priv);
1055 mlx5e_set_rx_mode_work(struct work_struct *work)
1057 struct mlx5e_priv *priv =
1058 container_of(work, struct mlx5e_priv, set_rx_mode_work);
1061 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1062 mlx5e_set_rx_mode_core(priv);
1067 mlx5e_destroy_groups(struct mlx5e_flow_table *ft)
1071 for (i = ft->num_groups - 1; i >= 0; i--) {
1072 if (!IS_ERR_OR_NULL(ft->g[i]))
1073 mlx5_destroy_flow_group(ft->g[i]);
1080 mlx5e_destroy_flow_table(struct mlx5e_flow_table *ft)
1082 mlx5e_destroy_groups(ft);
1084 mlx5_destroy_flow_table(ft->t);
1088 #define MLX5E_NUM_MAIN_GROUPS 10
1089 #define MLX5E_MAIN_GROUP0_SIZE BIT(4)
1090 #define MLX5E_MAIN_GROUP1_SIZE BIT(3)
1091 #define MLX5E_MAIN_GROUP2_SIZE BIT(1)
1092 #define MLX5E_MAIN_GROUP3_SIZE BIT(0)
1093 #define MLX5E_MAIN_GROUP4_SIZE BIT(14)
1094 #define MLX5E_MAIN_GROUP5_SIZE BIT(13)
1095 #define MLX5E_MAIN_GROUP6_SIZE BIT(11)
1096 #define MLX5E_MAIN_GROUP7_SIZE BIT(2)
1097 #define MLX5E_MAIN_GROUP8_SIZE BIT(1)
1098 #define MLX5E_MAIN_GROUP9_SIZE BIT(0)
1099 #define MLX5E_MAIN_TABLE_SIZE (MLX5E_MAIN_GROUP0_SIZE +\
1100 MLX5E_MAIN_GROUP1_SIZE +\
1101 MLX5E_MAIN_GROUP2_SIZE +\
1102 MLX5E_MAIN_GROUP3_SIZE +\
1103 MLX5E_MAIN_GROUP4_SIZE +\
1104 MLX5E_MAIN_GROUP5_SIZE +\
1105 MLX5E_MAIN_GROUP6_SIZE +\
1106 MLX5E_MAIN_GROUP7_SIZE +\
1107 MLX5E_MAIN_GROUP8_SIZE +\
1108 MLX5E_MAIN_GROUP9_SIZE +\
1112 mlx5e_create_main_groups_sub(struct mlx5e_flow_table *ft, u32 *in,
1115 u8 *mc = MLX5_ADDR_OF(create_flow_group_in, in, match_criteria);
1116 u8 *dmac = MLX5_ADDR_OF(create_flow_group_in, in,
1117 match_criteria.outer_headers.dmac_47_16);
1121 /* Tunnel rules need to be first in this list of groups */
1123 /* Start tunnel rules */
1124 memset(in, 0, inlen);
1125 MLX5_SET_CFG(in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
1126 MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.ethertype);
1127 MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.ip_protocol);
1128 MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.udp_dport);
1129 MLX5_SET_CFG(in, start_flow_index, ix);
1130 ix += MLX5E_MAIN_GROUP0_SIZE;
1131 MLX5_SET_CFG(in, end_flow_index, ix - 1);
1132 ft->g[ft->num_groups] = mlx5_create_flow_group(ft->t, in);
1133 if (IS_ERR(ft->g[ft->num_groups]))
1134 goto err_destory_groups;
1136 /* End Tunnel Rules */
1138 memset(in, 0, inlen);
1139 MLX5_SET_CFG(in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
1140 MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.ethertype);
1141 MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.ip_protocol);
1142 MLX5_SET_CFG(in, start_flow_index, ix);
1143 ix += MLX5E_MAIN_GROUP1_SIZE;
1144 MLX5_SET_CFG(in, end_flow_index, ix - 1);
1145 ft->g[ft->num_groups] = mlx5_create_flow_group(ft->t, in);
1146 if (IS_ERR(ft->g[ft->num_groups]))
1147 goto err_destory_groups;
1150 memset(in, 0, inlen);
1151 MLX5_SET_CFG(in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
1152 MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.ethertype);
1153 MLX5_SET_CFG(in, start_flow_index, ix);
1154 ix += MLX5E_MAIN_GROUP2_SIZE;
1155 MLX5_SET_CFG(in, end_flow_index, ix - 1);
1156 ft->g[ft->num_groups] = mlx5_create_flow_group(ft->t, in);
1157 if (IS_ERR(ft->g[ft->num_groups]))
1158 goto err_destory_groups;
1161 memset(in, 0, inlen);
1162 MLX5_SET_CFG(in, start_flow_index, ix);
1163 ix += MLX5E_MAIN_GROUP3_SIZE;
1164 MLX5_SET_CFG(in, end_flow_index, ix - 1);
1165 ft->g[ft->num_groups] = mlx5_create_flow_group(ft->t, in);
1166 if (IS_ERR(ft->g[ft->num_groups]))
1167 goto err_destory_groups;
1170 memset(in, 0, inlen);
1171 MLX5_SET_CFG(in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
1172 MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.ethertype);
1173 MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.ip_protocol);
1174 memset(dmac, 0xff, ETH_ALEN);
1175 MLX5_SET_CFG(in, start_flow_index, ix);
1176 ix += MLX5E_MAIN_GROUP4_SIZE;
1177 MLX5_SET_CFG(in, end_flow_index, ix - 1);
1178 ft->g[ft->num_groups] = mlx5_create_flow_group(ft->t, in);
1179 if (IS_ERR(ft->g[ft->num_groups]))
1180 goto err_destory_groups;
1183 memset(in, 0, inlen);
1184 MLX5_SET_CFG(in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
1185 MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.ethertype);
1186 memset(dmac, 0xff, ETH_ALEN);
1187 MLX5_SET_CFG(in, start_flow_index, ix);
1188 ix += MLX5E_MAIN_GROUP5_SIZE;
1189 MLX5_SET_CFG(in, end_flow_index, ix - 1);
1190 ft->g[ft->num_groups] = mlx5_create_flow_group(ft->t, in);
1191 if (IS_ERR(ft->g[ft->num_groups]))
1192 goto err_destory_groups;
1195 memset(in, 0, inlen);
1196 MLX5_SET_CFG(in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
1197 memset(dmac, 0xff, ETH_ALEN);
1198 MLX5_SET_CFG(in, start_flow_index, ix);
1199 ix += MLX5E_MAIN_GROUP6_SIZE;
1200 MLX5_SET_CFG(in, end_flow_index, ix - 1);
1201 ft->g[ft->num_groups] = mlx5_create_flow_group(ft->t, in);
1202 if (IS_ERR(ft->g[ft->num_groups]))
1203 goto err_destory_groups;
1206 memset(in, 0, inlen);
1207 MLX5_SET_CFG(in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
1208 MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.ethertype);
1209 MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.ip_protocol);
1211 MLX5_SET_CFG(in, start_flow_index, ix);
1212 ix += MLX5E_MAIN_GROUP7_SIZE;
1213 MLX5_SET_CFG(in, end_flow_index, ix - 1);
1214 ft->g[ft->num_groups] = mlx5_create_flow_group(ft->t, in);
1215 if (IS_ERR(ft->g[ft->num_groups]))
1216 goto err_destory_groups;
1219 memset(in, 0, inlen);
1220 MLX5_SET_CFG(in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
1221 MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.ethertype);
1223 MLX5_SET_CFG(in, start_flow_index, ix);
1224 ix += MLX5E_MAIN_GROUP8_SIZE;
1225 MLX5_SET_CFG(in, end_flow_index, ix - 1);
1226 ft->g[ft->num_groups] = mlx5_create_flow_group(ft->t, in);
1227 if (IS_ERR(ft->g[ft->num_groups]))
1228 goto err_destory_groups;
1231 memset(in, 0, inlen);
1232 MLX5_SET_CFG(in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
1234 MLX5_SET_CFG(in, start_flow_index, ix);
1235 ix += MLX5E_MAIN_GROUP9_SIZE;
1236 MLX5_SET_CFG(in, end_flow_index, ix - 1);
1237 ft->g[ft->num_groups] = mlx5_create_flow_group(ft->t, in);
1238 if (IS_ERR(ft->g[ft->num_groups]))
1239 goto err_destory_groups;
1245 err = PTR_ERR(ft->g[ft->num_groups]);
1246 ft->g[ft->num_groups] = NULL;
1247 mlx5e_destroy_groups(ft);
1253 mlx5e_create_main_groups(struct mlx5e_flow_table *ft)
1256 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1259 in = mlx5_vzalloc(inlen);
1263 err = mlx5e_create_main_groups_sub(ft, in, inlen);
1269 static int mlx5e_create_main_flow_table(struct mlx5e_priv *priv)
1271 struct mlx5e_flow_table *ft = &priv->fts.main;
1275 ft->t = mlx5_create_flow_table(priv->fts.ns, 0, "main",
1276 MLX5E_MAIN_TABLE_SIZE);
1278 if (IS_ERR(ft->t)) {
1279 err = PTR_ERR(ft->t);
1283 ft->g = kcalloc(MLX5E_NUM_MAIN_GROUPS, sizeof(*ft->g), GFP_KERNEL);
1286 goto err_destroy_main_flow_table;
1289 err = mlx5e_create_main_groups(ft);
1297 err_destroy_main_flow_table:
1298 mlx5_destroy_flow_table(ft->t);
1304 static void mlx5e_destroy_main_flow_table(struct mlx5e_priv *priv)
1306 mlx5e_destroy_flow_table(&priv->fts.main);
1309 #define MLX5E_NUM_VLAN_GROUPS 3
1310 #define MLX5E_VLAN_GROUP0_SIZE BIT(12)
1311 #define MLX5E_VLAN_GROUP1_SIZE BIT(1)
1312 #define MLX5E_VLAN_GROUP2_SIZE BIT(0)
1313 #define MLX5E_VLAN_TABLE_SIZE (MLX5E_VLAN_GROUP0_SIZE +\
1314 MLX5E_VLAN_GROUP1_SIZE +\
1315 MLX5E_VLAN_GROUP2_SIZE +\
1319 mlx5e_create_vlan_groups_sub(struct mlx5e_flow_table *ft, u32 *in,
1324 u8 *mc = MLX5_ADDR_OF(create_flow_group_in, in, match_criteria);
1326 memset(in, 0, inlen);
1327 MLX5_SET_CFG(in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
1328 MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.cvlan_tag);
1329 MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.first_vid);
1330 MLX5_SET_CFG(in, start_flow_index, ix);
1331 ix += MLX5E_VLAN_GROUP0_SIZE;
1332 MLX5_SET_CFG(in, end_flow_index, ix - 1);
1333 ft->g[ft->num_groups] = mlx5_create_flow_group(ft->t, in);
1334 if (IS_ERR(ft->g[ft->num_groups]))
1335 goto err_destory_groups;
1338 memset(in, 0, inlen);
1339 MLX5_SET_CFG(in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
1340 MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.cvlan_tag);
1341 MLX5_SET_CFG(in, start_flow_index, ix);
1342 ix += MLX5E_VLAN_GROUP1_SIZE;
1343 MLX5_SET_CFG(in, end_flow_index, ix - 1);
1344 ft->g[ft->num_groups] = mlx5_create_flow_group(ft->t, in);
1345 if (IS_ERR(ft->g[ft->num_groups]))
1346 goto err_destory_groups;
1349 memset(in, 0, inlen);
1350 MLX5_SET_CFG(in, match_criteria_enable, MLX5_MATCH_OUTER_HEADERS);
1351 MLX5_SET_TO_ONES(fte_match_param, mc, outer_headers.svlan_tag);
1352 MLX5_SET_CFG(in, start_flow_index, ix);
1353 ix += MLX5E_VLAN_GROUP2_SIZE;
1354 MLX5_SET_CFG(in, end_flow_index, ix - 1);
1355 ft->g[ft->num_groups] = mlx5_create_flow_group(ft->t, in);
1356 if (IS_ERR(ft->g[ft->num_groups]))
1357 goto err_destory_groups;
1363 err = PTR_ERR(ft->g[ft->num_groups]);
1364 ft->g[ft->num_groups] = NULL;
1365 mlx5e_destroy_groups(ft);
1371 mlx5e_create_vlan_groups(struct mlx5e_flow_table *ft)
1374 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1377 in = mlx5_vzalloc(inlen);
1381 err = mlx5e_create_vlan_groups_sub(ft, in, inlen);
1388 mlx5e_create_vlan_flow_table(struct mlx5e_priv *priv)
1390 struct mlx5e_flow_table *ft = &priv->fts.vlan;
1394 ft->t = mlx5_create_flow_table(priv->fts.ns, 0, "vlan",
1395 MLX5E_VLAN_TABLE_SIZE);
1397 if (IS_ERR(ft->t)) {
1398 err = PTR_ERR(ft->t);
1402 ft->g = kcalloc(MLX5E_NUM_VLAN_GROUPS, sizeof(*ft->g), GFP_KERNEL);
1405 goto err_destroy_vlan_flow_table;
1408 err = mlx5e_create_vlan_groups(ft);
1417 err_destroy_vlan_flow_table:
1418 mlx5_destroy_flow_table(ft->t);
1425 mlx5e_destroy_vlan_flow_table(struct mlx5e_priv *priv)
1427 mlx5e_destroy_flow_table(&priv->fts.vlan);
1430 #define MLX5E_NUM_INNER_RSS_GROUPS 3
1431 #define MLX5E_INNER_RSS_GROUP0_SIZE BIT(3)
1432 #define MLX5E_INNER_RSS_GROUP1_SIZE BIT(1)
1433 #define MLX5E_INNER_RSS_GROUP2_SIZE BIT(0)
1434 #define MLX5E_INNER_RSS_TABLE_SIZE (MLX5E_INNER_RSS_GROUP0_SIZE +\
1435 MLX5E_INNER_RSS_GROUP1_SIZE +\
1436 MLX5E_INNER_RSS_GROUP2_SIZE +\
1440 mlx5e_create_inner_rss_groups_sub(struct mlx5e_flow_table *ft, u32 *in,
1443 u8 *mc = MLX5_ADDR_OF(create_flow_group_in, in, match_criteria);
1447 memset(in, 0, inlen);
1448 MLX5_SET_CFG(in, match_criteria_enable, MLX5_MATCH_INNER_HEADERS);
1449 MLX5_SET_TO_ONES(fte_match_param, mc, inner_headers.ethertype);
1450 MLX5_SET_TO_ONES(fte_match_param, mc, inner_headers.ip_protocol);
1451 MLX5_SET_CFG(in, start_flow_index, ix);
1452 ix += MLX5E_INNER_RSS_GROUP0_SIZE;
1453 MLX5_SET_CFG(in, end_flow_index, ix - 1);
1454 ft->g[ft->num_groups] = mlx5_create_flow_group(ft->t, in);
1455 if (IS_ERR(ft->g[ft->num_groups]))
1456 goto err_destory_groups;
1459 memset(in, 0, inlen);
1460 MLX5_SET_CFG(in, match_criteria_enable, MLX5_MATCH_INNER_HEADERS);
1461 MLX5_SET_TO_ONES(fte_match_param, mc, inner_headers.ethertype);
1462 MLX5_SET_CFG(in, start_flow_index, ix);
1463 ix += MLX5E_INNER_RSS_GROUP1_SIZE;
1464 MLX5_SET_CFG(in, end_flow_index, ix - 1);
1465 ft->g[ft->num_groups] = mlx5_create_flow_group(ft->t, in);
1466 if (IS_ERR(ft->g[ft->num_groups]))
1467 goto err_destory_groups;
1470 memset(in, 0, inlen);
1471 MLX5_SET_CFG(in, start_flow_index, ix);
1472 ix += MLX5E_INNER_RSS_GROUP2_SIZE;
1473 MLX5_SET_CFG(in, end_flow_index, ix - 1);
1474 ft->g[ft->num_groups] = mlx5_create_flow_group(ft->t, in);
1475 if (IS_ERR(ft->g[ft->num_groups]))
1476 goto err_destory_groups;
1482 err = PTR_ERR(ft->g[ft->num_groups]);
1483 ft->g[ft->num_groups] = NULL;
1484 mlx5e_destroy_groups(ft);
1490 mlx5e_create_inner_rss_groups(struct mlx5e_flow_table *ft)
1493 int inlen = MLX5_ST_SZ_BYTES(create_flow_group_in);
1496 in = mlx5_vzalloc(inlen);
1500 err = mlx5e_create_inner_rss_groups_sub(ft, in, inlen);
1507 mlx5e_create_inner_rss_flow_table(struct mlx5e_priv *priv)
1509 struct mlx5e_flow_table *ft = &priv->fts.inner_rss;
1513 ft->t = mlx5_create_flow_table(priv->fts.ns, 0, "inner_rss",
1514 MLX5E_INNER_RSS_TABLE_SIZE);
1516 if (IS_ERR(ft->t)) {
1517 err = PTR_ERR(ft->t);
1521 ft->g = kcalloc(MLX5E_NUM_INNER_RSS_GROUPS, sizeof(*ft->g),
1525 goto err_destroy_inner_rss_flow_table;
1528 err = mlx5e_create_inner_rss_groups(ft);
1537 err_destroy_inner_rss_flow_table:
1538 mlx5_destroy_flow_table(ft->t);
1544 static void mlx5e_destroy_inner_rss_flow_table(struct mlx5e_priv *priv)
1546 mlx5e_destroy_flow_table(&priv->fts.inner_rss);
1550 mlx5e_open_flow_table(struct mlx5e_priv *priv)
1554 priv->fts.ns = mlx5_get_flow_namespace(priv->mdev,
1555 MLX5_FLOW_NAMESPACE_KERNEL);
1557 err = mlx5e_create_vlan_flow_table(priv);
1561 err = mlx5e_create_main_flow_table(priv);
1563 goto err_destroy_vlan_flow_table;
1565 err = mlx5e_create_inner_rss_flow_table(priv);
1567 goto err_destroy_main_flow_table;
1571 err_destroy_main_flow_table:
1572 mlx5e_destroy_main_flow_table(priv);
1573 err_destroy_vlan_flow_table:
1574 mlx5e_destroy_vlan_flow_table(priv);
1580 mlx5e_close_flow_table(struct mlx5e_priv *priv)
1583 mlx5e_handle_ifp_addr(priv);
1584 mlx5e_destroy_inner_rss_flow_table(priv);
1585 mlx5e_destroy_main_flow_table(priv);
1586 mlx5e_destroy_vlan_flow_table(priv);