2 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/sockio.h>
31 #include <machine/atomic.h>
33 #define ETH_DRIVER_VERSION "3.1.0-dev"
34 char mlx5e_version[] = "Mellanox Ethernet driver"
35 " (" ETH_DRIVER_VERSION ")";
37 struct mlx5e_rq_param {
38 u32 rqc [MLX5_ST_SZ_DW(rqc)];
39 struct mlx5_wq_param wq;
42 struct mlx5e_sq_param {
43 u32 sqc [MLX5_ST_SZ_DW(sqc)];
44 struct mlx5_wq_param wq;
47 struct mlx5e_cq_param {
48 u32 cqc [MLX5_ST_SZ_DW(cqc)];
49 struct mlx5_wq_param wq;
53 struct mlx5e_channel_param {
54 struct mlx5e_rq_param rq;
55 struct mlx5e_sq_param sq;
56 struct mlx5e_cq_param rx_cq;
57 struct mlx5e_cq_param tx_cq;
63 } mlx5e_mode_table[MLX5E_LINK_MODES_NUMBER] = {
65 [MLX5E_1000BASE_CX_SGMII] = {
66 .subtype = IFM_1000_CX_SGMII,
67 .baudrate = IF_Mbps(1000ULL),
69 [MLX5E_1000BASE_KX] = {
70 .subtype = IFM_1000_KX,
71 .baudrate = IF_Mbps(1000ULL),
73 [MLX5E_10GBASE_CX4] = {
74 .subtype = IFM_10G_CX4,
75 .baudrate = IF_Gbps(10ULL),
77 [MLX5E_10GBASE_KX4] = {
78 .subtype = IFM_10G_KX4,
79 .baudrate = IF_Gbps(10ULL),
81 [MLX5E_10GBASE_KR] = {
82 .subtype = IFM_10G_KR,
83 .baudrate = IF_Gbps(10ULL),
85 [MLX5E_20GBASE_KR2] = {
86 .subtype = IFM_20G_KR2,
87 .baudrate = IF_Gbps(20ULL),
89 [MLX5E_40GBASE_CR4] = {
90 .subtype = IFM_40G_CR4,
91 .baudrate = IF_Gbps(40ULL),
93 [MLX5E_40GBASE_KR4] = {
94 .subtype = IFM_40G_KR4,
95 .baudrate = IF_Gbps(40ULL),
97 [MLX5E_56GBASE_R4] = {
98 .subtype = IFM_56G_R4,
99 .baudrate = IF_Gbps(56ULL),
101 [MLX5E_10GBASE_CR] = {
102 .subtype = IFM_10G_CR1,
103 .baudrate = IF_Gbps(10ULL),
105 [MLX5E_10GBASE_SR] = {
106 .subtype = IFM_10G_SR,
107 .baudrate = IF_Gbps(10ULL),
109 [MLX5E_10GBASE_LR] = {
110 .subtype = IFM_10G_LR,
111 .baudrate = IF_Gbps(10ULL),
113 [MLX5E_40GBASE_SR4] = {
114 .subtype = IFM_40G_SR4,
115 .baudrate = IF_Gbps(40ULL),
117 [MLX5E_40GBASE_LR4] = {
118 .subtype = IFM_40G_LR4,
119 .baudrate = IF_Gbps(40ULL),
121 [MLX5E_100GBASE_CR4] = {
122 .subtype = IFM_100G_CR4,
123 .baudrate = IF_Gbps(100ULL),
125 [MLX5E_100GBASE_SR4] = {
126 .subtype = IFM_100G_SR4,
127 .baudrate = IF_Gbps(100ULL),
129 [MLX5E_100GBASE_KR4] = {
130 .subtype = IFM_100G_KR4,
131 .baudrate = IF_Gbps(100ULL),
133 [MLX5E_100GBASE_LR4] = {
134 .subtype = IFM_100G_LR4,
135 .baudrate = IF_Gbps(100ULL),
137 [MLX5E_100BASE_TX] = {
138 .subtype = IFM_100_TX,
139 .baudrate = IF_Mbps(100ULL),
141 [MLX5E_100BASE_T] = {
142 .subtype = IFM_100_T,
143 .baudrate = IF_Mbps(100ULL),
145 [MLX5E_10GBASE_T] = {
146 .subtype = IFM_10G_T,
147 .baudrate = IF_Gbps(10ULL),
149 [MLX5E_25GBASE_CR] = {
150 .subtype = IFM_25G_CR,
151 .baudrate = IF_Gbps(25ULL),
153 [MLX5E_25GBASE_KR] = {
154 .subtype = IFM_25G_KR,
155 .baudrate = IF_Gbps(25ULL),
157 [MLX5E_25GBASE_SR] = {
158 .subtype = IFM_25G_SR,
159 .baudrate = IF_Gbps(25ULL),
161 [MLX5E_50GBASE_CR2] = {
162 .subtype = IFM_50G_CR2,
163 .baudrate = IF_Gbps(50ULL),
165 [MLX5E_50GBASE_KR2] = {
166 .subtype = IFM_50G_KR2,
167 .baudrate = IF_Gbps(50ULL),
171 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
174 mlx5e_update_carrier(struct mlx5e_priv *priv)
176 struct mlx5_core_dev *mdev = priv->mdev;
177 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
183 port_state = mlx5_query_vport_state(mdev,
184 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
186 if (port_state == VPORT_STATE_UP) {
187 priv->media_status_last |= IFM_ACTIVE;
189 priv->media_status_last &= ~IFM_ACTIVE;
190 priv->media_active_last = IFM_ETHER;
191 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
195 error = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN);
197 priv->media_active_last = IFM_ETHER;
198 priv->ifp->if_baudrate = 1;
199 if_printf(priv->ifp, "%s: query port ptys failed: 0x%x\n",
203 eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
205 for (i = 0; i != MLX5E_LINK_MODES_NUMBER; i++) {
206 if (mlx5e_mode_table[i].baudrate == 0)
208 if (MLX5E_PROT_MASK(i) & eth_proto_oper) {
209 priv->ifp->if_baudrate =
210 mlx5e_mode_table[i].baudrate;
211 priv->media_active_last =
212 mlx5e_mode_table[i].subtype | IFM_ETHER | IFM_FDX;
215 if_link_state_change(priv->ifp, LINK_STATE_UP);
219 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
221 struct mlx5e_priv *priv = dev->if_softc;
223 ifmr->ifm_status = priv->media_status_last;
224 ifmr->ifm_active = priv->media_active_last |
225 (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
226 (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
231 mlx5e_find_link_mode(u32 subtype)
236 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
237 if (mlx5e_mode_table[i].baudrate == 0)
239 if (mlx5e_mode_table[i].subtype == subtype)
240 link_mode |= MLX5E_PROT_MASK(i);
247 mlx5e_media_change(struct ifnet *dev)
249 struct mlx5e_priv *priv = dev->if_softc;
250 struct mlx5_core_dev *mdev = priv->mdev;
257 locked = PRIV_LOCKED(priv);
261 if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
265 link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media));
267 /* query supported capabilities */
268 error = mlx5_query_port_proto_cap(mdev, ð_proto_cap, MLX5_PTYS_EN);
270 if_printf(dev, "Query port media capability failed\n");
273 /* check for autoselect */
274 if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
275 link_mode = eth_proto_cap;
276 if (link_mode == 0) {
277 if_printf(dev, "Port media capability is zero\n");
282 link_mode = link_mode & eth_proto_cap;
283 if (link_mode == 0) {
284 if_printf(dev, "Not supported link mode requested\n");
289 /* update pauseframe control bits */
290 priv->params.rx_pauseframe_control =
291 (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
292 priv->params.tx_pauseframe_control =
293 (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
295 /* check if device is opened */
296 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
298 /* reconfigure the hardware */
299 mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
300 mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN);
301 mlx5_set_port_pause(mdev, 1,
302 priv->params.rx_pauseframe_control,
303 priv->params.tx_pauseframe_control);
305 mlx5_set_port_status(mdev, MLX5_PORT_UP);
314 mlx5e_update_carrier_work(struct work_struct *work)
316 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
317 update_carrier_work);
320 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
321 mlx5e_update_carrier(priv);
326 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
328 struct mlx5_core_dev *mdev = priv->mdev;
329 struct mlx5e_pport_stats *s = &priv->stats.pport;
330 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
334 unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
338 in = mlx5_vzalloc(sz);
339 out = mlx5_vzalloc(sz);
340 if (in == NULL || out == NULL)
343 ptr = (uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
345 MLX5_SET(ppcnt_reg, in, local_port, 1);
347 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
348 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
349 for (x = y = 0; x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
350 s->arg[y] = be64toh(ptr[x]);
352 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
353 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
354 for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
355 s->arg[y] = be64toh(ptr[x]);
356 for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
357 MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
358 s_debug->arg[y] = be64toh(ptr[x]);
360 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
361 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
362 for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
363 s_debug->arg[y] = be64toh(ptr[x]);
365 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
366 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
367 for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
368 s_debug->arg[y] = be64toh(ptr[x]);
375 mlx5e_update_stats_work(struct work_struct *work)
377 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
379 struct mlx5_core_dev *mdev = priv->mdev;
380 struct mlx5e_vport_stats *s = &priv->stats.vport;
381 struct mlx5e_rq_stats *rq_stats;
382 struct mlx5e_sq_stats *sq_stats;
383 struct buf_ring *sq_br;
384 #if (__FreeBSD_version < 1100000)
385 struct ifnet *ifp = priv->ifp;
388 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
390 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
393 u64 tx_queue_dropped = 0;
394 u64 tx_defragged = 0;
395 u64 tx_offload_none = 0;
398 u64 sw_lro_queued = 0;
399 u64 sw_lro_flushed = 0;
400 u64 rx_csum_none = 0;
402 u32 rx_out_of_buffer = 0;
407 out = mlx5_vzalloc(outlen);
410 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
413 /* Collect firts the SW counters and then HW for consistency */
414 for (i = 0; i < priv->params.num_channels; i++) {
415 struct mlx5e_rq *rq = &priv->channel[i]->rq;
417 rq_stats = &priv->channel[i]->rq.stats;
419 /* collect stats from LRO */
420 rq_stats->sw_lro_queued = rq->lro.lro_queued;
421 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
422 sw_lro_queued += rq_stats->sw_lro_queued;
423 sw_lro_flushed += rq_stats->sw_lro_flushed;
424 lro_packets += rq_stats->lro_packets;
425 lro_bytes += rq_stats->lro_bytes;
426 rx_csum_none += rq_stats->csum_none;
427 rx_wqe_err += rq_stats->wqe_err;
429 for (j = 0; j < priv->num_tc; j++) {
430 sq_stats = &priv->channel[i]->sq[j].stats;
431 sq_br = priv->channel[i]->sq[j].br;
433 tso_packets += sq_stats->tso_packets;
434 tso_bytes += sq_stats->tso_bytes;
435 tx_queue_dropped += sq_stats->dropped;
436 tx_queue_dropped += sq_br->br_drops;
437 tx_defragged += sq_stats->defragged;
438 tx_offload_none += sq_stats->csum_offload_none;
442 /* update counters */
443 s->tso_packets = tso_packets;
444 s->tso_bytes = tso_bytes;
445 s->tx_queue_dropped = tx_queue_dropped;
446 s->tx_defragged = tx_defragged;
447 s->lro_packets = lro_packets;
448 s->lro_bytes = lro_bytes;
449 s->sw_lro_queued = sw_lro_queued;
450 s->sw_lro_flushed = sw_lro_flushed;
451 s->rx_csum_none = rx_csum_none;
452 s->rx_wqe_err = rx_wqe_err;
455 memset(in, 0, sizeof(in));
457 MLX5_SET(query_vport_counter_in, in, opcode,
458 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
459 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
460 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
462 memset(out, 0, outlen);
464 /* get number of out-of-buffer drops first */
465 if (mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
469 /* accumulate difference into a 64-bit counter */
470 s->rx_out_of_buffer += (u64)(u32)(rx_out_of_buffer - s->rx_out_of_buffer_prev);
471 s->rx_out_of_buffer_prev = rx_out_of_buffer;
473 /* get port statistics */
474 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
477 #define MLX5_GET_CTR(out, x) \
478 MLX5_GET64(query_vport_counter_out, out, x)
480 s->rx_error_packets =
481 MLX5_GET_CTR(out, received_errors.packets);
483 MLX5_GET_CTR(out, received_errors.octets);
484 s->tx_error_packets =
485 MLX5_GET_CTR(out, transmit_errors.packets);
487 MLX5_GET_CTR(out, transmit_errors.octets);
489 s->rx_unicast_packets =
490 MLX5_GET_CTR(out, received_eth_unicast.packets);
491 s->rx_unicast_bytes =
492 MLX5_GET_CTR(out, received_eth_unicast.octets);
493 s->tx_unicast_packets =
494 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
495 s->tx_unicast_bytes =
496 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
498 s->rx_multicast_packets =
499 MLX5_GET_CTR(out, received_eth_multicast.packets);
500 s->rx_multicast_bytes =
501 MLX5_GET_CTR(out, received_eth_multicast.octets);
502 s->tx_multicast_packets =
503 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
504 s->tx_multicast_bytes =
505 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
507 s->rx_broadcast_packets =
508 MLX5_GET_CTR(out, received_eth_broadcast.packets);
509 s->rx_broadcast_bytes =
510 MLX5_GET_CTR(out, received_eth_broadcast.octets);
511 s->tx_broadcast_packets =
512 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
513 s->tx_broadcast_bytes =
514 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
517 s->rx_unicast_packets +
518 s->rx_multicast_packets +
519 s->rx_broadcast_packets -
522 s->rx_unicast_bytes +
523 s->rx_multicast_bytes +
524 s->rx_broadcast_bytes;
526 s->tx_unicast_packets +
527 s->tx_multicast_packets +
528 s->tx_broadcast_packets;
530 s->tx_unicast_bytes +
531 s->tx_multicast_bytes +
532 s->tx_broadcast_bytes;
534 /* Update calculated offload counters */
535 s->tx_csum_offload = s->tx_packets - tx_offload_none;
536 s->rx_csum_good = s->rx_packets - s->rx_csum_none;
538 /* Update per port counters */
539 mlx5e_update_pport_counters(priv);
541 #if (__FreeBSD_version < 1100000)
542 /* no get_counters interface in fbsd 10 */
543 ifp->if_ipackets = s->rx_packets;
544 ifp->if_ierrors = s->rx_error_packets;
545 ifp->if_iqdrops = s->rx_out_of_buffer;
546 ifp->if_opackets = s->tx_packets;
547 ifp->if_oerrors = s->tx_error_packets;
548 ifp->if_snd.ifq_drops = s->tx_queue_dropped;
549 ifp->if_ibytes = s->rx_bytes;
550 ifp->if_obytes = s->tx_bytes;
559 mlx5e_update_stats(void *arg)
561 struct mlx5e_priv *priv = arg;
563 schedule_work(&priv->update_stats_work);
565 callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
569 mlx5e_async_event_sub(struct mlx5e_priv *priv,
570 enum mlx5_dev_event event)
573 case MLX5_DEV_EVENT_PORT_UP:
574 case MLX5_DEV_EVENT_PORT_DOWN:
575 schedule_work(&priv->update_carrier_work);
584 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
585 enum mlx5_dev_event event, unsigned long param)
587 struct mlx5e_priv *priv = vpriv;
589 mtx_lock(&priv->async_events_mtx);
590 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
591 mlx5e_async_event_sub(priv, event);
592 mtx_unlock(&priv->async_events_mtx);
596 mlx5e_enable_async_events(struct mlx5e_priv *priv)
598 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
602 mlx5e_disable_async_events(struct mlx5e_priv *priv)
604 mtx_lock(&priv->async_events_mtx);
605 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
606 mtx_unlock(&priv->async_events_mtx);
609 static const char *mlx5e_rq_stats_desc[] = {
610 MLX5E_RQ_STATS(MLX5E_STATS_DESC)
614 mlx5e_create_rq(struct mlx5e_channel *c,
615 struct mlx5e_rq_param *param,
618 struct mlx5e_priv *priv = c->priv;
619 struct mlx5_core_dev *mdev = priv->mdev;
621 void *rqc = param->rqc;
622 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
627 /* Create DMA descriptor TAG */
628 if ((err = -bus_dma_tag_create(
629 bus_get_dma_tag(mdev->pdev->dev.bsddev),
630 1, /* any alignment */
632 BUS_SPACE_MAXADDR, /* lowaddr */
633 BUS_SPACE_MAXADDR, /* highaddr */
634 NULL, NULL, /* filter, filterarg */
635 MJUM16BYTES, /* maxsize */
637 MJUM16BYTES, /* maxsegsize */
639 NULL, NULL, /* lockfunc, lockfuncarg */
643 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
646 goto err_free_dma_tag;
648 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
650 if (priv->params.hw_lro_en) {
651 rq->wqe_sz = priv->params.lro_wqe_sz;
653 rq->wqe_sz = MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
655 if (rq->wqe_sz > MJUM16BYTES) {
657 goto err_rq_wq_destroy;
658 } else if (rq->wqe_sz > MJUM9BYTES) {
659 rq->wqe_sz = MJUM16BYTES;
660 } else if (rq->wqe_sz > MJUMPAGESIZE) {
661 rq->wqe_sz = MJUM9BYTES;
662 } else if (rq->wqe_sz > MCLBYTES) {
663 rq->wqe_sz = MJUMPAGESIZE;
665 rq->wqe_sz = MCLBYTES;
668 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
670 err = -tcp_lro_init_args(&rq->lro, c->ifp, TCP_LRO_ENTRIES, wq_sz);
672 goto err_rq_wq_destroy;
674 rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
675 if (rq->mbuf == NULL) {
679 for (i = 0; i != wq_sz; i++) {
680 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
681 uint32_t byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
683 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
686 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
687 goto err_rq_mbuf_free;
689 wqe->data.lkey = c->mkey_be;
690 wqe->data.byte_count = cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
698 snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
699 mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
700 buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
705 free(rq->mbuf, M_MLX5EN);
707 tcp_lro_free(&rq->lro);
709 mlx5_wq_destroy(&rq->wq_ctrl);
711 bus_dma_tag_destroy(rq->dma_tag);
717 mlx5e_destroy_rq(struct mlx5e_rq *rq)
722 /* destroy all sysctl nodes */
723 sysctl_ctx_free(&rq->stats.ctx);
725 /* free leftover LRO packets, if any */
726 tcp_lro_free(&rq->lro);
728 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
729 for (i = 0; i != wq_sz; i++) {
730 if (rq->mbuf[i].mbuf != NULL) {
731 bus_dmamap_unload(rq->dma_tag,
732 rq->mbuf[i].dma_map);
733 m_freem(rq->mbuf[i].mbuf);
735 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
737 free(rq->mbuf, M_MLX5EN);
738 mlx5_wq_destroy(&rq->wq_ctrl);
742 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
744 struct mlx5e_channel *c = rq->channel;
745 struct mlx5e_priv *priv = c->priv;
746 struct mlx5_core_dev *mdev = priv->mdev;
754 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
755 sizeof(u64) * rq->wq_ctrl.buf.npages;
756 in = mlx5_vzalloc(inlen);
760 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
761 wq = MLX5_ADDR_OF(rqc, rqc, wq);
763 memcpy(rqc, param->rqc, sizeof(param->rqc));
765 MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
766 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
767 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
768 if (priv->counter_set_id >= 0)
769 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
770 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
772 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
774 mlx5_fill_page_array(&rq->wq_ctrl.buf,
775 (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
777 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
785 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
787 struct mlx5e_channel *c = rq->channel;
788 struct mlx5e_priv *priv = c->priv;
789 struct mlx5_core_dev *mdev = priv->mdev;
796 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
797 in = mlx5_vzalloc(inlen);
801 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
803 MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
804 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
805 MLX5_SET(rqc, rqc, state, next_state);
807 err = mlx5_core_modify_rq(mdev, in, inlen);
815 mlx5e_disable_rq(struct mlx5e_rq *rq)
817 struct mlx5e_channel *c = rq->channel;
818 struct mlx5e_priv *priv = c->priv;
819 struct mlx5_core_dev *mdev = priv->mdev;
821 mlx5_core_destroy_rq(mdev, rq->rqn);
825 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
827 struct mlx5e_channel *c = rq->channel;
828 struct mlx5e_priv *priv = c->priv;
829 struct mlx5_wq_ll *wq = &rq->wq;
832 for (i = 0; i < 1000; i++) {
833 if (wq->cur_sz >= priv->params.min_rx_wqes)
842 mlx5e_open_rq(struct mlx5e_channel *c,
843 struct mlx5e_rq_param *param,
848 err = mlx5e_create_rq(c, param, rq);
852 err = mlx5e_enable_rq(rq, param);
856 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
865 mlx5e_disable_rq(rq);
867 mlx5e_destroy_rq(rq);
873 mlx5e_close_rq(struct mlx5e_rq *rq)
876 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
880 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
882 /* wait till RQ is empty */
883 while (!mlx5_wq_ll_is_empty(&rq->wq)) {
885 rq->cq.mcq.comp(&rq->cq.mcq);
888 mlx5e_disable_rq(rq);
889 mlx5e_destroy_rq(rq);
893 mlx5e_free_sq_db(struct mlx5e_sq *sq)
895 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
898 for (x = 0; x != wq_sz; x++)
899 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
900 free(sq->mbuf, M_MLX5EN);
904 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
906 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
910 sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
911 if (sq->mbuf == NULL)
914 /* Create DMA descriptor MAPs */
915 for (x = 0; x != wq_sz; x++) {
916 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
919 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
920 free(sq->mbuf, M_MLX5EN);
927 static const char *mlx5e_sq_stats_desc[] = {
928 MLX5E_SQ_STATS(MLX5E_STATS_DESC)
932 mlx5e_create_sq(struct mlx5e_channel *c,
934 struct mlx5e_sq_param *param,
937 struct mlx5e_priv *priv = c->priv;
938 struct mlx5_core_dev *mdev = priv->mdev;
941 void *sqc = param->sqc;
942 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
949 /* Create DMA descriptor TAG */
950 if ((err = -bus_dma_tag_create(
951 bus_get_dma_tag(mdev->pdev->dev.bsddev),
952 1, /* any alignment */
954 BUS_SPACE_MAXADDR, /* lowaddr */
955 BUS_SPACE_MAXADDR, /* highaddr */
956 NULL, NULL, /* filter, filterarg */
957 MLX5E_MAX_TX_PAYLOAD_SIZE, /* maxsize */
958 MLX5E_MAX_TX_MBUF_FRAGS, /* nsegments */
959 MLX5E_MAX_TX_MBUF_SIZE, /* maxsegsize */
961 NULL, NULL, /* lockfunc, lockfuncarg */
965 err = mlx5_alloc_map_uar(mdev, &sq->uar);
967 goto err_free_dma_tag;
969 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq,
972 goto err_unmap_free_uar;
974 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
975 sq->uar_map = sq->uar.map;
976 sq->uar_bf_map = sq->uar.bf_map;
977 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
979 err = mlx5e_alloc_sq_db(sq);
981 goto err_sq_wq_destroy;
984 sq->mkey_be = c->mkey_be;
988 sq->br = buf_ring_alloc(MLX5E_SQ_TX_QUEUE_SIZE, M_MLX5EN,
989 M_WAITOK, &sq->lock);
990 if (sq->br == NULL) {
991 if_printf(c->ifp, "%s: Failed allocating sq drbr buffer\n",
997 sq->sq_tq = taskqueue_create_fast("mlx5e_que", M_WAITOK,
998 taskqueue_thread_enqueue, &sq->sq_tq);
999 if (sq->sq_tq == NULL) {
1000 if_printf(c->ifp, "%s: Failed allocating taskqueue\n",
1006 TASK_INIT(&sq->sq_task, 0, mlx5e_tx_que, sq);
1008 cpu_id = rss_getcpu(c->ix % rss_getnumbuckets());
1009 CPU_SETOF(cpu_id, &cpu_mask);
1010 taskqueue_start_threads_cpuset(&sq->sq_tq, 1, PI_NET, &cpu_mask,
1011 "%s TX SQ%d.%d CPU%d", c->ifp->if_xname, c->ix, tc, cpu_id);
1013 taskqueue_start_threads(&sq->sq_tq, 1, PI_NET,
1014 "%s TX SQ%d.%d", c->ifp->if_xname, c->ix, tc);
1016 snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1017 mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1018 buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1024 buf_ring_free(sq->br, M_MLX5EN);
1026 mlx5e_free_sq_db(sq);
1028 mlx5_wq_destroy(&sq->wq_ctrl);
1031 mlx5_unmap_free_uar(mdev, &sq->uar);
1034 bus_dma_tag_destroy(sq->dma_tag);
1040 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1042 struct mlx5e_channel *c = sq->channel;
1043 struct mlx5e_priv *priv = c->priv;
1045 /* destroy all sysctl nodes */
1046 sysctl_ctx_free(&sq->stats.ctx);
1048 mlx5e_free_sq_db(sq);
1049 mlx5_wq_destroy(&sq->wq_ctrl);
1050 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
1051 taskqueue_drain(sq->sq_tq, &sq->sq_task);
1052 taskqueue_free(sq->sq_tq);
1053 buf_ring_free(sq->br, M_MLX5EN);
1057 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
1059 struct mlx5e_channel *c = sq->channel;
1060 struct mlx5e_priv *priv = c->priv;
1061 struct mlx5_core_dev *mdev = priv->mdev;
1069 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1070 sizeof(u64) * sq->wq_ctrl.buf.npages;
1071 in = mlx5_vzalloc(inlen);
1075 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1076 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1078 memcpy(sqc, param->sqc, sizeof(param->sqc));
1080 MLX5_SET(sqc, sqc, tis_num_0, priv->tisn[sq->tc]);
1081 MLX5_SET(sqc, sqc, cqn, c->sq[sq->tc].cq.mcq.cqn);
1082 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1083 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1084 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1086 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1087 MLX5_SET(wq, wq, uar_page, sq->uar.index);
1088 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1090 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1092 mlx5_fill_page_array(&sq->wq_ctrl.buf,
1093 (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1095 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
1103 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1105 struct mlx5e_channel *c = sq->channel;
1106 struct mlx5e_priv *priv = c->priv;
1107 struct mlx5_core_dev *mdev = priv->mdev;
1114 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1115 in = mlx5_vzalloc(inlen);
1119 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1121 MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1122 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1123 MLX5_SET(sqc, sqc, state, next_state);
1125 err = mlx5_core_modify_sq(mdev, in, inlen);
1133 mlx5e_disable_sq(struct mlx5e_sq *sq)
1135 struct mlx5e_channel *c = sq->channel;
1136 struct mlx5e_priv *priv = c->priv;
1137 struct mlx5_core_dev *mdev = priv->mdev;
1139 mlx5_core_destroy_sq(mdev, sq->sqn);
1143 mlx5e_open_sq(struct mlx5e_channel *c,
1145 struct mlx5e_sq_param *param,
1146 struct mlx5e_sq *sq)
1150 err = mlx5e_create_sq(c, tc, param, sq);
1154 err = mlx5e_enable_sq(sq, param);
1156 goto err_destroy_sq;
1158 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1160 goto err_disable_sq;
1162 atomic_store_rel_int(&sq->queue_state, MLX5E_SQ_READY);
1167 mlx5e_disable_sq(sq);
1169 mlx5e_destroy_sq(sq);
1175 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1177 /* fill up remainder with NOPs */
1178 while (sq->cev_counter != 0) {
1179 while (!mlx5e_sq_has_room_for(sq, 1)) {
1180 if (can_sleep != 0) {
1181 mtx_unlock(&sq->lock);
1183 mtx_lock(&sq->lock);
1188 /* send a single NOP */
1189 mlx5e_send_nop(sq, 1);
1193 /* Check if we need to write the doorbell */
1194 if (likely(sq->doorbell.d64 != 0)) {
1195 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1196 sq->doorbell.d64 = 0;
1202 mlx5e_sq_cev_timeout(void *arg)
1204 struct mlx5e_sq *sq = arg;
1206 mtx_assert(&sq->lock, MA_OWNED);
1208 /* check next state */
1209 switch (sq->cev_next_state) {
1210 case MLX5E_CEV_STATE_SEND_NOPS:
1211 /* fill TX ring with NOPs, if any */
1212 mlx5e_sq_send_nops_locked(sq, 0);
1214 /* check if completed */
1215 if (sq->cev_counter == 0) {
1216 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1221 /* send NOPs on next timeout */
1222 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1227 callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1231 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1234 mtx_lock(&sq->lock);
1235 /* teardown event factor timer, if any */
1236 sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1237 callout_stop(&sq->cev_callout);
1239 /* send dummy NOPs in order to flush the transmit ring */
1240 mlx5e_sq_send_nops_locked(sq, 1);
1241 mtx_unlock(&sq->lock);
1243 /* make sure it is safe to free the callout */
1244 callout_drain(&sq->cev_callout);
1246 /* error out remaining requests */
1247 mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1249 /* wait till SQ is empty */
1250 mtx_lock(&sq->lock);
1251 while (sq->cc != sq->pc) {
1252 mtx_unlock(&sq->lock);
1254 sq->cq.mcq.comp(&sq->cq.mcq);
1255 mtx_lock(&sq->lock);
1257 mtx_unlock(&sq->lock);
1259 mlx5e_disable_sq(sq);
1260 mlx5e_destroy_sq(sq);
1264 mlx5e_create_cq(struct mlx5e_channel *c,
1265 struct mlx5e_cq_param *param,
1266 struct mlx5e_cq *cq,
1267 mlx5e_cq_comp_t *comp)
1269 struct mlx5e_priv *priv = c->priv;
1270 struct mlx5_core_dev *mdev = priv->mdev;
1271 struct mlx5_core_cq *mcq = &cq->mcq;
1277 param->wq.buf_numa_node = 0;
1278 param->wq.db_numa_node = 0;
1279 param->eq_ix = c->ix;
1281 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1286 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1289 mcq->set_ci_db = cq->wq_ctrl.db.db;
1290 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1291 *mcq->set_ci_db = 0;
1293 mcq->vector = param->eq_ix;
1295 mcq->event = mlx5e_cq_error_event;
1297 mcq->uar = &priv->cq_uar;
1299 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1300 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1311 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1313 mlx5_wq_destroy(&cq->wq_ctrl);
1317 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param,
1320 struct mlx5e_channel *c = cq->channel;
1321 struct mlx5e_priv *priv = c->priv;
1322 struct mlx5_core_dev *mdev = priv->mdev;
1323 struct mlx5_core_cq *mcq = &cq->mcq;
1331 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1332 sizeof(u64) * cq->wq_ctrl.buf.npages;
1333 in = mlx5_vzalloc(inlen);
1337 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1339 memcpy(cqc, param->cqc, sizeof(param->cqc));
1341 mlx5_fill_page_array(&cq->wq_ctrl.buf,
1342 (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1344 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1346 MLX5_SET(cqc, cqc, cq_period_mode, moderation_mode);
1347 MLX5_SET(cqc, cqc, c_eqn, eqn);
1348 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1349 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1351 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1353 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1366 mlx5e_disable_cq(struct mlx5e_cq *cq)
1368 struct mlx5e_channel *c = cq->channel;
1369 struct mlx5e_priv *priv = c->priv;
1370 struct mlx5_core_dev *mdev = priv->mdev;
1372 mlx5_core_destroy_cq(mdev, &cq->mcq);
1376 mlx5e_open_cq(struct mlx5e_channel *c,
1377 struct mlx5e_cq_param *param,
1378 struct mlx5e_cq *cq,
1379 mlx5e_cq_comp_t *comp,
1384 err = mlx5e_create_cq(c, param, cq, comp);
1388 err = mlx5e_enable_cq(cq, param, moderation_mode);
1390 goto err_destroy_cq;
1395 mlx5e_destroy_cq(cq);
1401 mlx5e_close_cq(struct mlx5e_cq *cq)
1403 mlx5e_disable_cq(cq);
1404 mlx5e_destroy_cq(cq);
1408 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1409 struct mlx5e_channel_param *cparam)
1411 u8 tx_moderation_mode;
1415 switch (c->priv->params.tx_cq_moderation_mode) {
1417 tx_moderation_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1420 if (MLX5_CAP_GEN(c->priv->mdev, cq_period_start_from_cqe))
1421 tx_moderation_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
1423 tx_moderation_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1426 for (tc = 0; tc < c->num_tc; tc++) {
1427 /* open completion queue */
1428 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
1429 &mlx5e_tx_cq_comp, tx_moderation_mode);
1431 goto err_close_tx_cqs;
1436 for (tc--; tc >= 0; tc--)
1437 mlx5e_close_cq(&c->sq[tc].cq);
1443 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1447 for (tc = 0; tc < c->num_tc; tc++)
1448 mlx5e_close_cq(&c->sq[tc].cq);
1452 mlx5e_open_sqs(struct mlx5e_channel *c,
1453 struct mlx5e_channel_param *cparam)
1458 for (tc = 0; tc < c->num_tc; tc++) {
1459 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1467 for (tc--; tc >= 0; tc--)
1468 mlx5e_close_sq_wait(&c->sq[tc]);
1474 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
1478 for (tc = 0; tc < c->num_tc; tc++)
1479 mlx5e_close_sq_wait(&c->sq[tc]);
1483 mlx5e_chan_mtx_init(struct mlx5e_channel *c)
1487 mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
1489 for (tc = 0; tc < c->num_tc; tc++) {
1490 struct mlx5e_sq *sq = c->sq + tc;
1492 mtx_init(&sq->lock, "mlx5tx", MTX_NETWORK_LOCK, MTX_DEF);
1493 mtx_init(&sq->comp_lock, "mlx5comp", MTX_NETWORK_LOCK,
1496 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
1498 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1500 /* ensure the TX completion event factor is not zero */
1501 if (sq->cev_factor == 0)
1507 mlx5e_chan_mtx_destroy(struct mlx5e_channel *c)
1511 mtx_destroy(&c->rq.mtx);
1513 for (tc = 0; tc < c->num_tc; tc++) {
1514 mtx_destroy(&c->sq[tc].lock);
1515 mtx_destroy(&c->sq[tc].comp_lock);
1520 mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1521 struct mlx5e_channel_param *cparam,
1522 struct mlx5e_channel *volatile *cp)
1524 struct mlx5e_channel *c;
1525 u8 rx_moderation_mode;
1528 c = malloc(sizeof(*c), M_MLX5EN, M_WAITOK | M_ZERO);
1535 c->pdev = &priv->mdev->pdev->dev;
1537 c->mkey_be = cpu_to_be32(priv->mr.key);
1538 c->num_tc = priv->num_tc;
1541 mlx5e_chan_mtx_init(c);
1543 /* open transmit completion queue */
1544 err = mlx5e_open_tx_cqs(c, cparam);
1548 switch (priv->params.rx_cq_moderation_mode) {
1550 rx_moderation_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1553 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1554 rx_moderation_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
1556 rx_moderation_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1560 /* open receive completion queue */
1561 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1562 &mlx5e_rx_cq_comp, rx_moderation_mode);
1564 goto err_close_tx_cqs;
1566 err = mlx5e_open_sqs(c, cparam);
1568 goto err_close_rx_cq;
1570 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1574 /* store channel pointer */
1577 /* poll receive queue initially */
1578 c->rq.cq.mcq.comp(&c->rq.cq.mcq);
1583 mlx5e_close_sqs_wait(c);
1586 mlx5e_close_cq(&c->rq.cq);
1589 mlx5e_close_tx_cqs(c);
1592 /* destroy mutexes */
1593 mlx5e_chan_mtx_destroy(c);
1599 mlx5e_close_channel(struct mlx5e_channel *volatile *pp)
1601 struct mlx5e_channel *c = *pp;
1603 /* check if channel is already closed */
1606 mlx5e_close_rq(&c->rq);
1610 mlx5e_close_channel_wait(struct mlx5e_channel *volatile *pp)
1612 struct mlx5e_channel *c = *pp;
1614 /* check if channel is already closed */
1617 /* ensure channel pointer is no longer used */
1620 mlx5e_close_rq_wait(&c->rq);
1621 mlx5e_close_sqs_wait(c);
1622 mlx5e_close_cq(&c->rq.cq);
1623 mlx5e_close_tx_cqs(c);
1624 /* destroy mutexes */
1625 mlx5e_chan_mtx_destroy(c);
1630 mlx5e_build_rq_param(struct mlx5e_priv *priv,
1631 struct mlx5e_rq_param *param)
1633 void *rqc = param->rqc;
1634 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1636 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1637 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1638 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1639 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1640 MLX5_SET(wq, wq, pd, priv->pdn);
1642 param->wq.buf_numa_node = 0;
1643 param->wq.db_numa_node = 0;
1644 param->wq.linear = 1;
1648 mlx5e_build_sq_param(struct mlx5e_priv *priv,
1649 struct mlx5e_sq_param *param)
1651 void *sqc = param->sqc;
1652 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1654 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1655 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1656 MLX5_SET(wq, wq, pd, priv->pdn);
1658 param->wq.buf_numa_node = 0;
1659 param->wq.db_numa_node = 0;
1660 param->wq.linear = 1;
1664 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1665 struct mlx5e_cq_param *param)
1667 void *cqc = param->cqc;
1669 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1673 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1674 struct mlx5e_cq_param *param)
1676 void *cqc = param->cqc;
1680 * TODO The sysctl to control on/off is a bool value for now, which means
1681 * we only support CSUM, once HASH is implemnted we'll need to address that.
1683 if (priv->params.cqe_zipping_en) {
1684 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1685 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
1688 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1689 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1690 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1692 mlx5e_build_common_cq_param(priv, param);
1696 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1697 struct mlx5e_cq_param *param)
1699 void *cqc = param->cqc;
1701 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1702 MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
1703 MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
1705 mlx5e_build_common_cq_param(priv, param);
1709 mlx5e_build_channel_param(struct mlx5e_priv *priv,
1710 struct mlx5e_channel_param *cparam)
1712 memset(cparam, 0, sizeof(*cparam));
1714 mlx5e_build_rq_param(priv, &cparam->rq);
1715 mlx5e_build_sq_param(priv, &cparam->sq);
1716 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1717 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1721 mlx5e_open_channels(struct mlx5e_priv *priv)
1723 struct mlx5e_channel_param cparam;
1729 priv->channel = malloc(priv->params.num_channels *
1730 sizeof(struct mlx5e_channel *), M_MLX5EN, M_WAITOK | M_ZERO);
1731 if (priv->channel == NULL)
1734 mlx5e_build_channel_param(priv, &cparam);
1735 for (i = 0; i < priv->params.num_channels; i++) {
1736 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1738 goto err_close_channels;
1741 for (j = 0; j < priv->params.num_channels; j++) {
1742 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1744 goto err_close_channels;
1750 for (i--; i >= 0; i--) {
1751 mlx5e_close_channel(&priv->channel[i]);
1752 mlx5e_close_channel_wait(&priv->channel[i]);
1755 /* remove "volatile" attribute from "channel" pointer */
1756 ptr = __DECONST(void *, priv->channel);
1757 priv->channel = NULL;
1759 free(ptr, M_MLX5EN);
1765 mlx5e_close_channels(struct mlx5e_priv *priv)
1770 if (priv->channel == NULL)
1773 for (i = 0; i < priv->params.num_channels; i++)
1774 mlx5e_close_channel(&priv->channel[i]);
1775 for (i = 0; i < priv->params.num_channels; i++)
1776 mlx5e_close_channel_wait(&priv->channel[i]);
1778 /* remove "volatile" attribute from "channel" pointer */
1779 ptr = __DECONST(void *, priv->channel);
1780 priv->channel = NULL;
1782 free(ptr, M_MLX5EN);
1786 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
1788 return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
1789 priv->params.tx_cq_moderation_usec,
1790 priv->params.tx_cq_moderation_pkts));
1794 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
1796 return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
1797 priv->params.rx_cq_moderation_usec,
1798 priv->params.rx_cq_moderation_pkts));
1802 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1810 err = mlx5e_refresh_rq_params(priv, &c->rq);
1814 for (i = 0; i != c->num_tc; i++) {
1815 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
1824 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
1828 if (priv->channel == NULL)
1831 for (i = 0; i < priv->params.num_channels; i++) {
1834 err = mlx5e_refresh_channel_params_sub(priv, priv->channel[i]);
1842 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
1844 struct mlx5_core_dev *mdev = priv->mdev;
1845 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1846 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1848 memset(in, 0, sizeof(in));
1850 MLX5_SET(tisc, tisc, prio, tc);
1851 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1853 return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
1857 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
1859 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1863 mlx5e_open_tises(struct mlx5e_priv *priv)
1865 int num_tc = priv->num_tc;
1869 for (tc = 0; tc < num_tc; tc++) {
1870 err = mlx5e_open_tis(priv, tc);
1872 goto err_close_tises;
1878 for (tc--; tc >= 0; tc--)
1879 mlx5e_close_tis(priv, tc);
1885 mlx5e_close_tises(struct mlx5e_priv *priv)
1887 int num_tc = priv->num_tc;
1890 for (tc = 0; tc < num_tc; tc++)
1891 mlx5e_close_tis(priv, tc);
1895 mlx5e_open_rqt(struct mlx5e_priv *priv)
1897 struct mlx5_core_dev *mdev = priv->mdev;
1899 u32 out[MLX5_ST_SZ_DW(create_rqt_out)];
1906 sz = 1 << priv->params.rx_hash_log_tbl_sz;
1908 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1909 in = mlx5_vzalloc(inlen);
1912 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1914 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1915 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1917 for (i = 0; i < sz; i++) {
1920 ix = rss_get_indirection_to_bucket(i);
1924 /* ensure we don't overflow */
1925 ix %= priv->params.num_channels;
1926 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix]->rq.rqn);
1929 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1931 memset(out, 0, sizeof(out));
1932 err = mlx5_cmd_exec_check_status(mdev, in, inlen, out, sizeof(out));
1934 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
1942 mlx5e_close_rqt(struct mlx5e_priv *priv)
1944 u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)];
1945 u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)];
1947 memset(in, 0, sizeof(in));
1949 MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
1950 MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
1952 mlx5_cmd_exec_check_status(priv->mdev, in, sizeof(in), out,
1957 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
1959 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1962 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1964 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1966 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
1967 MLX5_HASH_FIELD_SEL_DST_IP)
1969 #define MLX5_HASH_ALL (MLX5_HASH_FIELD_SEL_SRC_IP |\
1970 MLX5_HASH_FIELD_SEL_DST_IP |\
1971 MLX5_HASH_FIELD_SEL_L4_SPORT |\
1972 MLX5_HASH_FIELD_SEL_L4_DPORT)
1974 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
1975 MLX5_HASH_FIELD_SEL_DST_IP |\
1976 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1978 if (priv->params.hw_lro_en) {
1979 MLX5_SET(tirc, tirc, lro_enable_mask,
1980 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1981 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1982 MLX5_SET(tirc, tirc, lro_max_msg_sz,
1983 (priv->params.lro_wqe_sz -
1984 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1985 /* TODO: add the option to choose timer value dynamically */
1986 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1987 MLX5_CAP_ETH(priv->mdev,
1988 lro_timer_supported_periods[2]));
1991 /* setup parameters for hashing TIR type, if any */
1994 MLX5_SET(tirc, tirc, disp_type,
1995 MLX5_TIRC_DISP_TYPE_DIRECT);
1996 MLX5_SET(tirc, tirc, inline_rqn,
1997 priv->channel[0]->rq.rqn);
2000 MLX5_SET(tirc, tirc, disp_type,
2001 MLX5_TIRC_DISP_TYPE_INDIRECT);
2002 MLX5_SET(tirc, tirc, indirect_table,
2004 MLX5_SET(tirc, tirc, rx_hash_fn,
2005 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
2006 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
2009 * The FreeBSD RSS implementation does currently not
2010 * support symmetric Toeplitz hashes:
2012 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
2013 rss_getkey((uint8_t *)hkey);
2015 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2016 hkey[0] = cpu_to_be32(0xD181C62C);
2017 hkey[1] = cpu_to_be32(0xF7F4DB5B);
2018 hkey[2] = cpu_to_be32(0x1983A2FC);
2019 hkey[3] = cpu_to_be32(0x943E1ADB);
2020 hkey[4] = cpu_to_be32(0xD9389E6B);
2021 hkey[5] = cpu_to_be32(0xD1039C2C);
2022 hkey[6] = cpu_to_be32(0xA74499AD);
2023 hkey[7] = cpu_to_be32(0x593D56D9);
2024 hkey[8] = cpu_to_be32(0xF3253C06);
2025 hkey[9] = cpu_to_be32(0x2ADC1FFC);
2031 case MLX5E_TT_IPV4_TCP:
2032 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2033 MLX5_L3_PROT_TYPE_IPV4);
2034 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2035 MLX5_L4_PROT_TYPE_TCP);
2037 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2038 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2042 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2046 case MLX5E_TT_IPV6_TCP:
2047 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2048 MLX5_L3_PROT_TYPE_IPV6);
2049 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2050 MLX5_L4_PROT_TYPE_TCP);
2052 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2053 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2057 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2061 case MLX5E_TT_IPV4_UDP:
2062 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2063 MLX5_L3_PROT_TYPE_IPV4);
2064 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2065 MLX5_L4_PROT_TYPE_UDP);
2067 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2068 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2072 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2076 case MLX5E_TT_IPV6_UDP:
2077 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2078 MLX5_L3_PROT_TYPE_IPV6);
2079 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2080 MLX5_L4_PROT_TYPE_UDP);
2082 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2083 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2087 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2091 case MLX5E_TT_IPV4_IPSEC_AH:
2092 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2093 MLX5_L3_PROT_TYPE_IPV4);
2094 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2095 MLX5_HASH_IP_IPSEC_SPI);
2098 case MLX5E_TT_IPV6_IPSEC_AH:
2099 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2100 MLX5_L3_PROT_TYPE_IPV6);
2101 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2102 MLX5_HASH_IP_IPSEC_SPI);
2105 case MLX5E_TT_IPV4_IPSEC_ESP:
2106 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2107 MLX5_L3_PROT_TYPE_IPV4);
2108 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2109 MLX5_HASH_IP_IPSEC_SPI);
2112 case MLX5E_TT_IPV6_IPSEC_ESP:
2113 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2114 MLX5_L3_PROT_TYPE_IPV6);
2115 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2116 MLX5_HASH_IP_IPSEC_SPI);
2120 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2121 MLX5_L3_PROT_TYPE_IPV4);
2122 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2127 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2128 MLX5_L3_PROT_TYPE_IPV6);
2129 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2139 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2141 struct mlx5_core_dev *mdev = priv->mdev;
2147 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2148 in = mlx5_vzalloc(inlen);
2151 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2153 mlx5e_build_tir_ctx(priv, tirc, tt);
2155 err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2163 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2165 mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2169 mlx5e_open_tirs(struct mlx5e_priv *priv)
2174 for (i = 0; i < MLX5E_NUM_TT; i++) {
2175 err = mlx5e_open_tir(priv, i);
2177 goto err_close_tirs;
2183 for (i--; i >= 0; i--)
2184 mlx5e_close_tir(priv, i);
2190 mlx5e_close_tirs(struct mlx5e_priv *priv)
2194 for (i = 0; i < MLX5E_NUM_TT; i++)
2195 mlx5e_close_tir(priv, i);
2199 * SW MTU does not include headers,
2200 * HW MTU includes all headers and checksums.
2203 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2205 struct mlx5e_priv *priv = ifp->if_softc;
2206 struct mlx5_core_dev *mdev = priv->mdev;
2211 err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(sw_mtu));
2213 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n",
2214 __func__, sw_mtu, err);
2217 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2219 ifp->if_mtu = MLX5E_HW2SW_MTU(hw_mtu);
2221 if (ifp->if_mtu != sw_mtu) {
2222 if_printf(ifp, "Port MTU %d is different than "
2223 "ifp mtu %d\n", sw_mtu, (int)ifp->if_mtu);
2226 if_printf(ifp, "Query port MTU, after setting new "
2227 "MTU value, failed\n");
2228 ifp->if_mtu = sw_mtu;
2234 mlx5e_open_locked(struct ifnet *ifp)
2236 struct mlx5e_priv *priv = ifp->if_softc;
2240 /* check if already opened */
2241 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2245 if (rss_getnumbuckets() > priv->params.num_channels) {
2246 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than "
2247 "channels(%u) available\n", rss_getnumbuckets(),
2248 priv->params.num_channels);
2251 err = mlx5e_open_tises(priv);
2253 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n",
2257 err = mlx5_vport_alloc_q_counter(priv->mdev,
2258 MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
2260 if_printf(priv->ifp,
2261 "%s: mlx5_vport_alloc_q_counter failed: %d\n",
2263 goto err_close_tises;
2265 /* store counter set ID */
2266 priv->counter_set_id = set_id;
2268 err = mlx5e_open_channels(priv);
2270 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n",
2272 goto err_dalloc_q_counter;
2274 err = mlx5e_open_rqt(priv);
2276 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n",
2278 goto err_close_channels;
2280 err = mlx5e_open_tirs(priv);
2282 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n",
2284 goto err_close_rqls;
2286 err = mlx5e_open_flow_table(priv);
2288 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n",
2290 goto err_close_tirs;
2292 err = mlx5e_add_all_vlan_rules(priv);
2294 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
2296 goto err_close_flow_table;
2298 set_bit(MLX5E_STATE_OPENED, &priv->state);
2300 mlx5e_update_carrier(priv);
2301 mlx5e_set_rx_mode_core(priv);
2305 err_close_flow_table:
2306 mlx5e_close_flow_table(priv);
2309 mlx5e_close_tirs(priv);
2312 mlx5e_close_rqt(priv);
2315 mlx5e_close_channels(priv);
2317 err_dalloc_q_counter:
2318 mlx5_vport_dealloc_q_counter(priv->mdev,
2319 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2322 mlx5e_close_tises(priv);
2328 mlx5e_open(void *arg)
2330 struct mlx5e_priv *priv = arg;
2333 if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
2334 if_printf(priv->ifp,
2335 "%s: Setting port status to up failed\n",
2338 mlx5e_open_locked(priv->ifp);
2339 priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
2344 mlx5e_close_locked(struct ifnet *ifp)
2346 struct mlx5e_priv *priv = ifp->if_softc;
2348 /* check if already closed */
2349 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2352 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2354 mlx5e_set_rx_mode_core(priv);
2355 mlx5e_del_all_vlan_rules(priv);
2356 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
2357 mlx5e_close_flow_table(priv);
2358 mlx5e_close_tirs(priv);
2359 mlx5e_close_rqt(priv);
2360 mlx5e_close_channels(priv);
2361 mlx5_vport_dealloc_q_counter(priv->mdev,
2362 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2363 mlx5e_close_tises(priv);
2368 #if (__FreeBSD_version >= 1100000)
2370 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
2372 struct mlx5e_priv *priv = ifp->if_softc;
2375 /* PRIV_LOCK(priv); XXX not allowed */
2377 case IFCOUNTER_IPACKETS:
2378 retval = priv->stats.vport.rx_packets;
2380 case IFCOUNTER_IERRORS:
2381 retval = priv->stats.vport.rx_error_packets;
2383 case IFCOUNTER_IQDROPS:
2384 retval = priv->stats.vport.rx_out_of_buffer;
2386 case IFCOUNTER_OPACKETS:
2387 retval = priv->stats.vport.tx_packets;
2389 case IFCOUNTER_OERRORS:
2390 retval = priv->stats.vport.tx_error_packets;
2392 case IFCOUNTER_IBYTES:
2393 retval = priv->stats.vport.rx_bytes;
2395 case IFCOUNTER_OBYTES:
2396 retval = priv->stats.vport.tx_bytes;
2398 case IFCOUNTER_IMCASTS:
2399 retval = priv->stats.vport.rx_multicast_packets;
2401 case IFCOUNTER_OMCASTS:
2402 retval = priv->stats.vport.tx_multicast_packets;
2404 case IFCOUNTER_OQDROPS:
2405 retval = priv->stats.vport.tx_queue_dropped;
2408 retval = if_get_counter_default(ifp, cnt);
2411 /* PRIV_UNLOCK(priv); XXX not allowed */
2417 mlx5e_set_rx_mode(struct ifnet *ifp)
2419 struct mlx5e_priv *priv = ifp->if_softc;
2421 schedule_work(&priv->set_rx_mode_work);
2425 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2427 struct mlx5e_priv *priv;
2429 struct ifi2creq i2c;
2437 priv = ifp->if_softc;
2439 /* check if detaching */
2440 if (priv == NULL || priv->gone != 0)
2445 ifr = (struct ifreq *)data;
2448 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
2450 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
2451 ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
2454 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2456 mlx5e_close_locked(ifp);
2459 mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
2462 mlx5e_open_locked(ifp);
2465 if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n",
2466 MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
2471 if ((ifp->if_flags & IFF_UP) &&
2472 (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2473 mlx5e_set_rx_mode(ifp);
2477 if (ifp->if_flags & IFF_UP) {
2478 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2479 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2480 mlx5e_open_locked(ifp);
2481 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2482 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
2485 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2486 mlx5_set_port_status(priv->mdev,
2488 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2489 mlx5e_close_locked(ifp);
2490 mlx5e_update_carrier(priv);
2491 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2498 mlx5e_set_rx_mode(ifp);
2503 ifr = (struct ifreq *)data;
2504 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
2507 ifr = (struct ifreq *)data;
2509 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2511 if (mask & IFCAP_TXCSUM) {
2512 ifp->if_capenable ^= IFCAP_TXCSUM;
2513 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2515 if (IFCAP_TSO4 & ifp->if_capenable &&
2516 !(IFCAP_TXCSUM & ifp->if_capenable)) {
2517 ifp->if_capenable &= ~IFCAP_TSO4;
2518 ifp->if_hwassist &= ~CSUM_IP_TSO;
2520 "tso4 disabled due to -txcsum.\n");
2523 if (mask & IFCAP_TXCSUM_IPV6) {
2524 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
2525 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2527 if (IFCAP_TSO6 & ifp->if_capenable &&
2528 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2529 ifp->if_capenable &= ~IFCAP_TSO6;
2530 ifp->if_hwassist &= ~CSUM_IP6_TSO;
2532 "tso6 disabled due to -txcsum6.\n");
2535 if (mask & IFCAP_RXCSUM)
2536 ifp->if_capenable ^= IFCAP_RXCSUM;
2537 if (mask & IFCAP_RXCSUM_IPV6)
2538 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
2539 if (mask & IFCAP_TSO4) {
2540 if (!(IFCAP_TSO4 & ifp->if_capenable) &&
2541 !(IFCAP_TXCSUM & ifp->if_capenable)) {
2542 if_printf(ifp, "enable txcsum first.\n");
2546 ifp->if_capenable ^= IFCAP_TSO4;
2547 ifp->if_hwassist ^= CSUM_IP_TSO;
2549 if (mask & IFCAP_TSO6) {
2550 if (!(IFCAP_TSO6 & ifp->if_capenable) &&
2551 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2552 if_printf(ifp, "enable txcsum6 first.\n");
2556 ifp->if_capenable ^= IFCAP_TSO6;
2557 ifp->if_hwassist ^= CSUM_IP6_TSO;
2559 if (mask & IFCAP_VLAN_HWFILTER) {
2560 if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
2561 mlx5e_disable_vlan_filter(priv);
2563 mlx5e_enable_vlan_filter(priv);
2565 ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
2567 if (mask & IFCAP_VLAN_HWTAGGING)
2568 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2569 if (mask & IFCAP_WOL_MAGIC)
2570 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2572 VLAN_CAPABILITIES(ifp);
2573 /* turn off LRO means also turn of HW LRO - if it's on */
2574 if (mask & IFCAP_LRO) {
2575 int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2576 bool need_restart = false;
2578 ifp->if_capenable ^= IFCAP_LRO;
2579 if (!(ifp->if_capenable & IFCAP_LRO)) {
2580 if (priv->params.hw_lro_en) {
2581 priv->params.hw_lro_en = false;
2582 need_restart = true;
2583 /* Not sure this is the correct way */
2584 priv->params_ethtool.hw_lro = priv->params.hw_lro_en;
2587 if (was_opened && need_restart) {
2588 mlx5e_close_locked(ifp);
2589 mlx5e_open_locked(ifp);
2597 ifr = (struct ifreq *)data;
2600 * Copy from the user-space address ifr_data to the
2601 * kernel-space address i2c
2603 error = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
2607 if (i2c.len > sizeof(i2c.data)) {
2613 /* Get module_num which is required for the query_eeprom */
2614 error = mlx5_query_module_num(priv->mdev, &module_num);
2616 if_printf(ifp, "Query module num failed, eeprom "
2617 "reading is not supported\n");
2621 /* Check if module is present before doing an access */
2622 if (mlx5_query_module_status(priv->mdev, module_num) !=
2623 MLX5_MODULE_STATUS_PLUGGED) {
2628 * Currently 0XA0 and 0xA2 are the only addresses permitted.
2629 * The internal conversion is as follows:
2631 if (i2c.dev_addr == 0xA0)
2632 read_addr = MLX5E_I2C_ADDR_LOW;
2633 else if (i2c.dev_addr == 0xA2)
2634 read_addr = MLX5E_I2C_ADDR_HIGH;
2636 if_printf(ifp, "Query eeprom failed, "
2637 "Invalid Address: %X\n", i2c.dev_addr);
2641 error = mlx5_query_eeprom(priv->mdev,
2642 read_addr, MLX5E_EEPROM_LOW_PAGE,
2643 (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
2644 (uint32_t *)i2c.data, &size_read);
2646 if_printf(ifp, "Query eeprom failed, eeprom "
2647 "reading is not supported\n");
2652 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
2653 error = mlx5_query_eeprom(priv->mdev,
2654 read_addr, MLX5E_EEPROM_LOW_PAGE,
2655 (uint32_t)(i2c.offset + size_read),
2656 (uint32_t)(i2c.len - size_read), module_num,
2657 (uint32_t *)(i2c.data + size_read), &size_read);
2660 if_printf(ifp, "Query eeprom failed, eeprom "
2661 "reading is not supported\n");
2666 error = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
2672 error = ether_ioctl(ifp, command, data);
2679 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2682 * TODO: uncoment once FW really sets all these bits if
2683 * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
2684 * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
2685 * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
2689 /* TODO: add more must-to-have features */
2695 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
2696 struct mlx5e_priv *priv,
2697 int num_comp_vectors)
2700 * TODO: Consider link speed for setting "log_sq_size",
2701 * "log_rq_size" and "cq_moderation_xxx":
2703 priv->params.log_sq_size =
2704 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2705 priv->params.log_rq_size =
2706 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2707 priv->params.rx_cq_moderation_usec =
2708 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
2709 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
2710 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2711 priv->params.rx_cq_moderation_mode =
2712 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
2713 priv->params.rx_cq_moderation_pkts =
2714 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2715 priv->params.tx_cq_moderation_usec =
2716 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2717 priv->params.tx_cq_moderation_pkts =
2718 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2719 priv->params.min_rx_wqes =
2720 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
2721 priv->params.rx_hash_log_tbl_sz =
2722 (order_base_2(num_comp_vectors) >
2723 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
2724 order_base_2(num_comp_vectors) :
2725 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
2726 priv->params.num_tc = 1;
2727 priv->params.default_vlan_prio = 0;
2728 priv->counter_set_id = -1;
2731 * hw lro is currently defaulted to off. when it won't anymore we
2732 * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
2734 priv->params.hw_lro_en = false;
2735 priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2737 priv->params.cqe_zipping_en = !!MLX5_CAP_GEN(mdev, cqe_compression);
2740 priv->params.num_channels = num_comp_vectors;
2741 priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
2742 priv->queue_mapping_channel_mask =
2743 roundup_pow_of_two(num_comp_vectors) - 1;
2744 priv->num_tc = priv->params.num_tc;
2745 priv->default_vlan_prio = priv->params.default_vlan_prio;
2747 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2748 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2749 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2753 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2754 struct mlx5_core_mr *mr)
2756 struct ifnet *ifp = priv->ifp;
2757 struct mlx5_core_dev *mdev = priv->mdev;
2758 struct mlx5_create_mkey_mbox_in *in;
2761 in = mlx5_vzalloc(sizeof(*in));
2763 if_printf(ifp, "%s: failed to allocate inbox\n", __func__);
2766 in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2767 MLX5_PERM_LOCAL_READ |
2768 MLX5_ACCESS_MODE_PA;
2769 in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2770 in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2772 err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL,
2775 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n",
2783 static const char *mlx5e_vport_stats_desc[] = {
2784 MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
2787 static const char *mlx5e_pport_stats_desc[] = {
2788 MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
2792 mlx5e_priv_mtx_init(struct mlx5e_priv *priv)
2794 mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
2795 sx_init(&priv->state_lock, "mlx5state");
2796 callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
2800 mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv)
2802 mtx_destroy(&priv->async_events_mtx);
2803 sx_destroy(&priv->state_lock);
2807 sysctl_firmware(SYSCTL_HANDLER_ARGS)
2810 * %d.%d%.d the string format.
2811 * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
2812 * We need at most 5 chars to store that.
2813 * It also has: two "." and NULL at the end, which means we need 18
2814 * (5*3 + 3) chars at most.
2817 struct mlx5e_priv *priv = arg1;
2820 snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
2821 fw_rev_sub(priv->mdev));
2822 error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
2827 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
2829 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
2830 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
2831 sysctl_firmware, "A", "HCA firmware version");
2833 SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
2834 OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
2839 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
2841 #if (__FreeBSD_version < 1100000)
2845 /* Only receiving pauseframes is enabled by default */
2846 priv->params.tx_pauseframe_control = 0;
2847 priv->params.rx_pauseframe_control = 1;
2849 #if (__FreeBSD_version < 1100000)
2850 /* compute path for sysctl */
2851 snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
2852 device_get_unit(priv->mdev->pdev->dev.bsddev));
2854 /* try to fetch tunable, if any */
2855 TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
2857 /* compute path for sysctl */
2858 snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
2859 device_get_unit(priv->mdev->pdev->dev.bsddev));
2861 /* try to fetch tunable, if any */
2862 TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
2865 /* register pausframe SYSCTLs */
2866 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2867 OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
2868 &priv->params.tx_pauseframe_control, 0,
2869 "Set to enable TX pause frames. Clear to disable.");
2871 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2872 OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
2873 &priv->params.rx_pauseframe_control, 0,
2874 "Set to enable RX pause frames. Clear to disable.");
2877 priv->params.tx_pauseframe_control =
2878 priv->params.tx_pauseframe_control ? 1 : 0;
2879 priv->params.rx_pauseframe_control =
2880 priv->params.rx_pauseframe_control ? 1 : 0;
2882 /* update firmware */
2883 mlx5_set_port_pause(priv->mdev, 1,
2884 priv->params.rx_pauseframe_control,
2885 priv->params.tx_pauseframe_control);
2889 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
2891 static volatile int mlx5_en_unit;
2893 struct mlx5e_priv *priv;
2894 u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
2895 struct sysctl_oid_list *child;
2896 int ncv = mdev->priv.eq_table.num_comp_vectors;
2902 if (mlx5e_check_required_hca_cap(mdev)) {
2903 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
2906 priv = malloc(sizeof(*priv), M_MLX5EN, M_WAITOK | M_ZERO);
2908 mlx5_core_err(mdev, "malloc() failed\n");
2911 mlx5e_priv_mtx_init(priv);
2913 ifp = priv->ifp = if_alloc(IFT_ETHER);
2915 mlx5_core_err(mdev, "if_alloc() failed\n");
2918 ifp->if_softc = priv;
2919 if_initname(ifp, "mce", atomic_fetchadd_int(&mlx5_en_unit, 1));
2920 ifp->if_mtu = ETHERMTU;
2921 ifp->if_init = mlx5e_open;
2922 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2923 ifp->if_ioctl = mlx5e_ioctl;
2924 ifp->if_transmit = mlx5e_xmit;
2925 ifp->if_qflush = if_qflush;
2926 #if (__FreeBSD_version >= 1100000)
2927 ifp->if_get_counter = mlx5e_get_counter;
2929 ifp->if_snd.ifq_maxlen = ifqmaxlen;
2931 * Set driver features
2933 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
2934 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
2935 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
2936 ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
2937 ifp->if_capabilities |= IFCAP_LRO;
2938 ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
2940 /* set TSO limits so that we don't have to drop TX packets */
2941 ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
2942 ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
2943 ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
2945 ifp->if_capenable = ifp->if_capabilities;
2946 ifp->if_hwassist = 0;
2947 if (ifp->if_capenable & IFCAP_TSO)
2948 ifp->if_hwassist |= CSUM_TSO;
2949 if (ifp->if_capenable & IFCAP_TXCSUM)
2950 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2951 if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
2952 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2954 /* ifnet sysctl tree */
2955 sysctl_ctx_init(&priv->sysctl_ctx);
2956 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
2957 OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
2958 if (priv->sysctl_ifnet == NULL) {
2959 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
2960 goto err_free_sysctl;
2962 snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
2963 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2964 OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
2965 if (priv->sysctl_ifnet == NULL) {
2966 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
2967 goto err_free_sysctl;
2970 /* HW sysctl tree */
2971 child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
2972 priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
2973 OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
2974 if (priv->sysctl_hw == NULL) {
2975 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
2976 goto err_free_sysctl;
2978 mlx5e_build_ifp_priv(mdev, priv, ncv);
2979 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
2981 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n",
2983 goto err_free_sysctl;
2985 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2987 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n",
2989 goto err_unmap_free_uar;
2991 err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
2993 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n",
2995 goto err_dealloc_pd;
2997 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
2999 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n",
3001 goto err_dealloc_transport_domain;
3003 mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
3005 /* check if we should generate a random MAC address */
3006 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
3007 is_zero_ether_addr(dev_addr)) {
3008 random_ether_addr(dev_addr);
3009 if_printf(ifp, "Assigned random MAC address\n");
3012 /* set default MTU */
3013 mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
3016 device_set_desc(mdev->pdev->dev.bsddev, mlx5e_version);
3018 /* Set default media status */
3019 priv->media_status_last = IFM_AVALID;
3020 priv->media_active_last = IFM_ETHER | IFM_AUTO |
3021 IFM_ETH_RXPAUSE | IFM_FDX;
3023 /* setup default pauseframes configuration */
3024 mlx5e_setup_pauseframes(priv);
3026 err = mlx5_query_port_proto_cap(mdev, ð_proto_cap, MLX5_PTYS_EN);
3029 if_printf(ifp, "%s: Query port media capability failed, %d\n",
3033 /* Setup supported medias */
3034 ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
3035 mlx5e_media_change, mlx5e_media_status);
3037 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
3038 if (mlx5e_mode_table[i].baudrate == 0)
3040 if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
3041 ifmedia_add(&priv->media,
3042 mlx5e_mode_table[i].subtype |
3043 IFM_ETHER, 0, NULL);
3044 ifmedia_add(&priv->media,
3045 mlx5e_mode_table[i].subtype |
3046 IFM_ETHER | IFM_FDX |
3047 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3051 ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
3052 ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3053 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3055 /* Set autoselect by default */
3056 ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3057 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
3058 ether_ifattach(ifp, dev_addr);
3060 /* Register for VLAN events */
3061 priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
3062 mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
3063 priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
3064 mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
3066 /* Link is down by default */
3067 if_link_state_change(ifp, LINK_STATE_DOWN);
3069 mlx5e_enable_async_events(priv);
3071 mlx5e_add_hw_stats(priv);
3073 mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3074 "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
3075 priv->stats.vport.arg);
3077 mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3078 "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
3079 priv->stats.pport.arg);
3081 mlx5e_create_ethtool(priv);
3083 mtx_lock(&priv->async_events_mtx);
3084 mlx5e_update_stats(priv);
3085 mtx_unlock(&priv->async_events_mtx);
3089 err_dealloc_transport_domain:
3090 mlx5_dealloc_transport_domain(mdev, priv->tdn);
3093 mlx5_core_dealloc_pd(mdev, priv->pdn);
3096 mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3099 sysctl_ctx_free(&priv->sysctl_ctx);
3104 mlx5e_priv_mtx_destroy(priv);
3105 free(priv, M_MLX5EN);
3110 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
3112 struct mlx5e_priv *priv = vpriv;
3113 struct ifnet *ifp = priv->ifp;
3115 /* don't allow more IOCTLs */
3119 * Clear the device description to avoid use after free,
3120 * because the bsddev is not destroyed when this module is
3123 device_set_desc(mdev->pdev->dev.bsddev, NULL);
3125 /* XXX wait a bit to allow IOCTL handlers to complete */
3128 /* stop watchdog timer */
3129 callout_drain(&priv->watchdog);
3131 if (priv->vlan_attach != NULL)
3132 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
3133 if (priv->vlan_detach != NULL)
3134 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
3136 /* make sure device gets closed */
3138 mlx5e_close_locked(ifp);
3141 /* unregister device */
3142 ifmedia_removeall(&priv->media);
3143 ether_ifdetach(ifp);
3146 /* destroy all remaining sysctl nodes */
3147 if (priv->sysctl_debug)
3148 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
3149 sysctl_ctx_free(&priv->stats.vport.ctx);
3150 sysctl_ctx_free(&priv->stats.pport.ctx);
3151 sysctl_ctx_free(&priv->sysctl_ctx);
3153 mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
3154 mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
3155 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3156 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
3157 mlx5e_disable_async_events(priv);
3158 flush_scheduled_work();
3159 mlx5e_priv_mtx_destroy(priv);
3160 free(priv, M_MLX5EN);
3164 mlx5e_get_ifp(void *vpriv)
3166 struct mlx5e_priv *priv = vpriv;
3171 static struct mlx5_interface mlx5e_interface = {
3172 .add = mlx5e_create_ifp,
3173 .remove = mlx5e_destroy_ifp,
3174 .event = mlx5e_async_event,
3175 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3176 .get_dev = mlx5e_get_ifp,
3182 mlx5_register_interface(&mlx5e_interface);
3188 mlx5_unregister_interface(&mlx5e_interface);
3191 module_init_order(mlx5e_init, SI_ORDER_THIRD);
3192 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
3194 #if (__FreeBSD_version >= 1100000)
3195 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
3197 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
3198 MODULE_VERSION(mlx5en, 1);