sys/dev/mlx5/mlx5_en/mlx5_en_main.c

   1 /*-
   2  * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include "en.h"
  29
  30 #include <sys/sockio.h>
  31 #include <machine/atomic.h>
  32
  33 #ifndef ETH_DRIVER_VERSION
  34 #define ETH_DRIVER_VERSION      "3.5.0"
  35 #endif
  36 #define DRIVER_RELDATE  "November 2018"
  37
  38 static const char mlx5e_version[] = "mlx5en: Mellanox Ethernet driver "
  39         ETH_DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
  40
  41 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs);
  42
  43 struct mlx5e_channel_param {
  44         struct mlx5e_rq_param rq;
  45         struct mlx5e_sq_param sq;
  46         struct mlx5e_cq_param rx_cq;
  47         struct mlx5e_cq_param tx_cq;
  48 };
  49
  50 static const struct {
  51         u32     subtype;
  52         u64     baudrate;
  53 }       mlx5e_mode_table[MLX5E_LINK_MODES_NUMBER] = {
  54
  55         [MLX5E_1000BASE_CX_SGMII] = {
  56                 .subtype = IFM_1000_CX_SGMII,
  57                 .baudrate = IF_Mbps(1000ULL),
  58         },
  59         [MLX5E_1000BASE_KX] = {
  60                 .subtype = IFM_1000_KX,
  61                 .baudrate = IF_Mbps(1000ULL),
  62         },
  63         [MLX5E_10GBASE_CX4] = {
  64                 .subtype = IFM_10G_CX4,
  65                 .baudrate = IF_Gbps(10ULL),
  66         },
  67         [MLX5E_10GBASE_KX4] = {
  68                 .subtype = IFM_10G_KX4,
  69                 .baudrate = IF_Gbps(10ULL),
  70         },
  71         [MLX5E_10GBASE_KR] = {
  72                 .subtype = IFM_10G_KR,
  73                 .baudrate = IF_Gbps(10ULL),
  74         },
  75         [MLX5E_20GBASE_KR2] = {
  76                 .subtype = IFM_20G_KR2,
  77                 .baudrate = IF_Gbps(20ULL),
  78         },
  79         [MLX5E_40GBASE_CR4] = {
  80                 .subtype = IFM_40G_CR4,
  81                 .baudrate = IF_Gbps(40ULL),
  82         },
  83         [MLX5E_40GBASE_KR4] = {
  84                 .subtype = IFM_40G_KR4,
  85                 .baudrate = IF_Gbps(40ULL),
  86         },
  87         [MLX5E_56GBASE_R4] = {
  88                 .subtype = IFM_56G_R4,
  89                 .baudrate = IF_Gbps(56ULL),
  90         },
  91         [MLX5E_10GBASE_CR] = {
  92                 .subtype = IFM_10G_CR1,
  93                 .baudrate = IF_Gbps(10ULL),
  94         },
  95         [MLX5E_10GBASE_SR] = {
  96                 .subtype = IFM_10G_SR,
  97                 .baudrate = IF_Gbps(10ULL),
  98         },
  99         [MLX5E_10GBASE_ER] = {
 100                 .subtype = IFM_10G_ER,
 101                 .baudrate = IF_Gbps(10ULL),
 102         },
 103         [MLX5E_40GBASE_SR4] = {
 104                 .subtype = IFM_40G_SR4,
 105                 .baudrate = IF_Gbps(40ULL),
 106         },
 107         [MLX5E_40GBASE_LR4] = {
 108                 .subtype = IFM_40G_LR4,
 109                 .baudrate = IF_Gbps(40ULL),
 110         },
 111         [MLX5E_100GBASE_CR4] = {
 112                 .subtype = IFM_100G_CR4,
 113                 .baudrate = IF_Gbps(100ULL),
 114         },
 115         [MLX5E_100GBASE_SR4] = {
 116                 .subtype = IFM_100G_SR4,
 117                 .baudrate = IF_Gbps(100ULL),
 118         },
 119         [MLX5E_100GBASE_KR4] = {
 120                 .subtype = IFM_100G_KR4,
 121                 .baudrate = IF_Gbps(100ULL),
 122         },
 123         [MLX5E_100GBASE_LR4] = {
 124                 .subtype = IFM_100G_LR4,
 125                 .baudrate = IF_Gbps(100ULL),
 126         },
 127         [MLX5E_100BASE_TX] = {
 128                 .subtype = IFM_100_TX,
 129                 .baudrate = IF_Mbps(100ULL),
 130         },
 131         [MLX5E_1000BASE_T] = {
 132                 .subtype = IFM_1000_T,
 133                 .baudrate = IF_Mbps(1000ULL),
 134         },
 135         [MLX5E_10GBASE_T] = {
 136                 .subtype = IFM_10G_T,
 137                 .baudrate = IF_Gbps(10ULL),
 138         },
 139         [MLX5E_25GBASE_CR] = {
 140                 .subtype = IFM_25G_CR,
 141                 .baudrate = IF_Gbps(25ULL),
 142         },
 143         [MLX5E_25GBASE_KR] = {
 144                 .subtype = IFM_25G_KR,
 145                 .baudrate = IF_Gbps(25ULL),
 146         },
 147         [MLX5E_25GBASE_SR] = {
 148                 .subtype = IFM_25G_SR,
 149                 .baudrate = IF_Gbps(25ULL),
 150         },
 151         [MLX5E_50GBASE_CR2] = {
 152                 .subtype = IFM_50G_CR2,
 153                 .baudrate = IF_Gbps(50ULL),
 154         },
 155         [MLX5E_50GBASE_KR2] = {
 156                 .subtype = IFM_50G_KR2,
 157                 .baudrate = IF_Gbps(50ULL),
 158         },
 159 };
 160
 161 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
 162
 163 static void
 164 mlx5e_update_carrier(struct mlx5e_priv *priv)
 165 {
 166         struct mlx5_core_dev *mdev = priv->mdev;
 167         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 168         u32 eth_proto_oper;
 169         int error;
 170         u8 port_state;
 171         u8 is_er_type;
 172         u8 i;
 173
 174         port_state = mlx5_query_vport_state(mdev,
 175             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 176
 177         if (port_state == VPORT_STATE_UP) {
 178                 priv->media_status_last |= IFM_ACTIVE;
 179         } else {
 180                 priv->media_status_last &= ~IFM_ACTIVE;
 181                 priv->media_active_last = IFM_ETHER;
 182                 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
 183                 return;
 184         }
 185
 186         error = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
 187         if (error) {
 188                 priv->media_active_last = IFM_ETHER;
 189                 priv->ifp->if_baudrate = 1;
 190                 if_printf(priv->ifp, "%s: query port ptys failed: 0x%x\n",
 191                     __func__, error);
 192                 return;
 193         }
 194         eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
 195
 196         for (i = 0; i != MLX5E_LINK_MODES_NUMBER; i++) {
 197                 if (mlx5e_mode_table[i].baudrate == 0)
 198                         continue;
 199                 if (MLX5E_PROT_MASK(i) & eth_proto_oper) {
 200                         u32 subtype = mlx5e_mode_table[i].subtype;
 201
 202                         priv->ifp->if_baudrate =
 203                             mlx5e_mode_table[i].baudrate;
 204
 205                         switch (subtype) {
 206                         case IFM_10G_ER:
 207                                 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
 208                                 if (error != 0) {
 209                                         if_printf(priv->ifp, "%s: query port pddr failed: %d\n",
 210                                             __func__, error);
 211                                 }
 212                                 if (error != 0 || is_er_type == 0)
 213                                         subtype = IFM_10G_LR;
 214                                 break;
 215                         case IFM_40G_LR4:
 216                                 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
 217                                 if (error != 0) {
 218                                         if_printf(priv->ifp, "%s: query port pddr failed: %d\n",
 219                                             __func__, error);
 220                                 }
 221                                 if (error == 0 && is_er_type != 0)
 222                                         subtype = IFM_40G_ER4;
 223                                 break;
 224                         }
 225                         priv->media_active_last = subtype | IFM_ETHER | IFM_FDX;
 226                         break;
 227                 }
 228         }
 229         if_link_state_change(priv->ifp, LINK_STATE_UP);
 230 }
 231
 232 static void
 233 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
 234 {
 235         struct mlx5e_priv *priv = dev->if_softc;
 236
 237         ifmr->ifm_status = priv->media_status_last;
 238         ifmr->ifm_active = priv->media_active_last |
 239             (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
 240             (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
 241
 242 }
 243
 244 static u32
 245 mlx5e_find_link_mode(u32 subtype)
 246 {
 247         u32 i;
 248         u32 link_mode = 0;
 249
 250         switch (subtype) {
 251         case IFM_10G_LR:
 252                 subtype = IFM_10G_ER;
 253                 break;
 254         case IFM_40G_ER4:
 255                 subtype = IFM_40G_LR4;
 256                 break;
 257         }
 258
 259         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
 260                 if (mlx5e_mode_table[i].baudrate == 0)
 261                         continue;
 262                 if (mlx5e_mode_table[i].subtype == subtype)
 263                         link_mode |= MLX5E_PROT_MASK(i);
 264         }
 265
 266         return (link_mode);
 267 }
 268
 269 static int
 270 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv)
 271 {
 272         return (mlx5_set_port_pause_and_pfc(priv->mdev, 1,
 273             priv->params.rx_pauseframe_control,
 274             priv->params.tx_pauseframe_control,
 275             priv->params.rx_priority_flow_control,
 276             priv->params.tx_priority_flow_control));
 277 }
 278
 279 static int
 280 mlx5e_set_port_pfc(struct mlx5e_priv *priv)
 281 {
 282         int error;
 283
 284         if (priv->gone != 0) {
 285                 error = -ENXIO;
 286         } else if (priv->params.rx_pauseframe_control ||
 287             priv->params.tx_pauseframe_control) {
 288                 if_printf(priv->ifp,
 289                     "Global pauseframes must be disabled before enabling PFC.\n");
 290                 error = -EINVAL;
 291         } else {
 292                 error = mlx5e_set_port_pause_and_pfc(priv);
 293         }
 294         return (error);
 295 }
 296
 297 static int
 298 mlx5e_media_change(struct ifnet *dev)
 299 {
 300         struct mlx5e_priv *priv = dev->if_softc;
 301         struct mlx5_core_dev *mdev = priv->mdev;
 302         u32 eth_proto_cap;
 303         u32 link_mode;
 304         int was_opened;
 305         int locked;
 306         int error;
 307
 308         locked = PRIV_LOCKED(priv);
 309         if (!locked)
 310                 PRIV_LOCK(priv);
 311
 312         if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
 313                 error = EINVAL;
 314                 goto done;
 315         }
 316         link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media));
 317
 318         /* query supported capabilities */
 319         error = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
 320         if (error != 0) {
 321                 if_printf(dev, "Query port media capability failed\n");
 322                 goto done;
 323         }
 324         /* check for autoselect */
 325         if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
 326                 link_mode = eth_proto_cap;
 327                 if (link_mode == 0) {
 328                         if_printf(dev, "Port media capability is zero\n");
 329                         error = EINVAL;
 330                         goto done;
 331                 }
 332         } else {
 333                 link_mode = link_mode & eth_proto_cap;
 334                 if (link_mode == 0) {
 335                         if_printf(dev, "Not supported link mode requested\n");
 336                         error = EINVAL;
 337                         goto done;
 338                 }
 339         }
 340         if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
 341                 /* check if PFC is enabled */
 342                 if (priv->params.rx_priority_flow_control ||
 343                     priv->params.tx_priority_flow_control) {
 344                         if_printf(dev, "PFC must be disabled before enabling global pauseframes.\n");
 345                         error = EINVAL;
 346                         goto done;
 347                 }
 348         }
 349         /* update pauseframe control bits */
 350         priv->params.rx_pauseframe_control =
 351             (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
 352         priv->params.tx_pauseframe_control =
 353             (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
 354
 355         /* check if device is opened */
 356         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
 357
 358         /* reconfigure the hardware */
 359         mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
 360         mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN);
 361         error = -mlx5e_set_port_pause_and_pfc(priv);
 362         if (was_opened)
 363                 mlx5_set_port_status(mdev, MLX5_PORT_UP);
 364
 365 done:
 366         if (!locked)
 367                 PRIV_UNLOCK(priv);
 368         return (error);
 369 }
 370
 371 static void
 372 mlx5e_update_carrier_work(struct work_struct *work)
 373 {
 374         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 375             update_carrier_work);
 376
 377         PRIV_LOCK(priv);
 378         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 379                 mlx5e_update_carrier(priv);
 380         PRIV_UNLOCK(priv);
 381 }
 382
 383 /*
 384  * This function reads the physical port counters from the firmware
 385  * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
 386  * macros. The output is converted from big-endian 64-bit values into
 387  * host endian ones and stored in the "priv->stats.pport" structure.
 388  */
 389 static void
 390 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 391 {
 392         struct mlx5_core_dev *mdev = priv->mdev;
 393         struct mlx5e_pport_stats *s = &priv->stats.pport;
 394         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 395         u32 *in;
 396         u32 *out;
 397         const u64 *ptr;
 398         unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 399         unsigned x;
 400         unsigned y;
 401         unsigned z;
 402
 403         /* allocate firmware request structures */
 404         in = mlx5_vzalloc(sz);
 405         out = mlx5_vzalloc(sz);
 406         if (in == NULL || out == NULL)
 407                 goto free_out;
 408
 409         /*
 410          * Get pointer to the 64-bit counter set which is located at a
 411          * fixed offset in the output firmware request structure:
 412          */
 413         ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
 414
 415         MLX5_SET(ppcnt_reg, in, local_port, 1);
 416
 417         /* read IEEE802_3 counter group using predefined counter layout */
 418         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 419         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 420         for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM;
 421              x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
 422                 s->arg[y] = be64toh(ptr[x]);
 423
 424         /* read RFC2819 counter group using predefined counter layout */
 425         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 426         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 427         for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
 428                 s->arg[y] = be64toh(ptr[x]);
 429         for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
 430             MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
 431                 s_debug->arg[y] = be64toh(ptr[x]);
 432
 433         /* read RFC2863 counter group using predefined counter layout */
 434         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 435         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 436         for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
 437                 s_debug->arg[y] = be64toh(ptr[x]);
 438
 439         /* read physical layer stats counter group using predefined counter layout */
 440         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 441         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 442         for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
 443                 s_debug->arg[y] = be64toh(ptr[x]);
 444
 445         /* read Extended Ethernet counter group using predefined counter layout */
 446         MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
 447         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 448         for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++)
 449                 s_debug->arg[y] = be64toh(ptr[x]);
 450
 451         /* read per-priority counters */
 452         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 453
 454         /* iterate all the priorities */
 455         for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) {
 456                 MLX5_SET(ppcnt_reg, in, prio_tc, z);
 457                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 458
 459                 /* read per priority stats counter group using predefined counter layout */
 460                 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM /
 461                     MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++)
 462                         s->arg[y] = be64toh(ptr[x]);
 463         }
 464
 465 free_out:
 466         /* free firmware request structures */
 467         kvfree(in);
 468         kvfree(out);
 469 }
 470
 471 /*
 472  * This function is called regularly to collect all statistics
 473  * counters from the firmware. The values can be viewed through the
 474  * sysctl interface. Execution is serialized using the priv's global
 475  * configuration lock.
 476  */
 477 static void
 478 mlx5e_update_stats_locked(struct mlx5e_priv *priv)
 479 {
 480         struct mlx5_core_dev *mdev = priv->mdev;
 481         struct mlx5e_vport_stats *s = &priv->stats.vport;
 482         struct mlx5e_sq_stats *sq_stats;
 483         struct buf_ring *sq_br;
 484 #if (__FreeBSD_version < 1100000)
 485         struct ifnet *ifp = priv->ifp;
 486 #endif
 487
 488         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 489         u32 *out;
 490         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 491         u64 tso_packets = 0;
 492         u64 tso_bytes = 0;
 493         u64 tx_queue_dropped = 0;
 494         u64 tx_defragged = 0;
 495         u64 tx_offload_none = 0;
 496         u64 lro_packets = 0;
 497         u64 lro_bytes = 0;
 498         u64 sw_lro_queued = 0;
 499         u64 sw_lro_flushed = 0;
 500         u64 rx_csum_none = 0;
 501         u64 rx_wqe_err = 0;
 502         u32 rx_out_of_buffer = 0;
 503         int i;
 504         int j;
 505
 506         out = mlx5_vzalloc(outlen);
 507         if (out == NULL)
 508                 goto free_out;
 509
 510         /* Collect firts the SW counters and then HW for consistency */
 511         for (i = 0; i < priv->params.num_channels; i++) {
 512                 struct mlx5e_channel *pch = priv->channel + i;
 513                 struct mlx5e_rq *rq = &pch->rq;
 514                 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats;
 515
 516                 /* collect stats from LRO */
 517                 rq_stats->sw_lro_queued = rq->lro.lro_queued;
 518                 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
 519                 sw_lro_queued += rq_stats->sw_lro_queued;
 520                 sw_lro_flushed += rq_stats->sw_lro_flushed;
 521                 lro_packets += rq_stats->lro_packets;
 522                 lro_bytes += rq_stats->lro_bytes;
 523                 rx_csum_none += rq_stats->csum_none;
 524                 rx_wqe_err += rq_stats->wqe_err;
 525
 526                 for (j = 0; j < priv->num_tc; j++) {
 527                         sq_stats = &pch->sq[j].stats;
 528                         sq_br = pch->sq[j].br;
 529
 530                         tso_packets += sq_stats->tso_packets;
 531                         tso_bytes += sq_stats->tso_bytes;
 532                         tx_queue_dropped += sq_stats->dropped;
 533                         if (sq_br != NULL)
 534                                 tx_queue_dropped += sq_br->br_drops;
 535                         tx_defragged += sq_stats->defragged;
 536                         tx_offload_none += sq_stats->csum_offload_none;
 537                 }
 538         }
 539
 540         /* update counters */
 541         s->tso_packets = tso_packets;
 542         s->tso_bytes = tso_bytes;
 543         s->tx_queue_dropped = tx_queue_dropped;
 544         s->tx_defragged = tx_defragged;
 545         s->lro_packets = lro_packets;
 546         s->lro_bytes = lro_bytes;
 547         s->sw_lro_queued = sw_lro_queued;
 548         s->sw_lro_flushed = sw_lro_flushed;
 549         s->rx_csum_none = rx_csum_none;
 550         s->rx_wqe_err = rx_wqe_err;
 551
 552         /* HW counters */
 553         memset(in, 0, sizeof(in));
 554
 555         MLX5_SET(query_vport_counter_in, in, opcode,
 556             MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 557         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 558         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 559
 560         memset(out, 0, outlen);
 561
 562         /* get number of out-of-buffer drops first */
 563         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 &&
 564             mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
 565             &rx_out_of_buffer) == 0) {
 566                 /* accumulate difference into a 64-bit counter */
 567                 s->rx_out_of_buffer += (u64)(u32)(rx_out_of_buffer -
 568                     s->rx_out_of_buffer_prev);
 569                 s->rx_out_of_buffer_prev = rx_out_of_buffer;
 570         }
 571
 572         /* get port statistics */
 573         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen) == 0) {
 574 #define MLX5_GET_CTR(out, x) \
 575         MLX5_GET64(query_vport_counter_out, out, x)
 576
 577                 s->rx_error_packets =
 578                     MLX5_GET_CTR(out, received_errors.packets);
 579                 s->rx_error_bytes =
 580                     MLX5_GET_CTR(out, received_errors.octets);
 581                 s->tx_error_packets =
 582                     MLX5_GET_CTR(out, transmit_errors.packets);
 583                 s->tx_error_bytes =
 584                     MLX5_GET_CTR(out, transmit_errors.octets);
 585
 586                 s->rx_unicast_packets =
 587                     MLX5_GET_CTR(out, received_eth_unicast.packets);
 588                 s->rx_unicast_bytes =
 589                     MLX5_GET_CTR(out, received_eth_unicast.octets);
 590                 s->tx_unicast_packets =
 591                     MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 592                 s->tx_unicast_bytes =
 593                     MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 594
 595                 s->rx_multicast_packets =
 596                     MLX5_GET_CTR(out, received_eth_multicast.packets);
 597                 s->rx_multicast_bytes =
 598                     MLX5_GET_CTR(out, received_eth_multicast.octets);
 599                 s->tx_multicast_packets =
 600                     MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 601                 s->tx_multicast_bytes =
 602                     MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 603
 604                 s->rx_broadcast_packets =
 605                     MLX5_GET_CTR(out, received_eth_broadcast.packets);
 606                 s->rx_broadcast_bytes =
 607                     MLX5_GET_CTR(out, received_eth_broadcast.octets);
 608                 s->tx_broadcast_packets =
 609                     MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 610                 s->tx_broadcast_bytes =
 611                     MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 612
 613                 s->rx_packets = s->rx_unicast_packets +
 614                     s->rx_multicast_packets + s->rx_broadcast_packets -
 615                     s->rx_out_of_buffer;
 616                 s->rx_bytes = s->rx_unicast_bytes + s->rx_multicast_bytes +
 617                     s->rx_broadcast_bytes;
 618                 s->tx_packets = s->tx_unicast_packets +
 619                     s->tx_multicast_packets + s->tx_broadcast_packets;
 620                 s->tx_bytes = s->tx_unicast_bytes + s->tx_multicast_bytes +
 621                     s->tx_broadcast_bytes;
 622
 623                 /* Update calculated offload counters */
 624                 s->tx_csum_offload = s->tx_packets - tx_offload_none;
 625                 s->rx_csum_good = s->rx_packets - s->rx_csum_none;
 626         }
 627
 628         /* Get physical port counters */
 629         mlx5e_update_pport_counters(priv);
 630
 631         s->tx_jumbo_packets =
 632             priv->stats.port_stats_debug.tx_stat_p1519to2047octets +
 633             priv->stats.port_stats_debug.tx_stat_p2048to4095octets +
 634             priv->stats.port_stats_debug.tx_stat_p4096to8191octets +
 635             priv->stats.port_stats_debug.tx_stat_p8192to10239octets;
 636
 637 #if (__FreeBSD_version < 1100000)
 638         /* no get_counters interface in fbsd 10 */
 639         ifp->if_ipackets = s->rx_packets;
 640         ifp->if_ierrors = s->rx_error_packets +
 641             priv->stats.pport.alignment_err +
 642             priv->stats.pport.check_seq_err +
 643             priv->stats.pport.crc_align_errors +
 644             priv->stats.pport.in_range_len_errors +
 645             priv->stats.pport.jabbers +
 646             priv->stats.pport.out_of_range_len +
 647             priv->stats.pport.oversize_pkts +
 648             priv->stats.pport.symbol_err +
 649             priv->stats.pport.too_long_errors +
 650             priv->stats.pport.undersize_pkts +
 651             priv->stats.pport.unsupported_op_rx;
 652         ifp->if_iqdrops = s->rx_out_of_buffer +
 653             priv->stats.pport.drop_events;
 654         ifp->if_opackets = s->tx_packets;
 655         ifp->if_oerrors = s->tx_error_packets;
 656         ifp->if_snd.ifq_drops = s->tx_queue_dropped;
 657         ifp->if_ibytes = s->rx_bytes;
 658         ifp->if_obytes = s->tx_bytes;
 659         ifp->if_collisions =
 660             priv->stats.pport.collisions;
 661 #endif
 662
 663 free_out:
 664         kvfree(out);
 665
 666         /* Update diagnostics, if any */
 667         if (priv->params_ethtool.diag_pci_enable ||
 668             priv->params_ethtool.diag_general_enable) {
 669                 int error = mlx5_core_get_diagnostics_full(mdev,
 670                     priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL,
 671                     priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL);
 672                 if (error != 0)
 673                         if_printf(priv->ifp, "Failed reading diagnostics: %d\n", error);
 674         }
 675 }
 676
 677 static void
 678 mlx5e_update_stats_work(struct work_struct *work)
 679 {
 680         struct mlx5e_priv *priv;
 681
 682         priv  = container_of(work, struct mlx5e_priv, update_stats_work);
 683         PRIV_LOCK(priv);
 684         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
 685                 mlx5e_update_stats_locked(priv);
 686         PRIV_UNLOCK(priv);
 687 }
 688
 689 static void
 690 mlx5e_update_stats(void *arg)
 691 {
 692         struct mlx5e_priv *priv = arg;
 693
 694         queue_work(priv->wq, &priv->update_stats_work);
 695
 696         callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
 697 }
 698
 699 static void
 700 mlx5e_async_event_sub(struct mlx5e_priv *priv,
 701     enum mlx5_dev_event event)
 702 {
 703         switch (event) {
 704         case MLX5_DEV_EVENT_PORT_UP:
 705         case MLX5_DEV_EVENT_PORT_DOWN:
 706                 queue_work(priv->wq, &priv->update_carrier_work);
 707                 break;
 708
 709         default:
 710                 break;
 711         }
 712 }
 713
 714 static void
 715 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 716     enum mlx5_dev_event event, unsigned long param)
 717 {
 718         struct mlx5e_priv *priv = vpriv;
 719
 720         mtx_lock(&priv->async_events_mtx);
 721         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 722                 mlx5e_async_event_sub(priv, event);
 723         mtx_unlock(&priv->async_events_mtx);
 724 }
 725
 726 static void
 727 mlx5e_enable_async_events(struct mlx5e_priv *priv)
 728 {
 729         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 730 }
 731
 732 static void
 733 mlx5e_disable_async_events(struct mlx5e_priv *priv)
 734 {
 735         mtx_lock(&priv->async_events_mtx);
 736         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 737         mtx_unlock(&priv->async_events_mtx);
 738 }
 739
 740 static const char *mlx5e_rq_stats_desc[] = {
 741         MLX5E_RQ_STATS(MLX5E_STATS_DESC)
 742 };
 743
 744 static int
 745 mlx5e_create_rq(struct mlx5e_channel *c,
 746     struct mlx5e_rq_param *param,
 747     struct mlx5e_rq *rq)
 748 {
 749         struct mlx5e_priv *priv = c->priv;
 750         struct mlx5_core_dev *mdev = priv->mdev;
 751         char buffer[16];
 752         void *rqc = param->rqc;
 753         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 754         int wq_sz;
 755         int err;
 756         int i;
 757         u32 nsegs, wqe_sz;
 758
 759         err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
 760         if (err != 0)
 761                 goto done;
 762
 763         /* Create DMA descriptor TAG */
 764         if ((err = -bus_dma_tag_create(
 765             bus_get_dma_tag(mdev->pdev->dev.bsddev),
 766             1,                          /* any alignment */
 767             0,                          /* no boundary */
 768             BUS_SPACE_MAXADDR,          /* lowaddr */
 769             BUS_SPACE_MAXADDR,          /* highaddr */
 770             NULL, NULL,                 /* filter, filterarg */
 771             nsegs * MLX5E_MAX_RX_BYTES, /* maxsize */
 772             nsegs,                      /* nsegments */
 773             nsegs * MLX5E_MAX_RX_BYTES, /* maxsegsize */
 774             0,                          /* flags */
 775             NULL, NULL,                 /* lockfunc, lockfuncarg */
 776             &rq->dma_tag)))
 777                 goto done;
 778
 779         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 780             &rq->wq_ctrl);
 781         if (err)
 782                 goto err_free_dma_tag;
 783
 784         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 785
 786         err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs);
 787         if (err != 0)
 788                 goto err_rq_wq_destroy;
 789
 790         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 791
 792         err = -tcp_lro_init_args(&rq->lro, c->ifp, TCP_LRO_ENTRIES, wq_sz);
 793         if (err)
 794                 goto err_rq_wq_destroy;
 795
 796         rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
 797         for (i = 0; i != wq_sz; i++) {
 798                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 799 #if (MLX5E_MAX_RX_SEGS == 1)
 800                 uint32_t byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 801 #else
 802                 int j;
 803 #endif
 804
 805                 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
 806                 if (err != 0) {
 807                         while (i--)
 808                                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 809                         goto err_rq_mbuf_free;
 810                 }
 811
 812                 /* set value for constant fields */
 813 #if (MLX5E_MAX_RX_SEGS == 1)
 814                 wqe->data[0].lkey = c->mkey_be;
 815                 wqe->data[0].byte_count = cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
 816 #else
 817                 for (j = 0; j < rq->nsegs; j++)
 818                         wqe->data[j].lkey = c->mkey_be;
 819 #endif
 820         }
 821
 822         INIT_WORK(&rq->dim.work, mlx5e_dim_work);
 823         if (priv->params.rx_cq_moderation_mode < 2) {
 824                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
 825         } else {
 826                 void *cqc = container_of(param,
 827                     struct mlx5e_channel_param, rq)->rx_cq.cqc;
 828
 829                 switch (MLX5_GET(cqc, cqc, cq_period_mode)) {
 830                 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 831                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 832                         break;
 833                 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 834                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 835                         break;
 836                 default:
 837                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
 838                         break;
 839                 }
 840         }
 841
 842         rq->ifp = c->ifp;
 843         rq->channel = c;
 844         rq->ix = c->ix;
 845
 846         snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
 847         mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
 848             buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
 849             rq->stats.arg);
 850         return (0);
 851
 852 err_rq_mbuf_free:
 853         free(rq->mbuf, M_MLX5EN);
 854         tcp_lro_free(&rq->lro);
 855 err_rq_wq_destroy:
 856         mlx5_wq_destroy(&rq->wq_ctrl);
 857 err_free_dma_tag:
 858         bus_dma_tag_destroy(rq->dma_tag);
 859 done:
 860         return (err);
 861 }
 862
 863 static void
 864 mlx5e_destroy_rq(struct mlx5e_rq *rq)
 865 {
 866         int wq_sz;
 867         int i;
 868
 869         /* destroy all sysctl nodes */
 870         sysctl_ctx_free(&rq->stats.ctx);
 871
 872         /* free leftover LRO packets, if any */
 873         tcp_lro_free(&rq->lro);
 874
 875         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 876         for (i = 0; i != wq_sz; i++) {
 877                 if (rq->mbuf[i].mbuf != NULL) {
 878                         bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map);
 879                         m_freem(rq->mbuf[i].mbuf);
 880                 }
 881                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 882         }
 883         free(rq->mbuf, M_MLX5EN);
 884         mlx5_wq_destroy(&rq->wq_ctrl);
 885 }
 886
 887 static int
 888 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 889 {
 890         struct mlx5e_channel *c = rq->channel;
 891         struct mlx5e_priv *priv = c->priv;
 892         struct mlx5_core_dev *mdev = priv->mdev;
 893
 894         void *in;
 895         void *rqc;
 896         void *wq;
 897         int inlen;
 898         int err;
 899
 900         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 901             sizeof(u64) * rq->wq_ctrl.buf.npages;
 902         in = mlx5_vzalloc(inlen);
 903         if (in == NULL)
 904                 return (-ENOMEM);
 905
 906         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 907         wq = MLX5_ADDR_OF(rqc, rqc, wq);
 908
 909         memcpy(rqc, param->rqc, sizeof(param->rqc));
 910
 911         MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
 912         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
 913         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
 914         if (priv->counter_set_id >= 0)
 915                 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
 916         MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
 917             PAGE_SHIFT);
 918         MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
 919
 920         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 921             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
 922
 923         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 924
 925         kvfree(in);
 926
 927         return (err);
 928 }
 929
 930 static int
 931 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
 932 {
 933         struct mlx5e_channel *c = rq->channel;
 934         struct mlx5e_priv *priv = c->priv;
 935         struct mlx5_core_dev *mdev = priv->mdev;
 936
 937         void *in;
 938         void *rqc;
 939         int inlen;
 940         int err;
 941
 942         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 943         in = mlx5_vzalloc(inlen);
 944         if (in == NULL)
 945                 return (-ENOMEM);
 946
 947         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 948
 949         MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
 950         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 951         MLX5_SET(rqc, rqc, state, next_state);
 952
 953         err = mlx5_core_modify_rq(mdev, in, inlen);
 954
 955         kvfree(in);
 956
 957         return (err);
 958 }
 959
 960 static void
 961 mlx5e_disable_rq(struct mlx5e_rq *rq)
 962 {
 963         struct mlx5e_channel *c = rq->channel;
 964         struct mlx5e_priv *priv = c->priv;
 965         struct mlx5_core_dev *mdev = priv->mdev;
 966
 967         mlx5_core_destroy_rq(mdev, rq->rqn);
 968 }
 969
 970 static int
 971 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 972 {
 973         struct mlx5e_channel *c = rq->channel;
 974         struct mlx5e_priv *priv = c->priv;
 975         struct mlx5_wq_ll *wq = &rq->wq;
 976         int i;
 977
 978         for (i = 0; i < 1000; i++) {
 979                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 980                         return (0);
 981
 982                 msleep(4);
 983         }
 984         return (-ETIMEDOUT);
 985 }
 986
 987 static int
 988 mlx5e_open_rq(struct mlx5e_channel *c,
 989     struct mlx5e_rq_param *param,
 990     struct mlx5e_rq *rq)
 991 {
 992         int err;
 993
 994         err = mlx5e_create_rq(c, param, rq);
 995         if (err)
 996                 return (err);
 997
 998         err = mlx5e_enable_rq(rq, param);
 999         if (err)
1000                 goto err_destroy_rq;
1001
1002         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1003         if (err)
1004                 goto err_disable_rq;
1005
1006         c->rq.enabled = 1;
1007
1008         return (0);
1009
1010 err_disable_rq:
1011         mlx5e_disable_rq(rq);
1012 err_destroy_rq:
1013         mlx5e_destroy_rq(rq);
1014
1015         return (err);
1016 }
1017
1018 static void
1019 mlx5e_close_rq(struct mlx5e_rq *rq)
1020 {
1021         mtx_lock(&rq->mtx);
1022         rq->enabled = 0;
1023         callout_stop(&rq->watchdog);
1024         mtx_unlock(&rq->mtx);
1025
1026         callout_drain(&rq->watchdog);
1027
1028         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
1029 }
1030
1031 static void
1032 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
1033 {
1034
1035         mlx5e_disable_rq(rq);
1036         mlx5e_close_cq(&rq->cq);
1037         cancel_work_sync(&rq->dim.work);
1038         mlx5e_destroy_rq(rq);
1039 }
1040
1041 void
1042 mlx5e_free_sq_db(struct mlx5e_sq *sq)
1043 {
1044         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1045         int x;
1046
1047         for (x = 0; x != wq_sz; x++)
1048                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1049         free(sq->mbuf, M_MLX5EN);
1050 }
1051
1052 int
1053 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
1054 {
1055         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1056         int err;
1057         int x;
1058
1059         sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1060
1061         /* Create DMA descriptor MAPs */
1062         for (x = 0; x != wq_sz; x++) {
1063                 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
1064                 if (err != 0) {
1065                         while (x--)
1066                                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1067                         free(sq->mbuf, M_MLX5EN);
1068                         return (err);
1069                 }
1070         }
1071         return (0);
1072 }
1073
1074 static const char *mlx5e_sq_stats_desc[] = {
1075         MLX5E_SQ_STATS(MLX5E_STATS_DESC)
1076 };
1077
1078 void
1079 mlx5e_update_sq_inline(struct mlx5e_sq *sq)
1080 {
1081         sq->max_inline = sq->priv->params.tx_max_inline;
1082         sq->min_inline_mode = sq->priv->params.tx_min_inline_mode;
1083
1084         /*
1085          * Check if trust state is DSCP or if inline mode is NONE which
1086          * indicates CX-5 or newer hardware.
1087          */
1088         if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP ||
1089             sq->min_inline_mode == MLX5_INLINE_MODE_NONE) {
1090                 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert))
1091                         sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN;
1092                 else
1093                         sq->min_insert_caps = MLX5E_INSERT_NON_VLAN;
1094         } else {
1095                 sq->min_insert_caps = 0;
1096         }
1097 }
1098
1099 static void
1100 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1101 {
1102         int i;
1103
1104         for (i = 0; i != c->num_tc; i++) {
1105                 mtx_lock(&c->sq[i].lock);
1106                 mlx5e_update_sq_inline(&c->sq[i]);
1107                 mtx_unlock(&c->sq[i].lock);
1108         }
1109 }
1110
1111 void
1112 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv)
1113 {
1114         int i;
1115
1116         /* check if channels are closed */
1117         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
1118                 return;
1119
1120         for (i = 0; i < priv->params.num_channels; i++)
1121                 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]);
1122 }
1123
1124 static int
1125 mlx5e_create_sq(struct mlx5e_channel *c,
1126     int tc,
1127     struct mlx5e_sq_param *param,
1128     struct mlx5e_sq *sq)
1129 {
1130         struct mlx5e_priv *priv = c->priv;
1131         struct mlx5_core_dev *mdev = priv->mdev;
1132         char buffer[16];
1133         void *sqc = param->sqc;
1134         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1135         int err;
1136
1137         /* Create DMA descriptor TAG */
1138         if ((err = -bus_dma_tag_create(
1139             bus_get_dma_tag(mdev->pdev->dev.bsddev),
1140             1,                          /* any alignment */
1141             0,                          /* no boundary */
1142             BUS_SPACE_MAXADDR,          /* lowaddr */
1143             BUS_SPACE_MAXADDR,          /* highaddr */
1144             NULL, NULL,                 /* filter, filterarg */
1145             MLX5E_MAX_TX_PAYLOAD_SIZE,  /* maxsize */
1146             MLX5E_MAX_TX_MBUF_FRAGS,    /* nsegments */
1147             MLX5E_MAX_TX_MBUF_SIZE,     /* maxsegsize */
1148             0,                          /* flags */
1149             NULL, NULL,                 /* lockfunc, lockfuncarg */
1150             &sq->dma_tag)))
1151                 goto done;
1152
1153         err = mlx5_alloc_map_uar(mdev, &sq->uar);
1154         if (err)
1155                 goto err_free_dma_tag;
1156
1157         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
1158             &sq->wq_ctrl);
1159         if (err)
1160                 goto err_unmap_free_uar;
1161
1162         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1163         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1164
1165         err = mlx5e_alloc_sq_db(sq);
1166         if (err)
1167                 goto err_sq_wq_destroy;
1168
1169         sq->mkey_be = c->mkey_be;
1170         sq->ifp = priv->ifp;
1171         sq->priv = priv;
1172         sq->tc = tc;
1173
1174         mlx5e_update_sq_inline(sq);
1175
1176         snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1177         mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1178             buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1179             sq->stats.arg);
1180
1181         return (0);
1182
1183 err_sq_wq_destroy:
1184         mlx5_wq_destroy(&sq->wq_ctrl);
1185
1186 err_unmap_free_uar:
1187         mlx5_unmap_free_uar(mdev, &sq->uar);
1188
1189 err_free_dma_tag:
1190         bus_dma_tag_destroy(sq->dma_tag);
1191 done:
1192         return (err);
1193 }
1194
1195 static void
1196 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1197 {
1198         /* destroy all sysctl nodes */
1199         sysctl_ctx_free(&sq->stats.ctx);
1200
1201         mlx5e_free_sq_db(sq);
1202         mlx5_wq_destroy(&sq->wq_ctrl);
1203         mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1204 }
1205
1206 int
1207 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1208     int tis_num)
1209 {
1210         void *in;
1211         void *sqc;
1212         void *wq;
1213         int inlen;
1214         int err;
1215
1216         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1217             sizeof(u64) * sq->wq_ctrl.buf.npages;
1218         in = mlx5_vzalloc(inlen);
1219         if (in == NULL)
1220                 return (-ENOMEM);
1221
1222         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1223         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1224
1225         memcpy(sqc, param->sqc, sizeof(param->sqc));
1226
1227         MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1228         MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1229         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1230         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1231         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1232
1233         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1234         MLX5_SET(wq, wq, uar_page, sq->uar.index);
1235         MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1236             PAGE_SHIFT);
1237         MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1238
1239         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1240             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1241
1242         err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1243
1244         kvfree(in);
1245
1246         return (err);
1247 }
1248
1249 int
1250 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1251 {
1252         void *in;
1253         void *sqc;
1254         int inlen;
1255         int err;
1256
1257         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1258         in = mlx5_vzalloc(inlen);
1259         if (in == NULL)
1260                 return (-ENOMEM);
1261
1262         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1263
1264         MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1265         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1266         MLX5_SET(sqc, sqc, state, next_state);
1267
1268         err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1269
1270         kvfree(in);
1271
1272         return (err);
1273 }
1274
1275 void
1276 mlx5e_disable_sq(struct mlx5e_sq *sq)
1277 {
1278
1279         mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1280 }
1281
1282 static int
1283 mlx5e_open_sq(struct mlx5e_channel *c,
1284     int tc,
1285     struct mlx5e_sq_param *param,
1286     struct mlx5e_sq *sq)
1287 {
1288         int err;
1289
1290         err = mlx5e_create_sq(c, tc, param, sq);
1291         if (err)
1292                 return (err);
1293
1294         err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1295         if (err)
1296                 goto err_destroy_sq;
1297
1298         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1299         if (err)
1300                 goto err_disable_sq;
1301
1302         WRITE_ONCE(sq->running, 1);
1303
1304         return (0);
1305
1306 err_disable_sq:
1307         mlx5e_disable_sq(sq);
1308 err_destroy_sq:
1309         mlx5e_destroy_sq(sq);
1310
1311         return (err);
1312 }
1313
1314 static void
1315 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1316 {
1317         /* fill up remainder with NOPs */
1318         while (sq->cev_counter != 0) {
1319                 while (!mlx5e_sq_has_room_for(sq, 1)) {
1320                         if (can_sleep != 0) {
1321                                 mtx_unlock(&sq->lock);
1322                                 msleep(4);
1323                                 mtx_lock(&sq->lock);
1324                         } else {
1325                                 goto done;
1326                         }
1327                 }
1328                 /* send a single NOP */
1329                 mlx5e_send_nop(sq, 1);
1330                 atomic_thread_fence_rel();
1331         }
1332 done:
1333         /* Check if we need to write the doorbell */
1334         if (likely(sq->doorbell.d64 != 0)) {
1335                 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1336                 sq->doorbell.d64 = 0;
1337         }
1338 }
1339
1340 void
1341 mlx5e_sq_cev_timeout(void *arg)
1342 {
1343         struct mlx5e_sq *sq = arg;
1344
1345         mtx_assert(&sq->lock, MA_OWNED);
1346
1347         /* check next state */
1348         switch (sq->cev_next_state) {
1349         case MLX5E_CEV_STATE_SEND_NOPS:
1350                 /* fill TX ring with NOPs, if any */
1351                 mlx5e_sq_send_nops_locked(sq, 0);
1352
1353                 /* check if completed */
1354                 if (sq->cev_counter == 0) {
1355                         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1356                         return;
1357                 }
1358                 break;
1359         default:
1360                 /* send NOPs on next timeout */
1361                 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1362                 break;
1363         }
1364
1365         /* restart timer */
1366         callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1367 }
1368
1369 void
1370 mlx5e_drain_sq(struct mlx5e_sq *sq)
1371 {
1372         int error;
1373         struct mlx5_core_dev *mdev= sq->priv->mdev;
1374
1375         /*
1376          * Check if already stopped.
1377          *
1378          * NOTE: Serialization of this function is managed by the
1379          * caller ensuring the priv's state lock is locked or in case
1380          * of rate limit support, a single thread manages drain and
1381          * resume of SQs. The "running" variable can therefore safely
1382          * be read without any locks.
1383          */
1384         if (READ_ONCE(sq->running) == 0)
1385                 return;
1386
1387         /* don't put more packets into the SQ */
1388         WRITE_ONCE(sq->running, 0);
1389
1390         /* serialize access to DMA rings */
1391         mtx_lock(&sq->lock);
1392
1393         /* teardown event factor timer, if any */
1394         sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1395         callout_stop(&sq->cev_callout);
1396
1397         /* send dummy NOPs in order to flush the transmit ring */
1398         mlx5e_sq_send_nops_locked(sq, 1);
1399         mtx_unlock(&sq->lock);
1400
1401         /* make sure it is safe to free the callout */
1402         callout_drain(&sq->cev_callout);
1403
1404         /* wait till SQ is empty or link is down */
1405         mtx_lock(&sq->lock);
1406         while (sq->cc != sq->pc &&
1407             (sq->priv->media_status_last & IFM_ACTIVE) != 0 &&
1408             mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1409                 mtx_unlock(&sq->lock);
1410                 msleep(1);
1411                 sq->cq.mcq.comp(&sq->cq.mcq);
1412                 mtx_lock(&sq->lock);
1413         }
1414         mtx_unlock(&sq->lock);
1415
1416         /* error out remaining requests */
1417         error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1418         if (error != 0) {
1419                 if_printf(sq->ifp,
1420                     "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error);
1421         }
1422
1423         /* wait till SQ is empty */
1424         mtx_lock(&sq->lock);
1425         while (sq->cc != sq->pc &&
1426                mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1427                 mtx_unlock(&sq->lock);
1428                 msleep(1);
1429                 sq->cq.mcq.comp(&sq->cq.mcq);
1430                 mtx_lock(&sq->lock);
1431         }
1432         mtx_unlock(&sq->lock);
1433 }
1434
1435 static void
1436 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1437 {
1438
1439         mlx5e_drain_sq(sq);
1440         mlx5e_disable_sq(sq);
1441         mlx5e_destroy_sq(sq);
1442 }
1443
1444 static int
1445 mlx5e_create_cq(struct mlx5e_priv *priv,
1446     struct mlx5e_cq_param *param,
1447     struct mlx5e_cq *cq,
1448     mlx5e_cq_comp_t *comp,
1449     int eq_ix)
1450 {
1451         struct mlx5_core_dev *mdev = priv->mdev;
1452         struct mlx5_core_cq *mcq = &cq->mcq;
1453         int eqn_not_used;
1454         int irqn;
1455         int err;
1456         u32 i;
1457
1458         param->wq.buf_numa_node = 0;
1459         param->wq.db_numa_node = 0;
1460
1461         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1462             &cq->wq_ctrl);
1463         if (err)
1464                 return (err);
1465
1466         mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1467
1468         mcq->cqe_sz = 64;
1469         mcq->set_ci_db = cq->wq_ctrl.db.db;
1470         mcq->arm_db = cq->wq_ctrl.db.db + 1;
1471         *mcq->set_ci_db = 0;
1472         *mcq->arm_db = 0;
1473         mcq->vector = eq_ix;
1474         mcq->comp = comp;
1475         mcq->event = mlx5e_cq_error_event;
1476         mcq->irqn = irqn;
1477         mcq->uar = &priv->cq_uar;
1478
1479         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1480                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1481
1482                 cqe->op_own = 0xf1;
1483         }
1484
1485         cq->priv = priv;
1486
1487         return (0);
1488 }
1489
1490 static void
1491 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1492 {
1493         mlx5_wq_destroy(&cq->wq_ctrl);
1494 }
1495
1496 static int
1497 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1498 {
1499         struct mlx5_core_cq *mcq = &cq->mcq;
1500         void *in;
1501         void *cqc;
1502         int inlen;
1503         int irqn_not_used;
1504         int eqn;
1505         int err;
1506
1507         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1508             sizeof(u64) * cq->wq_ctrl.buf.npages;
1509         in = mlx5_vzalloc(inlen);
1510         if (in == NULL)
1511                 return (-ENOMEM);
1512
1513         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1514
1515         memcpy(cqc, param->cqc, sizeof(param->cqc));
1516
1517         mlx5_fill_page_array(&cq->wq_ctrl.buf,
1518             (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1519
1520         mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
1521
1522         MLX5_SET(cqc, cqc, c_eqn, eqn);
1523         MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1524         MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1525             PAGE_SHIFT);
1526         MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1527
1528         err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
1529
1530         kvfree(in);
1531
1532         if (err)
1533                 return (err);
1534
1535         mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock));
1536
1537         return (0);
1538 }
1539
1540 static void
1541 mlx5e_disable_cq(struct mlx5e_cq *cq)
1542 {
1543
1544         mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
1545 }
1546
1547 int
1548 mlx5e_open_cq(struct mlx5e_priv *priv,
1549     struct mlx5e_cq_param *param,
1550     struct mlx5e_cq *cq,
1551     mlx5e_cq_comp_t *comp,
1552     int eq_ix)
1553 {
1554         int err;
1555
1556         err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
1557         if (err)
1558                 return (err);
1559
1560         err = mlx5e_enable_cq(cq, param, eq_ix);
1561         if (err)
1562                 goto err_destroy_cq;
1563
1564         return (0);
1565
1566 err_destroy_cq:
1567         mlx5e_destroy_cq(cq);
1568
1569         return (err);
1570 }
1571
1572 void
1573 mlx5e_close_cq(struct mlx5e_cq *cq)
1574 {
1575         mlx5e_disable_cq(cq);
1576         mlx5e_destroy_cq(cq);
1577 }
1578
1579 static int
1580 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1581     struct mlx5e_channel_param *cparam)
1582 {
1583         int err;
1584         int tc;
1585
1586         for (tc = 0; tc < c->num_tc; tc++) {
1587                 /* open completion queue */
1588                 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
1589                     &mlx5e_tx_cq_comp, c->ix);
1590                 if (err)
1591                         goto err_close_tx_cqs;
1592         }
1593         return (0);
1594
1595 err_close_tx_cqs:
1596         for (tc--; tc >= 0; tc--)
1597                 mlx5e_close_cq(&c->sq[tc].cq);
1598
1599         return (err);
1600 }
1601
1602 static void
1603 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1604 {
1605         int tc;
1606
1607         for (tc = 0; tc < c->num_tc; tc++)
1608                 mlx5e_close_cq(&c->sq[tc].cq);
1609 }
1610
1611 static int
1612 mlx5e_open_sqs(struct mlx5e_channel *c,
1613     struct mlx5e_channel_param *cparam)
1614 {
1615         int err;
1616         int tc;
1617
1618         for (tc = 0; tc < c->num_tc; tc++) {
1619                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1620                 if (err)
1621                         goto err_close_sqs;
1622         }
1623
1624         return (0);
1625
1626 err_close_sqs:
1627         for (tc--; tc >= 0; tc--)
1628                 mlx5e_close_sq_wait(&c->sq[tc]);
1629
1630         return (err);
1631 }
1632
1633 static void
1634 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
1635 {
1636         int tc;
1637
1638         for (tc = 0; tc < c->num_tc; tc++)
1639                 mlx5e_close_sq_wait(&c->sq[tc]);
1640 }
1641
1642 static void
1643 mlx5e_chan_mtx_init(struct mlx5e_channel *c)
1644 {
1645         int tc;
1646
1647         mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
1648
1649         callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
1650
1651         for (tc = 0; tc < c->num_tc; tc++) {
1652                 struct mlx5e_sq *sq = c->sq + tc;
1653
1654                 mtx_init(&sq->lock, "mlx5tx",
1655                     MTX_NETWORK_LOCK " TX", MTX_DEF);
1656                 mtx_init(&sq->comp_lock, "mlx5comp",
1657                     MTX_NETWORK_LOCK " TX", MTX_DEF);
1658
1659                 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
1660
1661                 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1662
1663                 /* ensure the TX completion event factor is not zero */
1664                 if (sq->cev_factor == 0)
1665                         sq->cev_factor = 1;
1666         }
1667 }
1668
1669 static void
1670 mlx5e_chan_mtx_destroy(struct mlx5e_channel *c)
1671 {
1672         int tc;
1673
1674         mtx_destroy(&c->rq.mtx);
1675
1676         for (tc = 0; tc < c->num_tc; tc++) {
1677                 mtx_destroy(&c->sq[tc].lock);
1678                 mtx_destroy(&c->sq[tc].comp_lock);
1679         }
1680 }
1681
1682 static int
1683 mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1684     struct mlx5e_channel_param *cparam,
1685     struct mlx5e_channel *c)
1686 {
1687         int err;
1688
1689         memset(c, 0, sizeof(*c));
1690
1691         c->priv = priv;
1692         c->ix = ix;
1693         c->ifp = priv->ifp;
1694         c->mkey_be = cpu_to_be32(priv->mr.key);
1695         c->num_tc = priv->num_tc;
1696
1697         /* init mutexes */
1698         mlx5e_chan_mtx_init(c);
1699
1700         /* open transmit completion queue */
1701         err = mlx5e_open_tx_cqs(c, cparam);
1702         if (err)
1703                 goto err_free;
1704
1705         /* open receive completion queue */
1706         err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
1707             &mlx5e_rx_cq_comp, c->ix);
1708         if (err)
1709                 goto err_close_tx_cqs;
1710
1711         err = mlx5e_open_sqs(c, cparam);
1712         if (err)
1713                 goto err_close_rx_cq;
1714
1715         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1716         if (err)
1717                 goto err_close_sqs;
1718
1719         /* poll receive queue initially */
1720         c->rq.cq.mcq.comp(&c->rq.cq.mcq);
1721
1722         return (0);
1723
1724 err_close_sqs:
1725         mlx5e_close_sqs_wait(c);
1726
1727 err_close_rx_cq:
1728         mlx5e_close_cq(&c->rq.cq);
1729
1730 err_close_tx_cqs:
1731         mlx5e_close_tx_cqs(c);
1732
1733 err_free:
1734         /* destroy mutexes */
1735         mlx5e_chan_mtx_destroy(c);
1736         return (err);
1737 }
1738
1739 static void
1740 mlx5e_close_channel(struct mlx5e_channel *c)
1741 {
1742         mlx5e_close_rq(&c->rq);
1743 }
1744
1745 static void
1746 mlx5e_close_channel_wait(struct mlx5e_channel *c)
1747 {
1748         mlx5e_close_rq_wait(&c->rq);
1749         mlx5e_close_sqs_wait(c);
1750         mlx5e_close_tx_cqs(c);
1751         /* destroy mutexes */
1752         mlx5e_chan_mtx_destroy(c);
1753 }
1754
1755 static int
1756 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs)
1757 {
1758         u32 r, n;
1759
1760         r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz :
1761             MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
1762         if (r > MJUM16BYTES)
1763                 return (-ENOMEM);
1764
1765         if (r > MJUM9BYTES)
1766                 r = MJUM16BYTES;
1767         else if (r > MJUMPAGESIZE)
1768                 r = MJUM9BYTES;
1769         else if (r > MCLBYTES)
1770                 r = MJUMPAGESIZE;
1771         else
1772                 r = MCLBYTES;
1773
1774         /*
1775          * n + 1 must be a power of two, because stride size must be.
1776          * Stride size is 16 * (n + 1), as the first segment is
1777          * control.
1778          */
1779         for (n = howmany(r, MLX5E_MAX_RX_BYTES); !powerof2(n + 1); n++)
1780                 ;
1781
1782         *wqe_sz = r;
1783         *nsegs = n;
1784         return (0);
1785 }
1786
1787 static void
1788 mlx5e_build_rq_param(struct mlx5e_priv *priv,
1789     struct mlx5e_rq_param *param)
1790 {
1791         void *rqc = param->rqc;
1792         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1793         u32 wqe_sz, nsegs;
1794
1795         mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
1796         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1797         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1798         MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) +
1799             nsegs * sizeof(struct mlx5_wqe_data_seg)));
1800         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1801         MLX5_SET(wq, wq, pd, priv->pdn);
1802
1803         param->wq.buf_numa_node = 0;
1804         param->wq.db_numa_node = 0;
1805         param->wq.linear = 1;
1806 }
1807
1808 static void
1809 mlx5e_build_sq_param(struct mlx5e_priv *priv,
1810     struct mlx5e_sq_param *param)
1811 {
1812         void *sqc = param->sqc;
1813         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1814
1815         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1816         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1817         MLX5_SET(wq, wq, pd, priv->pdn);
1818
1819         param->wq.buf_numa_node = 0;
1820         param->wq.db_numa_node = 0;
1821         param->wq.linear = 1;
1822 }
1823
1824 static void
1825 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1826     struct mlx5e_cq_param *param)
1827 {
1828         void *cqc = param->cqc;
1829
1830         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1831 }
1832
1833 static void
1834 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr)
1835 {
1836
1837         *ptr = net_dim_get_profile(mode, MLX5E_DIM_DEFAULT_PROFILE);
1838
1839         /* apply LRO restrictions */
1840         if (priv->params.hw_lro_en &&
1841             ptr->pkts > MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO) {
1842                 ptr->pkts = MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO;
1843         }
1844 }
1845
1846 static void
1847 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1848     struct mlx5e_cq_param *param)
1849 {
1850         struct net_dim_cq_moder curr;
1851         void *cqc = param->cqc;
1852
1853
1854         /*
1855          * TODO The sysctl to control on/off is a bool value for now, which means
1856          * we only support CSUM, once HASH is implemnted we'll need to address that.
1857          */
1858         if (priv->params.cqe_zipping_en) {
1859                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1860                 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
1861         }
1862
1863         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1864
1865         switch (priv->params.rx_cq_moderation_mode) {
1866         case 0:
1867                 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1868                 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1869                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1870                 break;
1871         case 1:
1872                 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1873                 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1874                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1875                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1876                 else
1877                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1878                 break;
1879         case 2:
1880                 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr);
1881                 MLX5_SET(cqc, cqc, cq_period, curr.usec);
1882                 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
1883                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1884                 break;
1885         case 3:
1886                 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr);
1887                 MLX5_SET(cqc, cqc, cq_period, curr.usec);
1888                 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
1889                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1890                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1891                 else
1892                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1893                 break;
1894         default:
1895                 break;
1896         }
1897
1898         mlx5e_dim_build_cq_param(priv, param);
1899
1900         mlx5e_build_common_cq_param(priv, param);
1901 }
1902
1903 static void
1904 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1905     struct mlx5e_cq_param *param)
1906 {
1907         void *cqc = param->cqc;
1908
1909         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1910         MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
1911         MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
1912
1913         switch (priv->params.tx_cq_moderation_mode) {
1914         case 0:
1915                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1916                 break;
1917         default:
1918                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1919                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1920                 else
1921                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1922                 break;
1923         }
1924
1925         mlx5e_build_common_cq_param(priv, param);
1926 }
1927
1928 static void
1929 mlx5e_build_channel_param(struct mlx5e_priv *priv,
1930     struct mlx5e_channel_param *cparam)
1931 {
1932         memset(cparam, 0, sizeof(*cparam));
1933
1934         mlx5e_build_rq_param(priv, &cparam->rq);
1935         mlx5e_build_sq_param(priv, &cparam->sq);
1936         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1937         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1938 }
1939
1940 static int
1941 mlx5e_open_channels(struct mlx5e_priv *priv)
1942 {
1943         struct mlx5e_channel_param cparam;
1944         int err;
1945         int i;
1946         int j;
1947
1948         mlx5e_build_channel_param(priv, &cparam);
1949         for (i = 0; i < priv->params.num_channels; i++) {
1950                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1951                 if (err)
1952                         goto err_close_channels;
1953         }
1954
1955         for (j = 0; j < priv->params.num_channels; j++) {
1956                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j].rq);
1957                 if (err)
1958                         goto err_close_channels;
1959         }
1960
1961         return (0);
1962
1963 err_close_channels:
1964         while (i--) {
1965                 mlx5e_close_channel(&priv->channel[i]);
1966                 mlx5e_close_channel_wait(&priv->channel[i]);
1967         }
1968         return (err);
1969 }
1970
1971 static void
1972 mlx5e_close_channels(struct mlx5e_priv *priv)
1973 {
1974         int i;
1975
1976         for (i = 0; i < priv->params.num_channels; i++)
1977                 mlx5e_close_channel(&priv->channel[i]);
1978         for (i = 0; i < priv->params.num_channels; i++)
1979                 mlx5e_close_channel_wait(&priv->channel[i]);
1980 }
1981
1982 static int
1983 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
1984 {
1985
1986         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
1987                 uint8_t cq_mode;
1988
1989                 switch (priv->params.tx_cq_moderation_mode) {
1990                 case 0:
1991                 case 2:
1992                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1993                         break;
1994                 default:
1995                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
1996                         break;
1997                 }
1998
1999                 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq,
2000                     priv->params.tx_cq_moderation_usec,
2001                     priv->params.tx_cq_moderation_pkts,
2002                     cq_mode));
2003         }
2004
2005         return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
2006             priv->params.tx_cq_moderation_usec,
2007             priv->params.tx_cq_moderation_pkts));
2008 }
2009
2010 static int
2011 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
2012 {
2013
2014         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2015                 uint8_t cq_mode;
2016                 uint8_t dim_mode;
2017                 int retval;
2018
2019                 switch (priv->params.rx_cq_moderation_mode) {
2020                 case 0:
2021                 case 2:
2022                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2023                         dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2024                         break;
2025                 default:
2026                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2027                         dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
2028                         break;
2029                 }
2030
2031                 /* tear down dynamic interrupt moderation */
2032                 mtx_lock(&rq->mtx);
2033                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
2034                 mtx_unlock(&rq->mtx);
2035
2036                 /* wait for dynamic interrupt moderation work task, if any */
2037                 cancel_work_sync(&rq->dim.work);
2038
2039                 if (priv->params.rx_cq_moderation_mode >= 2) {
2040                         struct net_dim_cq_moder curr;
2041
2042                         mlx5e_get_default_profile(priv, dim_mode, &curr);
2043
2044                         retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2045                             curr.usec, curr.pkts, cq_mode);
2046
2047                         /* set dynamic interrupt moderation mode and zero defaults */
2048                         mtx_lock(&rq->mtx);
2049                         rq->dim.mode = dim_mode;
2050                         rq->dim.state = 0;
2051                         rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE;
2052                         mtx_unlock(&rq->mtx);
2053                 } else {
2054                         retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2055                             priv->params.rx_cq_moderation_usec,
2056                             priv->params.rx_cq_moderation_pkts,
2057                             cq_mode);
2058                 }
2059                 return (retval);
2060         }
2061
2062         return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
2063             priv->params.rx_cq_moderation_usec,
2064             priv->params.rx_cq_moderation_pkts));
2065 }
2066
2067 static int
2068 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
2069 {
2070         int err;
2071         int i;
2072
2073         err = mlx5e_refresh_rq_params(priv, &c->rq);
2074         if (err)
2075                 goto done;
2076
2077         for (i = 0; i != c->num_tc; i++) {
2078                 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
2079                 if (err)
2080                         goto done;
2081         }
2082 done:
2083         return (err);
2084 }
2085
2086 int
2087 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
2088 {
2089         int i;
2090
2091         /* check if channels are closed */
2092         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2093                 return (EINVAL);
2094
2095         for (i = 0; i < priv->params.num_channels; i++) {
2096                 int err;
2097
2098                 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]);
2099                 if (err)
2100                         return (err);
2101         }
2102         return (0);
2103 }
2104
2105 static int
2106 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
2107 {
2108         struct mlx5_core_dev *mdev = priv->mdev;
2109         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
2110         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2111
2112         memset(in, 0, sizeof(in));
2113
2114         MLX5_SET(tisc, tisc, prio, tc);
2115         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
2116
2117         return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
2118 }
2119
2120 static void
2121 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
2122 {
2123         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2124 }
2125
2126 static int
2127 mlx5e_open_tises(struct mlx5e_priv *priv)
2128 {
2129         int num_tc = priv->num_tc;
2130         int err;
2131         int tc;
2132
2133         for (tc = 0; tc < num_tc; tc++) {
2134                 err = mlx5e_open_tis(priv, tc);
2135                 if (err)
2136                         goto err_close_tises;
2137         }
2138
2139         return (0);
2140
2141 err_close_tises:
2142         for (tc--; tc >= 0; tc--)
2143                 mlx5e_close_tis(priv, tc);
2144
2145         return (err);
2146 }
2147
2148 static void
2149 mlx5e_close_tises(struct mlx5e_priv *priv)
2150 {
2151         int num_tc = priv->num_tc;
2152         int tc;
2153
2154         for (tc = 0; tc < num_tc; tc++)
2155                 mlx5e_close_tis(priv, tc);
2156 }
2157
2158 static int
2159 mlx5e_open_rqt(struct mlx5e_priv *priv)
2160 {
2161         struct mlx5_core_dev *mdev = priv->mdev;
2162         u32 *in;
2163         u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
2164         void *rqtc;
2165         int inlen;
2166         int err;
2167         int sz;
2168         int i;
2169
2170         sz = 1 << priv->params.rx_hash_log_tbl_sz;
2171
2172         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2173         in = mlx5_vzalloc(inlen);
2174         if (in == NULL)
2175                 return (-ENOMEM);
2176         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2177
2178         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2179         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2180
2181         for (i = 0; i < sz; i++) {
2182                 int ix = i;
2183 #ifdef RSS
2184                 ix = rss_get_indirection_to_bucket(ix);
2185 #endif
2186                 /* ensure we don't overflow */
2187                 ix %= priv->params.num_channels;
2188
2189                 /* apply receive side scaling stride, if any */
2190                 ix -= ix % (int)priv->params.channels_rsss;
2191
2192                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn);
2193         }
2194
2195         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
2196
2197         err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
2198         if (!err)
2199                 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
2200
2201         kvfree(in);
2202
2203         return (err);
2204 }
2205
2206 static void
2207 mlx5e_close_rqt(struct mlx5e_priv *priv)
2208 {
2209         u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0};
2210         u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0};
2211
2212         MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
2213         MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
2214
2215         mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out));
2216 }
2217
2218 static void
2219 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
2220 {
2221         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2222         __be32 *hkey;
2223
2224         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2225
2226 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2227
2228 #define MLX5_HASH_IP     (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2229                           MLX5_HASH_FIELD_SEL_DST_IP)
2230
2231 #define MLX5_HASH_ALL    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2232                           MLX5_HASH_FIELD_SEL_DST_IP   |\
2233                           MLX5_HASH_FIELD_SEL_L4_SPORT |\
2234                           MLX5_HASH_FIELD_SEL_L4_DPORT)
2235
2236 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2237                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2238                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2239
2240         if (priv->params.hw_lro_en) {
2241                 MLX5_SET(tirc, tirc, lro_enable_mask,
2242                     MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2243                     MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2244                 MLX5_SET(tirc, tirc, lro_max_msg_sz,
2245                     (priv->params.lro_wqe_sz -
2246                     ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2247                 /* TODO: add the option to choose timer value dynamically */
2248                 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
2249                     MLX5_CAP_ETH(priv->mdev,
2250                     lro_timer_supported_periods[2]));
2251         }
2252
2253         /* setup parameters for hashing TIR type, if any */
2254         switch (tt) {
2255         case MLX5E_TT_ANY:
2256                 MLX5_SET(tirc, tirc, disp_type,
2257                     MLX5_TIRC_DISP_TYPE_DIRECT);
2258                 MLX5_SET(tirc, tirc, inline_rqn,
2259                     priv->channel[0].rq.rqn);
2260                 break;
2261         default:
2262                 MLX5_SET(tirc, tirc, disp_type,
2263                     MLX5_TIRC_DISP_TYPE_INDIRECT);
2264                 MLX5_SET(tirc, tirc, indirect_table,
2265                     priv->rqtn);
2266                 MLX5_SET(tirc, tirc, rx_hash_fn,
2267                     MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
2268                 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
2269 #ifdef RSS
2270                 /*
2271                  * The FreeBSD RSS implementation does currently not
2272                  * support symmetric Toeplitz hashes:
2273                  */
2274                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
2275                 rss_getkey((uint8_t *)hkey);
2276 #else
2277                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2278                 hkey[0] = cpu_to_be32(0xD181C62C);
2279                 hkey[1] = cpu_to_be32(0xF7F4DB5B);
2280                 hkey[2] = cpu_to_be32(0x1983A2FC);
2281                 hkey[3] = cpu_to_be32(0x943E1ADB);
2282                 hkey[4] = cpu_to_be32(0xD9389E6B);
2283                 hkey[5] = cpu_to_be32(0xD1039C2C);
2284                 hkey[6] = cpu_to_be32(0xA74499AD);
2285                 hkey[7] = cpu_to_be32(0x593D56D9);
2286                 hkey[8] = cpu_to_be32(0xF3253C06);
2287                 hkey[9] = cpu_to_be32(0x2ADC1FFC);
2288 #endif
2289                 break;
2290         }
2291
2292         switch (tt) {
2293         case MLX5E_TT_IPV4_TCP:
2294                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2295                     MLX5_L3_PROT_TYPE_IPV4);
2296                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2297                     MLX5_L4_PROT_TYPE_TCP);
2298 #ifdef RSS
2299                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2300                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2301                             MLX5_HASH_IP);
2302                 } else
2303 #endif
2304                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2305                     MLX5_HASH_ALL);
2306                 break;
2307
2308         case MLX5E_TT_IPV6_TCP:
2309                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2310                     MLX5_L3_PROT_TYPE_IPV6);
2311                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2312                     MLX5_L4_PROT_TYPE_TCP);
2313 #ifdef RSS
2314                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2315                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2316                             MLX5_HASH_IP);
2317                 } else
2318 #endif
2319                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2320                     MLX5_HASH_ALL);
2321                 break;
2322
2323         case MLX5E_TT_IPV4_UDP:
2324                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2325                     MLX5_L3_PROT_TYPE_IPV4);
2326                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2327                     MLX5_L4_PROT_TYPE_UDP);
2328 #ifdef RSS
2329                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2330                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2331                             MLX5_HASH_IP);
2332                 } else
2333 #endif
2334                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2335                     MLX5_HASH_ALL);
2336                 break;
2337
2338         case MLX5E_TT_IPV6_UDP:
2339                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2340                     MLX5_L3_PROT_TYPE_IPV6);
2341                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2342                     MLX5_L4_PROT_TYPE_UDP);
2343 #ifdef RSS
2344                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2345                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2346                             MLX5_HASH_IP);
2347                 } else
2348 #endif
2349                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2350                     MLX5_HASH_ALL);
2351                 break;
2352
2353         case MLX5E_TT_IPV4_IPSEC_AH:
2354                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2355                     MLX5_L3_PROT_TYPE_IPV4);
2356                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2357                     MLX5_HASH_IP_IPSEC_SPI);
2358                 break;
2359
2360         case MLX5E_TT_IPV6_IPSEC_AH:
2361                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2362                     MLX5_L3_PROT_TYPE_IPV6);
2363                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2364                     MLX5_HASH_IP_IPSEC_SPI);
2365                 break;
2366
2367         case MLX5E_TT_IPV4_IPSEC_ESP:
2368                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2369                     MLX5_L3_PROT_TYPE_IPV4);
2370                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2371                     MLX5_HASH_IP_IPSEC_SPI);
2372                 break;
2373
2374         case MLX5E_TT_IPV6_IPSEC_ESP:
2375                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2376                     MLX5_L3_PROT_TYPE_IPV6);
2377                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2378                     MLX5_HASH_IP_IPSEC_SPI);
2379                 break;
2380
2381         case MLX5E_TT_IPV4:
2382                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2383                     MLX5_L3_PROT_TYPE_IPV4);
2384                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2385                     MLX5_HASH_IP);
2386                 break;
2387
2388         case MLX5E_TT_IPV6:
2389                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2390                     MLX5_L3_PROT_TYPE_IPV6);
2391                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2392                     MLX5_HASH_IP);
2393                 break;
2394
2395         default:
2396                 break;
2397         }
2398 }
2399
2400 static int
2401 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2402 {
2403         struct mlx5_core_dev *mdev = priv->mdev;
2404         u32 *in;
2405         void *tirc;
2406         int inlen;
2407         int err;
2408
2409         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2410         in = mlx5_vzalloc(inlen);
2411         if (in == NULL)
2412                 return (-ENOMEM);
2413         tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2414
2415         mlx5e_build_tir_ctx(priv, tirc, tt);
2416
2417         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2418
2419         kvfree(in);
2420
2421         return (err);
2422 }
2423
2424 static void
2425 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2426 {
2427         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2428 }
2429
2430 static int
2431 mlx5e_open_tirs(struct mlx5e_priv *priv)
2432 {
2433         int err;
2434         int i;
2435
2436         for (i = 0; i < MLX5E_NUM_TT; i++) {
2437                 err = mlx5e_open_tir(priv, i);
2438                 if (err)
2439                         goto err_close_tirs;
2440         }
2441
2442         return (0);
2443
2444 err_close_tirs:
2445         for (i--; i >= 0; i--)
2446                 mlx5e_close_tir(priv, i);
2447
2448         return (err);
2449 }
2450
2451 static void
2452 mlx5e_close_tirs(struct mlx5e_priv *priv)
2453 {
2454         int i;
2455
2456         for (i = 0; i < MLX5E_NUM_TT; i++)
2457                 mlx5e_close_tir(priv, i);
2458 }
2459
2460 /*
2461  * SW MTU does not include headers,
2462  * HW MTU includes all headers and checksums.
2463  */
2464 static int
2465 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2466 {
2467         struct mlx5e_priv *priv = ifp->if_softc;
2468         struct mlx5_core_dev *mdev = priv->mdev;
2469         int hw_mtu;
2470         int err;
2471
2472         hw_mtu = MLX5E_SW2HW_MTU(sw_mtu);
2473
2474         err = mlx5_set_port_mtu(mdev, hw_mtu);
2475         if (err) {
2476                 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n",
2477                     __func__, sw_mtu, err);
2478                 return (err);
2479         }
2480
2481         /* Update vport context MTU */
2482         err = mlx5_set_vport_mtu(mdev, hw_mtu);
2483         if (err) {
2484                 if_printf(ifp, "%s: Failed updating vport context with MTU size, err=%d\n",
2485                     __func__, err);
2486         }
2487
2488         ifp->if_mtu = sw_mtu;
2489
2490         err = mlx5_query_vport_mtu(mdev, &hw_mtu);
2491         if (err || !hw_mtu) {
2492                 /* fallback to port oper mtu */
2493                 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2494         }
2495         if (err) {
2496                 if_printf(ifp, "Query port MTU, after setting new "
2497                     "MTU value, failed\n");
2498                 return (err);
2499         } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
2500                 err = -E2BIG,
2501                 if_printf(ifp, "Port MTU %d is smaller than "
2502                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2503         } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
2504                 err = -EINVAL;
2505                 if_printf(ifp, "Port MTU %d is bigger than "
2506                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2507         }
2508         priv->params_ethtool.hw_mtu = hw_mtu;
2509
2510         return (err);
2511 }
2512
2513 int
2514 mlx5e_open_locked(struct ifnet *ifp)
2515 {
2516         struct mlx5e_priv *priv = ifp->if_softc;
2517         int err;
2518         u16 set_id;
2519
2520         /* check if already opened */
2521         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2522                 return (0);
2523
2524 #ifdef RSS
2525         if (rss_getnumbuckets() > priv->params.num_channels) {
2526                 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than "
2527                     "channels(%u) available\n", rss_getnumbuckets(),
2528                     priv->params.num_channels);
2529         }
2530 #endif
2531         err = mlx5e_open_tises(priv);
2532         if (err) {
2533                 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n",
2534                     __func__, err);
2535                 return (err);
2536         }
2537         err = mlx5_vport_alloc_q_counter(priv->mdev,
2538             MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
2539         if (err) {
2540                 if_printf(priv->ifp,
2541                     "%s: mlx5_vport_alloc_q_counter failed: %d\n",
2542                     __func__, err);
2543                 goto err_close_tises;
2544         }
2545         /* store counter set ID */
2546         priv->counter_set_id = set_id;
2547
2548         err = mlx5e_open_channels(priv);
2549         if (err) {
2550                 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n",
2551                     __func__, err);
2552                 goto err_dalloc_q_counter;
2553         }
2554         err = mlx5e_open_rqt(priv);
2555         if (err) {
2556                 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n",
2557                     __func__, err);
2558                 goto err_close_channels;
2559         }
2560         err = mlx5e_open_tirs(priv);
2561         if (err) {
2562                 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n",
2563                     __func__, err);
2564                 goto err_close_rqls;
2565         }
2566         err = mlx5e_open_flow_table(priv);
2567         if (err) {
2568                 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n",
2569                     __func__, err);
2570                 goto err_close_tirs;
2571         }
2572         err = mlx5e_add_all_vlan_rules(priv);
2573         if (err) {
2574                 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
2575                     __func__, err);
2576                 goto err_close_flow_table;
2577         }
2578         set_bit(MLX5E_STATE_OPENED, &priv->state);
2579
2580         mlx5e_update_carrier(priv);
2581         mlx5e_set_rx_mode_core(priv);
2582
2583         return (0);
2584
2585 err_close_flow_table:
2586         mlx5e_close_flow_table(priv);
2587
2588 err_close_tirs:
2589         mlx5e_close_tirs(priv);
2590
2591 err_close_rqls:
2592         mlx5e_close_rqt(priv);
2593
2594 err_close_channels:
2595         mlx5e_close_channels(priv);
2596
2597 err_dalloc_q_counter:
2598         mlx5_vport_dealloc_q_counter(priv->mdev,
2599             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2600
2601 err_close_tises:
2602         mlx5e_close_tises(priv);
2603
2604         return (err);
2605 }
2606
2607 static void
2608 mlx5e_open(void *arg)
2609 {
2610         struct mlx5e_priv *priv = arg;
2611
2612         PRIV_LOCK(priv);
2613         if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
2614                 if_printf(priv->ifp,
2615                     "%s: Setting port status to up failed\n",
2616                     __func__);
2617
2618         mlx5e_open_locked(priv->ifp);
2619         priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
2620         PRIV_UNLOCK(priv);
2621 }
2622
2623 int
2624 mlx5e_close_locked(struct ifnet *ifp)
2625 {
2626         struct mlx5e_priv *priv = ifp->if_softc;
2627
2628         /* check if already closed */
2629         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2630                 return (0);
2631
2632         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2633
2634         mlx5e_set_rx_mode_core(priv);
2635         mlx5e_del_all_vlan_rules(priv);
2636         if_link_state_change(priv->ifp, LINK_STATE_DOWN);
2637         mlx5e_close_flow_table(priv);
2638         mlx5e_close_tirs(priv);
2639         mlx5e_close_rqt(priv);
2640         mlx5e_close_channels(priv);
2641         mlx5_vport_dealloc_q_counter(priv->mdev,
2642             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2643         mlx5e_close_tises(priv);
2644
2645         return (0);
2646 }
2647
2648 #if (__FreeBSD_version >= 1100000)
2649 static uint64_t
2650 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
2651 {
2652         struct mlx5e_priv *priv = ifp->if_softc;
2653         u64 retval;
2654
2655         /* PRIV_LOCK(priv); XXX not allowed */
2656         switch (cnt) {
2657         case IFCOUNTER_IPACKETS:
2658                 retval = priv->stats.vport.rx_packets;
2659                 break;
2660         case IFCOUNTER_IERRORS:
2661                 retval = priv->stats.vport.rx_error_packets +
2662                     priv->stats.pport.alignment_err +
2663                     priv->stats.pport.check_seq_err +
2664                     priv->stats.pport.crc_align_errors +
2665                     priv->stats.pport.in_range_len_errors +
2666                     priv->stats.pport.jabbers +
2667                     priv->stats.pport.out_of_range_len +
2668                     priv->stats.pport.oversize_pkts +
2669                     priv->stats.pport.symbol_err +
2670                     priv->stats.pport.too_long_errors +
2671                     priv->stats.pport.undersize_pkts +
2672                     priv->stats.pport.unsupported_op_rx;
2673                 break;
2674         case IFCOUNTER_IQDROPS:
2675                 retval = priv->stats.vport.rx_out_of_buffer +
2676                     priv->stats.pport.drop_events;
2677                 break;
2678         case IFCOUNTER_OPACKETS:
2679                 retval = priv->stats.vport.tx_packets;
2680                 break;
2681         case IFCOUNTER_OERRORS:
2682                 retval = priv->stats.vport.tx_error_packets;
2683                 break;
2684         case IFCOUNTER_IBYTES:
2685                 retval = priv->stats.vport.rx_bytes;
2686                 break;
2687         case IFCOUNTER_OBYTES:
2688                 retval = priv->stats.vport.tx_bytes;
2689                 break;
2690         case IFCOUNTER_IMCASTS:
2691                 retval = priv->stats.vport.rx_multicast_packets;
2692                 break;
2693         case IFCOUNTER_OMCASTS:
2694                 retval = priv->stats.vport.tx_multicast_packets;
2695                 break;
2696         case IFCOUNTER_OQDROPS:
2697                 retval = priv->stats.vport.tx_queue_dropped;
2698                 break;
2699         case IFCOUNTER_COLLISIONS:
2700                 retval = priv->stats.pport.collisions;
2701                 break;
2702         default:
2703                 retval = if_get_counter_default(ifp, cnt);
2704                 break;
2705         }
2706         /* PRIV_UNLOCK(priv); XXX not allowed */
2707         return (retval);
2708 }
2709 #endif
2710
2711 static void
2712 mlx5e_set_rx_mode(struct ifnet *ifp)
2713 {
2714         struct mlx5e_priv *priv = ifp->if_softc;
2715
2716         queue_work(priv->wq, &priv->set_rx_mode_work);
2717 }
2718
2719 static int
2720 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2721 {
2722         struct mlx5e_priv *priv;
2723         struct ifreq *ifr;
2724         struct ifi2creq i2c;
2725         int error = 0;
2726         int mask = 0;
2727         int size_read = 0;
2728         int module_status;
2729         int module_num;
2730         int max_mtu;
2731         uint8_t read_addr;
2732
2733         priv = ifp->if_softc;
2734
2735         /* check if detaching */
2736         if (priv == NULL || priv->gone != 0)
2737                 return (ENXIO);
2738
2739         switch (command) {
2740         case SIOCSIFMTU:
2741                 ifr = (struct ifreq *)data;
2742
2743                 PRIV_LOCK(priv);
2744                 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
2745
2746                 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
2747                     ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
2748                         int was_opened;
2749
2750                         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2751                         if (was_opened)
2752                                 mlx5e_close_locked(ifp);
2753
2754                         /* set new MTU */
2755                         mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
2756
2757                         if (was_opened)
2758                                 mlx5e_open_locked(ifp);
2759                 } else {
2760                         error = EINVAL;
2761                         if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n",
2762                             MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
2763                 }
2764                 PRIV_UNLOCK(priv);
2765                 break;
2766         case SIOCSIFFLAGS:
2767                 if ((ifp->if_flags & IFF_UP) &&
2768                     (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2769                         mlx5e_set_rx_mode(ifp);
2770                         break;
2771                 }
2772                 PRIV_LOCK(priv);
2773                 if (ifp->if_flags & IFF_UP) {
2774                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2775                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2776                                         mlx5e_open_locked(ifp);
2777                                 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2778                                 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
2779                         }
2780                 } else {
2781                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2782                                 mlx5_set_port_status(priv->mdev,
2783                                     MLX5_PORT_DOWN);
2784                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2785                                         mlx5e_close_locked(ifp);
2786                                 mlx5e_update_carrier(priv);
2787                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2788                         }
2789                 }
2790                 PRIV_UNLOCK(priv);
2791                 break;
2792         case SIOCADDMULTI:
2793         case SIOCDELMULTI:
2794                 mlx5e_set_rx_mode(ifp);
2795                 break;
2796         case SIOCSIFMEDIA:
2797         case SIOCGIFMEDIA:
2798         case SIOCGIFXMEDIA:
2799                 ifr = (struct ifreq *)data;
2800                 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
2801                 break;
2802         case SIOCSIFCAP:
2803                 ifr = (struct ifreq *)data;
2804                 PRIV_LOCK(priv);
2805                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2806
2807                 if (mask & IFCAP_TXCSUM) {
2808                         ifp->if_capenable ^= IFCAP_TXCSUM;
2809                         ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2810
2811                         if (IFCAP_TSO4 & ifp->if_capenable &&
2812                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2813                                 ifp->if_capenable &= ~IFCAP_TSO4;
2814                                 ifp->if_hwassist &= ~CSUM_IP_TSO;
2815                                 if_printf(ifp,
2816                                     "tso4 disabled due to -txcsum.\n");
2817                         }
2818                 }
2819                 if (mask & IFCAP_TXCSUM_IPV6) {
2820                         ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
2821                         ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2822
2823                         if (IFCAP_TSO6 & ifp->if_capenable &&
2824                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2825                                 ifp->if_capenable &= ~IFCAP_TSO6;
2826                                 ifp->if_hwassist &= ~CSUM_IP6_TSO;
2827                                 if_printf(ifp,
2828                                     "tso6 disabled due to -txcsum6.\n");
2829                         }
2830                 }
2831                 if (mask & IFCAP_RXCSUM)
2832                         ifp->if_capenable ^= IFCAP_RXCSUM;
2833                 if (mask & IFCAP_RXCSUM_IPV6)
2834                         ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
2835                 if (mask & IFCAP_TSO4) {
2836                         if (!(IFCAP_TSO4 & ifp->if_capenable) &&
2837                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2838                                 if_printf(ifp, "enable txcsum first.\n");
2839                                 error = EAGAIN;
2840                                 goto out;
2841                         }
2842                         ifp->if_capenable ^= IFCAP_TSO4;
2843                         ifp->if_hwassist ^= CSUM_IP_TSO;
2844                 }
2845                 if (mask & IFCAP_TSO6) {
2846                         if (!(IFCAP_TSO6 & ifp->if_capenable) &&
2847                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2848                                 if_printf(ifp, "enable txcsum6 first.\n");
2849                                 error = EAGAIN;
2850                                 goto out;
2851                         }
2852                         ifp->if_capenable ^= IFCAP_TSO6;
2853                         ifp->if_hwassist ^= CSUM_IP6_TSO;
2854                 }
2855                 if (mask & IFCAP_VLAN_HWFILTER) {
2856                         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
2857                                 mlx5e_disable_vlan_filter(priv);
2858                         else
2859                                 mlx5e_enable_vlan_filter(priv);
2860
2861                         ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
2862                 }
2863                 if (mask & IFCAP_VLAN_HWTAGGING)
2864                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2865                 if (mask & IFCAP_WOL_MAGIC)
2866                         ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2867
2868                 VLAN_CAPABILITIES(ifp);
2869                 /* turn off LRO means also turn of HW LRO - if it's on */
2870                 if (mask & IFCAP_LRO) {
2871                         int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2872                         bool need_restart = false;
2873
2874                         ifp->if_capenable ^= IFCAP_LRO;
2875
2876                         /* figure out if updating HW LRO is needed */
2877                         if (!(ifp->if_capenable & IFCAP_LRO)) {
2878                                 if (priv->params.hw_lro_en) {
2879                                         priv->params.hw_lro_en = false;
2880                                         need_restart = true;
2881                                 }
2882                         } else {
2883                                 if (priv->params.hw_lro_en == false &&
2884                                     priv->params_ethtool.hw_lro != 0) {
2885                                         priv->params.hw_lro_en = true;
2886                                         need_restart = true;
2887                                 }
2888                         }
2889                         if (was_opened && need_restart) {
2890                                 mlx5e_close_locked(ifp);
2891                                 mlx5e_open_locked(ifp);
2892                         }
2893                 }
2894 out:
2895                 PRIV_UNLOCK(priv);
2896                 break;
2897
2898         case SIOCGI2C:
2899                 ifr = (struct ifreq *)data;
2900
2901                 /*
2902                  * Copy from the user-space address ifr_data to the
2903                  * kernel-space address i2c
2904                  */
2905                 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
2906                 if (error)
2907                         break;
2908
2909                 if (i2c.len > sizeof(i2c.data)) {
2910                         error = EINVAL;
2911                         break;
2912                 }
2913
2914                 PRIV_LOCK(priv);
2915                 /* Get module_num which is required for the query_eeprom */
2916                 error = mlx5_query_module_num(priv->mdev, &module_num);
2917                 if (error) {
2918                         if_printf(ifp, "Query module num failed, eeprom "
2919                             "reading is not supported\n");
2920                         error = EINVAL;
2921                         goto err_i2c;
2922                 }
2923                 /* Check if module is present before doing an access */
2924                 module_status = mlx5_query_module_status(priv->mdev, module_num);
2925                 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED &&
2926                     module_status != MLX5_MODULE_STATUS_PLUGGED_DISABLED) {
2927                         error = EINVAL;
2928                         goto err_i2c;
2929                 }
2930                 /*
2931                  * Currently 0XA0 and 0xA2 are the only addresses permitted.
2932                  * The internal conversion is as follows:
2933                  */
2934                 if (i2c.dev_addr == 0xA0)
2935                         read_addr = MLX5E_I2C_ADDR_LOW;
2936                 else if (i2c.dev_addr == 0xA2)
2937                         read_addr = MLX5E_I2C_ADDR_HIGH;
2938                 else {
2939                         if_printf(ifp, "Query eeprom failed, "
2940                             "Invalid Address: %X\n", i2c.dev_addr);
2941                         error = EINVAL;
2942                         goto err_i2c;
2943                 }
2944                 error = mlx5_query_eeprom(priv->mdev,
2945                     read_addr, MLX5E_EEPROM_LOW_PAGE,
2946                     (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
2947                     (uint32_t *)i2c.data, &size_read);
2948                 if (error) {
2949                         if_printf(ifp, "Query eeprom failed, eeprom "
2950                             "reading is not supported\n");
2951                         error = EINVAL;
2952                         goto err_i2c;
2953                 }
2954
2955                 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
2956                         error = mlx5_query_eeprom(priv->mdev,
2957                             read_addr, MLX5E_EEPROM_LOW_PAGE,
2958                             (uint32_t)(i2c.offset + size_read),
2959                             (uint32_t)(i2c.len - size_read), module_num,
2960                             (uint32_t *)(i2c.data + size_read), &size_read);
2961                 }
2962                 if (error) {
2963                         if_printf(ifp, "Query eeprom failed, eeprom "
2964                             "reading is not supported\n");
2965                         error = EINVAL;
2966                         goto err_i2c;
2967                 }
2968
2969                 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
2970 err_i2c:
2971                 PRIV_UNLOCK(priv);
2972                 break;
2973
2974         default:
2975                 error = ether_ioctl(ifp, command, data);
2976                 break;
2977         }
2978         return (error);
2979 }
2980
2981 static int
2982 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2983 {
2984         /*
2985          * TODO: uncoment once FW really sets all these bits if
2986          * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
2987          * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
2988          * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
2989          * -ENOTSUPP;
2990          */
2991
2992         /* TODO: add more must-to-have features */
2993
2994         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2995                 return (-ENODEV);
2996
2997         return (0);
2998 }
2999
3000 static u16
3001 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3002 {
3003         uint32_t bf_buf_size = (1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U;
3004
3005         bf_buf_size -= sizeof(struct mlx5e_tx_wqe) - 2;
3006
3007         /* verify against driver hardware limit */
3008         if (bf_buf_size > MLX5E_MAX_TX_INLINE)
3009                 bf_buf_size = MLX5E_MAX_TX_INLINE;
3010
3011         return (bf_buf_size);
3012 }
3013
3014 static int
3015 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
3016     struct mlx5e_priv *priv,
3017     int num_comp_vectors)
3018 {
3019         int err;
3020
3021         /*
3022          * TODO: Consider link speed for setting "log_sq_size",
3023          * "log_rq_size" and "cq_moderation_xxx":
3024          */
3025         priv->params.log_sq_size =
3026             MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3027         priv->params.log_rq_size =
3028             MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3029         priv->params.rx_cq_moderation_usec =
3030             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3031             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
3032             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3033         priv->params.rx_cq_moderation_mode =
3034             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
3035         priv->params.rx_cq_moderation_pkts =
3036             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3037         priv->params.tx_cq_moderation_usec =
3038             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3039         priv->params.tx_cq_moderation_pkts =
3040             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3041         priv->params.min_rx_wqes =
3042             MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
3043         priv->params.rx_hash_log_tbl_sz =
3044             (order_base_2(num_comp_vectors) >
3045             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
3046             order_base_2(num_comp_vectors) :
3047             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
3048         priv->params.num_tc = 1;
3049         priv->params.default_vlan_prio = 0;
3050         priv->counter_set_id = -1;
3051         priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3052
3053         err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3054         if (err)
3055                 return (err);
3056
3057         /*
3058          * hw lro is currently defaulted to off. when it won't anymore we
3059          * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
3060          */
3061         priv->params.hw_lro_en = false;
3062         priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3063
3064         /*
3065          * CQE zipping is currently defaulted to off. when it won't
3066          * anymore we will consider the HW capability:
3067          * "!!MLX5_CAP_GEN(mdev, cqe_compression)"
3068          */
3069         priv->params.cqe_zipping_en = false;
3070
3071         priv->mdev = mdev;
3072         priv->params.num_channels = num_comp_vectors;
3073         priv->params.channels_rsss = 1;
3074         priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
3075         priv->queue_mapping_channel_mask =
3076             roundup_pow_of_two(num_comp_vectors) - 1;
3077         priv->num_tc = priv->params.num_tc;
3078         priv->default_vlan_prio = priv->params.default_vlan_prio;
3079
3080         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3081         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3082         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3083
3084         return (0);
3085 }
3086
3087 static int
3088 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
3089                   struct mlx5_core_mr *mkey)
3090 {
3091         struct ifnet *ifp = priv->ifp;
3092         struct mlx5_core_dev *mdev = priv->mdev;
3093         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3094         void *mkc;
3095         u32 *in;
3096         int err;
3097
3098         in = mlx5_vzalloc(inlen);
3099         if (in == NULL) {
3100                 if_printf(ifp, "%s: failed to allocate inbox\n", __func__);
3101                 return (-ENOMEM);
3102         }
3103
3104         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3105         MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA);
3106         MLX5_SET(mkc, mkc, lw, 1);
3107         MLX5_SET(mkc, mkc, lr, 1);
3108
3109         MLX5_SET(mkc, mkc, pd, pdn);
3110         MLX5_SET(mkc, mkc, length64, 1);
3111         MLX5_SET(mkc, mkc, qpn, 0xffffff);
3112
3113         err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
3114         if (err)
3115                 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n",
3116                     __func__, err);
3117
3118         kvfree(in);
3119         return (err);
3120 }
3121
3122 static const char *mlx5e_vport_stats_desc[] = {
3123         MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
3124 };
3125
3126 static const char *mlx5e_pport_stats_desc[] = {
3127         MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
3128 };
3129
3130 static void
3131 mlx5e_priv_mtx_init(struct mlx5e_priv *priv)
3132 {
3133         mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
3134         sx_init(&priv->state_lock, "mlx5state");
3135         callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
3136         MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
3137 }
3138
3139 static void
3140 mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv)
3141 {
3142         mtx_destroy(&priv->async_events_mtx);
3143         sx_destroy(&priv->state_lock);
3144 }
3145
3146 static int
3147 sysctl_firmware(SYSCTL_HANDLER_ARGS)
3148 {
3149         /*
3150          * %d.%d%.d the string format.
3151          * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
3152          * We need at most 5 chars to store that.
3153          * It also has: two "." and NULL at the end, which means we need 18
3154          * (5*3 + 3) chars at most.
3155          */
3156         char fw[18];
3157         struct mlx5e_priv *priv = arg1;
3158         int error;
3159
3160         snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
3161             fw_rev_sub(priv->mdev));
3162         error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
3163         return (error);
3164 }
3165
3166 static void
3167 mlx5e_disable_tx_dma(struct mlx5e_channel *ch)
3168 {
3169         int i;
3170
3171         for (i = 0; i < ch->num_tc; i++)
3172                 mlx5e_drain_sq(&ch->sq[i]);
3173 }
3174
3175 static void
3176 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq)
3177 {
3178
3179         sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP);
3180         sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8);
3181         mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
3182         sq->doorbell.d64 = 0;
3183 }
3184
3185 void
3186 mlx5e_resume_sq(struct mlx5e_sq *sq)
3187 {
3188         int err;
3189
3190         /* check if already enabled */
3191         if (READ_ONCE(sq->running) != 0)
3192                 return;
3193
3194         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR,
3195             MLX5_SQC_STATE_RST);
3196         if (err != 0) {
3197                 if_printf(sq->ifp,
3198                     "mlx5e_modify_sq() from ERR to RST failed: %d\n", err);
3199         }
3200
3201         sq->cc = 0;
3202         sq->pc = 0;
3203
3204         /* reset doorbell prior to moving from RST to RDY */
3205         mlx5e_reset_sq_doorbell_record(sq);
3206
3207         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST,
3208             MLX5_SQC_STATE_RDY);
3209         if (err != 0) {
3210                 if_printf(sq->ifp,
3211                     "mlx5e_modify_sq() from RST to RDY failed: %d\n", err);
3212         }
3213
3214         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
3215         WRITE_ONCE(sq->running, 1);
3216 }
3217
3218 static void
3219 mlx5e_enable_tx_dma(struct mlx5e_channel *ch)
3220 {
3221         int i;
3222
3223         for (i = 0; i < ch->num_tc; i++)
3224                 mlx5e_resume_sq(&ch->sq[i]);
3225 }
3226
3227 static void
3228 mlx5e_disable_rx_dma(struct mlx5e_channel *ch)
3229 {
3230         struct mlx5e_rq *rq = &ch->rq;
3231         int err;
3232
3233         mtx_lock(&rq->mtx);
3234         rq->enabled = 0;
3235         callout_stop(&rq->watchdog);
3236         mtx_unlock(&rq->mtx);
3237
3238         callout_drain(&rq->watchdog);
3239
3240         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
3241         if (err != 0) {
3242                 if_printf(rq->ifp,
3243                     "mlx5e_modify_rq() from RDY to RST failed: %d\n", err);
3244         }
3245
3246         while (!mlx5_wq_ll_is_empty(&rq->wq)) {
3247                 msleep(1);
3248                 rq->cq.mcq.comp(&rq->cq.mcq);
3249         }
3250
3251         /*
3252          * Transitioning into RST state will allow the FW to track less ERR state queues,
3253          * thus reducing the recv queue flushing time
3254          */
3255         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST);
3256         if (err != 0) {
3257                 if_printf(rq->ifp,
3258                     "mlx5e_modify_rq() from ERR to RST failed: %d\n", err);
3259         }
3260 }
3261
3262 static void
3263 mlx5e_enable_rx_dma(struct mlx5e_channel *ch)
3264 {
3265         struct mlx5e_rq *rq = &ch->rq;
3266         int err;
3267
3268         rq->wq.wqe_ctr = 0;
3269         mlx5_wq_ll_update_db_record(&rq->wq);
3270         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3271         if (err != 0) {
3272                 if_printf(rq->ifp,
3273                     "mlx5e_modify_rq() from RST to RDY failed: %d\n", err);
3274         }
3275
3276         rq->enabled = 1;
3277
3278         rq->cq.mcq.comp(&rq->cq.mcq);
3279 }
3280
3281 void
3282 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value)
3283 {
3284         int i;
3285
3286         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3287                 return;
3288
3289         for (i = 0; i < priv->params.num_channels; i++) {
3290                 if (value)
3291                         mlx5e_disable_tx_dma(&priv->channel[i]);
3292                 else
3293                         mlx5e_enable_tx_dma(&priv->channel[i]);
3294         }
3295 }
3296
3297 void
3298 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value)
3299 {
3300         int i;
3301
3302         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3303                 return;
3304
3305         for (i = 0; i < priv->params.num_channels; i++) {
3306                 if (value)
3307                         mlx5e_disable_rx_dma(&priv->channel[i]);
3308                 else
3309                         mlx5e_enable_rx_dma(&priv->channel[i]);
3310         }
3311 }
3312
3313 static void
3314 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
3315 {
3316         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3317             OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
3318             sysctl_firmware, "A", "HCA firmware version");
3319
3320         SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3321             OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
3322             "Board ID");
3323 }
3324
3325 static int
3326 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3327 {
3328         struct mlx5e_priv *priv = arg1;
3329         uint8_t temp[MLX5E_MAX_PRIORITY];
3330         uint32_t tx_pfc;
3331         int err;
3332         int i;
3333
3334         PRIV_LOCK(priv);
3335
3336         tx_pfc = priv->params.tx_priority_flow_control;
3337
3338         for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3339                 temp[i] = (tx_pfc >> i) & 1;
3340
3341         err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3342         if (err || !req->newptr)
3343                 goto done;
3344         err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3345         if (err)
3346                 goto done;
3347
3348         priv->params.tx_priority_flow_control = 0;
3349
3350         /* range check input value */
3351         for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3352                 if (temp[i] > 1) {
3353                         err = ERANGE;
3354                         goto done;
3355                 }
3356                 priv->params.tx_priority_flow_control |= (temp[i] << i);
3357         }
3358
3359         /* check if update is required */
3360         if (tx_pfc != priv->params.tx_priority_flow_control)
3361                 err = -mlx5e_set_port_pfc(priv);
3362 done:
3363         if (err != 0)
3364                 priv->params.tx_priority_flow_control= tx_pfc;
3365         PRIV_UNLOCK(priv);
3366
3367         return (err);
3368 }
3369
3370 static int
3371 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3372 {
3373         struct mlx5e_priv *priv = arg1;
3374         uint8_t temp[MLX5E_MAX_PRIORITY];
3375         uint32_t rx_pfc;
3376         int err;
3377         int i;
3378
3379         PRIV_LOCK(priv);
3380
3381         rx_pfc = priv->params.rx_priority_flow_control;
3382
3383         for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3384                 temp[i] = (rx_pfc >> i) & 1;
3385
3386         err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3387         if (err || !req->newptr)
3388                 goto done;
3389         err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3390         if (err)
3391                 goto done;
3392
3393         priv->params.rx_priority_flow_control = 0;
3394
3395         /* range check input value */
3396         for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3397                 if (temp[i] > 1) {
3398                         err = ERANGE;
3399                         goto done;
3400                 }
3401                 priv->params.rx_priority_flow_control |= (temp[i] << i);
3402         }
3403
3404         /* check if update is required */
3405         if (rx_pfc != priv->params.rx_priority_flow_control)
3406                 err = -mlx5e_set_port_pfc(priv);
3407 done:
3408         if (err != 0)
3409                 priv->params.rx_priority_flow_control= rx_pfc;
3410         PRIV_UNLOCK(priv);
3411
3412         return (err);
3413 }
3414
3415 static void
3416 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
3417 {
3418 #if (__FreeBSD_version < 1100000)
3419         char path[96];
3420 #endif
3421         int error;
3422
3423         /* enable pauseframes by default */
3424         priv->params.tx_pauseframe_control = 1;
3425         priv->params.rx_pauseframe_control = 1;
3426
3427         /* disable ports flow control, PFC, by default */
3428         priv->params.tx_priority_flow_control = 0;
3429         priv->params.rx_priority_flow_control = 0;
3430
3431 #if (__FreeBSD_version < 1100000)
3432         /* compute path for sysctl */
3433         snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
3434             device_get_unit(priv->mdev->pdev->dev.bsddev));
3435
3436         /* try to fetch tunable, if any */
3437         TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
3438
3439         /* compute path for sysctl */
3440         snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
3441             device_get_unit(priv->mdev->pdev->dev.bsddev));
3442
3443         /* try to fetch tunable, if any */
3444         TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
3445 #endif
3446
3447         /* register pauseframe SYSCTLs */
3448         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3449             OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
3450             &priv->params.tx_pauseframe_control, 0,
3451             "Set to enable TX pause frames. Clear to disable.");
3452
3453         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3454             OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
3455             &priv->params.rx_pauseframe_control, 0,
3456             "Set to enable RX pause frames. Clear to disable.");
3457
3458         /* register priority flow control, PFC, SYSCTLs */
3459         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3460             OID_AUTO, "tx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
3461             CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_tx_priority_flow_control, "CU",
3462             "Set to enable TX ports flow control frames for priorities 0..7. Clear to disable.");
3463
3464         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3465             OID_AUTO, "rx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
3466             CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_rx_priority_flow_control, "CU",
3467             "Set to enable RX ports flow control frames for priorities 0..7. Clear to disable.");
3468
3469         PRIV_LOCK(priv);
3470
3471         /* range check */
3472         priv->params.tx_pauseframe_control =
3473             priv->params.tx_pauseframe_control ? 1 : 0;
3474         priv->params.rx_pauseframe_control =
3475             priv->params.rx_pauseframe_control ? 1 : 0;
3476
3477         /* update firmware */
3478         error = mlx5e_set_port_pause_and_pfc(priv);
3479         if (error == -EINVAL) {
3480                 if_printf(priv->ifp,
3481                     "Global pauseframes must be disabled before enabling PFC.\n");
3482                 priv->params.rx_priority_flow_control = 0;
3483                 priv->params.tx_priority_flow_control = 0;
3484
3485                 /* update firmware */
3486                 (void) mlx5e_set_port_pause_and_pfc(priv);
3487         }
3488         PRIV_UNLOCK(priv);
3489 }
3490
3491 static void *
3492 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
3493 {
3494         struct ifnet *ifp;
3495         struct mlx5e_priv *priv;
3496         u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
3497         struct sysctl_oid_list *child;
3498         int ncv = mdev->priv.eq_table.num_comp_vectors;
3499         char unit[16];
3500         int err;
3501         int i;
3502         u32 eth_proto_cap;
3503
3504         if (mlx5e_check_required_hca_cap(mdev)) {
3505                 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
3506                 return (NULL);
3507         }
3508         /*
3509          * Try to allocate the priv and make room for worst-case
3510          * number of channel structures:
3511          */
3512         priv = malloc(sizeof(*priv) +
3513             (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors),
3514             M_MLX5EN, M_WAITOK | M_ZERO);
3515         mlx5e_priv_mtx_init(priv);
3516
3517         ifp = priv->ifp = if_alloc(IFT_ETHER);
3518         if (ifp == NULL) {
3519                 mlx5_core_err(mdev, "if_alloc() failed\n");
3520                 goto err_free_priv;
3521         }
3522         ifp->if_softc = priv;
3523         if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev));
3524         ifp->if_mtu = ETHERMTU;
3525         ifp->if_init = mlx5e_open;
3526         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
3527         ifp->if_ioctl = mlx5e_ioctl;
3528         ifp->if_transmit = mlx5e_xmit;
3529         ifp->if_qflush = if_qflush;
3530 #if (__FreeBSD_version >= 1100000)
3531         ifp->if_get_counter = mlx5e_get_counter;
3532 #endif
3533         ifp->if_snd.ifq_maxlen = ifqmaxlen;
3534         /*
3535          * Set driver features
3536          */
3537         ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
3538         ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
3539         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
3540         ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
3541         ifp->if_capabilities |= IFCAP_LRO;
3542         ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
3543         ifp->if_capabilities |= IFCAP_HWSTATS;
3544
3545         /* set TSO limits so that we don't have to drop TX packets */
3546         ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
3547         ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
3548         ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
3549
3550         ifp->if_capenable = ifp->if_capabilities;
3551         ifp->if_hwassist = 0;
3552         if (ifp->if_capenable & IFCAP_TSO)
3553                 ifp->if_hwassist |= CSUM_TSO;
3554         if (ifp->if_capenable & IFCAP_TXCSUM)
3555                 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
3556         if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
3557                 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3558
3559         /* ifnet sysctl tree */
3560         sysctl_ctx_init(&priv->sysctl_ctx);
3561         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
3562             OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
3563         if (priv->sysctl_ifnet == NULL) {
3564                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3565                 goto err_free_sysctl;
3566         }
3567         snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
3568         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3569             OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
3570         if (priv->sysctl_ifnet == NULL) {
3571                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3572                 goto err_free_sysctl;
3573         }
3574
3575         /* HW sysctl tree */
3576         child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
3577         priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
3578             OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
3579         if (priv->sysctl_hw == NULL) {
3580                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3581                 goto err_free_sysctl;
3582         }
3583
3584         err = mlx5e_build_ifp_priv(mdev, priv, ncv);
3585         if (err) {
3586                 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err);
3587                 goto err_free_sysctl;
3588         }
3589
3590         snprintf(unit, sizeof(unit), "mce%u_wq",
3591             device_get_unit(mdev->pdev->dev.bsddev));
3592         priv->wq = alloc_workqueue(unit, 0, 1);
3593         if (priv->wq == NULL) {
3594                 if_printf(ifp, "%s: alloc_workqueue failed\n", __func__);
3595                 goto err_free_sysctl;
3596         }
3597
3598         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
3599         if (err) {
3600                 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n",
3601                     __func__, err);
3602                 goto err_free_wq;
3603         }
3604         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
3605         if (err) {
3606                 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n",
3607                     __func__, err);
3608                 goto err_unmap_free_uar;
3609         }
3610         err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
3611         if (err) {
3612                 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n",
3613                     __func__, err);
3614                 goto err_dealloc_pd;
3615         }
3616         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
3617         if (err) {
3618                 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n",
3619                     __func__, err);
3620                 goto err_dealloc_transport_domain;
3621         }
3622         mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
3623
3624         /* check if we should generate a random MAC address */
3625         if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
3626             is_zero_ether_addr(dev_addr)) {
3627                 random_ether_addr(dev_addr);
3628                 if_printf(ifp, "Assigned random MAC address\n");
3629         }
3630
3631         /* set default MTU */
3632         mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
3633
3634         /* Set default media status */
3635         priv->media_status_last = IFM_AVALID;
3636         priv->media_active_last = IFM_ETHER | IFM_AUTO |
3637             IFM_ETH_RXPAUSE | IFM_FDX;
3638
3639         /* setup default pauseframes configuration */
3640         mlx5e_setup_pauseframes(priv);
3641
3642         err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
3643         if (err) {
3644                 eth_proto_cap = 0;
3645                 if_printf(ifp, "%s: Query port media capability failed, %d\n",
3646                     __func__, err);
3647         }
3648
3649         /* Setup supported medias */
3650         ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
3651             mlx5e_media_change, mlx5e_media_status);
3652
3653         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
3654                 if (mlx5e_mode_table[i].baudrate == 0)
3655                         continue;
3656                 if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
3657                         ifmedia_add(&priv->media,
3658                             mlx5e_mode_table[i].subtype |
3659                             IFM_ETHER, 0, NULL);
3660                         ifmedia_add(&priv->media,
3661                             mlx5e_mode_table[i].subtype |
3662                             IFM_ETHER | IFM_FDX |
3663                             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3664                 }
3665         }
3666
3667         /* Additional supported medias */
3668         ifmedia_add(&priv->media, IFM_10G_LR | IFM_ETHER, 0, NULL);
3669         ifmedia_add(&priv->media, IFM_10G_LR |
3670             IFM_ETHER | IFM_FDX |
3671             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3672
3673         ifmedia_add(&priv->media, IFM_40G_ER4 | IFM_ETHER, 0, NULL);
3674         ifmedia_add(&priv->media, IFM_40G_ER4 |
3675             IFM_ETHER | IFM_FDX |
3676             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3677
3678         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
3679         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3680             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3681
3682         /* Set autoselect by default */
3683         ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3684             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
3685         ether_ifattach(ifp, dev_addr);
3686
3687         /* Register for VLAN events */
3688         priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
3689             mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
3690         priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
3691             mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
3692
3693         /* Link is down by default */
3694         if_link_state_change(ifp, LINK_STATE_DOWN);
3695
3696         mlx5e_enable_async_events(priv);
3697
3698         mlx5e_add_hw_stats(priv);
3699
3700         mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3701             "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
3702             priv->stats.vport.arg);
3703
3704         mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3705             "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
3706             priv->stats.pport.arg);
3707
3708         mlx5e_create_ethtool(priv);
3709
3710         mtx_lock(&priv->async_events_mtx);
3711         mlx5e_update_stats(priv);
3712         mtx_unlock(&priv->async_events_mtx);
3713
3714         return (priv);
3715
3716 err_dealloc_transport_domain:
3717         mlx5_dealloc_transport_domain(mdev, priv->tdn);
3718
3719 err_dealloc_pd:
3720         mlx5_core_dealloc_pd(mdev, priv->pdn);
3721
3722 err_unmap_free_uar:
3723         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3724
3725 err_free_wq:
3726         destroy_workqueue(priv->wq);
3727
3728 err_free_sysctl:
3729         sysctl_ctx_free(&priv->sysctl_ctx);
3730         if (priv->sysctl_debug)
3731                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
3732         if_free(ifp);
3733
3734 err_free_priv:
3735         mlx5e_priv_mtx_destroy(priv);
3736         free(priv, M_MLX5EN);
3737         return (NULL);
3738 }
3739
3740 static void
3741 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
3742 {
3743         struct mlx5e_priv *priv = vpriv;
3744         struct ifnet *ifp = priv->ifp;
3745
3746         /* don't allow more IOCTLs */
3747         priv->gone = 1;
3748
3749         /* XXX wait a bit to allow IOCTL handlers to complete */
3750         pause("W", hz);
3751
3752         /* stop watchdog timer */
3753         callout_drain(&priv->watchdog);
3754
3755         if (priv->vlan_attach != NULL)
3756                 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
3757         if (priv->vlan_detach != NULL)
3758                 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
3759
3760         /* make sure device gets closed */
3761         PRIV_LOCK(priv);
3762         mlx5e_close_locked(ifp);
3763         PRIV_UNLOCK(priv);
3764
3765         /* unregister device */
3766         ifmedia_removeall(&priv->media);
3767         ether_ifdetach(ifp);
3768         if_free(ifp);
3769
3770         /* destroy all remaining sysctl nodes */
3771         sysctl_ctx_free(&priv->stats.vport.ctx);
3772         sysctl_ctx_free(&priv->stats.pport.ctx);
3773         if (priv->sysctl_debug)
3774                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
3775         sysctl_ctx_free(&priv->sysctl_ctx);
3776
3777         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
3778         mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
3779         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3780         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
3781         mlx5e_disable_async_events(priv);
3782         destroy_workqueue(priv->wq);
3783         mlx5e_priv_mtx_destroy(priv);
3784         free(priv, M_MLX5EN);
3785 }
3786
3787 static void *
3788 mlx5e_get_ifp(void *vpriv)
3789 {
3790         struct mlx5e_priv *priv = vpriv;
3791
3792         return (priv->ifp);
3793 }
3794
3795 static struct mlx5_interface mlx5e_interface = {
3796         .add = mlx5e_create_ifp,
3797         .remove = mlx5e_destroy_ifp,
3798         .event = mlx5e_async_event,
3799         .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3800         .get_dev = mlx5e_get_ifp,
3801 };
3802
3803 void
3804 mlx5e_init(void)
3805 {
3806         mlx5_register_interface(&mlx5e_interface);
3807 }
3808
3809 void
3810 mlx5e_cleanup(void)
3811 {
3812         mlx5_unregister_interface(&mlx5e_interface);
3813 }
3814
3815 static void
3816 mlx5e_show_version(void __unused *arg)
3817 {
3818
3819         printf("%s", mlx5e_version);
3820 }
3821 SYSINIT(mlx5e_show_version, SI_SUB_DRIVERS, SI_ORDER_ANY, mlx5e_show_version, NULL);
3822
3823 module_init_order(mlx5e_init, SI_ORDER_THIRD);
3824 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
3825
3826 #if (__FreeBSD_version >= 1100000)
3827 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
3828 #endif
3829 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
3830 MODULE_VERSION(mlx5en, 1);