sys/dev/mlx5/mlx5_en/mlx5_en_main.c

   1 /*-
   2  * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include "en.h"
  29
  30 #include <sys/sockio.h>
  31 #include <machine/atomic.h>
  32
  33 #ifndef ETH_DRIVER_VERSION
  34 #define ETH_DRIVER_VERSION      "3.5.0"
  35 #endif
  36 #define DRIVER_RELDATE  "November 2018"
  37
  38 static const char mlx5e_version[] = "mlx5en: Mellanox Ethernet driver "
  39         ETH_DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
  40
  41 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs);
  42
  43 struct mlx5e_channel_param {
  44         struct mlx5e_rq_param rq;
  45         struct mlx5e_sq_param sq;
  46         struct mlx5e_cq_param rx_cq;
  47         struct mlx5e_cq_param tx_cq;
  48 };
  49
  50 static const struct {
  51         u32     subtype;
  52         u64     baudrate;
  53 }       mlx5e_mode_table[MLX5E_LINK_MODES_NUMBER] = {
  54
  55         [MLX5E_1000BASE_CX_SGMII] = {
  56                 .subtype = IFM_1000_CX_SGMII,
  57                 .baudrate = IF_Mbps(1000ULL),
  58         },
  59         [MLX5E_1000BASE_KX] = {
  60                 .subtype = IFM_1000_KX,
  61                 .baudrate = IF_Mbps(1000ULL),
  62         },
  63         [MLX5E_10GBASE_CX4] = {
  64                 .subtype = IFM_10G_CX4,
  65                 .baudrate = IF_Gbps(10ULL),
  66         },
  67         [MLX5E_10GBASE_KX4] = {
  68                 .subtype = IFM_10G_KX4,
  69                 .baudrate = IF_Gbps(10ULL),
  70         },
  71         [MLX5E_10GBASE_KR] = {
  72                 .subtype = IFM_10G_KR,
  73                 .baudrate = IF_Gbps(10ULL),
  74         },
  75         [MLX5E_20GBASE_KR2] = {
  76                 .subtype = IFM_20G_KR2,
  77                 .baudrate = IF_Gbps(20ULL),
  78         },
  79         [MLX5E_40GBASE_CR4] = {
  80                 .subtype = IFM_40G_CR4,
  81                 .baudrate = IF_Gbps(40ULL),
  82         },
  83         [MLX5E_40GBASE_KR4] = {
  84                 .subtype = IFM_40G_KR4,
  85                 .baudrate = IF_Gbps(40ULL),
  86         },
  87         [MLX5E_56GBASE_R4] = {
  88                 .subtype = IFM_56G_R4,
  89                 .baudrate = IF_Gbps(56ULL),
  90         },
  91         [MLX5E_10GBASE_CR] = {
  92                 .subtype = IFM_10G_CR1,
  93                 .baudrate = IF_Gbps(10ULL),
  94         },
  95         [MLX5E_10GBASE_SR] = {
  96                 .subtype = IFM_10G_SR,
  97                 .baudrate = IF_Gbps(10ULL),
  98         },
  99         [MLX5E_10GBASE_ER] = {
 100                 .subtype = IFM_10G_ER,
 101                 .baudrate = IF_Gbps(10ULL),
 102         },
 103         [MLX5E_40GBASE_SR4] = {
 104                 .subtype = IFM_40G_SR4,
 105                 .baudrate = IF_Gbps(40ULL),
 106         },
 107         [MLX5E_40GBASE_LR4] = {
 108                 .subtype = IFM_40G_LR4,
 109                 .baudrate = IF_Gbps(40ULL),
 110         },
 111         [MLX5E_100GBASE_CR4] = {
 112                 .subtype = IFM_100G_CR4,
 113                 .baudrate = IF_Gbps(100ULL),
 114         },
 115         [MLX5E_100GBASE_SR4] = {
 116                 .subtype = IFM_100G_SR4,
 117                 .baudrate = IF_Gbps(100ULL),
 118         },
 119         [MLX5E_100GBASE_KR4] = {
 120                 .subtype = IFM_100G_KR4,
 121                 .baudrate = IF_Gbps(100ULL),
 122         },
 123         [MLX5E_100GBASE_LR4] = {
 124                 .subtype = IFM_100G_LR4,
 125                 .baudrate = IF_Gbps(100ULL),
 126         },
 127         [MLX5E_100BASE_TX] = {
 128                 .subtype = IFM_100_TX,
 129                 .baudrate = IF_Mbps(100ULL),
 130         },
 131         [MLX5E_1000BASE_T] = {
 132                 .subtype = IFM_1000_T,
 133                 .baudrate = IF_Mbps(1000ULL),
 134         },
 135         [MLX5E_10GBASE_T] = {
 136                 .subtype = IFM_10G_T,
 137                 .baudrate = IF_Gbps(10ULL),
 138         },
 139         [MLX5E_25GBASE_CR] = {
 140                 .subtype = IFM_25G_CR,
 141                 .baudrate = IF_Gbps(25ULL),
 142         },
 143         [MLX5E_25GBASE_KR] = {
 144                 .subtype = IFM_25G_KR,
 145                 .baudrate = IF_Gbps(25ULL),
 146         },
 147         [MLX5E_25GBASE_SR] = {
 148                 .subtype = IFM_25G_SR,
 149                 .baudrate = IF_Gbps(25ULL),
 150         },
 151         [MLX5E_50GBASE_CR2] = {
 152                 .subtype = IFM_50G_CR2,
 153                 .baudrate = IF_Gbps(50ULL),
 154         },
 155         [MLX5E_50GBASE_KR2] = {
 156                 .subtype = IFM_50G_KR2,
 157                 .baudrate = IF_Gbps(50ULL),
 158         },
 159 };
 160
 161 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
 162
 163 static void
 164 mlx5e_update_carrier(struct mlx5e_priv *priv)
 165 {
 166         struct mlx5_core_dev *mdev = priv->mdev;
 167         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 168         u32 eth_proto_oper;
 169         int error;
 170         u8 port_state;
 171         u8 is_er_type;
 172         u8 i;
 173
 174         port_state = mlx5_query_vport_state(mdev,
 175             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 176
 177         if (port_state == VPORT_STATE_UP) {
 178                 priv->media_status_last |= IFM_ACTIVE;
 179         } else {
 180                 priv->media_status_last &= ~IFM_ACTIVE;
 181                 priv->media_active_last = IFM_ETHER;
 182                 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
 183                 return;
 184         }
 185
 186         error = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
 187         if (error) {
 188                 priv->media_active_last = IFM_ETHER;
 189                 priv->ifp->if_baudrate = 1;
 190                 if_printf(priv->ifp, "%s: query port ptys failed: 0x%x\n",
 191                     __func__, error);
 192                 return;
 193         }
 194         eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
 195
 196         for (i = 0; i != MLX5E_LINK_MODES_NUMBER; i++) {
 197                 if (mlx5e_mode_table[i].baudrate == 0)
 198                         continue;
 199                 if (MLX5E_PROT_MASK(i) & eth_proto_oper) {
 200                         u32 subtype = mlx5e_mode_table[i].subtype;
 201
 202                         priv->ifp->if_baudrate =
 203                             mlx5e_mode_table[i].baudrate;
 204
 205                         switch (subtype) {
 206                         case IFM_10G_ER:
 207                                 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
 208                                 if (error != 0) {
 209                                         if_printf(priv->ifp, "%s: query port pddr failed: %d\n",
 210                                             __func__, error);
 211                                 }
 212                                 if (error != 0 || is_er_type == 0)
 213                                         subtype = IFM_10G_LR;
 214                                 break;
 215                         case IFM_40G_LR4:
 216                                 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
 217                                 if (error != 0) {
 218                                         if_printf(priv->ifp, "%s: query port pddr failed: %d\n",
 219                                             __func__, error);
 220                                 }
 221                                 if (error == 0 && is_er_type != 0)
 222                                         subtype = IFM_40G_ER4;
 223                                 break;
 224                         }
 225                         priv->media_active_last = subtype | IFM_ETHER | IFM_FDX;
 226                         break;
 227                 }
 228         }
 229         if_link_state_change(priv->ifp, LINK_STATE_UP);
 230 }
 231
 232 static void
 233 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
 234 {
 235         struct mlx5e_priv *priv = dev->if_softc;
 236
 237         ifmr->ifm_status = priv->media_status_last;
 238         ifmr->ifm_active = priv->media_active_last |
 239             (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
 240             (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
 241
 242 }
 243
 244 static u32
 245 mlx5e_find_link_mode(u32 subtype)
 246 {
 247         u32 i;
 248         u32 link_mode = 0;
 249
 250         switch (subtype) {
 251         case IFM_10G_LR:
 252                 subtype = IFM_10G_ER;
 253                 break;
 254         case IFM_40G_ER4:
 255                 subtype = IFM_40G_LR4;
 256                 break;
 257         }
 258
 259         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
 260                 if (mlx5e_mode_table[i].baudrate == 0)
 261                         continue;
 262                 if (mlx5e_mode_table[i].subtype == subtype)
 263                         link_mode |= MLX5E_PROT_MASK(i);
 264         }
 265
 266         return (link_mode);
 267 }
 268
 269 static int
 270 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv)
 271 {
 272         return (mlx5_set_port_pause_and_pfc(priv->mdev, 1,
 273             priv->params.rx_pauseframe_control,
 274             priv->params.tx_pauseframe_control,
 275             priv->params.rx_priority_flow_control,
 276             priv->params.tx_priority_flow_control));
 277 }
 278
 279 static int
 280 mlx5e_set_port_pfc(struct mlx5e_priv *priv)
 281 {
 282         int error;
 283
 284         if (priv->gone != 0) {
 285                 error = -ENXIO;
 286         } else if (priv->params.rx_pauseframe_control ||
 287             priv->params.tx_pauseframe_control) {
 288                 if_printf(priv->ifp,
 289                     "Global pauseframes must be disabled before enabling PFC.\n");
 290                 error = -EINVAL;
 291         } else {
 292                 error = mlx5e_set_port_pause_and_pfc(priv);
 293         }
 294         return (error);
 295 }
 296
 297 static int
 298 mlx5e_media_change(struct ifnet *dev)
 299 {
 300         struct mlx5e_priv *priv = dev->if_softc;
 301         struct mlx5_core_dev *mdev = priv->mdev;
 302         u32 eth_proto_cap;
 303         u32 link_mode;
 304         int was_opened;
 305         int locked;
 306         int error;
 307
 308         locked = PRIV_LOCKED(priv);
 309         if (!locked)
 310                 PRIV_LOCK(priv);
 311
 312         if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
 313                 error = EINVAL;
 314                 goto done;
 315         }
 316         link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media));
 317
 318         /* query supported capabilities */
 319         error = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
 320         if (error != 0) {
 321                 if_printf(dev, "Query port media capability failed\n");
 322                 goto done;
 323         }
 324         /* check for autoselect */
 325         if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
 326                 link_mode = eth_proto_cap;
 327                 if (link_mode == 0) {
 328                         if_printf(dev, "Port media capability is zero\n");
 329                         error = EINVAL;
 330                         goto done;
 331                 }
 332         } else {
 333                 link_mode = link_mode & eth_proto_cap;
 334                 if (link_mode == 0) {
 335                         if_printf(dev, "Not supported link mode requested\n");
 336                         error = EINVAL;
 337                         goto done;
 338                 }
 339         }
 340         if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
 341                 /* check if PFC is enabled */
 342                 if (priv->params.rx_priority_flow_control ||
 343                     priv->params.tx_priority_flow_control) {
 344                         if_printf(dev, "PFC must be disabled before enabling global pauseframes.\n");
 345                         error = EINVAL;
 346                         goto done;
 347                 }
 348         }
 349         /* update pauseframe control bits */
 350         priv->params.rx_pauseframe_control =
 351             (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
 352         priv->params.tx_pauseframe_control =
 353             (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
 354
 355         /* check if device is opened */
 356         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
 357
 358         /* reconfigure the hardware */
 359         mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
 360         mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN);
 361         error = -mlx5e_set_port_pause_and_pfc(priv);
 362         if (was_opened)
 363                 mlx5_set_port_status(mdev, MLX5_PORT_UP);
 364
 365 done:
 366         if (!locked)
 367                 PRIV_UNLOCK(priv);
 368         return (error);
 369 }
 370
 371 static void
 372 mlx5e_update_carrier_work(struct work_struct *work)
 373 {
 374         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 375             update_carrier_work);
 376
 377         PRIV_LOCK(priv);
 378         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 379                 mlx5e_update_carrier(priv);
 380         PRIV_UNLOCK(priv);
 381 }
 382
 383 /*
 384  * This function reads the physical port counters from the firmware
 385  * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
 386  * macros. The output is converted from big-endian 64-bit values into
 387  * host endian ones and stored in the "priv->stats.pport" structure.
 388  */
 389 static void
 390 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 391 {
 392         struct mlx5_core_dev *mdev = priv->mdev;
 393         struct mlx5e_pport_stats *s = &priv->stats.pport;
 394         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 395         u32 *in;
 396         u32 *out;
 397         const u64 *ptr;
 398         unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 399         unsigned x;
 400         unsigned y;
 401         unsigned z;
 402
 403         /* allocate firmware request structures */
 404         in = mlx5_vzalloc(sz);
 405         out = mlx5_vzalloc(sz);
 406         if (in == NULL || out == NULL)
 407                 goto free_out;
 408
 409         /*
 410          * Get pointer to the 64-bit counter set which is located at a
 411          * fixed offset in the output firmware request structure:
 412          */
 413         ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
 414
 415         MLX5_SET(ppcnt_reg, in, local_port, 1);
 416
 417         /* read IEEE802_3 counter group using predefined counter layout */
 418         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 419         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 420         for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM;
 421              x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
 422                 s->arg[y] = be64toh(ptr[x]);
 423
 424         /* read RFC2819 counter group using predefined counter layout */
 425         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 426         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 427         for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
 428                 s->arg[y] = be64toh(ptr[x]);
 429         for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
 430             MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
 431                 s_debug->arg[y] = be64toh(ptr[x]);
 432
 433         /* read RFC2863 counter group using predefined counter layout */
 434         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 435         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 436         for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
 437                 s_debug->arg[y] = be64toh(ptr[x]);
 438
 439         /* read physical layer stats counter group using predefined counter layout */
 440         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 441         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 442         for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
 443                 s_debug->arg[y] = be64toh(ptr[x]);
 444
 445         /* read Extended Ethernet counter group using predefined counter layout */
 446         MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
 447         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 448         for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++)
 449                 s_debug->arg[y] = be64toh(ptr[x]);
 450
 451         /* read per-priority counters */
 452         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 453
 454         /* iterate all the priorities */
 455         for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) {
 456                 MLX5_SET(ppcnt_reg, in, prio_tc, z);
 457                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 458
 459                 /* read per priority stats counter group using predefined counter layout */
 460                 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM /
 461                     MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++)
 462                         s->arg[y] = be64toh(ptr[x]);
 463         }
 464
 465 free_out:
 466         /* free firmware request structures */
 467         kvfree(in);
 468         kvfree(out);
 469 }
 470
 471 /*
 472  * This function is called regularly to collect all statistics
 473  * counters from the firmware. The values can be viewed through the
 474  * sysctl interface. Execution is serialized using the priv's global
 475  * configuration lock.
 476  */
 477 static void
 478 mlx5e_update_stats_locked(struct mlx5e_priv *priv)
 479 {
 480         struct mlx5_core_dev *mdev = priv->mdev;
 481         struct mlx5e_vport_stats *s = &priv->stats.vport;
 482         struct mlx5e_sq_stats *sq_stats;
 483         struct buf_ring *sq_br;
 484 #if (__FreeBSD_version < 1100000)
 485         struct ifnet *ifp = priv->ifp;
 486 #endif
 487
 488         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 489         u32 *out;
 490         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 491         u64 tso_packets = 0;
 492         u64 tso_bytes = 0;
 493         u64 tx_queue_dropped = 0;
 494         u64 tx_defragged = 0;
 495         u64 tx_offload_none = 0;
 496         u64 lro_packets = 0;
 497         u64 lro_bytes = 0;
 498         u64 sw_lro_queued = 0;
 499         u64 sw_lro_flushed = 0;
 500         u64 rx_csum_none = 0;
 501         u64 rx_wqe_err = 0;
 502         u32 rx_out_of_buffer = 0;
 503         int i;
 504         int j;
 505
 506         out = mlx5_vzalloc(outlen);
 507         if (out == NULL)
 508                 goto free_out;
 509
 510         /* Collect firts the SW counters and then HW for consistency */
 511         for (i = 0; i < priv->params.num_channels; i++) {
 512                 struct mlx5e_channel *pch = priv->channel + i;
 513                 struct mlx5e_rq *rq = &pch->rq;
 514                 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats;
 515
 516                 /* collect stats from LRO */
 517                 rq_stats->sw_lro_queued = rq->lro.lro_queued;
 518                 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
 519                 sw_lro_queued += rq_stats->sw_lro_queued;
 520                 sw_lro_flushed += rq_stats->sw_lro_flushed;
 521                 lro_packets += rq_stats->lro_packets;
 522                 lro_bytes += rq_stats->lro_bytes;
 523                 rx_csum_none += rq_stats->csum_none;
 524                 rx_wqe_err += rq_stats->wqe_err;
 525
 526                 for (j = 0; j < priv->num_tc; j++) {
 527                         sq_stats = &pch->sq[j].stats;
 528                         sq_br = pch->sq[j].br;
 529
 530                         tso_packets += sq_stats->tso_packets;
 531                         tso_bytes += sq_stats->tso_bytes;
 532                         tx_queue_dropped += sq_stats->dropped;
 533                         if (sq_br != NULL)
 534                                 tx_queue_dropped += sq_br->br_drops;
 535                         tx_defragged += sq_stats->defragged;
 536                         tx_offload_none += sq_stats->csum_offload_none;
 537                 }
 538         }
 539
 540         /* update counters */
 541         s->tso_packets = tso_packets;
 542         s->tso_bytes = tso_bytes;
 543         s->tx_queue_dropped = tx_queue_dropped;
 544         s->tx_defragged = tx_defragged;
 545         s->lro_packets = lro_packets;
 546         s->lro_bytes = lro_bytes;
 547         s->sw_lro_queued = sw_lro_queued;
 548         s->sw_lro_flushed = sw_lro_flushed;
 549         s->rx_csum_none = rx_csum_none;
 550         s->rx_wqe_err = rx_wqe_err;
 551
 552         /* HW counters */
 553         memset(in, 0, sizeof(in));
 554
 555         MLX5_SET(query_vport_counter_in, in, opcode,
 556             MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 557         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 558         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 559
 560         memset(out, 0, outlen);
 561
 562         /* get number of out-of-buffer drops first */
 563         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 &&
 564             mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
 565             &rx_out_of_buffer) == 0) {
 566                 /* accumulate difference into a 64-bit counter */
 567                 s->rx_out_of_buffer += (u64)(u32)(rx_out_of_buffer -
 568                     s->rx_out_of_buffer_prev);
 569                 s->rx_out_of_buffer_prev = rx_out_of_buffer;
 570         }
 571
 572         /* get port statistics */
 573         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen) == 0) {
 574 #define MLX5_GET_CTR(out, x) \
 575         MLX5_GET64(query_vport_counter_out, out, x)
 576
 577                 s->rx_error_packets =
 578                     MLX5_GET_CTR(out, received_errors.packets);
 579                 s->rx_error_bytes =
 580                     MLX5_GET_CTR(out, received_errors.octets);
 581                 s->tx_error_packets =
 582                     MLX5_GET_CTR(out, transmit_errors.packets);
 583                 s->tx_error_bytes =
 584                     MLX5_GET_CTR(out, transmit_errors.octets);
 585
 586                 s->rx_unicast_packets =
 587                     MLX5_GET_CTR(out, received_eth_unicast.packets);
 588                 s->rx_unicast_bytes =
 589                     MLX5_GET_CTR(out, received_eth_unicast.octets);
 590                 s->tx_unicast_packets =
 591                     MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 592                 s->tx_unicast_bytes =
 593                     MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 594
 595                 s->rx_multicast_packets =
 596                     MLX5_GET_CTR(out, received_eth_multicast.packets);
 597                 s->rx_multicast_bytes =
 598                     MLX5_GET_CTR(out, received_eth_multicast.octets);
 599                 s->tx_multicast_packets =
 600                     MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 601                 s->tx_multicast_bytes =
 602                     MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 603
 604                 s->rx_broadcast_packets =
 605                     MLX5_GET_CTR(out, received_eth_broadcast.packets);
 606                 s->rx_broadcast_bytes =
 607                     MLX5_GET_CTR(out, received_eth_broadcast.octets);
 608                 s->tx_broadcast_packets =
 609                     MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 610                 s->tx_broadcast_bytes =
 611                     MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 612
 613                 s->rx_packets = s->rx_unicast_packets +
 614                     s->rx_multicast_packets + s->rx_broadcast_packets -
 615                     s->rx_out_of_buffer;
 616                 s->rx_bytes = s->rx_unicast_bytes + s->rx_multicast_bytes +
 617                     s->rx_broadcast_bytes;
 618                 s->tx_packets = s->tx_unicast_packets +
 619                     s->tx_multicast_packets + s->tx_broadcast_packets;
 620                 s->tx_bytes = s->tx_unicast_bytes + s->tx_multicast_bytes +
 621                     s->tx_broadcast_bytes;
 622
 623                 /* Update calculated offload counters */
 624                 s->tx_csum_offload = s->tx_packets - tx_offload_none;
 625                 s->rx_csum_good = s->rx_packets - s->rx_csum_none;
 626         }
 627
 628         /* Get physical port counters */
 629         mlx5e_update_pport_counters(priv);
 630
 631         s->tx_jumbo_packets =
 632             priv->stats.port_stats_debug.tx_stat_p1519to2047octets +
 633             priv->stats.port_stats_debug.tx_stat_p2048to4095octets +
 634             priv->stats.port_stats_debug.tx_stat_p4096to8191octets +
 635             priv->stats.port_stats_debug.tx_stat_p8192to10239octets;
 636
 637 #if (__FreeBSD_version < 1100000)
 638         /* no get_counters interface in fbsd 10 */
 639         ifp->if_ipackets = s->rx_packets;
 640         ifp->if_ierrors = s->rx_error_packets +
 641             priv->stats.pport.alignment_err +
 642             priv->stats.pport.check_seq_err +
 643             priv->stats.pport.crc_align_errors +
 644             priv->stats.pport.in_range_len_errors +
 645             priv->stats.pport.jabbers +
 646             priv->stats.pport.out_of_range_len +
 647             priv->stats.pport.oversize_pkts +
 648             priv->stats.pport.symbol_err +
 649             priv->stats.pport.too_long_errors +
 650             priv->stats.pport.undersize_pkts +
 651             priv->stats.pport.unsupported_op_rx;
 652         ifp->if_iqdrops = s->rx_out_of_buffer +
 653             priv->stats.pport.drop_events;
 654         ifp->if_opackets = s->tx_packets;
 655         ifp->if_oerrors = s->tx_error_packets;
 656         ifp->if_snd.ifq_drops = s->tx_queue_dropped;
 657         ifp->if_ibytes = s->rx_bytes;
 658         ifp->if_obytes = s->tx_bytes;
 659         ifp->if_collisions =
 660             priv->stats.pport.collisions;
 661 #endif
 662
 663 free_out:
 664         kvfree(out);
 665
 666         /* Update diagnostics, if any */
 667         if (priv->params_ethtool.diag_pci_enable ||
 668             priv->params_ethtool.diag_general_enable) {
 669                 int error = mlx5_core_get_diagnostics_full(mdev,
 670                     priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL,
 671                     priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL);
 672                 if (error != 0)
 673                         if_printf(priv->ifp, "Failed reading diagnostics: %d\n", error);
 674         }
 675 }
 676
 677 static void
 678 mlx5e_update_stats_work(struct work_struct *work)
 679 {
 680         struct mlx5e_priv *priv;
 681
 682         priv  = container_of(work, struct mlx5e_priv, update_stats_work);
 683         PRIV_LOCK(priv);
 684         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
 685                 mlx5e_update_stats_locked(priv);
 686         PRIV_UNLOCK(priv);
 687 }
 688
 689 static void
 690 mlx5e_update_stats(void *arg)
 691 {
 692         struct mlx5e_priv *priv = arg;
 693
 694         queue_work(priv->wq, &priv->update_stats_work);
 695
 696         callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
 697 }
 698
 699 static void
 700 mlx5e_async_event_sub(struct mlx5e_priv *priv,
 701     enum mlx5_dev_event event)
 702 {
 703         switch (event) {
 704         case MLX5_DEV_EVENT_PORT_UP:
 705         case MLX5_DEV_EVENT_PORT_DOWN:
 706                 queue_work(priv->wq, &priv->update_carrier_work);
 707                 break;
 708
 709         default:
 710                 break;
 711         }
 712 }
 713
 714 static void
 715 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 716     enum mlx5_dev_event event, unsigned long param)
 717 {
 718         struct mlx5e_priv *priv = vpriv;
 719
 720         mtx_lock(&priv->async_events_mtx);
 721         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 722                 mlx5e_async_event_sub(priv, event);
 723         mtx_unlock(&priv->async_events_mtx);
 724 }
 725
 726 static void
 727 mlx5e_enable_async_events(struct mlx5e_priv *priv)
 728 {
 729         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 730 }
 731
 732 static void
 733 mlx5e_disable_async_events(struct mlx5e_priv *priv)
 734 {
 735         mtx_lock(&priv->async_events_mtx);
 736         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 737         mtx_unlock(&priv->async_events_mtx);
 738 }
 739
 740 static void mlx5e_calibration_callout(void *arg);
 741 static int mlx5e_calibration_duration = 20;
 742 static int mlx5e_fast_calibration = 1;
 743 static int mlx5e_normal_calibration = 30;
 744
 745 static SYSCTL_NODE(_hw_mlx5, OID_AUTO, calibr, CTLFLAG_RW, 0,
 746     "MLX5 timestamp calibration parameteres");
 747
 748 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, duration, CTLFLAG_RWTUN,
 749     &mlx5e_calibration_duration, 0,
 750     "Duration of initial calibration");
 751 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, fast, CTLFLAG_RWTUN,
 752     &mlx5e_fast_calibration, 0,
 753     "Recalibration interval during initial calibration");
 754 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, normal, CTLFLAG_RWTUN,
 755     &mlx5e_normal_calibration, 0,
 756     "Recalibration interval during normal operations");
 757
 758 /*
 759  * Ignites the calibration process.
 760  */
 761 static void
 762 mlx5e_reset_calibration_callout(struct mlx5e_priv *priv)
 763 {
 764
 765         if (priv->clbr_done == 0)
 766                 mlx5e_calibration_callout(priv);
 767         else
 768                 callout_reset_curcpu(&priv->tstmp_clbr, (priv->clbr_done <
 769                     mlx5e_calibration_duration ? mlx5e_fast_calibration :
 770                     mlx5e_normal_calibration) * hz, mlx5e_calibration_callout,
 771                     priv);
 772 }
 773
 774 static uint64_t
 775 mlx5e_timespec2usec(const struct timespec *ts)
 776 {
 777
 778         return ((uint64_t)ts->tv_sec * 1000000000 + ts->tv_nsec);
 779 }
 780
 781 static uint64_t
 782 mlx5e_hw_clock(struct mlx5e_priv *priv)
 783 {
 784         struct mlx5_init_seg *iseg;
 785         uint32_t hw_h, hw_h1, hw_l;
 786
 787         iseg = priv->mdev->iseg;
 788         do {
 789                 hw_h = ioread32be(&iseg->internal_timer_h);
 790                 hw_l = ioread32be(&iseg->internal_timer_l);
 791                 hw_h1 = ioread32be(&iseg->internal_timer_h);
 792         } while (hw_h1 != hw_h);
 793         return (((uint64_t)hw_h << 32) | hw_l);
 794 }
 795
 796 /*
 797  * The calibration callout, it runs either in the context of the
 798  * thread which enables calibration, or in callout.  It takes the
 799  * snapshot of system and adapter clocks, then advances the pointers to
 800  * the calibration point to allow rx path to read the consistent data
 801  * lockless.
 802  */
 803 static void
 804 mlx5e_calibration_callout(void *arg)
 805 {
 806         struct mlx5e_priv *priv;
 807         struct mlx5e_clbr_point *next, *curr;
 808         struct timespec ts;
 809         int clbr_curr_next;
 810
 811         priv = arg;
 812         curr = &priv->clbr_points[priv->clbr_curr];
 813         clbr_curr_next = priv->clbr_curr + 1;
 814         if (clbr_curr_next >= nitems(priv->clbr_points))
 815                 clbr_curr_next = 0;
 816         next = &priv->clbr_points[clbr_curr_next];
 817
 818         next->base_prev = curr->base_curr;
 819         next->clbr_hw_prev = curr->clbr_hw_curr;
 820
 821         next->clbr_hw_curr = mlx5e_hw_clock(priv);
 822         if (((next->clbr_hw_curr - curr->clbr_hw_prev) >> MLX5E_TSTMP_PREC) ==
 823             0) {
 824                 if_printf(priv->ifp, "HW failed tstmp frozen %#jx %#jx,"
 825                     "disabling\n", next->clbr_hw_curr, curr->clbr_hw_prev);
 826                 priv->clbr_done = 0;
 827                 return;
 828         }
 829
 830         nanouptime(&ts);
 831         next->base_curr = mlx5e_timespec2usec(&ts);
 832
 833         curr->clbr_gen = 0;
 834         atomic_thread_fence_rel();
 835         priv->clbr_curr = clbr_curr_next;
 836         atomic_store_rel_int(&next->clbr_gen, ++(priv->clbr_gen));
 837
 838         if (priv->clbr_done < mlx5e_calibration_duration)
 839                 priv->clbr_done++;
 840         mlx5e_reset_calibration_callout(priv);
 841 }
 842
 843 static const char *mlx5e_rq_stats_desc[] = {
 844         MLX5E_RQ_STATS(MLX5E_STATS_DESC)
 845 };
 846
 847 static int
 848 mlx5e_create_rq(struct mlx5e_channel *c,
 849     struct mlx5e_rq_param *param,
 850     struct mlx5e_rq *rq)
 851 {
 852         struct mlx5e_priv *priv = c->priv;
 853         struct mlx5_core_dev *mdev = priv->mdev;
 854         char buffer[16];
 855         void *rqc = param->rqc;
 856         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 857         int wq_sz;
 858         int err;
 859         int i;
 860         u32 nsegs, wqe_sz;
 861
 862         err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
 863         if (err != 0)
 864                 goto done;
 865
 866         /* Create DMA descriptor TAG */
 867         if ((err = -bus_dma_tag_create(
 868             bus_get_dma_tag(mdev->pdev->dev.bsddev),
 869             1,                          /* any alignment */
 870             0,                          /* no boundary */
 871             BUS_SPACE_MAXADDR,          /* lowaddr */
 872             BUS_SPACE_MAXADDR,          /* highaddr */
 873             NULL, NULL,                 /* filter, filterarg */
 874             nsegs * MLX5E_MAX_RX_BYTES, /* maxsize */
 875             nsegs,                      /* nsegments */
 876             nsegs * MLX5E_MAX_RX_BYTES, /* maxsegsize */
 877             0,                          /* flags */
 878             NULL, NULL,                 /* lockfunc, lockfuncarg */
 879             &rq->dma_tag)))
 880                 goto done;
 881
 882         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 883             &rq->wq_ctrl);
 884         if (err)
 885                 goto err_free_dma_tag;
 886
 887         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 888
 889         err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs);
 890         if (err != 0)
 891                 goto err_rq_wq_destroy;
 892
 893         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 894
 895         err = -tcp_lro_init_args(&rq->lro, c->tag.m_snd_tag.ifp, TCP_LRO_ENTRIES, wq_sz);
 896         if (err)
 897                 goto err_rq_wq_destroy;
 898
 899         rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
 900         for (i = 0; i != wq_sz; i++) {
 901                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 902 #if (MLX5E_MAX_RX_SEGS == 1)
 903                 uint32_t byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 904 #else
 905                 int j;
 906 #endif
 907
 908                 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
 909                 if (err != 0) {
 910                         while (i--)
 911                                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 912                         goto err_rq_mbuf_free;
 913                 }
 914
 915                 /* set value for constant fields */
 916 #if (MLX5E_MAX_RX_SEGS == 1)
 917                 wqe->data[0].lkey = c->mkey_be;
 918                 wqe->data[0].byte_count = cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
 919 #else
 920                 for (j = 0; j < rq->nsegs; j++)
 921                         wqe->data[j].lkey = c->mkey_be;
 922 #endif
 923         }
 924
 925         INIT_WORK(&rq->dim.work, mlx5e_dim_work);
 926         if (priv->params.rx_cq_moderation_mode < 2) {
 927                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
 928         } else {
 929                 void *cqc = container_of(param,
 930                     struct mlx5e_channel_param, rq)->rx_cq.cqc;
 931
 932                 switch (MLX5_GET(cqc, cqc, cq_period_mode)) {
 933                 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 934                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 935                         break;
 936                 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 937                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 938                         break;
 939                 default:
 940                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
 941                         break;
 942                 }
 943         }
 944
 945         rq->ifp = c->tag.m_snd_tag.ifp;
 946         rq->channel = c;
 947         rq->ix = c->ix;
 948
 949         snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
 950         mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
 951             buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
 952             rq->stats.arg);
 953         return (0);
 954
 955 err_rq_mbuf_free:
 956         free(rq->mbuf, M_MLX5EN);
 957         tcp_lro_free(&rq->lro);
 958 err_rq_wq_destroy:
 959         mlx5_wq_destroy(&rq->wq_ctrl);
 960 err_free_dma_tag:
 961         bus_dma_tag_destroy(rq->dma_tag);
 962 done:
 963         return (err);
 964 }
 965
 966 static void
 967 mlx5e_destroy_rq(struct mlx5e_rq *rq)
 968 {
 969         int wq_sz;
 970         int i;
 971
 972         /* destroy all sysctl nodes */
 973         sysctl_ctx_free(&rq->stats.ctx);
 974
 975         /* free leftover LRO packets, if any */
 976         tcp_lro_free(&rq->lro);
 977
 978         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 979         for (i = 0; i != wq_sz; i++) {
 980                 if (rq->mbuf[i].mbuf != NULL) {
 981                         bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map);
 982                         m_freem(rq->mbuf[i].mbuf);
 983                 }
 984                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 985         }
 986         free(rq->mbuf, M_MLX5EN);
 987         mlx5_wq_destroy(&rq->wq_ctrl);
 988 }
 989
 990 static int
 991 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 992 {
 993         struct mlx5e_channel *c = rq->channel;
 994         struct mlx5e_priv *priv = c->priv;
 995         struct mlx5_core_dev *mdev = priv->mdev;
 996
 997         void *in;
 998         void *rqc;
 999         void *wq;
1000         int inlen;
1001         int err;
1002
1003         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
1004             sizeof(u64) * rq->wq_ctrl.buf.npages;
1005         in = mlx5_vzalloc(inlen);
1006         if (in == NULL)
1007                 return (-ENOMEM);
1008
1009         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1010         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1011
1012         memcpy(rqc, param->rqc, sizeof(param->rqc));
1013
1014         MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
1015         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1016         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1017         if (priv->counter_set_id >= 0)
1018                 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
1019         MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
1020             PAGE_SHIFT);
1021         MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
1022
1023         mlx5_fill_page_array(&rq->wq_ctrl.buf,
1024             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1025
1026         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
1027
1028         kvfree(in);
1029
1030         return (err);
1031 }
1032
1033 static int
1034 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
1035 {
1036         struct mlx5e_channel *c = rq->channel;
1037         struct mlx5e_priv *priv = c->priv;
1038         struct mlx5_core_dev *mdev = priv->mdev;
1039
1040         void *in;
1041         void *rqc;
1042         int inlen;
1043         int err;
1044
1045         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1046         in = mlx5_vzalloc(inlen);
1047         if (in == NULL)
1048                 return (-ENOMEM);
1049
1050         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1051
1052         MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
1053         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
1054         MLX5_SET(rqc, rqc, state, next_state);
1055
1056         err = mlx5_core_modify_rq(mdev, in, inlen);
1057
1058         kvfree(in);
1059
1060         return (err);
1061 }
1062
1063 static void
1064 mlx5e_disable_rq(struct mlx5e_rq *rq)
1065 {
1066         struct mlx5e_channel *c = rq->channel;
1067         struct mlx5e_priv *priv = c->priv;
1068         struct mlx5_core_dev *mdev = priv->mdev;
1069
1070         mlx5_core_destroy_rq(mdev, rq->rqn);
1071 }
1072
1073 static int
1074 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
1075 {
1076         struct mlx5e_channel *c = rq->channel;
1077         struct mlx5e_priv *priv = c->priv;
1078         struct mlx5_wq_ll *wq = &rq->wq;
1079         int i;
1080
1081         for (i = 0; i < 1000; i++) {
1082                 if (wq->cur_sz >= priv->params.min_rx_wqes)
1083                         return (0);
1084
1085                 msleep(4);
1086         }
1087         return (-ETIMEDOUT);
1088 }
1089
1090 static int
1091 mlx5e_open_rq(struct mlx5e_channel *c,
1092     struct mlx5e_rq_param *param,
1093     struct mlx5e_rq *rq)
1094 {
1095         int err;
1096
1097         err = mlx5e_create_rq(c, param, rq);
1098         if (err)
1099                 return (err);
1100
1101         err = mlx5e_enable_rq(rq, param);
1102         if (err)
1103                 goto err_destroy_rq;
1104
1105         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1106         if (err)
1107                 goto err_disable_rq;
1108
1109         c->rq.enabled = 1;
1110
1111         return (0);
1112
1113 err_disable_rq:
1114         mlx5e_disable_rq(rq);
1115 err_destroy_rq:
1116         mlx5e_destroy_rq(rq);
1117
1118         return (err);
1119 }
1120
1121 static void
1122 mlx5e_close_rq(struct mlx5e_rq *rq)
1123 {
1124         mtx_lock(&rq->mtx);
1125         rq->enabled = 0;
1126         callout_stop(&rq->watchdog);
1127         mtx_unlock(&rq->mtx);
1128
1129         callout_drain(&rq->watchdog);
1130
1131         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
1132 }
1133
1134 static void
1135 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
1136 {
1137
1138         mlx5e_disable_rq(rq);
1139         mlx5e_close_cq(&rq->cq);
1140         cancel_work_sync(&rq->dim.work);
1141         mlx5e_destroy_rq(rq);
1142 }
1143
1144 void
1145 mlx5e_free_sq_db(struct mlx5e_sq *sq)
1146 {
1147         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1148         int x;
1149
1150         for (x = 0; x != wq_sz; x++)
1151                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1152         free(sq->mbuf, M_MLX5EN);
1153 }
1154
1155 int
1156 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
1157 {
1158         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1159         int err;
1160         int x;
1161
1162         sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1163
1164         /* Create DMA descriptor MAPs */
1165         for (x = 0; x != wq_sz; x++) {
1166                 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
1167                 if (err != 0) {
1168                         while (x--)
1169                                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1170                         free(sq->mbuf, M_MLX5EN);
1171                         return (err);
1172                 }
1173         }
1174         return (0);
1175 }
1176
1177 static const char *mlx5e_sq_stats_desc[] = {
1178         MLX5E_SQ_STATS(MLX5E_STATS_DESC)
1179 };
1180
1181 void
1182 mlx5e_update_sq_inline(struct mlx5e_sq *sq)
1183 {
1184         sq->max_inline = sq->priv->params.tx_max_inline;
1185         sq->min_inline_mode = sq->priv->params.tx_min_inline_mode;
1186
1187         /*
1188          * Check if trust state is DSCP or if inline mode is NONE which
1189          * indicates CX-5 or newer hardware.
1190          */
1191         if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP ||
1192             sq->min_inline_mode == MLX5_INLINE_MODE_NONE) {
1193                 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert))
1194                         sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN;
1195                 else
1196                         sq->min_insert_caps = MLX5E_INSERT_NON_VLAN;
1197         } else {
1198                 sq->min_insert_caps = 0;
1199         }
1200 }
1201
1202 static void
1203 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1204 {
1205         int i;
1206
1207         for (i = 0; i != c->num_tc; i++) {
1208                 mtx_lock(&c->sq[i].lock);
1209                 mlx5e_update_sq_inline(&c->sq[i]);
1210                 mtx_unlock(&c->sq[i].lock);
1211         }
1212 }
1213
1214 void
1215 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv)
1216 {
1217         int i;
1218
1219         /* check if channels are closed */
1220         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
1221                 return;
1222
1223         for (i = 0; i < priv->params.num_channels; i++)
1224                 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]);
1225 }
1226
1227 static int
1228 mlx5e_create_sq(struct mlx5e_channel *c,
1229     int tc,
1230     struct mlx5e_sq_param *param,
1231     struct mlx5e_sq *sq)
1232 {
1233         struct mlx5e_priv *priv = c->priv;
1234         struct mlx5_core_dev *mdev = priv->mdev;
1235         char buffer[16];
1236         void *sqc = param->sqc;
1237         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1238         int err;
1239
1240         /* Create DMA descriptor TAG */
1241         if ((err = -bus_dma_tag_create(
1242             bus_get_dma_tag(mdev->pdev->dev.bsddev),
1243             1,                          /* any alignment */
1244             0,                          /* no boundary */
1245             BUS_SPACE_MAXADDR,          /* lowaddr */
1246             BUS_SPACE_MAXADDR,          /* highaddr */
1247             NULL, NULL,                 /* filter, filterarg */
1248             MLX5E_MAX_TX_PAYLOAD_SIZE,  /* maxsize */
1249             MLX5E_MAX_TX_MBUF_FRAGS,    /* nsegments */
1250             MLX5E_MAX_TX_MBUF_SIZE,     /* maxsegsize */
1251             0,                          /* flags */
1252             NULL, NULL,                 /* lockfunc, lockfuncarg */
1253             &sq->dma_tag)))
1254                 goto done;
1255
1256         err = mlx5_alloc_map_uar(mdev, &sq->uar);
1257         if (err)
1258                 goto err_free_dma_tag;
1259
1260         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
1261             &sq->wq_ctrl);
1262         if (err)
1263                 goto err_unmap_free_uar;
1264
1265         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1266         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1267
1268         err = mlx5e_alloc_sq_db(sq);
1269         if (err)
1270                 goto err_sq_wq_destroy;
1271
1272         sq->mkey_be = c->mkey_be;
1273         sq->ifp = priv->ifp;
1274         sq->priv = priv;
1275         sq->tc = tc;
1276
1277         mlx5e_update_sq_inline(sq);
1278
1279         snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1280         mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1281             buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1282             sq->stats.arg);
1283
1284         return (0);
1285
1286 err_sq_wq_destroy:
1287         mlx5_wq_destroy(&sq->wq_ctrl);
1288
1289 err_unmap_free_uar:
1290         mlx5_unmap_free_uar(mdev, &sq->uar);
1291
1292 err_free_dma_tag:
1293         bus_dma_tag_destroy(sq->dma_tag);
1294 done:
1295         return (err);
1296 }
1297
1298 static void
1299 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1300 {
1301         /* destroy all sysctl nodes */
1302         sysctl_ctx_free(&sq->stats.ctx);
1303
1304         mlx5e_free_sq_db(sq);
1305         mlx5_wq_destroy(&sq->wq_ctrl);
1306         mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1307 }
1308
1309 int
1310 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1311     int tis_num)
1312 {
1313         void *in;
1314         void *sqc;
1315         void *wq;
1316         int inlen;
1317         int err;
1318
1319         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1320             sizeof(u64) * sq->wq_ctrl.buf.npages;
1321         in = mlx5_vzalloc(inlen);
1322         if (in == NULL)
1323                 return (-ENOMEM);
1324
1325         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1326         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1327
1328         memcpy(sqc, param->sqc, sizeof(param->sqc));
1329
1330         MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1331         MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1332         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1333         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1334         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1335
1336         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1337         MLX5_SET(wq, wq, uar_page, sq->uar.index);
1338         MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1339             PAGE_SHIFT);
1340         MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1341
1342         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1343             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1344
1345         err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1346
1347         kvfree(in);
1348
1349         return (err);
1350 }
1351
1352 int
1353 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1354 {
1355         void *in;
1356         void *sqc;
1357         int inlen;
1358         int err;
1359
1360         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1361         in = mlx5_vzalloc(inlen);
1362         if (in == NULL)
1363                 return (-ENOMEM);
1364
1365         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1366
1367         MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1368         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1369         MLX5_SET(sqc, sqc, state, next_state);
1370
1371         err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1372
1373         kvfree(in);
1374
1375         return (err);
1376 }
1377
1378 void
1379 mlx5e_disable_sq(struct mlx5e_sq *sq)
1380 {
1381
1382         mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1383 }
1384
1385 static int
1386 mlx5e_open_sq(struct mlx5e_channel *c,
1387     int tc,
1388     struct mlx5e_sq_param *param,
1389     struct mlx5e_sq *sq)
1390 {
1391         int err;
1392
1393         err = mlx5e_create_sq(c, tc, param, sq);
1394         if (err)
1395                 return (err);
1396
1397         err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1398         if (err)
1399                 goto err_destroy_sq;
1400
1401         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1402         if (err)
1403                 goto err_disable_sq;
1404
1405         WRITE_ONCE(sq->running, 1);
1406
1407         return (0);
1408
1409 err_disable_sq:
1410         mlx5e_disable_sq(sq);
1411 err_destroy_sq:
1412         mlx5e_destroy_sq(sq);
1413
1414         return (err);
1415 }
1416
1417 static void
1418 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1419 {
1420         /* fill up remainder with NOPs */
1421         while (sq->cev_counter != 0) {
1422                 while (!mlx5e_sq_has_room_for(sq, 1)) {
1423                         if (can_sleep != 0) {
1424                                 mtx_unlock(&sq->lock);
1425                                 msleep(4);
1426                                 mtx_lock(&sq->lock);
1427                         } else {
1428                                 goto done;
1429                         }
1430                 }
1431                 /* send a single NOP */
1432                 mlx5e_send_nop(sq, 1);
1433                 atomic_thread_fence_rel();
1434         }
1435 done:
1436         /* Check if we need to write the doorbell */
1437         if (likely(sq->doorbell.d64 != 0)) {
1438                 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1439                 sq->doorbell.d64 = 0;
1440         }
1441 }
1442
1443 void
1444 mlx5e_sq_cev_timeout(void *arg)
1445 {
1446         struct mlx5e_sq *sq = arg;
1447
1448         mtx_assert(&sq->lock, MA_OWNED);
1449
1450         /* check next state */
1451         switch (sq->cev_next_state) {
1452         case MLX5E_CEV_STATE_SEND_NOPS:
1453                 /* fill TX ring with NOPs, if any */
1454                 mlx5e_sq_send_nops_locked(sq, 0);
1455
1456                 /* check if completed */
1457                 if (sq->cev_counter == 0) {
1458                         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1459                         return;
1460                 }
1461                 break;
1462         default:
1463                 /* send NOPs on next timeout */
1464                 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1465                 break;
1466         }
1467
1468         /* restart timer */
1469         callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1470 }
1471
1472 void
1473 mlx5e_drain_sq(struct mlx5e_sq *sq)
1474 {
1475         int error;
1476         struct mlx5_core_dev *mdev= sq->priv->mdev;
1477
1478         /*
1479          * Check if already stopped.
1480          *
1481          * NOTE: Serialization of this function is managed by the
1482          * caller ensuring the priv's state lock is locked or in case
1483          * of rate limit support, a single thread manages drain and
1484          * resume of SQs. The "running" variable can therefore safely
1485          * be read without any locks.
1486          */
1487         if (READ_ONCE(sq->running) == 0)
1488                 return;
1489
1490         /* don't put more packets into the SQ */
1491         WRITE_ONCE(sq->running, 0);
1492
1493         /* serialize access to DMA rings */
1494         mtx_lock(&sq->lock);
1495
1496         /* teardown event factor timer, if any */
1497         sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1498         callout_stop(&sq->cev_callout);
1499
1500         /* send dummy NOPs in order to flush the transmit ring */
1501         mlx5e_sq_send_nops_locked(sq, 1);
1502         mtx_unlock(&sq->lock);
1503
1504         /* make sure it is safe to free the callout */
1505         callout_drain(&sq->cev_callout);
1506
1507         /* wait till SQ is empty or link is down */
1508         mtx_lock(&sq->lock);
1509         while (sq->cc != sq->pc &&
1510             (sq->priv->media_status_last & IFM_ACTIVE) != 0 &&
1511             mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1512                 mtx_unlock(&sq->lock);
1513                 msleep(1);
1514                 sq->cq.mcq.comp(&sq->cq.mcq);
1515                 mtx_lock(&sq->lock);
1516         }
1517         mtx_unlock(&sq->lock);
1518
1519         /* error out remaining requests */
1520         error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1521         if (error != 0) {
1522                 if_printf(sq->ifp,
1523                     "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error);
1524         }
1525
1526         /* wait till SQ is empty */
1527         mtx_lock(&sq->lock);
1528         while (sq->cc != sq->pc &&
1529                mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1530                 mtx_unlock(&sq->lock);
1531                 msleep(1);
1532                 sq->cq.mcq.comp(&sq->cq.mcq);
1533                 mtx_lock(&sq->lock);
1534         }
1535         mtx_unlock(&sq->lock);
1536 }
1537
1538 static void
1539 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1540 {
1541
1542         mlx5e_drain_sq(sq);
1543         mlx5e_disable_sq(sq);
1544         mlx5e_destroy_sq(sq);
1545 }
1546
1547 static int
1548 mlx5e_create_cq(struct mlx5e_priv *priv,
1549     struct mlx5e_cq_param *param,
1550     struct mlx5e_cq *cq,
1551     mlx5e_cq_comp_t *comp,
1552     int eq_ix)
1553 {
1554         struct mlx5_core_dev *mdev = priv->mdev;
1555         struct mlx5_core_cq *mcq = &cq->mcq;
1556         int eqn_not_used;
1557         int irqn;
1558         int err;
1559         u32 i;
1560
1561         param->wq.buf_numa_node = 0;
1562         param->wq.db_numa_node = 0;
1563
1564         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1565             &cq->wq_ctrl);
1566         if (err)
1567                 return (err);
1568
1569         mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1570
1571         mcq->cqe_sz = 64;
1572         mcq->set_ci_db = cq->wq_ctrl.db.db;
1573         mcq->arm_db = cq->wq_ctrl.db.db + 1;
1574         *mcq->set_ci_db = 0;
1575         *mcq->arm_db = 0;
1576         mcq->vector = eq_ix;
1577         mcq->comp = comp;
1578         mcq->event = mlx5e_cq_error_event;
1579         mcq->irqn = irqn;
1580         mcq->uar = &priv->cq_uar;
1581
1582         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1583                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1584
1585                 cqe->op_own = 0xf1;
1586         }
1587
1588         cq->priv = priv;
1589
1590         return (0);
1591 }
1592
1593 static void
1594 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1595 {
1596         mlx5_wq_destroy(&cq->wq_ctrl);
1597 }
1598
1599 static int
1600 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1601 {
1602         struct mlx5_core_cq *mcq = &cq->mcq;
1603         void *in;
1604         void *cqc;
1605         int inlen;
1606         int irqn_not_used;
1607         int eqn;
1608         int err;
1609
1610         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1611             sizeof(u64) * cq->wq_ctrl.buf.npages;
1612         in = mlx5_vzalloc(inlen);
1613         if (in == NULL)
1614                 return (-ENOMEM);
1615
1616         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1617
1618         memcpy(cqc, param->cqc, sizeof(param->cqc));
1619
1620         mlx5_fill_page_array(&cq->wq_ctrl.buf,
1621             (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1622
1623         mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
1624
1625         MLX5_SET(cqc, cqc, c_eqn, eqn);
1626         MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1627         MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1628             PAGE_SHIFT);
1629         MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1630
1631         err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
1632
1633         kvfree(in);
1634
1635         if (err)
1636                 return (err);
1637
1638         mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock));
1639
1640         return (0);
1641 }
1642
1643 static void
1644 mlx5e_disable_cq(struct mlx5e_cq *cq)
1645 {
1646
1647         mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
1648 }
1649
1650 int
1651 mlx5e_open_cq(struct mlx5e_priv *priv,
1652     struct mlx5e_cq_param *param,
1653     struct mlx5e_cq *cq,
1654     mlx5e_cq_comp_t *comp,
1655     int eq_ix)
1656 {
1657         int err;
1658
1659         err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
1660         if (err)
1661                 return (err);
1662
1663         err = mlx5e_enable_cq(cq, param, eq_ix);
1664         if (err)
1665                 goto err_destroy_cq;
1666
1667         return (0);
1668
1669 err_destroy_cq:
1670         mlx5e_destroy_cq(cq);
1671
1672         return (err);
1673 }
1674
1675 void
1676 mlx5e_close_cq(struct mlx5e_cq *cq)
1677 {
1678         mlx5e_disable_cq(cq);
1679         mlx5e_destroy_cq(cq);
1680 }
1681
1682 static int
1683 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1684     struct mlx5e_channel_param *cparam)
1685 {
1686         int err;
1687         int tc;
1688
1689         for (tc = 0; tc < c->num_tc; tc++) {
1690                 /* open completion queue */
1691                 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
1692                     &mlx5e_tx_cq_comp, c->ix);
1693                 if (err)
1694                         goto err_close_tx_cqs;
1695         }
1696         return (0);
1697
1698 err_close_tx_cqs:
1699         for (tc--; tc >= 0; tc--)
1700                 mlx5e_close_cq(&c->sq[tc].cq);
1701
1702         return (err);
1703 }
1704
1705 static void
1706 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1707 {
1708         int tc;
1709
1710         for (tc = 0; tc < c->num_tc; tc++)
1711                 mlx5e_close_cq(&c->sq[tc].cq);
1712 }
1713
1714 static int
1715 mlx5e_open_sqs(struct mlx5e_channel *c,
1716     struct mlx5e_channel_param *cparam)
1717 {
1718         int err;
1719         int tc;
1720
1721         for (tc = 0; tc < c->num_tc; tc++) {
1722                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1723                 if (err)
1724                         goto err_close_sqs;
1725         }
1726
1727         return (0);
1728
1729 err_close_sqs:
1730         for (tc--; tc >= 0; tc--)
1731                 mlx5e_close_sq_wait(&c->sq[tc]);
1732
1733         return (err);
1734 }
1735
1736 static void
1737 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
1738 {
1739         int tc;
1740
1741         for (tc = 0; tc < c->num_tc; tc++)
1742                 mlx5e_close_sq_wait(&c->sq[tc]);
1743 }
1744
1745 static void
1746 mlx5e_chan_mtx_init(struct mlx5e_channel *c)
1747 {
1748         int tc;
1749
1750         mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
1751
1752         callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
1753
1754         for (tc = 0; tc < c->num_tc; tc++) {
1755                 struct mlx5e_sq *sq = c->sq + tc;
1756
1757                 mtx_init(&sq->lock, "mlx5tx",
1758                     MTX_NETWORK_LOCK " TX", MTX_DEF);
1759                 mtx_init(&sq->comp_lock, "mlx5comp",
1760                     MTX_NETWORK_LOCK " TX", MTX_DEF);
1761
1762                 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
1763
1764                 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1765
1766                 /* ensure the TX completion event factor is not zero */
1767                 if (sq->cev_factor == 0)
1768                         sq->cev_factor = 1;
1769         }
1770 }
1771
1772 static void
1773 mlx5e_chan_mtx_destroy(struct mlx5e_channel *c)
1774 {
1775         int tc;
1776
1777         mtx_destroy(&c->rq.mtx);
1778
1779         for (tc = 0; tc < c->num_tc; tc++) {
1780                 mtx_destroy(&c->sq[tc].lock);
1781                 mtx_destroy(&c->sq[tc].comp_lock);
1782         }
1783 }
1784
1785 static int
1786 mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1787     struct mlx5e_channel_param *cparam,
1788     struct mlx5e_channel *c)
1789 {
1790         int err;
1791
1792         memset(c, 0, sizeof(*c));
1793
1794         c->priv = priv;
1795         c->ix = ix;
1796         /* setup send tag */
1797         c->tag.m_snd_tag.ifp = priv->ifp;
1798         c->tag.type = IF_SND_TAG_TYPE_UNLIMITED;
1799         c->mkey_be = cpu_to_be32(priv->mr.key);
1800         c->num_tc = priv->num_tc;
1801
1802         /* init mutexes */
1803         mlx5e_chan_mtx_init(c);
1804
1805         /* open transmit completion queue */
1806         err = mlx5e_open_tx_cqs(c, cparam);
1807         if (err)
1808                 goto err_free;
1809
1810         /* open receive completion queue */
1811         err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
1812             &mlx5e_rx_cq_comp, c->ix);
1813         if (err)
1814                 goto err_close_tx_cqs;
1815
1816         err = mlx5e_open_sqs(c, cparam);
1817         if (err)
1818                 goto err_close_rx_cq;
1819
1820         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1821         if (err)
1822                 goto err_close_sqs;
1823
1824         /* poll receive queue initially */
1825         c->rq.cq.mcq.comp(&c->rq.cq.mcq);
1826
1827         return (0);
1828
1829 err_close_sqs:
1830         mlx5e_close_sqs_wait(c);
1831
1832 err_close_rx_cq:
1833         mlx5e_close_cq(&c->rq.cq);
1834
1835 err_close_tx_cqs:
1836         mlx5e_close_tx_cqs(c);
1837
1838 err_free:
1839         /* destroy mutexes */
1840         mlx5e_chan_mtx_destroy(c);
1841         return (err);
1842 }
1843
1844 static void
1845 mlx5e_close_channel(struct mlx5e_channel *c)
1846 {
1847         mlx5e_close_rq(&c->rq);
1848 }
1849
1850 static void
1851 mlx5e_close_channel_wait(struct mlx5e_channel *c)
1852 {
1853         mlx5e_close_rq_wait(&c->rq);
1854         mlx5e_close_sqs_wait(c);
1855         mlx5e_close_tx_cqs(c);
1856         /* destroy mutexes */
1857         mlx5e_chan_mtx_destroy(c);
1858 }
1859
1860 static int
1861 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs)
1862 {
1863         u32 r, n;
1864
1865         r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz :
1866             MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
1867         if (r > MJUM16BYTES)
1868                 return (-ENOMEM);
1869
1870         if (r > MJUM9BYTES)
1871                 r = MJUM16BYTES;
1872         else if (r > MJUMPAGESIZE)
1873                 r = MJUM9BYTES;
1874         else if (r > MCLBYTES)
1875                 r = MJUMPAGESIZE;
1876         else
1877                 r = MCLBYTES;
1878
1879         /*
1880          * n + 1 must be a power of two, because stride size must be.
1881          * Stride size is 16 * (n + 1), as the first segment is
1882          * control.
1883          */
1884         for (n = howmany(r, MLX5E_MAX_RX_BYTES); !powerof2(n + 1); n++)
1885                 ;
1886
1887         *wqe_sz = r;
1888         *nsegs = n;
1889         return (0);
1890 }
1891
1892 static void
1893 mlx5e_build_rq_param(struct mlx5e_priv *priv,
1894     struct mlx5e_rq_param *param)
1895 {
1896         void *rqc = param->rqc;
1897         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1898         u32 wqe_sz, nsegs;
1899
1900         mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
1901         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1902         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1903         MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) +
1904             nsegs * sizeof(struct mlx5_wqe_data_seg)));
1905         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1906         MLX5_SET(wq, wq, pd, priv->pdn);
1907
1908         param->wq.buf_numa_node = 0;
1909         param->wq.db_numa_node = 0;
1910         param->wq.linear = 1;
1911 }
1912
1913 static void
1914 mlx5e_build_sq_param(struct mlx5e_priv *priv,
1915     struct mlx5e_sq_param *param)
1916 {
1917         void *sqc = param->sqc;
1918         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1919
1920         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1921         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1922         MLX5_SET(wq, wq, pd, priv->pdn);
1923
1924         param->wq.buf_numa_node = 0;
1925         param->wq.db_numa_node = 0;
1926         param->wq.linear = 1;
1927 }
1928
1929 static void
1930 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1931     struct mlx5e_cq_param *param)
1932 {
1933         void *cqc = param->cqc;
1934
1935         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1936 }
1937
1938 static void
1939 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr)
1940 {
1941
1942         *ptr = net_dim_get_profile(mode, MLX5E_DIM_DEFAULT_PROFILE);
1943
1944         /* apply LRO restrictions */
1945         if (priv->params.hw_lro_en &&
1946             ptr->pkts > MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO) {
1947                 ptr->pkts = MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO;
1948         }
1949 }
1950
1951 static void
1952 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1953     struct mlx5e_cq_param *param)
1954 {
1955         struct net_dim_cq_moder curr;
1956         void *cqc = param->cqc;
1957
1958
1959         /*
1960          * TODO The sysctl to control on/off is a bool value for now, which means
1961          * we only support CSUM, once HASH is implemnted we'll need to address that.
1962          */
1963         if (priv->params.cqe_zipping_en) {
1964                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1965                 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
1966         }
1967
1968         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1969
1970         switch (priv->params.rx_cq_moderation_mode) {
1971         case 0:
1972                 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1973                 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1974                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1975                 break;
1976         case 1:
1977                 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1978                 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1979                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1980                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1981                 else
1982                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1983                 break;
1984         case 2:
1985                 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr);
1986                 MLX5_SET(cqc, cqc, cq_period, curr.usec);
1987                 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
1988                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1989                 break;
1990         case 3:
1991                 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr);
1992                 MLX5_SET(cqc, cqc, cq_period, curr.usec);
1993                 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
1994                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1995                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1996                 else
1997                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1998                 break;
1999         default:
2000                 break;
2001         }
2002
2003         mlx5e_dim_build_cq_param(priv, param);
2004
2005         mlx5e_build_common_cq_param(priv, param);
2006 }
2007
2008 static void
2009 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2010     struct mlx5e_cq_param *param)
2011 {
2012         void *cqc = param->cqc;
2013
2014         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
2015         MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
2016         MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
2017
2018         switch (priv->params.tx_cq_moderation_mode) {
2019         case 0:
2020                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2021                 break;
2022         default:
2023                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2024                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2025                 else
2026                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2027                 break;
2028         }
2029
2030         mlx5e_build_common_cq_param(priv, param);
2031 }
2032
2033 static void
2034 mlx5e_build_channel_param(struct mlx5e_priv *priv,
2035     struct mlx5e_channel_param *cparam)
2036 {
2037         memset(cparam, 0, sizeof(*cparam));
2038
2039         mlx5e_build_rq_param(priv, &cparam->rq);
2040         mlx5e_build_sq_param(priv, &cparam->sq);
2041         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
2042         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
2043 }
2044
2045 static int
2046 mlx5e_open_channels(struct mlx5e_priv *priv)
2047 {
2048         struct mlx5e_channel_param cparam;
2049         int err;
2050         int i;
2051         int j;
2052
2053         mlx5e_build_channel_param(priv, &cparam);
2054         for (i = 0; i < priv->params.num_channels; i++) {
2055                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
2056                 if (err)
2057                         goto err_close_channels;
2058         }
2059
2060         for (j = 0; j < priv->params.num_channels; j++) {
2061                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j].rq);
2062                 if (err)
2063                         goto err_close_channels;
2064         }
2065         return (0);
2066
2067 err_close_channels:
2068         while (i--) {
2069                 mlx5e_close_channel(&priv->channel[i]);
2070                 mlx5e_close_channel_wait(&priv->channel[i]);
2071         }
2072         return (err);
2073 }
2074
2075 static void
2076 mlx5e_close_channels(struct mlx5e_priv *priv)
2077 {
2078         int i;
2079
2080         for (i = 0; i < priv->params.num_channels; i++)
2081                 mlx5e_close_channel(&priv->channel[i]);
2082         for (i = 0; i < priv->params.num_channels; i++)
2083                 mlx5e_close_channel_wait(&priv->channel[i]);
2084 }
2085
2086 static int
2087 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
2088 {
2089
2090         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2091                 uint8_t cq_mode;
2092
2093                 switch (priv->params.tx_cq_moderation_mode) {
2094                 case 0:
2095                 case 2:
2096                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2097                         break;
2098                 default:
2099                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2100                         break;
2101                 }
2102
2103                 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq,
2104                     priv->params.tx_cq_moderation_usec,
2105                     priv->params.tx_cq_moderation_pkts,
2106                     cq_mode));
2107         }
2108
2109         return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
2110             priv->params.tx_cq_moderation_usec,
2111             priv->params.tx_cq_moderation_pkts));
2112 }
2113
2114 static int
2115 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
2116 {
2117
2118         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2119                 uint8_t cq_mode;
2120                 uint8_t dim_mode;
2121                 int retval;
2122
2123                 switch (priv->params.rx_cq_moderation_mode) {
2124                 case 0:
2125                 case 2:
2126                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2127                         dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2128                         break;
2129                 default:
2130                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2131                         dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
2132                         break;
2133                 }
2134
2135                 /* tear down dynamic interrupt moderation */
2136                 mtx_lock(&rq->mtx);
2137                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
2138                 mtx_unlock(&rq->mtx);
2139
2140                 /* wait for dynamic interrupt moderation work task, if any */
2141                 cancel_work_sync(&rq->dim.work);
2142
2143                 if (priv->params.rx_cq_moderation_mode >= 2) {
2144                         struct net_dim_cq_moder curr;
2145
2146                         mlx5e_get_default_profile(priv, dim_mode, &curr);
2147
2148                         retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2149                             curr.usec, curr.pkts, cq_mode);
2150
2151                         /* set dynamic interrupt moderation mode and zero defaults */
2152                         mtx_lock(&rq->mtx);
2153                         rq->dim.mode = dim_mode;
2154                         rq->dim.state = 0;
2155                         rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE;
2156                         mtx_unlock(&rq->mtx);
2157                 } else {
2158                         retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2159                             priv->params.rx_cq_moderation_usec,
2160                             priv->params.rx_cq_moderation_pkts,
2161                             cq_mode);
2162                 }
2163                 return (retval);
2164         }
2165
2166         return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
2167             priv->params.rx_cq_moderation_usec,
2168             priv->params.rx_cq_moderation_pkts));
2169 }
2170
2171 static int
2172 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
2173 {
2174         int err;
2175         int i;
2176
2177         err = mlx5e_refresh_rq_params(priv, &c->rq);
2178         if (err)
2179                 goto done;
2180
2181         for (i = 0; i != c->num_tc; i++) {
2182                 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
2183                 if (err)
2184                         goto done;
2185         }
2186 done:
2187         return (err);
2188 }
2189
2190 int
2191 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
2192 {
2193         int i;
2194
2195         /* check if channels are closed */
2196         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2197                 return (EINVAL);
2198
2199         for (i = 0; i < priv->params.num_channels; i++) {
2200                 int err;
2201
2202                 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]);
2203                 if (err)
2204                         return (err);
2205         }
2206         return (0);
2207 }
2208
2209 static int
2210 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
2211 {
2212         struct mlx5_core_dev *mdev = priv->mdev;
2213         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
2214         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2215
2216         memset(in, 0, sizeof(in));
2217
2218         MLX5_SET(tisc, tisc, prio, tc);
2219         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
2220
2221         return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
2222 }
2223
2224 static void
2225 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
2226 {
2227         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2228 }
2229
2230 static int
2231 mlx5e_open_tises(struct mlx5e_priv *priv)
2232 {
2233         int num_tc = priv->num_tc;
2234         int err;
2235         int tc;
2236
2237         for (tc = 0; tc < num_tc; tc++) {
2238                 err = mlx5e_open_tis(priv, tc);
2239                 if (err)
2240                         goto err_close_tises;
2241         }
2242
2243         return (0);
2244
2245 err_close_tises:
2246         for (tc--; tc >= 0; tc--)
2247                 mlx5e_close_tis(priv, tc);
2248
2249         return (err);
2250 }
2251
2252 static void
2253 mlx5e_close_tises(struct mlx5e_priv *priv)
2254 {
2255         int num_tc = priv->num_tc;
2256         int tc;
2257
2258         for (tc = 0; tc < num_tc; tc++)
2259                 mlx5e_close_tis(priv, tc);
2260 }
2261
2262 static int
2263 mlx5e_open_rqt(struct mlx5e_priv *priv)
2264 {
2265         struct mlx5_core_dev *mdev = priv->mdev;
2266         u32 *in;
2267         u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
2268         void *rqtc;
2269         int inlen;
2270         int err;
2271         int sz;
2272         int i;
2273
2274         sz = 1 << priv->params.rx_hash_log_tbl_sz;
2275
2276         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2277         in = mlx5_vzalloc(inlen);
2278         if (in == NULL)
2279                 return (-ENOMEM);
2280         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2281
2282         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2283         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2284
2285         for (i = 0; i < sz; i++) {
2286                 int ix = i;
2287 #ifdef RSS
2288                 ix = rss_get_indirection_to_bucket(ix);
2289 #endif
2290                 /* ensure we don't overflow */
2291                 ix %= priv->params.num_channels;
2292
2293                 /* apply receive side scaling stride, if any */
2294                 ix -= ix % (int)priv->params.channels_rsss;
2295
2296                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn);
2297         }
2298
2299         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
2300
2301         err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
2302         if (!err)
2303                 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
2304
2305         kvfree(in);
2306
2307         return (err);
2308 }
2309
2310 static void
2311 mlx5e_close_rqt(struct mlx5e_priv *priv)
2312 {
2313         u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0};
2314         u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0};
2315
2316         MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
2317         MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
2318
2319         mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out));
2320 }
2321
2322 static void
2323 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
2324 {
2325         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2326         __be32 *hkey;
2327
2328         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2329
2330 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2331
2332 #define MLX5_HASH_IP     (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2333                           MLX5_HASH_FIELD_SEL_DST_IP)
2334
2335 #define MLX5_HASH_ALL    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2336                           MLX5_HASH_FIELD_SEL_DST_IP   |\
2337                           MLX5_HASH_FIELD_SEL_L4_SPORT |\
2338                           MLX5_HASH_FIELD_SEL_L4_DPORT)
2339
2340 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2341                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2342                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2343
2344         if (priv->params.hw_lro_en) {
2345                 MLX5_SET(tirc, tirc, lro_enable_mask,
2346                     MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2347                     MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2348                 MLX5_SET(tirc, tirc, lro_max_msg_sz,
2349                     (priv->params.lro_wqe_sz -
2350                     ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2351                 /* TODO: add the option to choose timer value dynamically */
2352                 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
2353                     MLX5_CAP_ETH(priv->mdev,
2354                     lro_timer_supported_periods[2]));
2355         }
2356
2357         /* setup parameters for hashing TIR type, if any */
2358         switch (tt) {
2359         case MLX5E_TT_ANY:
2360                 MLX5_SET(tirc, tirc, disp_type,
2361                     MLX5_TIRC_DISP_TYPE_DIRECT);
2362                 MLX5_SET(tirc, tirc, inline_rqn,
2363                     priv->channel[0].rq.rqn);
2364                 break;
2365         default:
2366                 MLX5_SET(tirc, tirc, disp_type,
2367                     MLX5_TIRC_DISP_TYPE_INDIRECT);
2368                 MLX5_SET(tirc, tirc, indirect_table,
2369                     priv->rqtn);
2370                 MLX5_SET(tirc, tirc, rx_hash_fn,
2371                     MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
2372                 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
2373 #ifdef RSS
2374                 /*
2375                  * The FreeBSD RSS implementation does currently not
2376                  * support symmetric Toeplitz hashes:
2377                  */
2378                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
2379                 rss_getkey((uint8_t *)hkey);
2380 #else
2381                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2382                 hkey[0] = cpu_to_be32(0xD181C62C);
2383                 hkey[1] = cpu_to_be32(0xF7F4DB5B);
2384                 hkey[2] = cpu_to_be32(0x1983A2FC);
2385                 hkey[3] = cpu_to_be32(0x943E1ADB);
2386                 hkey[4] = cpu_to_be32(0xD9389E6B);
2387                 hkey[5] = cpu_to_be32(0xD1039C2C);
2388                 hkey[6] = cpu_to_be32(0xA74499AD);
2389                 hkey[7] = cpu_to_be32(0x593D56D9);
2390                 hkey[8] = cpu_to_be32(0xF3253C06);
2391                 hkey[9] = cpu_to_be32(0x2ADC1FFC);
2392 #endif
2393                 break;
2394         }
2395
2396         switch (tt) {
2397         case MLX5E_TT_IPV4_TCP:
2398                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2399                     MLX5_L3_PROT_TYPE_IPV4);
2400                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2401                     MLX5_L4_PROT_TYPE_TCP);
2402 #ifdef RSS
2403                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2404                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2405                             MLX5_HASH_IP);
2406                 } else
2407 #endif
2408                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2409                     MLX5_HASH_ALL);
2410                 break;
2411
2412         case MLX5E_TT_IPV6_TCP:
2413                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2414                     MLX5_L3_PROT_TYPE_IPV6);
2415                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2416                     MLX5_L4_PROT_TYPE_TCP);
2417 #ifdef RSS
2418                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2419                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2420                             MLX5_HASH_IP);
2421                 } else
2422 #endif
2423                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2424                     MLX5_HASH_ALL);
2425                 break;
2426
2427         case MLX5E_TT_IPV4_UDP:
2428                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2429                     MLX5_L3_PROT_TYPE_IPV4);
2430                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2431                     MLX5_L4_PROT_TYPE_UDP);
2432 #ifdef RSS
2433                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2434                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2435                             MLX5_HASH_IP);
2436                 } else
2437 #endif
2438                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2439                     MLX5_HASH_ALL);
2440                 break;
2441
2442         case MLX5E_TT_IPV6_UDP:
2443                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2444                     MLX5_L3_PROT_TYPE_IPV6);
2445                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2446                     MLX5_L4_PROT_TYPE_UDP);
2447 #ifdef RSS
2448                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2449                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2450                             MLX5_HASH_IP);
2451                 } else
2452 #endif
2453                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2454                     MLX5_HASH_ALL);
2455                 break;
2456
2457         case MLX5E_TT_IPV4_IPSEC_AH:
2458                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2459                     MLX5_L3_PROT_TYPE_IPV4);
2460                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2461                     MLX5_HASH_IP_IPSEC_SPI);
2462                 break;
2463
2464         case MLX5E_TT_IPV6_IPSEC_AH:
2465                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2466                     MLX5_L3_PROT_TYPE_IPV6);
2467                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2468                     MLX5_HASH_IP_IPSEC_SPI);
2469                 break;
2470
2471         case MLX5E_TT_IPV4_IPSEC_ESP:
2472                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2473                     MLX5_L3_PROT_TYPE_IPV4);
2474                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2475                     MLX5_HASH_IP_IPSEC_SPI);
2476                 break;
2477
2478         case MLX5E_TT_IPV6_IPSEC_ESP:
2479                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2480                     MLX5_L3_PROT_TYPE_IPV6);
2481                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2482                     MLX5_HASH_IP_IPSEC_SPI);
2483                 break;
2484
2485         case MLX5E_TT_IPV4:
2486                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2487                     MLX5_L3_PROT_TYPE_IPV4);
2488                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2489                     MLX5_HASH_IP);
2490                 break;
2491
2492         case MLX5E_TT_IPV6:
2493                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2494                     MLX5_L3_PROT_TYPE_IPV6);
2495                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2496                     MLX5_HASH_IP);
2497                 break;
2498
2499         default:
2500                 break;
2501         }
2502 }
2503
2504 static int
2505 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2506 {
2507         struct mlx5_core_dev *mdev = priv->mdev;
2508         u32 *in;
2509         void *tirc;
2510         int inlen;
2511         int err;
2512
2513         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2514         in = mlx5_vzalloc(inlen);
2515         if (in == NULL)
2516                 return (-ENOMEM);
2517         tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2518
2519         mlx5e_build_tir_ctx(priv, tirc, tt);
2520
2521         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2522
2523         kvfree(in);
2524
2525         return (err);
2526 }
2527
2528 static void
2529 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2530 {
2531         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2532 }
2533
2534 static int
2535 mlx5e_open_tirs(struct mlx5e_priv *priv)
2536 {
2537         int err;
2538         int i;
2539
2540         for (i = 0; i < MLX5E_NUM_TT; i++) {
2541                 err = mlx5e_open_tir(priv, i);
2542                 if (err)
2543                         goto err_close_tirs;
2544         }
2545
2546         return (0);
2547
2548 err_close_tirs:
2549         for (i--; i >= 0; i--)
2550                 mlx5e_close_tir(priv, i);
2551
2552         return (err);
2553 }
2554
2555 static void
2556 mlx5e_close_tirs(struct mlx5e_priv *priv)
2557 {
2558         int i;
2559
2560         for (i = 0; i < MLX5E_NUM_TT; i++)
2561                 mlx5e_close_tir(priv, i);
2562 }
2563
2564 /*
2565  * SW MTU does not include headers,
2566  * HW MTU includes all headers and checksums.
2567  */
2568 static int
2569 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2570 {
2571         struct mlx5e_priv *priv = ifp->if_softc;
2572         struct mlx5_core_dev *mdev = priv->mdev;
2573         int hw_mtu;
2574         int err;
2575
2576         hw_mtu = MLX5E_SW2HW_MTU(sw_mtu);
2577
2578         err = mlx5_set_port_mtu(mdev, hw_mtu);
2579         if (err) {
2580                 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n",
2581                     __func__, sw_mtu, err);
2582                 return (err);
2583         }
2584
2585         /* Update vport context MTU */
2586         err = mlx5_set_vport_mtu(mdev, hw_mtu);
2587         if (err) {
2588                 if_printf(ifp, "%s: Failed updating vport context with MTU size, err=%d\n",
2589                     __func__, err);
2590         }
2591
2592         ifp->if_mtu = sw_mtu;
2593
2594         err = mlx5_query_vport_mtu(mdev, &hw_mtu);
2595         if (err || !hw_mtu) {
2596                 /* fallback to port oper mtu */
2597                 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2598         }
2599         if (err) {
2600                 if_printf(ifp, "Query port MTU, after setting new "
2601                     "MTU value, failed\n");
2602                 return (err);
2603         } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
2604                 err = -E2BIG,
2605                 if_printf(ifp, "Port MTU %d is smaller than "
2606                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2607         } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
2608                 err = -EINVAL;
2609                 if_printf(ifp, "Port MTU %d is bigger than "
2610                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2611         }
2612         priv->params_ethtool.hw_mtu = hw_mtu;
2613
2614         return (err);
2615 }
2616
2617 int
2618 mlx5e_open_locked(struct ifnet *ifp)
2619 {
2620         struct mlx5e_priv *priv = ifp->if_softc;
2621         int err;
2622         u16 set_id;
2623
2624         /* check if already opened */
2625         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2626                 return (0);
2627
2628 #ifdef RSS
2629         if (rss_getnumbuckets() > priv->params.num_channels) {
2630                 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than "
2631                     "channels(%u) available\n", rss_getnumbuckets(),
2632                     priv->params.num_channels);
2633         }
2634 #endif
2635         err = mlx5e_open_tises(priv);
2636         if (err) {
2637                 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n",
2638                     __func__, err);
2639                 return (err);
2640         }
2641         err = mlx5_vport_alloc_q_counter(priv->mdev,
2642             MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
2643         if (err) {
2644                 if_printf(priv->ifp,
2645                     "%s: mlx5_vport_alloc_q_counter failed: %d\n",
2646                     __func__, err);
2647                 goto err_close_tises;
2648         }
2649         /* store counter set ID */
2650         priv->counter_set_id = set_id;
2651
2652         err = mlx5e_open_channels(priv);
2653         if (err) {
2654                 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n",
2655                     __func__, err);
2656                 goto err_dalloc_q_counter;
2657         }
2658         err = mlx5e_open_rqt(priv);
2659         if (err) {
2660                 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n",
2661                     __func__, err);
2662                 goto err_close_channels;
2663         }
2664         err = mlx5e_open_tirs(priv);
2665         if (err) {
2666                 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n",
2667                     __func__, err);
2668                 goto err_close_rqls;
2669         }
2670         err = mlx5e_open_flow_table(priv);
2671         if (err) {
2672                 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n",
2673                     __func__, err);
2674                 goto err_close_tirs;
2675         }
2676         err = mlx5e_add_all_vlan_rules(priv);
2677         if (err) {
2678                 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
2679                     __func__, err);
2680                 goto err_close_flow_table;
2681         }
2682         set_bit(MLX5E_STATE_OPENED, &priv->state);
2683
2684         mlx5e_update_carrier(priv);
2685         mlx5e_set_rx_mode_core(priv);
2686
2687         return (0);
2688
2689 err_close_flow_table:
2690         mlx5e_close_flow_table(priv);
2691
2692 err_close_tirs:
2693         mlx5e_close_tirs(priv);
2694
2695 err_close_rqls:
2696         mlx5e_close_rqt(priv);
2697
2698 err_close_channels:
2699         mlx5e_close_channels(priv);
2700
2701 err_dalloc_q_counter:
2702         mlx5_vport_dealloc_q_counter(priv->mdev,
2703             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2704
2705 err_close_tises:
2706         mlx5e_close_tises(priv);
2707
2708         return (err);
2709 }
2710
2711 static void
2712 mlx5e_open(void *arg)
2713 {
2714         struct mlx5e_priv *priv = arg;
2715
2716         PRIV_LOCK(priv);
2717         if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
2718                 if_printf(priv->ifp,
2719                     "%s: Setting port status to up failed\n",
2720                     __func__);
2721
2722         mlx5e_open_locked(priv->ifp);
2723         priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
2724         PRIV_UNLOCK(priv);
2725 }
2726
2727 int
2728 mlx5e_close_locked(struct ifnet *ifp)
2729 {
2730         struct mlx5e_priv *priv = ifp->if_softc;
2731
2732         /* check if already closed */
2733         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2734                 return (0);
2735
2736         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2737
2738         mlx5e_set_rx_mode_core(priv);
2739         mlx5e_del_all_vlan_rules(priv);
2740         if_link_state_change(priv->ifp, LINK_STATE_DOWN);
2741         mlx5e_close_flow_table(priv);
2742         mlx5e_close_tirs(priv);
2743         mlx5e_close_rqt(priv);
2744         mlx5e_close_channels(priv);
2745         mlx5_vport_dealloc_q_counter(priv->mdev,
2746             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2747         mlx5e_close_tises(priv);
2748
2749         return (0);
2750 }
2751
2752 #if (__FreeBSD_version >= 1100000)
2753 static uint64_t
2754 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
2755 {
2756         struct mlx5e_priv *priv = ifp->if_softc;
2757         u64 retval;
2758
2759         /* PRIV_LOCK(priv); XXX not allowed */
2760         switch (cnt) {
2761         case IFCOUNTER_IPACKETS:
2762                 retval = priv->stats.vport.rx_packets;
2763                 break;
2764         case IFCOUNTER_IERRORS:
2765                 retval = priv->stats.vport.rx_error_packets +
2766                     priv->stats.pport.alignment_err +
2767                     priv->stats.pport.check_seq_err +
2768                     priv->stats.pport.crc_align_errors +
2769                     priv->stats.pport.in_range_len_errors +
2770                     priv->stats.pport.jabbers +
2771                     priv->stats.pport.out_of_range_len +
2772                     priv->stats.pport.oversize_pkts +
2773                     priv->stats.pport.symbol_err +
2774                     priv->stats.pport.too_long_errors +
2775                     priv->stats.pport.undersize_pkts +
2776                     priv->stats.pport.unsupported_op_rx;
2777                 break;
2778         case IFCOUNTER_IQDROPS:
2779                 retval = priv->stats.vport.rx_out_of_buffer +
2780                     priv->stats.pport.drop_events;
2781                 break;
2782         case IFCOUNTER_OPACKETS:
2783                 retval = priv->stats.vport.tx_packets;
2784                 break;
2785         case IFCOUNTER_OERRORS:
2786                 retval = priv->stats.vport.tx_error_packets;
2787                 break;
2788         case IFCOUNTER_IBYTES:
2789                 retval = priv->stats.vport.rx_bytes;
2790                 break;
2791         case IFCOUNTER_OBYTES:
2792                 retval = priv->stats.vport.tx_bytes;
2793                 break;
2794         case IFCOUNTER_IMCASTS:
2795                 retval = priv->stats.vport.rx_multicast_packets;
2796                 break;
2797         case IFCOUNTER_OMCASTS:
2798                 retval = priv->stats.vport.tx_multicast_packets;
2799                 break;
2800         case IFCOUNTER_OQDROPS:
2801                 retval = priv->stats.vport.tx_queue_dropped;
2802                 break;
2803         case IFCOUNTER_COLLISIONS:
2804                 retval = priv->stats.pport.collisions;
2805                 break;
2806         default:
2807                 retval = if_get_counter_default(ifp, cnt);
2808                 break;
2809         }
2810         /* PRIV_UNLOCK(priv); XXX not allowed */
2811         return (retval);
2812 }
2813 #endif
2814
2815 static void
2816 mlx5e_set_rx_mode(struct ifnet *ifp)
2817 {
2818         struct mlx5e_priv *priv = ifp->if_softc;
2819
2820         queue_work(priv->wq, &priv->set_rx_mode_work);
2821 }
2822
2823 static int
2824 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2825 {
2826         struct mlx5e_priv *priv;
2827         struct ifreq *ifr;
2828         struct ifi2creq i2c;
2829         int error = 0;
2830         int mask = 0;
2831         int size_read = 0;
2832         int module_status;
2833         int module_num;
2834         int max_mtu;
2835         uint8_t read_addr;
2836
2837         priv = ifp->if_softc;
2838
2839         /* check if detaching */
2840         if (priv == NULL || priv->gone != 0)
2841                 return (ENXIO);
2842
2843         switch (command) {
2844         case SIOCSIFMTU:
2845                 ifr = (struct ifreq *)data;
2846
2847                 PRIV_LOCK(priv);
2848                 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
2849
2850                 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
2851                     ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
2852                         int was_opened;
2853
2854                         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2855                         if (was_opened)
2856                                 mlx5e_close_locked(ifp);
2857
2858                         /* set new MTU */
2859                         mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
2860
2861                         if (was_opened)
2862                                 mlx5e_open_locked(ifp);
2863                 } else {
2864                         error = EINVAL;
2865                         if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n",
2866                             MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
2867                 }
2868                 PRIV_UNLOCK(priv);
2869                 break;
2870         case SIOCSIFFLAGS:
2871                 if ((ifp->if_flags & IFF_UP) &&
2872                     (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2873                         mlx5e_set_rx_mode(ifp);
2874                         break;
2875                 }
2876                 PRIV_LOCK(priv);
2877                 if (ifp->if_flags & IFF_UP) {
2878                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2879                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2880                                         mlx5e_open_locked(ifp);
2881                                 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2882                                 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
2883                         }
2884                 } else {
2885                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2886                                 mlx5_set_port_status(priv->mdev,
2887                                     MLX5_PORT_DOWN);
2888                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2889                                         mlx5e_close_locked(ifp);
2890                                 mlx5e_update_carrier(priv);
2891                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2892                         }
2893                 }
2894                 PRIV_UNLOCK(priv);
2895                 break;
2896         case SIOCADDMULTI:
2897         case SIOCDELMULTI:
2898                 mlx5e_set_rx_mode(ifp);
2899                 break;
2900         case SIOCSIFMEDIA:
2901         case SIOCGIFMEDIA:
2902         case SIOCGIFXMEDIA:
2903                 ifr = (struct ifreq *)data;
2904                 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
2905                 break;
2906         case SIOCSIFCAP:
2907                 ifr = (struct ifreq *)data;
2908                 PRIV_LOCK(priv);
2909                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2910
2911                 if (mask & IFCAP_TXCSUM) {
2912                         ifp->if_capenable ^= IFCAP_TXCSUM;
2913                         ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2914
2915                         if (IFCAP_TSO4 & ifp->if_capenable &&
2916                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2917                                 ifp->if_capenable &= ~IFCAP_TSO4;
2918                                 ifp->if_hwassist &= ~CSUM_IP_TSO;
2919                                 if_printf(ifp,
2920                                     "tso4 disabled due to -txcsum.\n");
2921                         }
2922                 }
2923                 if (mask & IFCAP_TXCSUM_IPV6) {
2924                         ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
2925                         ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2926
2927                         if (IFCAP_TSO6 & ifp->if_capenable &&
2928                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2929                                 ifp->if_capenable &= ~IFCAP_TSO6;
2930                                 ifp->if_hwassist &= ~CSUM_IP6_TSO;
2931                                 if_printf(ifp,
2932                                     "tso6 disabled due to -txcsum6.\n");
2933                         }
2934                 }
2935                 if (mask & IFCAP_RXCSUM)
2936                         ifp->if_capenable ^= IFCAP_RXCSUM;
2937                 if (mask & IFCAP_RXCSUM_IPV6)
2938                         ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
2939                 if (mask & IFCAP_TSO4) {
2940                         if (!(IFCAP_TSO4 & ifp->if_capenable) &&
2941                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2942                                 if_printf(ifp, "enable txcsum first.\n");
2943                                 error = EAGAIN;
2944                                 goto out;
2945                         }
2946                         ifp->if_capenable ^= IFCAP_TSO4;
2947                         ifp->if_hwassist ^= CSUM_IP_TSO;
2948                 }
2949                 if (mask & IFCAP_TSO6) {
2950                         if (!(IFCAP_TSO6 & ifp->if_capenable) &&
2951                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2952                                 if_printf(ifp, "enable txcsum6 first.\n");
2953                                 error = EAGAIN;
2954                                 goto out;
2955                         }
2956                         ifp->if_capenable ^= IFCAP_TSO6;
2957                         ifp->if_hwassist ^= CSUM_IP6_TSO;
2958                 }
2959                 if (mask & IFCAP_VLAN_HWFILTER) {
2960                         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
2961                                 mlx5e_disable_vlan_filter(priv);
2962                         else
2963                                 mlx5e_enable_vlan_filter(priv);
2964
2965                         ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
2966                 }
2967                 if (mask & IFCAP_VLAN_HWTAGGING)
2968                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2969                 if (mask & IFCAP_WOL_MAGIC)
2970                         ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2971
2972                 VLAN_CAPABILITIES(ifp);
2973                 /* turn off LRO means also turn of HW LRO - if it's on */
2974                 if (mask & IFCAP_LRO) {
2975                         int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2976                         bool need_restart = false;
2977
2978                         ifp->if_capenable ^= IFCAP_LRO;
2979
2980                         /* figure out if updating HW LRO is needed */
2981                         if (!(ifp->if_capenable & IFCAP_LRO)) {
2982                                 if (priv->params.hw_lro_en) {
2983                                         priv->params.hw_lro_en = false;
2984                                         need_restart = true;
2985                                 }
2986                         } else {
2987                                 if (priv->params.hw_lro_en == false &&
2988                                     priv->params_ethtool.hw_lro != 0) {
2989                                         priv->params.hw_lro_en = true;
2990                                         need_restart = true;
2991                                 }
2992                         }
2993                         if (was_opened && need_restart) {
2994                                 mlx5e_close_locked(ifp);
2995                                 mlx5e_open_locked(ifp);
2996                         }
2997                 }
2998                 if (mask & IFCAP_HWRXTSTMP) {
2999                         ifp->if_capenable ^= IFCAP_HWRXTSTMP;
3000                         if (ifp->if_capenable & IFCAP_HWRXTSTMP) {
3001                                 if (priv->clbr_done == 0)
3002                                         mlx5e_reset_calibration_callout(priv);
3003                         } else {
3004                                 callout_drain(&priv->tstmp_clbr);
3005                                 priv->clbr_done = 0;
3006                         }
3007                 }
3008 out:
3009                 PRIV_UNLOCK(priv);
3010                 break;
3011
3012         case SIOCGI2C:
3013                 ifr = (struct ifreq *)data;
3014
3015                 /*
3016                  * Copy from the user-space address ifr_data to the
3017                  * kernel-space address i2c
3018                  */
3019                 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
3020                 if (error)
3021                         break;
3022
3023                 if (i2c.len > sizeof(i2c.data)) {
3024                         error = EINVAL;
3025                         break;
3026                 }
3027
3028                 PRIV_LOCK(priv);
3029                 /* Get module_num which is required for the query_eeprom */
3030                 error = mlx5_query_module_num(priv->mdev, &module_num);
3031                 if (error) {
3032                         if_printf(ifp, "Query module num failed, eeprom "
3033                             "reading is not supported\n");
3034                         error = EINVAL;
3035                         goto err_i2c;
3036                 }
3037                 /* Check if module is present before doing an access */
3038                 module_status = mlx5_query_module_status(priv->mdev, module_num);
3039                 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED &&
3040                     module_status != MLX5_MODULE_STATUS_PLUGGED_DISABLED) {
3041                         error = EINVAL;
3042                         goto err_i2c;
3043                 }
3044                 /*
3045                  * Currently 0XA0 and 0xA2 are the only addresses permitted.
3046                  * The internal conversion is as follows:
3047                  */
3048                 if (i2c.dev_addr == 0xA0)
3049                         read_addr = MLX5E_I2C_ADDR_LOW;
3050                 else if (i2c.dev_addr == 0xA2)
3051                         read_addr = MLX5E_I2C_ADDR_HIGH;
3052                 else {
3053                         if_printf(ifp, "Query eeprom failed, "
3054                             "Invalid Address: %X\n", i2c.dev_addr);
3055                         error = EINVAL;
3056                         goto err_i2c;
3057                 }
3058                 error = mlx5_query_eeprom(priv->mdev,
3059                     read_addr, MLX5E_EEPROM_LOW_PAGE,
3060                     (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
3061                     (uint32_t *)i2c.data, &size_read);
3062                 if (error) {
3063                         if_printf(ifp, "Query eeprom failed, eeprom "
3064                             "reading is not supported\n");
3065                         error = EINVAL;
3066                         goto err_i2c;
3067                 }
3068
3069                 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
3070                         error = mlx5_query_eeprom(priv->mdev,
3071                             read_addr, MLX5E_EEPROM_LOW_PAGE,
3072                             (uint32_t)(i2c.offset + size_read),
3073                             (uint32_t)(i2c.len - size_read), module_num,
3074                             (uint32_t *)(i2c.data + size_read), &size_read);
3075                 }
3076                 if (error) {
3077                         if_printf(ifp, "Query eeprom failed, eeprom "
3078                             "reading is not supported\n");
3079                         error = EINVAL;
3080                         goto err_i2c;
3081                 }
3082
3083                 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
3084 err_i2c:
3085                 PRIV_UNLOCK(priv);
3086                 break;
3087
3088         default:
3089                 error = ether_ioctl(ifp, command, data);
3090                 break;
3091         }
3092         return (error);
3093 }
3094
3095 static int
3096 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3097 {
3098         /*
3099          * TODO: uncoment once FW really sets all these bits if
3100          * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
3101          * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
3102          * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
3103          * -ENOTSUPP;
3104          */
3105
3106         /* TODO: add more must-to-have features */
3107
3108         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3109                 return (-ENODEV);
3110
3111         return (0);
3112 }
3113
3114 static u16
3115 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3116 {
3117         uint32_t bf_buf_size = (1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U;
3118
3119         bf_buf_size -= sizeof(struct mlx5e_tx_wqe) - 2;
3120
3121         /* verify against driver hardware limit */
3122         if (bf_buf_size > MLX5E_MAX_TX_INLINE)
3123                 bf_buf_size = MLX5E_MAX_TX_INLINE;
3124
3125         return (bf_buf_size);
3126 }
3127
3128 static int
3129 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
3130     struct mlx5e_priv *priv,
3131     int num_comp_vectors)
3132 {
3133         int err;
3134
3135         /*
3136          * TODO: Consider link speed for setting "log_sq_size",
3137          * "log_rq_size" and "cq_moderation_xxx":
3138          */
3139         priv->params.log_sq_size =
3140             MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3141         priv->params.log_rq_size =
3142             MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3143         priv->params.rx_cq_moderation_usec =
3144             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3145             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
3146             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3147         priv->params.rx_cq_moderation_mode =
3148             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
3149         priv->params.rx_cq_moderation_pkts =
3150             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3151         priv->params.tx_cq_moderation_usec =
3152             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3153         priv->params.tx_cq_moderation_pkts =
3154             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3155         priv->params.min_rx_wqes =
3156             MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
3157         priv->params.rx_hash_log_tbl_sz =
3158             (order_base_2(num_comp_vectors) >
3159             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
3160             order_base_2(num_comp_vectors) :
3161             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
3162         priv->params.num_tc = 1;
3163         priv->params.default_vlan_prio = 0;
3164         priv->counter_set_id = -1;
3165         priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3166
3167         err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3168         if (err)
3169                 return (err);
3170
3171         /*
3172          * hw lro is currently defaulted to off. when it won't anymore we
3173          * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
3174          */
3175         priv->params.hw_lro_en = false;
3176         priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3177
3178         /*
3179          * CQE zipping is currently defaulted to off. when it won't
3180          * anymore we will consider the HW capability:
3181          * "!!MLX5_CAP_GEN(mdev, cqe_compression)"
3182          */
3183         priv->params.cqe_zipping_en = false;
3184
3185         priv->mdev = mdev;
3186         priv->params.num_channels = num_comp_vectors;
3187         priv->params.channels_rsss = 1;
3188         priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
3189         priv->queue_mapping_channel_mask =
3190             roundup_pow_of_two(num_comp_vectors) - 1;
3191         priv->num_tc = priv->params.num_tc;
3192         priv->default_vlan_prio = priv->params.default_vlan_prio;
3193
3194         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3195         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3196         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3197
3198         return (0);
3199 }
3200
3201 static int
3202 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
3203                   struct mlx5_core_mr *mkey)
3204 {
3205         struct ifnet *ifp = priv->ifp;
3206         struct mlx5_core_dev *mdev = priv->mdev;
3207         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3208         void *mkc;
3209         u32 *in;
3210         int err;
3211
3212         in = mlx5_vzalloc(inlen);
3213         if (in == NULL) {
3214                 if_printf(ifp, "%s: failed to allocate inbox\n", __func__);
3215                 return (-ENOMEM);
3216         }
3217
3218         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3219         MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA);
3220         MLX5_SET(mkc, mkc, lw, 1);
3221         MLX5_SET(mkc, mkc, lr, 1);
3222
3223         MLX5_SET(mkc, mkc, pd, pdn);
3224         MLX5_SET(mkc, mkc, length64, 1);
3225         MLX5_SET(mkc, mkc, qpn, 0xffffff);
3226
3227         err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
3228         if (err)
3229                 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n",
3230                     __func__, err);
3231
3232         kvfree(in);
3233         return (err);
3234 }
3235
3236 static const char *mlx5e_vport_stats_desc[] = {
3237         MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
3238 };
3239
3240 static const char *mlx5e_pport_stats_desc[] = {
3241         MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
3242 };
3243
3244 static void
3245 mlx5e_priv_mtx_init(struct mlx5e_priv *priv)
3246 {
3247         mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
3248         sx_init(&priv->state_lock, "mlx5state");
3249         callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
3250         MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
3251 }
3252
3253 static void
3254 mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv)
3255 {
3256         mtx_destroy(&priv->async_events_mtx);
3257         sx_destroy(&priv->state_lock);
3258 }
3259
3260 static int
3261 sysctl_firmware(SYSCTL_HANDLER_ARGS)
3262 {
3263         /*
3264          * %d.%d%.d the string format.
3265          * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
3266          * We need at most 5 chars to store that.
3267          * It also has: two "." and NULL at the end, which means we need 18
3268          * (5*3 + 3) chars at most.
3269          */
3270         char fw[18];
3271         struct mlx5e_priv *priv = arg1;
3272         int error;
3273
3274         snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
3275             fw_rev_sub(priv->mdev));
3276         error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
3277         return (error);
3278 }
3279
3280 static void
3281 mlx5e_disable_tx_dma(struct mlx5e_channel *ch)
3282 {
3283         int i;
3284
3285         for (i = 0; i < ch->num_tc; i++)
3286                 mlx5e_drain_sq(&ch->sq[i]);
3287 }
3288
3289 static void
3290 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq)
3291 {
3292
3293         sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP);
3294         sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8);
3295         mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
3296         sq->doorbell.d64 = 0;
3297 }
3298
3299 void
3300 mlx5e_resume_sq(struct mlx5e_sq *sq)
3301 {
3302         int err;
3303
3304         /* check if already enabled */
3305         if (READ_ONCE(sq->running) != 0)
3306                 return;
3307
3308         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR,
3309             MLX5_SQC_STATE_RST);
3310         if (err != 0) {
3311                 if_printf(sq->ifp,
3312                     "mlx5e_modify_sq() from ERR to RST failed: %d\n", err);
3313         }
3314
3315         sq->cc = 0;
3316         sq->pc = 0;
3317
3318         /* reset doorbell prior to moving from RST to RDY */
3319         mlx5e_reset_sq_doorbell_record(sq);
3320
3321         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST,
3322             MLX5_SQC_STATE_RDY);
3323         if (err != 0) {
3324                 if_printf(sq->ifp,
3325                     "mlx5e_modify_sq() from RST to RDY failed: %d\n", err);
3326         }
3327
3328         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
3329         WRITE_ONCE(sq->running, 1);
3330 }
3331
3332 static void
3333 mlx5e_enable_tx_dma(struct mlx5e_channel *ch)
3334 {
3335         int i;
3336
3337         for (i = 0; i < ch->num_tc; i++)
3338                 mlx5e_resume_sq(&ch->sq[i]);
3339 }
3340
3341 static void
3342 mlx5e_disable_rx_dma(struct mlx5e_channel *ch)
3343 {
3344         struct mlx5e_rq *rq = &ch->rq;
3345         int err;
3346
3347         mtx_lock(&rq->mtx);
3348         rq->enabled = 0;
3349         callout_stop(&rq->watchdog);
3350         mtx_unlock(&rq->mtx);
3351
3352         callout_drain(&rq->watchdog);
3353
3354         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
3355         if (err != 0) {
3356                 if_printf(rq->ifp,
3357                     "mlx5e_modify_rq() from RDY to RST failed: %d\n", err);
3358         }
3359
3360         while (!mlx5_wq_ll_is_empty(&rq->wq)) {
3361                 msleep(1);
3362                 rq->cq.mcq.comp(&rq->cq.mcq);
3363         }
3364
3365         /*
3366          * Transitioning into RST state will allow the FW to track less ERR state queues,
3367          * thus reducing the recv queue flushing time
3368          */
3369         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST);
3370         if (err != 0) {
3371                 if_printf(rq->ifp,
3372                     "mlx5e_modify_rq() from ERR to RST failed: %d\n", err);
3373         }
3374 }
3375
3376 static void
3377 mlx5e_enable_rx_dma(struct mlx5e_channel *ch)
3378 {
3379         struct mlx5e_rq *rq = &ch->rq;
3380         int err;
3381
3382         rq->wq.wqe_ctr = 0;
3383         mlx5_wq_ll_update_db_record(&rq->wq);
3384         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3385         if (err != 0) {
3386                 if_printf(rq->ifp,
3387                     "mlx5e_modify_rq() from RST to RDY failed: %d\n", err);
3388         }
3389
3390         rq->enabled = 1;
3391
3392         rq->cq.mcq.comp(&rq->cq.mcq);
3393 }
3394
3395 void
3396 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value)
3397 {
3398         int i;
3399
3400         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3401                 return;
3402
3403         for (i = 0; i < priv->params.num_channels; i++) {
3404                 if (value)
3405                         mlx5e_disable_tx_dma(&priv->channel[i]);
3406                 else
3407                         mlx5e_enable_tx_dma(&priv->channel[i]);
3408         }
3409 }
3410
3411 void
3412 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value)
3413 {
3414         int i;
3415
3416         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3417                 return;
3418
3419         for (i = 0; i < priv->params.num_channels; i++) {
3420                 if (value)
3421                         mlx5e_disable_rx_dma(&priv->channel[i]);
3422                 else
3423                         mlx5e_enable_rx_dma(&priv->channel[i]);
3424         }
3425 }
3426
3427 static void
3428 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
3429 {
3430         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3431             OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
3432             sysctl_firmware, "A", "HCA firmware version");
3433
3434         SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3435             OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
3436             "Board ID");
3437 }
3438
3439 static int
3440 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3441 {
3442         struct mlx5e_priv *priv = arg1;
3443         uint8_t temp[MLX5E_MAX_PRIORITY];
3444         uint32_t tx_pfc;
3445         int err;
3446         int i;
3447
3448         PRIV_LOCK(priv);
3449
3450         tx_pfc = priv->params.tx_priority_flow_control;
3451
3452         for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3453                 temp[i] = (tx_pfc >> i) & 1;
3454
3455         err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3456         if (err || !req->newptr)
3457                 goto done;
3458         err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3459         if (err)
3460                 goto done;
3461
3462         priv->params.tx_priority_flow_control = 0;
3463
3464         /* range check input value */
3465         for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3466                 if (temp[i] > 1) {
3467                         err = ERANGE;
3468                         goto done;
3469                 }
3470                 priv->params.tx_priority_flow_control |= (temp[i] << i);
3471         }
3472
3473         /* check if update is required */
3474         if (tx_pfc != priv->params.tx_priority_flow_control)
3475                 err = -mlx5e_set_port_pfc(priv);
3476 done:
3477         if (err != 0)
3478                 priv->params.tx_priority_flow_control= tx_pfc;
3479         PRIV_UNLOCK(priv);
3480
3481         return (err);
3482 }
3483
3484 static int
3485 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3486 {
3487         struct mlx5e_priv *priv = arg1;
3488         uint8_t temp[MLX5E_MAX_PRIORITY];
3489         uint32_t rx_pfc;
3490         int err;
3491         int i;
3492
3493         PRIV_LOCK(priv);
3494
3495         rx_pfc = priv->params.rx_priority_flow_control;
3496
3497         for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3498                 temp[i] = (rx_pfc >> i) & 1;
3499
3500         err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3501         if (err || !req->newptr)
3502                 goto done;
3503         err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3504         if (err)
3505                 goto done;
3506
3507         priv->params.rx_priority_flow_control = 0;
3508
3509         /* range check input value */
3510         for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3511                 if (temp[i] > 1) {
3512                         err = ERANGE;
3513                         goto done;
3514                 }
3515                 priv->params.rx_priority_flow_control |= (temp[i] << i);
3516         }
3517
3518         /* check if update is required */
3519         if (rx_pfc != priv->params.rx_priority_flow_control)
3520                 err = -mlx5e_set_port_pfc(priv);
3521 done:
3522         if (err != 0)
3523                 priv->params.rx_priority_flow_control= rx_pfc;
3524         PRIV_UNLOCK(priv);
3525
3526         return (err);
3527 }
3528
3529 static void
3530 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
3531 {
3532 #if (__FreeBSD_version < 1100000)
3533         char path[96];
3534 #endif
3535         int error;
3536
3537         /* enable pauseframes by default */
3538         priv->params.tx_pauseframe_control = 1;
3539         priv->params.rx_pauseframe_control = 1;
3540
3541         /* disable ports flow control, PFC, by default */
3542         priv->params.tx_priority_flow_control = 0;
3543         priv->params.rx_priority_flow_control = 0;
3544
3545 #if (__FreeBSD_version < 1100000)
3546         /* compute path for sysctl */
3547         snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
3548             device_get_unit(priv->mdev->pdev->dev.bsddev));
3549
3550         /* try to fetch tunable, if any */
3551         TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
3552
3553         /* compute path for sysctl */
3554         snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
3555             device_get_unit(priv->mdev->pdev->dev.bsddev));
3556
3557         /* try to fetch tunable, if any */
3558         TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
3559 #endif
3560
3561         /* register pauseframe SYSCTLs */
3562         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3563             OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
3564             &priv->params.tx_pauseframe_control, 0,
3565             "Set to enable TX pause frames. Clear to disable.");
3566
3567         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3568             OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
3569             &priv->params.rx_pauseframe_control, 0,
3570             "Set to enable RX pause frames. Clear to disable.");
3571
3572         /* register priority flow control, PFC, SYSCTLs */
3573         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3574             OID_AUTO, "tx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
3575             CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_tx_priority_flow_control, "CU",
3576             "Set to enable TX ports flow control frames for priorities 0..7. Clear to disable.");
3577
3578         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3579             OID_AUTO, "rx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
3580             CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_rx_priority_flow_control, "CU",
3581             "Set to enable RX ports flow control frames for priorities 0..7. Clear to disable.");
3582
3583         PRIV_LOCK(priv);
3584
3585         /* range check */
3586         priv->params.tx_pauseframe_control =
3587             priv->params.tx_pauseframe_control ? 1 : 0;
3588         priv->params.rx_pauseframe_control =
3589             priv->params.rx_pauseframe_control ? 1 : 0;
3590
3591         /* update firmware */
3592         error = mlx5e_set_port_pause_and_pfc(priv);
3593         if (error == -EINVAL) {
3594                 if_printf(priv->ifp,
3595                     "Global pauseframes must be disabled before enabling PFC.\n");
3596                 priv->params.rx_priority_flow_control = 0;
3597                 priv->params.tx_priority_flow_control = 0;
3598
3599                 /* update firmware */
3600                 (void) mlx5e_set_port_pause_and_pfc(priv);
3601         }
3602         PRIV_UNLOCK(priv);
3603 }
3604
3605 static int
3606 mlx5e_ul_snd_tag_alloc(struct ifnet *ifp,
3607     union if_snd_tag_alloc_params *params,
3608     struct m_snd_tag **ppmt)
3609 {
3610         struct mlx5e_priv *priv;
3611         struct mlx5e_channel *pch;
3612
3613         priv = ifp->if_softc;
3614
3615         if (unlikely(priv->gone || params->hdr.flowtype == M_HASHTYPE_NONE)) {
3616                 return (EOPNOTSUPP);
3617         } else {
3618                 /* keep this code synced with mlx5e_select_queue() */
3619                 u32 ch = priv->params.num_channels;
3620 #ifdef RSS
3621                 u32 temp;
3622
3623                 if (rss_hash2bucket(params->hdr.flowid,
3624                     params->hdr.flowtype, &temp) == 0)
3625                         ch = temp % ch;
3626                 else
3627 #endif
3628                         ch = (params->hdr.flowid % 128) % ch;
3629
3630                 /*
3631                  * NOTE: The channels array is only freed at detach
3632                  * and it safe to return a pointer to the send tag
3633                  * inside the channels structure as long as we
3634                  * reference the priv.
3635                  */
3636                 pch = priv->channel + ch;
3637
3638                 /* check if send queue is not running */
3639                 if (unlikely(pch->sq[0].running == 0))
3640                         return (ENXIO);
3641                 mlx5e_ref_channel(priv);
3642                 *ppmt = &pch->tag.m_snd_tag;
3643                 return (0);
3644         }
3645 }
3646
3647 static int
3648 mlx5e_ul_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
3649 {
3650         struct mlx5e_channel *pch =
3651             container_of(pmt, struct mlx5e_channel, tag.m_snd_tag);
3652
3653         params->unlimited.max_rate = -1ULL;
3654         params->unlimited.queue_level = mlx5e_sq_queue_level(&pch->sq[0]);
3655         return (0);
3656 }
3657
3658 static void
3659 mlx5e_ul_snd_tag_free(struct m_snd_tag *pmt)
3660 {
3661         struct mlx5e_channel *pch =
3662             container_of(pmt, struct mlx5e_channel, tag.m_snd_tag);
3663
3664         mlx5e_unref_channel(pch->priv);
3665 }
3666
3667 static int
3668 mlx5e_snd_tag_alloc(struct ifnet *ifp,
3669     union if_snd_tag_alloc_params *params,
3670     struct m_snd_tag **ppmt)
3671 {
3672
3673         switch (params->hdr.type) {
3674 #ifdef RATELIMIT
3675         case IF_SND_TAG_TYPE_RATE_LIMIT:
3676                 return (mlx5e_rl_snd_tag_alloc(ifp, params, ppmt));
3677 #endif
3678         case IF_SND_TAG_TYPE_UNLIMITED:
3679                 return (mlx5e_ul_snd_tag_alloc(ifp, params, ppmt));
3680         default:
3681                 return (EOPNOTSUPP);
3682         }
3683 }
3684
3685 static int
3686 mlx5e_snd_tag_modify(struct m_snd_tag *pmt, union if_snd_tag_modify_params *params)
3687 {
3688         struct mlx5e_snd_tag *tag =
3689             container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
3690
3691         switch (tag->type) {
3692 #ifdef RATELIMIT
3693         case IF_SND_TAG_TYPE_RATE_LIMIT:
3694                 return (mlx5e_rl_snd_tag_modify(pmt, params));
3695 #endif
3696         case IF_SND_TAG_TYPE_UNLIMITED:
3697         default:
3698                 return (EOPNOTSUPP);
3699         }
3700 }
3701
3702 static int
3703 mlx5e_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
3704 {
3705         struct mlx5e_snd_tag *tag =
3706             container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
3707
3708         switch (tag->type) {
3709 #ifdef RATELIMIT
3710         case IF_SND_TAG_TYPE_RATE_LIMIT:
3711                 return (mlx5e_rl_snd_tag_query(pmt, params));
3712 #endif
3713         case IF_SND_TAG_TYPE_UNLIMITED:
3714                 return (mlx5e_ul_snd_tag_query(pmt, params));
3715         default:
3716                 return (EOPNOTSUPP);
3717         }
3718 }
3719
3720 static void
3721 mlx5e_snd_tag_free(struct m_snd_tag *pmt)
3722 {
3723         struct mlx5e_snd_tag *tag =
3724             container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
3725
3726         switch (tag->type) {
3727 #ifdef RATELIMIT
3728         case IF_SND_TAG_TYPE_RATE_LIMIT:
3729                 mlx5e_rl_snd_tag_free(pmt);
3730                 break;
3731 #endif
3732         case IF_SND_TAG_TYPE_UNLIMITED:
3733                 mlx5e_ul_snd_tag_free(pmt);
3734                 break;
3735         default:
3736                 break;
3737         }
3738 }
3739
3740 static void *
3741 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
3742 {
3743         struct ifnet *ifp;
3744         struct mlx5e_priv *priv;
3745         u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
3746         struct sysctl_oid_list *child;
3747         int ncv = mdev->priv.eq_table.num_comp_vectors;
3748         char unit[16];
3749         int err;
3750         int i;
3751         u32 eth_proto_cap;
3752
3753         if (mlx5e_check_required_hca_cap(mdev)) {
3754                 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
3755                 return (NULL);
3756         }
3757         /*
3758          * Try to allocate the priv and make room for worst-case
3759          * number of channel structures:
3760          */
3761         priv = malloc(sizeof(*priv) +
3762             (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors),
3763             M_MLX5EN, M_WAITOK | M_ZERO);
3764         mlx5e_priv_mtx_init(priv);
3765
3766         ifp = priv->ifp = if_alloc(IFT_ETHER);
3767         if (ifp == NULL) {
3768                 mlx5_core_err(mdev, "if_alloc() failed\n");
3769                 goto err_free_priv;
3770         }
3771         ifp->if_softc = priv;
3772         if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev));
3773         ifp->if_mtu = ETHERMTU;
3774         ifp->if_init = mlx5e_open;
3775         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
3776         ifp->if_ioctl = mlx5e_ioctl;
3777         ifp->if_transmit = mlx5e_xmit;
3778         ifp->if_qflush = if_qflush;
3779 #if (__FreeBSD_version >= 1100000)
3780         ifp->if_get_counter = mlx5e_get_counter;
3781 #endif
3782         ifp->if_snd.ifq_maxlen = ifqmaxlen;
3783         /*
3784          * Set driver features
3785          */
3786         ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
3787         ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
3788         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
3789         ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
3790         ifp->if_capabilities |= IFCAP_LRO;
3791         ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
3792         ifp->if_capabilities |= IFCAP_HWSTATS | IFCAP_HWRXTSTMP;
3793         ifp->if_capabilities |= IFCAP_TXRTLMT;
3794         ifp->if_snd_tag_alloc = mlx5e_snd_tag_alloc;
3795         ifp->if_snd_tag_free = mlx5e_snd_tag_free;
3796         ifp->if_snd_tag_modify = mlx5e_snd_tag_modify;
3797         ifp->if_snd_tag_query = mlx5e_snd_tag_query;
3798
3799         /* set TSO limits so that we don't have to drop TX packets */
3800         ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
3801         ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
3802         ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
3803
3804         ifp->if_capenable = ifp->if_capabilities;
3805         ifp->if_hwassist = 0;
3806         if (ifp->if_capenable & IFCAP_TSO)
3807                 ifp->if_hwassist |= CSUM_TSO;
3808         if (ifp->if_capenable & IFCAP_TXCSUM)
3809                 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
3810         if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
3811                 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3812
3813         /* ifnet sysctl tree */
3814         sysctl_ctx_init(&priv->sysctl_ctx);
3815         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
3816             OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
3817         if (priv->sysctl_ifnet == NULL) {
3818                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3819                 goto err_free_sysctl;
3820         }
3821         snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
3822         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3823             OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
3824         if (priv->sysctl_ifnet == NULL) {
3825                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3826                 goto err_free_sysctl;
3827         }
3828
3829         /* HW sysctl tree */
3830         child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
3831         priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
3832             OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
3833         if (priv->sysctl_hw == NULL) {
3834                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3835                 goto err_free_sysctl;
3836         }
3837
3838         err = mlx5e_build_ifp_priv(mdev, priv, ncv);
3839         if (err) {
3840                 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err);
3841                 goto err_free_sysctl;
3842         }
3843
3844         snprintf(unit, sizeof(unit), "mce%u_wq",
3845             device_get_unit(mdev->pdev->dev.bsddev));
3846         priv->wq = alloc_workqueue(unit, 0, 1);
3847         if (priv->wq == NULL) {
3848                 if_printf(ifp, "%s: alloc_workqueue failed\n", __func__);
3849                 goto err_free_sysctl;
3850         }
3851
3852         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
3853         if (err) {
3854                 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n",
3855                     __func__, err);
3856                 goto err_free_wq;
3857         }
3858         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
3859         if (err) {
3860                 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n",
3861                     __func__, err);
3862                 goto err_unmap_free_uar;
3863         }
3864         err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
3865         if (err) {
3866                 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n",
3867                     __func__, err);
3868                 goto err_dealloc_pd;
3869         }
3870         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
3871         if (err) {
3872                 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n",
3873                     __func__, err);
3874                 goto err_dealloc_transport_domain;
3875         }
3876         mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
3877
3878         /* check if we should generate a random MAC address */
3879         if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
3880             is_zero_ether_addr(dev_addr)) {
3881                 random_ether_addr(dev_addr);
3882                 if_printf(ifp, "Assigned random MAC address\n");
3883         }
3884 #ifdef RATELIMIT
3885         err = mlx5e_rl_init(priv);
3886         if (err) {
3887                 if_printf(ifp, "%s: mlx5e_rl_init failed, %d\n",
3888                     __func__, err);
3889                 goto err_create_mkey;
3890         }
3891 #endif
3892
3893         /* set default MTU */
3894         mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
3895
3896         /* Set default media status */
3897         priv->media_status_last = IFM_AVALID;
3898         priv->media_active_last = IFM_ETHER | IFM_AUTO |
3899             IFM_ETH_RXPAUSE | IFM_FDX;
3900
3901         /* setup default pauseframes configuration */
3902         mlx5e_setup_pauseframes(priv);
3903
3904         err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
3905         if (err) {
3906                 eth_proto_cap = 0;
3907                 if_printf(ifp, "%s: Query port media capability failed, %d\n",
3908                     __func__, err);
3909         }
3910
3911         /* Setup supported medias */
3912         ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
3913             mlx5e_media_change, mlx5e_media_status);
3914
3915         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
3916                 if (mlx5e_mode_table[i].baudrate == 0)
3917                         continue;
3918                 if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
3919                         ifmedia_add(&priv->media,
3920                             mlx5e_mode_table[i].subtype |
3921                             IFM_ETHER, 0, NULL);
3922                         ifmedia_add(&priv->media,
3923                             mlx5e_mode_table[i].subtype |
3924                             IFM_ETHER | IFM_FDX |
3925                             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3926                 }
3927         }
3928
3929         /* Additional supported medias */
3930         ifmedia_add(&priv->media, IFM_10G_LR | IFM_ETHER, 0, NULL);
3931         ifmedia_add(&priv->media, IFM_10G_LR |
3932             IFM_ETHER | IFM_FDX |
3933             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3934
3935         ifmedia_add(&priv->media, IFM_40G_ER4 | IFM_ETHER, 0, NULL);
3936         ifmedia_add(&priv->media, IFM_40G_ER4 |
3937             IFM_ETHER | IFM_FDX |
3938             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3939
3940         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
3941         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3942             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3943
3944         /* Set autoselect by default */
3945         ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3946             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
3947         ether_ifattach(ifp, dev_addr);
3948
3949         /* Register for VLAN events */
3950         priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
3951             mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
3952         priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
3953             mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
3954
3955         /* Link is down by default */
3956         if_link_state_change(ifp, LINK_STATE_DOWN);
3957
3958         mlx5e_enable_async_events(priv);
3959
3960         mlx5e_add_hw_stats(priv);
3961
3962         mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3963             "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
3964             priv->stats.vport.arg);
3965
3966         mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3967             "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
3968             priv->stats.pport.arg);
3969
3970         mlx5e_create_ethtool(priv);
3971
3972         mtx_lock(&priv->async_events_mtx);
3973         mlx5e_update_stats(priv);
3974         mtx_unlock(&priv->async_events_mtx);
3975
3976         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3977             OID_AUTO, "rx_clbr_done", CTLFLAG_RD,
3978             &priv->clbr_done, 0,
3979             "RX timestamps calibration state");
3980         callout_init(&priv->tstmp_clbr, CALLOUT_DIRECT);
3981         mlx5e_reset_calibration_callout(priv);
3982
3983         return (priv);
3984
3985 #ifdef RATELIMIT
3986 err_create_mkey:
3987         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
3988 #endif
3989 err_dealloc_transport_domain:
3990         mlx5_dealloc_transport_domain(mdev, priv->tdn);
3991
3992 err_dealloc_pd:
3993         mlx5_core_dealloc_pd(mdev, priv->pdn);
3994
3995 err_unmap_free_uar:
3996         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3997
3998 err_free_wq:
3999         destroy_workqueue(priv->wq);
4000
4001 err_free_sysctl:
4002         sysctl_ctx_free(&priv->sysctl_ctx);
4003         if (priv->sysctl_debug)
4004                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4005         if_free(ifp);
4006
4007 err_free_priv:
4008         mlx5e_priv_mtx_destroy(priv);
4009         free(priv, M_MLX5EN);
4010         return (NULL);
4011 }
4012
4013 static void
4014 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
4015 {
4016         struct mlx5e_priv *priv = vpriv;
4017         struct ifnet *ifp = priv->ifp;
4018
4019         /* don't allow more IOCTLs */
4020         priv->gone = 1;
4021
4022         /* XXX wait a bit to allow IOCTL handlers to complete */
4023         pause("W", hz);
4024
4025 #ifdef RATELIMIT
4026         /*
4027          * The kernel can have reference(s) via the m_snd_tag's into
4028          * the ratelimit channels, and these must go away before
4029          * detaching:
4030          */
4031         while (READ_ONCE(priv->rl.stats.tx_active_connections) != 0) {
4032                 if_printf(priv->ifp, "Waiting for all ratelimit connections "
4033                     "to terminate\n");
4034                 pause("W", hz);
4035         }
4036 #endif
4037         /* stop watchdog timer */
4038         callout_drain(&priv->watchdog);
4039
4040         callout_drain(&priv->tstmp_clbr);
4041
4042         if (priv->vlan_attach != NULL)
4043                 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
4044         if (priv->vlan_detach != NULL)
4045                 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
4046
4047         /* make sure device gets closed */
4048         PRIV_LOCK(priv);
4049         mlx5e_close_locked(ifp);
4050         PRIV_UNLOCK(priv);
4051
4052         /* wait for all unlimited send tags to go away */
4053         while (priv->channel_refs != 0) {
4054                 if_printf(priv->ifp, "Waiting for all unlimited connections "
4055                     "to terminate\n");
4056                 pause("W", hz);
4057         }
4058
4059         /* unregister device */
4060         ifmedia_removeall(&priv->media);
4061         ether_ifdetach(ifp);
4062         if_free(ifp);
4063
4064 #ifdef RATELIMIT
4065         mlx5e_rl_cleanup(priv);
4066 #endif
4067         /* destroy all remaining sysctl nodes */
4068         sysctl_ctx_free(&priv->stats.vport.ctx);
4069         sysctl_ctx_free(&priv->stats.pport.ctx);
4070         if (priv->sysctl_debug)
4071                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4072         sysctl_ctx_free(&priv->sysctl_ctx);
4073
4074         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
4075         mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
4076         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
4077         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
4078         mlx5e_disable_async_events(priv);
4079         destroy_workqueue(priv->wq);
4080         mlx5e_priv_mtx_destroy(priv);
4081         free(priv, M_MLX5EN);
4082 }
4083
4084 static void *
4085 mlx5e_get_ifp(void *vpriv)
4086 {
4087         struct mlx5e_priv *priv = vpriv;
4088
4089         return (priv->ifp);
4090 }
4091
4092 static struct mlx5_interface mlx5e_interface = {
4093         .add = mlx5e_create_ifp,
4094         .remove = mlx5e_destroy_ifp,
4095         .event = mlx5e_async_event,
4096         .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4097         .get_dev = mlx5e_get_ifp,
4098 };
4099
4100 void
4101 mlx5e_init(void)
4102 {
4103         mlx5_register_interface(&mlx5e_interface);
4104 }
4105
4106 void
4107 mlx5e_cleanup(void)
4108 {
4109         mlx5_unregister_interface(&mlx5e_interface);
4110 }
4111
4112 static void
4113 mlx5e_show_version(void __unused *arg)
4114 {
4115
4116         printf("%s", mlx5e_version);
4117 }
4118 SYSINIT(mlx5e_show_version, SI_SUB_DRIVERS, SI_ORDER_ANY, mlx5e_show_version, NULL);
4119
4120 module_init_order(mlx5e_init, SI_ORDER_THIRD);
4121 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
4122
4123 #if (__FreeBSD_version >= 1100000)
4124 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
4125 #endif
4126 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
4127 MODULE_VERSION(mlx5en, 1);