sys/dev/mlx5/mlx5_en/mlx5_en_main.c

   1 /*-
   2  * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include "en.h"
  29
  30 #include <sys/sockio.h>
  31 #include <machine/atomic.h>
  32
  33 #define ETH_DRIVER_VERSION      "3.1.0-dev"
  34 char mlx5e_version[] = "Mellanox Ethernet driver"
  35     " (" ETH_DRIVER_VERSION ")";
  36
  37 struct mlx5e_channel_param {
  38         struct mlx5e_rq_param rq;
  39         struct mlx5e_sq_param sq;
  40         struct mlx5e_cq_param rx_cq;
  41         struct mlx5e_cq_param tx_cq;
  42 };
  43
  44 static const struct {
  45         u32     subtype;
  46         u64     baudrate;
  47 }       mlx5e_mode_table[MLX5E_LINK_MODES_NUMBER] = {
  48
  49         [MLX5E_1000BASE_CX_SGMII] = {
  50                 .subtype = IFM_1000_CX_SGMII,
  51                 .baudrate = IF_Mbps(1000ULL),
  52         },
  53         [MLX5E_1000BASE_KX] = {
  54                 .subtype = IFM_1000_KX,
  55                 .baudrate = IF_Mbps(1000ULL),
  56         },
  57         [MLX5E_10GBASE_CX4] = {
  58                 .subtype = IFM_10G_CX4,
  59                 .baudrate = IF_Gbps(10ULL),
  60         },
  61         [MLX5E_10GBASE_KX4] = {
  62                 .subtype = IFM_10G_KX4,
  63                 .baudrate = IF_Gbps(10ULL),
  64         },
  65         [MLX5E_10GBASE_KR] = {
  66                 .subtype = IFM_10G_KR,
  67                 .baudrate = IF_Gbps(10ULL),
  68         },
  69         [MLX5E_20GBASE_KR2] = {
  70                 .subtype = IFM_20G_KR2,
  71                 .baudrate = IF_Gbps(20ULL),
  72         },
  73         [MLX5E_40GBASE_CR4] = {
  74                 .subtype = IFM_40G_CR4,
  75                 .baudrate = IF_Gbps(40ULL),
  76         },
  77         [MLX5E_40GBASE_KR4] = {
  78                 .subtype = IFM_40G_KR4,
  79                 .baudrate = IF_Gbps(40ULL),
  80         },
  81         [MLX5E_56GBASE_R4] = {
  82                 .subtype = IFM_56G_R4,
  83                 .baudrate = IF_Gbps(56ULL),
  84         },
  85         [MLX5E_10GBASE_CR] = {
  86                 .subtype = IFM_10G_CR1,
  87                 .baudrate = IF_Gbps(10ULL),
  88         },
  89         [MLX5E_10GBASE_SR] = {
  90                 .subtype = IFM_10G_SR,
  91                 .baudrate = IF_Gbps(10ULL),
  92         },
  93         [MLX5E_10GBASE_LR] = {
  94                 .subtype = IFM_10G_LR,
  95                 .baudrate = IF_Gbps(10ULL),
  96         },
  97         [MLX5E_40GBASE_SR4] = {
  98                 .subtype = IFM_40G_SR4,
  99                 .baudrate = IF_Gbps(40ULL),
 100         },
 101         [MLX5E_40GBASE_LR4] = {
 102                 .subtype = IFM_40G_LR4,
 103                 .baudrate = IF_Gbps(40ULL),
 104         },
 105         [MLX5E_100GBASE_CR4] = {
 106                 .subtype = IFM_100G_CR4,
 107                 .baudrate = IF_Gbps(100ULL),
 108         },
 109         [MLX5E_100GBASE_SR4] = {
 110                 .subtype = IFM_100G_SR4,
 111                 .baudrate = IF_Gbps(100ULL),
 112         },
 113         [MLX5E_100GBASE_KR4] = {
 114                 .subtype = IFM_100G_KR4,
 115                 .baudrate = IF_Gbps(100ULL),
 116         },
 117         [MLX5E_100GBASE_LR4] = {
 118                 .subtype = IFM_100G_LR4,
 119                 .baudrate = IF_Gbps(100ULL),
 120         },
 121         [MLX5E_100BASE_TX] = {
 122                 .subtype = IFM_100_TX,
 123                 .baudrate = IF_Mbps(100ULL),
 124         },
 125         [MLX5E_100BASE_T] = {
 126                 .subtype = IFM_100_T,
 127                 .baudrate = IF_Mbps(100ULL),
 128         },
 129         [MLX5E_10GBASE_T] = {
 130                 .subtype = IFM_10G_T,
 131                 .baudrate = IF_Gbps(10ULL),
 132         },
 133         [MLX5E_25GBASE_CR] = {
 134                 .subtype = IFM_25G_CR,
 135                 .baudrate = IF_Gbps(25ULL),
 136         },
 137         [MLX5E_25GBASE_KR] = {
 138                 .subtype = IFM_25G_KR,
 139                 .baudrate = IF_Gbps(25ULL),
 140         },
 141         [MLX5E_25GBASE_SR] = {
 142                 .subtype = IFM_25G_SR,
 143                 .baudrate = IF_Gbps(25ULL),
 144         },
 145         [MLX5E_50GBASE_CR2] = {
 146                 .subtype = IFM_50G_CR2,
 147                 .baudrate = IF_Gbps(50ULL),
 148         },
 149         [MLX5E_50GBASE_KR2] = {
 150                 .subtype = IFM_50G_KR2,
 151                 .baudrate = IF_Gbps(50ULL),
 152         },
 153 };
 154
 155 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
 156
 157 static void
 158 mlx5e_update_carrier(struct mlx5e_priv *priv)
 159 {
 160         struct mlx5_core_dev *mdev = priv->mdev;
 161         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 162         u32 eth_proto_oper;
 163         int error;
 164         u8 port_state;
 165         u8 i;
 166
 167         port_state = mlx5_query_vport_state(mdev,
 168             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 169
 170         if (port_state == VPORT_STATE_UP) {
 171                 priv->media_status_last |= IFM_ACTIVE;
 172         } else {
 173                 priv->media_status_last &= ~IFM_ACTIVE;
 174                 priv->media_active_last = IFM_ETHER;
 175                 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
 176                 return;
 177         }
 178
 179         error = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN);
 180         if (error) {
 181                 priv->media_active_last = IFM_ETHER;
 182                 priv->ifp->if_baudrate = 1;
 183                 if_printf(priv->ifp, "%s: query port ptys failed: 0x%x\n",
 184                     __func__, error);
 185                 return;
 186         }
 187         eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
 188
 189         for (i = 0; i != MLX5E_LINK_MODES_NUMBER; i++) {
 190                 if (mlx5e_mode_table[i].baudrate == 0)
 191                         continue;
 192                 if (MLX5E_PROT_MASK(i) & eth_proto_oper) {
 193                         priv->ifp->if_baudrate =
 194                             mlx5e_mode_table[i].baudrate;
 195                         priv->media_active_last =
 196                             mlx5e_mode_table[i].subtype | IFM_ETHER | IFM_FDX;
 197                 }
 198         }
 199         if_link_state_change(priv->ifp, LINK_STATE_UP);
 200 }
 201
 202 static void
 203 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
 204 {
 205         struct mlx5e_priv *priv = dev->if_softc;
 206
 207         ifmr->ifm_status = priv->media_status_last;
 208         ifmr->ifm_active = priv->media_active_last |
 209             (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
 210             (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
 211
 212 }
 213
 214 static u32
 215 mlx5e_find_link_mode(u32 subtype)
 216 {
 217         u32 i;
 218         u32 link_mode = 0;
 219
 220         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
 221                 if (mlx5e_mode_table[i].baudrate == 0)
 222                         continue;
 223                 if (mlx5e_mode_table[i].subtype == subtype)
 224                         link_mode |= MLX5E_PROT_MASK(i);
 225         }
 226
 227         return (link_mode);
 228 }
 229
 230 static int
 231 mlx5e_media_change(struct ifnet *dev)
 232 {
 233         struct mlx5e_priv *priv = dev->if_softc;
 234         struct mlx5_core_dev *mdev = priv->mdev;
 235         u32 eth_proto_cap;
 236         u32 link_mode;
 237         int was_opened;
 238         int locked;
 239         int error;
 240
 241         locked = PRIV_LOCKED(priv);
 242         if (!locked)
 243                 PRIV_LOCK(priv);
 244
 245         if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
 246                 error = EINVAL;
 247                 goto done;
 248         }
 249         link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media));
 250
 251         /* query supported capabilities */
 252         error = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
 253         if (error != 0) {
 254                 if_printf(dev, "Query port media capability failed\n");
 255                 goto done;
 256         }
 257         /* check for autoselect */
 258         if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
 259                 link_mode = eth_proto_cap;
 260                 if (link_mode == 0) {
 261                         if_printf(dev, "Port media capability is zero\n");
 262                         error = EINVAL;
 263                         goto done;
 264                 }
 265         } else {
 266                 link_mode = link_mode & eth_proto_cap;
 267                 if (link_mode == 0) {
 268                         if_printf(dev, "Not supported link mode requested\n");
 269                         error = EINVAL;
 270                         goto done;
 271                 }
 272         }
 273         /* update pauseframe control bits */
 274         priv->params.rx_pauseframe_control =
 275             (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
 276         priv->params.tx_pauseframe_control =
 277             (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
 278
 279         /* check if device is opened */
 280         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
 281
 282         /* reconfigure the hardware */
 283         mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
 284         mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN);
 285         mlx5_set_port_pause(mdev, 1,
 286             priv->params.rx_pauseframe_control,
 287             priv->params.tx_pauseframe_control);
 288         if (was_opened)
 289                 mlx5_set_port_status(mdev, MLX5_PORT_UP);
 290
 291 done:
 292         if (!locked)
 293                 PRIV_UNLOCK(priv);
 294         return (error);
 295 }
 296
 297 static void
 298 mlx5e_update_carrier_work(struct work_struct *work)
 299 {
 300         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 301             update_carrier_work);
 302
 303         PRIV_LOCK(priv);
 304         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 305                 mlx5e_update_carrier(priv);
 306         PRIV_UNLOCK(priv);
 307 }
 308
 309 /*
 310  * This function reads the physical port counters from the firmware
 311  * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
 312  * macros. The output is converted from big-endian 64-bit values into
 313  * host endian ones and stored in the "priv->stats.pport" structure.
 314  */
 315 static void
 316 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 317 {
 318         struct mlx5_core_dev *mdev = priv->mdev;
 319         struct mlx5e_pport_stats *s = &priv->stats.pport;
 320         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 321         u32 *in;
 322         u32 *out;
 323         const u64 *ptr;
 324         unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 325         unsigned x;
 326         unsigned y;
 327
 328         /* allocate firmware request structures */
 329         in = mlx5_vzalloc(sz);
 330         out = mlx5_vzalloc(sz);
 331         if (in == NULL || out == NULL)
 332                 goto free_out;
 333
 334         /*
 335          * Get pointer to the 64-bit counter set which is located at a
 336          * fixed offset in the output firmware request structure:
 337          */
 338         ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
 339
 340         MLX5_SET(ppcnt_reg, in, local_port, 1);
 341
 342         /* read IEEE802_3 counter group using predefined counter layout */
 343         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 344         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 345         for (x = y = 0; x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
 346                 s->arg[y] = be64toh(ptr[x]);
 347
 348         /* read RFC2819 counter group using predefined counter layout */
 349         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 350         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 351         for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
 352                 s->arg[y] = be64toh(ptr[x]);
 353         for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
 354             MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
 355                 s_debug->arg[y] = be64toh(ptr[x]);
 356
 357         /* read RFC2863 counter group using predefined counter layout */
 358         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 359         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 360         for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
 361                 s_debug->arg[y] = be64toh(ptr[x]);
 362
 363         /* read physical layer stats counter group using predefined counter layout */
 364         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 365         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 366         for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
 367                 s_debug->arg[y] = be64toh(ptr[x]);
 368 free_out:
 369         /* free firmware request structures */
 370         kvfree(in);
 371         kvfree(out);
 372 }
 373
 374 /*
 375  * This function is called regularly to collect all statistics
 376  * counters from the firmware. The values can be viewed through the
 377  * sysctl interface. Execution is serialized using the priv's global
 378  * configuration lock.
 379  */
 380 static void
 381 mlx5e_update_stats_work(struct work_struct *work)
 382 {
 383         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 384             update_stats_work);
 385         struct mlx5_core_dev *mdev = priv->mdev;
 386         struct mlx5e_vport_stats *s = &priv->stats.vport;
 387         struct mlx5e_rq_stats *rq_stats;
 388         struct mlx5e_sq_stats *sq_stats;
 389         struct buf_ring *sq_br;
 390 #if (__FreeBSD_version < 1100000)
 391         struct ifnet *ifp = priv->ifp;
 392 #endif
 393
 394         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 395         u32 *out;
 396         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 397         u64 tso_packets = 0;
 398         u64 tso_bytes = 0;
 399         u64 tx_queue_dropped = 0;
 400         u64 tx_defragged = 0;
 401         u64 tx_offload_none = 0;
 402         u64 lro_packets = 0;
 403         u64 lro_bytes = 0;
 404         u64 sw_lro_queued = 0;
 405         u64 sw_lro_flushed = 0;
 406         u64 rx_csum_none = 0;
 407         u64 rx_wqe_err = 0;
 408         u32 rx_out_of_buffer = 0;
 409         int i;
 410         int j;
 411
 412         PRIV_LOCK(priv);
 413         out = mlx5_vzalloc(outlen);
 414         if (out == NULL)
 415                 goto free_out;
 416         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
 417                 goto free_out;
 418
 419         /* Collect firts the SW counters and then HW for consistency */
 420         for (i = 0; i < priv->params.num_channels; i++) {
 421                 struct mlx5e_rq *rq = &priv->channel[i]->rq;
 422
 423                 rq_stats = &priv->channel[i]->rq.stats;
 424
 425                 /* collect stats from LRO */
 426                 rq_stats->sw_lro_queued = rq->lro.lro_queued;
 427                 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
 428                 sw_lro_queued += rq_stats->sw_lro_queued;
 429                 sw_lro_flushed += rq_stats->sw_lro_flushed;
 430                 lro_packets += rq_stats->lro_packets;
 431                 lro_bytes += rq_stats->lro_bytes;
 432                 rx_csum_none += rq_stats->csum_none;
 433                 rx_wqe_err += rq_stats->wqe_err;
 434
 435                 for (j = 0; j < priv->num_tc; j++) {
 436                         sq_stats = &priv->channel[i]->sq[j].stats;
 437                         sq_br = priv->channel[i]->sq[j].br;
 438
 439                         tso_packets += sq_stats->tso_packets;
 440                         tso_bytes += sq_stats->tso_bytes;
 441                         tx_queue_dropped += sq_stats->dropped;
 442                         tx_queue_dropped += sq_br->br_drops;
 443                         tx_defragged += sq_stats->defragged;
 444                         tx_offload_none += sq_stats->csum_offload_none;
 445                 }
 446         }
 447
 448         /* update counters */
 449         s->tso_packets = tso_packets;
 450         s->tso_bytes = tso_bytes;
 451         s->tx_queue_dropped = tx_queue_dropped;
 452         s->tx_defragged = tx_defragged;
 453         s->lro_packets = lro_packets;
 454         s->lro_bytes = lro_bytes;
 455         s->sw_lro_queued = sw_lro_queued;
 456         s->sw_lro_flushed = sw_lro_flushed;
 457         s->rx_csum_none = rx_csum_none;
 458         s->rx_wqe_err = rx_wqe_err;
 459
 460         /* HW counters */
 461         memset(in, 0, sizeof(in));
 462
 463         MLX5_SET(query_vport_counter_in, in, opcode,
 464             MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 465         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 466         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 467
 468         memset(out, 0, outlen);
 469
 470         /* get number of out-of-buffer drops first */
 471         if (mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
 472             &rx_out_of_buffer))
 473                 goto free_out;
 474
 475         /* accumulate difference into a 64-bit counter */
 476         s->rx_out_of_buffer += (u64)(u32)(rx_out_of_buffer - s->rx_out_of_buffer_prev);
 477         s->rx_out_of_buffer_prev = rx_out_of_buffer;
 478
 479         /* get port statistics */
 480         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
 481                 goto free_out;
 482
 483 #define MLX5_GET_CTR(out, x) \
 484         MLX5_GET64(query_vport_counter_out, out, x)
 485
 486         s->rx_error_packets =
 487             MLX5_GET_CTR(out, received_errors.packets);
 488         s->rx_error_bytes =
 489             MLX5_GET_CTR(out, received_errors.octets);
 490         s->tx_error_packets =
 491             MLX5_GET_CTR(out, transmit_errors.packets);
 492         s->tx_error_bytes =
 493             MLX5_GET_CTR(out, transmit_errors.octets);
 494
 495         s->rx_unicast_packets =
 496             MLX5_GET_CTR(out, received_eth_unicast.packets);
 497         s->rx_unicast_bytes =
 498             MLX5_GET_CTR(out, received_eth_unicast.octets);
 499         s->tx_unicast_packets =
 500             MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 501         s->tx_unicast_bytes =
 502             MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 503
 504         s->rx_multicast_packets =
 505             MLX5_GET_CTR(out, received_eth_multicast.packets);
 506         s->rx_multicast_bytes =
 507             MLX5_GET_CTR(out, received_eth_multicast.octets);
 508         s->tx_multicast_packets =
 509             MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 510         s->tx_multicast_bytes =
 511             MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 512
 513         s->rx_broadcast_packets =
 514             MLX5_GET_CTR(out, received_eth_broadcast.packets);
 515         s->rx_broadcast_bytes =
 516             MLX5_GET_CTR(out, received_eth_broadcast.octets);
 517         s->tx_broadcast_packets =
 518             MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 519         s->tx_broadcast_bytes =
 520             MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 521
 522         s->rx_packets =
 523             s->rx_unicast_packets +
 524             s->rx_multicast_packets +
 525             s->rx_broadcast_packets -
 526             s->rx_out_of_buffer;
 527         s->rx_bytes =
 528             s->rx_unicast_bytes +
 529             s->rx_multicast_bytes +
 530             s->rx_broadcast_bytes;
 531         s->tx_packets =
 532             s->tx_unicast_packets +
 533             s->tx_multicast_packets +
 534             s->tx_broadcast_packets;
 535         s->tx_bytes =
 536             s->tx_unicast_bytes +
 537             s->tx_multicast_bytes +
 538             s->tx_broadcast_bytes;
 539
 540         /* Update calculated offload counters */
 541         s->tx_csum_offload = s->tx_packets - tx_offload_none;
 542         s->rx_csum_good = s->rx_packets - s->rx_csum_none;
 543
 544         /* Update per port counters */
 545         mlx5e_update_pport_counters(priv);
 546
 547 #if (__FreeBSD_version < 1100000)
 548         /* no get_counters interface in fbsd 10 */
 549         ifp->if_ipackets = s->rx_packets;
 550         ifp->if_ierrors = s->rx_error_packets;
 551         ifp->if_iqdrops = s->rx_out_of_buffer;
 552         ifp->if_opackets = s->tx_packets;
 553         ifp->if_oerrors = s->tx_error_packets;
 554         ifp->if_snd.ifq_drops = s->tx_queue_dropped;
 555         ifp->if_ibytes = s->rx_bytes;
 556         ifp->if_obytes = s->tx_bytes;
 557 #endif
 558
 559 free_out:
 560         kvfree(out);
 561         PRIV_UNLOCK(priv);
 562 }
 563
 564 static void
 565 mlx5e_update_stats(void *arg)
 566 {
 567         struct mlx5e_priv *priv = arg;
 568
 569         schedule_work(&priv->update_stats_work);
 570
 571         callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
 572 }
 573
 574 static void
 575 mlx5e_async_event_sub(struct mlx5e_priv *priv,
 576     enum mlx5_dev_event event)
 577 {
 578         switch (event) {
 579         case MLX5_DEV_EVENT_PORT_UP:
 580         case MLX5_DEV_EVENT_PORT_DOWN:
 581                 schedule_work(&priv->update_carrier_work);
 582                 break;
 583
 584         default:
 585                 break;
 586         }
 587 }
 588
 589 static void
 590 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 591     enum mlx5_dev_event event, unsigned long param)
 592 {
 593         struct mlx5e_priv *priv = vpriv;
 594
 595         mtx_lock(&priv->async_events_mtx);
 596         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 597                 mlx5e_async_event_sub(priv, event);
 598         mtx_unlock(&priv->async_events_mtx);
 599 }
 600
 601 static void
 602 mlx5e_enable_async_events(struct mlx5e_priv *priv)
 603 {
 604         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 605 }
 606
 607 static void
 608 mlx5e_disable_async_events(struct mlx5e_priv *priv)
 609 {
 610         mtx_lock(&priv->async_events_mtx);
 611         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 612         mtx_unlock(&priv->async_events_mtx);
 613 }
 614
 615 static const char *mlx5e_rq_stats_desc[] = {
 616         MLX5E_RQ_STATS(MLX5E_STATS_DESC)
 617 };
 618
 619 static int
 620 mlx5e_create_rq(struct mlx5e_channel *c,
 621     struct mlx5e_rq_param *param,
 622     struct mlx5e_rq *rq)
 623 {
 624         struct mlx5e_priv *priv = c->priv;
 625         struct mlx5_core_dev *mdev = priv->mdev;
 626         char buffer[16];
 627         void *rqc = param->rqc;
 628         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 629         int wq_sz;
 630         int err;
 631         int i;
 632
 633         /* Create DMA descriptor TAG */
 634         if ((err = -bus_dma_tag_create(
 635             bus_get_dma_tag(mdev->pdev->dev.bsddev),
 636             1,                          /* any alignment */
 637             0,                          /* no boundary */
 638             BUS_SPACE_MAXADDR,          /* lowaddr */
 639             BUS_SPACE_MAXADDR,          /* highaddr */
 640             NULL, NULL,                 /* filter, filterarg */
 641             MJUM16BYTES,                /* maxsize */
 642             1,                          /* nsegments */
 643             MJUM16BYTES,                /* maxsegsize */
 644             0,                          /* flags */
 645             NULL, NULL,                 /* lockfunc, lockfuncarg */
 646             &rq->dma_tag)))
 647                 goto done;
 648
 649         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 650             &rq->wq_ctrl);
 651         if (err)
 652                 goto err_free_dma_tag;
 653
 654         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 655
 656         if (priv->params.hw_lro_en) {
 657                 rq->wqe_sz = priv->params.lro_wqe_sz;
 658         } else {
 659                 rq->wqe_sz = MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
 660         }
 661         if (rq->wqe_sz > MJUM16BYTES) {
 662                 err = -ENOMEM;
 663                 goto err_rq_wq_destroy;
 664         } else if (rq->wqe_sz > MJUM9BYTES) {
 665                 rq->wqe_sz = MJUM16BYTES;
 666         } else if (rq->wqe_sz > MJUMPAGESIZE) {
 667                 rq->wqe_sz = MJUM9BYTES;
 668         } else if (rq->wqe_sz > MCLBYTES) {
 669                 rq->wqe_sz = MJUMPAGESIZE;
 670         } else {
 671                 rq->wqe_sz = MCLBYTES;
 672         }
 673
 674         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 675
 676         err = -tcp_lro_init_args(&rq->lro, c->ifp, TCP_LRO_ENTRIES, wq_sz);
 677         if (err)
 678                 goto err_rq_wq_destroy;
 679
 680         rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
 681         for (i = 0; i != wq_sz; i++) {
 682                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 683                 uint32_t byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 684
 685                 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
 686                 if (err != 0) {
 687                         while (i--)
 688                                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 689                         goto err_rq_mbuf_free;
 690                 }
 691                 wqe->data.lkey = c->mkey_be;
 692                 wqe->data.byte_count = cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
 693         }
 694
 695         rq->ifp = c->ifp;
 696         rq->channel = c;
 697         rq->ix = c->ix;
 698
 699         snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
 700         mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
 701             buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
 702             rq->stats.arg);
 703         return (0);
 704
 705 err_rq_mbuf_free:
 706         free(rq->mbuf, M_MLX5EN);
 707         tcp_lro_free(&rq->lro);
 708 err_rq_wq_destroy:
 709         mlx5_wq_destroy(&rq->wq_ctrl);
 710 err_free_dma_tag:
 711         bus_dma_tag_destroy(rq->dma_tag);
 712 done:
 713         return (err);
 714 }
 715
 716 static void
 717 mlx5e_destroy_rq(struct mlx5e_rq *rq)
 718 {
 719         int wq_sz;
 720         int i;
 721
 722         /* destroy all sysctl nodes */
 723         sysctl_ctx_free(&rq->stats.ctx);
 724
 725         /* free leftover LRO packets, if any */
 726         tcp_lro_free(&rq->lro);
 727
 728         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 729         for (i = 0; i != wq_sz; i++) {
 730                 if (rq->mbuf[i].mbuf != NULL) {
 731                         bus_dmamap_unload(rq->dma_tag,
 732                             rq->mbuf[i].dma_map);
 733                         m_freem(rq->mbuf[i].mbuf);
 734                 }
 735                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 736         }
 737         free(rq->mbuf, M_MLX5EN);
 738         mlx5_wq_destroy(&rq->wq_ctrl);
 739 }
 740
 741 static int
 742 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 743 {
 744         struct mlx5e_channel *c = rq->channel;
 745         struct mlx5e_priv *priv = c->priv;
 746         struct mlx5_core_dev *mdev = priv->mdev;
 747
 748         void *in;
 749         void *rqc;
 750         void *wq;
 751         int inlen;
 752         int err;
 753
 754         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 755             sizeof(u64) * rq->wq_ctrl.buf.npages;
 756         in = mlx5_vzalloc(inlen);
 757         if (in == NULL)
 758                 return (-ENOMEM);
 759
 760         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 761         wq = MLX5_ADDR_OF(rqc, rqc, wq);
 762
 763         memcpy(rqc, param->rqc, sizeof(param->rqc));
 764
 765         MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
 766         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
 767         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
 768         if (priv->counter_set_id >= 0)
 769                 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
 770         MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
 771             PAGE_SHIFT);
 772         MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
 773
 774         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 775             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
 776
 777         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 778
 779         kvfree(in);
 780
 781         return (err);
 782 }
 783
 784 static int
 785 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
 786 {
 787         struct mlx5e_channel *c = rq->channel;
 788         struct mlx5e_priv *priv = c->priv;
 789         struct mlx5_core_dev *mdev = priv->mdev;
 790
 791         void *in;
 792         void *rqc;
 793         int inlen;
 794         int err;
 795
 796         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 797         in = mlx5_vzalloc(inlen);
 798         if (in == NULL)
 799                 return (-ENOMEM);
 800
 801         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 802
 803         MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
 804         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 805         MLX5_SET(rqc, rqc, state, next_state);
 806
 807         err = mlx5_core_modify_rq(mdev, in, inlen);
 808
 809         kvfree(in);
 810
 811         return (err);
 812 }
 813
 814 static void
 815 mlx5e_disable_rq(struct mlx5e_rq *rq)
 816 {
 817         struct mlx5e_channel *c = rq->channel;
 818         struct mlx5e_priv *priv = c->priv;
 819         struct mlx5_core_dev *mdev = priv->mdev;
 820
 821         mlx5_core_destroy_rq(mdev, rq->rqn);
 822 }
 823
 824 static int
 825 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 826 {
 827         struct mlx5e_channel *c = rq->channel;
 828         struct mlx5e_priv *priv = c->priv;
 829         struct mlx5_wq_ll *wq = &rq->wq;
 830         int i;
 831
 832         for (i = 0; i < 1000; i++) {
 833                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 834                         return (0);
 835
 836                 msleep(4);
 837         }
 838         return (-ETIMEDOUT);
 839 }
 840
 841 static int
 842 mlx5e_open_rq(struct mlx5e_channel *c,
 843     struct mlx5e_rq_param *param,
 844     struct mlx5e_rq *rq)
 845 {
 846         int err;
 847
 848         err = mlx5e_create_rq(c, param, rq);
 849         if (err)
 850                 return (err);
 851
 852         err = mlx5e_enable_rq(rq, param);
 853         if (err)
 854                 goto err_destroy_rq;
 855
 856         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 857         if (err)
 858                 goto err_disable_rq;
 859
 860         c->rq.enabled = 1;
 861
 862         return (0);
 863
 864 err_disable_rq:
 865         mlx5e_disable_rq(rq);
 866 err_destroy_rq:
 867         mlx5e_destroy_rq(rq);
 868
 869         return (err);
 870 }
 871
 872 static void
 873 mlx5e_close_rq(struct mlx5e_rq *rq)
 874 {
 875         mtx_lock(&rq->mtx);
 876         rq->enabled = 0;
 877         callout_stop(&rq->watchdog);
 878         mtx_unlock(&rq->mtx);
 879
 880         callout_drain(&rq->watchdog);
 881
 882         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
 883 }
 884
 885 static void
 886 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
 887 {
 888         /* wait till RQ is empty */
 889         while (!mlx5_wq_ll_is_empty(&rq->wq)) {
 890                 msleep(4);
 891                 rq->cq.mcq.comp(&rq->cq.mcq);
 892         }
 893
 894         mlx5e_disable_rq(rq);
 895         mlx5e_destroy_rq(rq);
 896 }
 897
 898 void
 899 mlx5e_free_sq_db(struct mlx5e_sq *sq)
 900 {
 901         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 902         int x;
 903
 904         for (x = 0; x != wq_sz; x++)
 905                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
 906         free(sq->mbuf, M_MLX5EN);
 907 }
 908
 909 int
 910 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
 911 {
 912         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
 913         int err;
 914         int x;
 915
 916         sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
 917
 918         /* Create DMA descriptor MAPs */
 919         for (x = 0; x != wq_sz; x++) {
 920                 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
 921                 if (err != 0) {
 922                         while (x--)
 923                                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
 924                         free(sq->mbuf, M_MLX5EN);
 925                         return (err);
 926                 }
 927         }
 928         return (0);
 929 }
 930
 931 static const char *mlx5e_sq_stats_desc[] = {
 932         MLX5E_SQ_STATS(MLX5E_STATS_DESC)
 933 };
 934
 935 static int
 936 mlx5e_create_sq(struct mlx5e_channel *c,
 937     int tc,
 938     struct mlx5e_sq_param *param,
 939     struct mlx5e_sq *sq)
 940 {
 941         struct mlx5e_priv *priv = c->priv;
 942         struct mlx5_core_dev *mdev = priv->mdev;
 943         char buffer[16];
 944
 945         void *sqc = param->sqc;
 946         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
 947 #ifdef RSS
 948         cpuset_t cpu_mask;
 949         int cpu_id;
 950 #endif
 951         int err;
 952
 953         /* Create DMA descriptor TAG */
 954         if ((err = -bus_dma_tag_create(
 955             bus_get_dma_tag(mdev->pdev->dev.bsddev),
 956             1,                          /* any alignment */
 957             0,                          /* no boundary */
 958             BUS_SPACE_MAXADDR,          /* lowaddr */
 959             BUS_SPACE_MAXADDR,          /* highaddr */
 960             NULL, NULL,                 /* filter, filterarg */
 961             MLX5E_MAX_TX_PAYLOAD_SIZE,  /* maxsize */
 962             MLX5E_MAX_TX_MBUF_FRAGS,    /* nsegments */
 963             MLX5E_MAX_TX_MBUF_SIZE,     /* maxsegsize */
 964             0,                          /* flags */
 965             NULL, NULL,                 /* lockfunc, lockfuncarg */
 966             &sq->dma_tag)))
 967                 goto done;
 968
 969         err = mlx5_alloc_map_uar(mdev, &sq->uar);
 970         if (err)
 971                 goto err_free_dma_tag;
 972
 973         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
 974             &sq->wq_ctrl);
 975         if (err)
 976                 goto err_unmap_free_uar;
 977
 978         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
 979         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
 980
 981         err = mlx5e_alloc_sq_db(sq);
 982         if (err)
 983                 goto err_sq_wq_destroy;
 984
 985         sq->mkey_be = c->mkey_be;
 986         sq->ifp = priv->ifp;
 987         sq->priv = priv;
 988         sq->tc = tc;
 989
 990         sq->br = buf_ring_alloc(MLX5E_SQ_TX_QUEUE_SIZE, M_MLX5EN,
 991             M_WAITOK, &sq->lock);
 992         if (sq->br == NULL) {
 993                 if_printf(c->ifp, "%s: Failed allocating sq drbr buffer\n",
 994                     __func__);
 995                 err = -ENOMEM;
 996                 goto err_free_sq_db;
 997         }
 998
 999         sq->sq_tq = taskqueue_create_fast("mlx5e_que", M_WAITOK,
1000             taskqueue_thread_enqueue, &sq->sq_tq);
1001         if (sq->sq_tq == NULL) {
1002                 if_printf(c->ifp, "%s: Failed allocating taskqueue\n",
1003                     __func__);
1004                 err = -ENOMEM;
1005                 goto err_free_drbr;
1006         }
1007
1008         TASK_INIT(&sq->sq_task, 0, mlx5e_tx_que, sq);
1009 #ifdef RSS
1010         cpu_id = rss_getcpu(c->ix % rss_getnumbuckets());
1011         CPU_SETOF(cpu_id, &cpu_mask);
1012         taskqueue_start_threads_cpuset(&sq->sq_tq, 1, PI_NET, &cpu_mask,
1013             "%s TX SQ%d.%d CPU%d", c->ifp->if_xname, c->ix, tc, cpu_id);
1014 #else
1015         taskqueue_start_threads(&sq->sq_tq, 1, PI_NET,
1016             "%s TX SQ%d.%d", c->ifp->if_xname, c->ix, tc);
1017 #endif
1018         snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1019         mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1020             buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1021             sq->stats.arg);
1022
1023         return (0);
1024
1025 err_free_drbr:
1026         buf_ring_free(sq->br, M_MLX5EN);
1027 err_free_sq_db:
1028         mlx5e_free_sq_db(sq);
1029 err_sq_wq_destroy:
1030         mlx5_wq_destroy(&sq->wq_ctrl);
1031
1032 err_unmap_free_uar:
1033         mlx5_unmap_free_uar(mdev, &sq->uar);
1034
1035 err_free_dma_tag:
1036         bus_dma_tag_destroy(sq->dma_tag);
1037 done:
1038         return (err);
1039 }
1040
1041 static void
1042 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1043 {
1044         /* destroy all sysctl nodes */
1045         sysctl_ctx_free(&sq->stats.ctx);
1046
1047         mlx5e_free_sq_db(sq);
1048         mlx5_wq_destroy(&sq->wq_ctrl);
1049         mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1050         taskqueue_drain(sq->sq_tq, &sq->sq_task);
1051         taskqueue_free(sq->sq_tq);
1052         buf_ring_free(sq->br, M_MLX5EN);
1053 }
1054
1055 int
1056 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1057     int tis_num)
1058 {
1059         void *in;
1060         void *sqc;
1061         void *wq;
1062         int inlen;
1063         int err;
1064
1065         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1066             sizeof(u64) * sq->wq_ctrl.buf.npages;
1067         in = mlx5_vzalloc(inlen);
1068         if (in == NULL)
1069                 return (-ENOMEM);
1070
1071         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1072         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1073
1074         memcpy(sqc, param->sqc, sizeof(param->sqc));
1075
1076         MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1077         MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1078         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1079         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1080         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1081
1082         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1083         MLX5_SET(wq, wq, uar_page, sq->uar.index);
1084         MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1085             PAGE_SHIFT);
1086         MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1087
1088         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1089             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1090
1091         err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1092
1093         kvfree(in);
1094
1095         return (err);
1096 }
1097
1098 int
1099 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1100 {
1101         void *in;
1102         void *sqc;
1103         int inlen;
1104         int err;
1105
1106         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1107         in = mlx5_vzalloc(inlen);
1108         if (in == NULL)
1109                 return (-ENOMEM);
1110
1111         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1112
1113         MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1114         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1115         MLX5_SET(sqc, sqc, state, next_state);
1116
1117         err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1118
1119         kvfree(in);
1120
1121         return (err);
1122 }
1123
1124 void
1125 mlx5e_disable_sq(struct mlx5e_sq *sq)
1126 {
1127
1128         mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1129 }
1130
1131 static int
1132 mlx5e_open_sq(struct mlx5e_channel *c,
1133     int tc,
1134     struct mlx5e_sq_param *param,
1135     struct mlx5e_sq *sq)
1136 {
1137         int err;
1138
1139         err = mlx5e_create_sq(c, tc, param, sq);
1140         if (err)
1141                 return (err);
1142
1143         err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1144         if (err)
1145                 goto err_destroy_sq;
1146
1147         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1148         if (err)
1149                 goto err_disable_sq;
1150
1151         atomic_store_rel_int(&sq->queue_state, MLX5E_SQ_READY);
1152
1153         return (0);
1154
1155 err_disable_sq:
1156         mlx5e_disable_sq(sq);
1157 err_destroy_sq:
1158         mlx5e_destroy_sq(sq);
1159
1160         return (err);
1161 }
1162
1163 static void
1164 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1165 {
1166         /* fill up remainder with NOPs */
1167         while (sq->cev_counter != 0) {
1168                 while (!mlx5e_sq_has_room_for(sq, 1)) {
1169                         if (can_sleep != 0) {
1170                                 mtx_unlock(&sq->lock);
1171                                 msleep(4);
1172                                 mtx_lock(&sq->lock);
1173                         } else {
1174                                 goto done;
1175                         }
1176                 }
1177                 /* send a single NOP */
1178                 mlx5e_send_nop(sq, 1);
1179                 wmb();
1180         }
1181 done:
1182         /* Check if we need to write the doorbell */
1183         if (likely(sq->doorbell.d64 != 0)) {
1184                 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1185                 sq->doorbell.d64 = 0;
1186         }
1187         return;
1188 }
1189
1190 void
1191 mlx5e_sq_cev_timeout(void *arg)
1192 {
1193         struct mlx5e_sq *sq = arg;
1194
1195         mtx_assert(&sq->lock, MA_OWNED);
1196
1197         /* check next state */
1198         switch (sq->cev_next_state) {
1199         case MLX5E_CEV_STATE_SEND_NOPS:
1200                 /* fill TX ring with NOPs, if any */
1201                 mlx5e_sq_send_nops_locked(sq, 0);
1202
1203                 /* check if completed */
1204                 if (sq->cev_counter == 0) {
1205                         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1206                         return;
1207                 }
1208                 break;
1209         default:
1210                 /* send NOPs on next timeout */
1211                 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1212                 break;
1213         }
1214
1215         /* restart timer */
1216         callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1217 }
1218
1219 void
1220 mlx5e_drain_sq(struct mlx5e_sq *sq)
1221 {
1222
1223         mtx_lock(&sq->lock);
1224         /* teardown event factor timer, if any */
1225         sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1226         callout_stop(&sq->cev_callout);
1227
1228         /* send dummy NOPs in order to flush the transmit ring */
1229         mlx5e_sq_send_nops_locked(sq, 1);
1230         mtx_unlock(&sq->lock);
1231
1232         /* make sure it is safe to free the callout */
1233         callout_drain(&sq->cev_callout);
1234
1235         /* error out remaining requests */
1236         mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1237
1238         /* wait till SQ is empty */
1239         mtx_lock(&sq->lock);
1240         while (sq->cc != sq->pc) {
1241                 mtx_unlock(&sq->lock);
1242                 msleep(4);
1243                 sq->cq.mcq.comp(&sq->cq.mcq);
1244                 mtx_lock(&sq->lock);
1245         }
1246         mtx_unlock(&sq->lock);
1247 }
1248
1249 static void
1250 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1251 {
1252
1253         mlx5e_drain_sq(sq);
1254         mlx5e_disable_sq(sq);
1255         mlx5e_destroy_sq(sq);
1256 }
1257
1258 static int
1259 mlx5e_create_cq(struct mlx5e_priv *priv,
1260     struct mlx5e_cq_param *param,
1261     struct mlx5e_cq *cq,
1262     mlx5e_cq_comp_t *comp,
1263     int eq_ix)
1264 {
1265         struct mlx5_core_dev *mdev = priv->mdev;
1266         struct mlx5_core_cq *mcq = &cq->mcq;
1267         int eqn_not_used;
1268         int irqn;
1269         int err;
1270         u32 i;
1271
1272         param->wq.buf_numa_node = 0;
1273         param->wq.db_numa_node = 0;
1274
1275         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1276             &cq->wq_ctrl);
1277         if (err)
1278                 return (err);
1279
1280         mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1281
1282         mcq->cqe_sz = 64;
1283         mcq->set_ci_db = cq->wq_ctrl.db.db;
1284         mcq->arm_db = cq->wq_ctrl.db.db + 1;
1285         *mcq->set_ci_db = 0;
1286         *mcq->arm_db = 0;
1287         mcq->vector = eq_ix;
1288         mcq->comp = comp;
1289         mcq->event = mlx5e_cq_error_event;
1290         mcq->irqn = irqn;
1291         mcq->uar = &priv->cq_uar;
1292
1293         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1294                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1295
1296                 cqe->op_own = 0xf1;
1297         }
1298
1299         cq->priv = priv;
1300
1301         return (0);
1302 }
1303
1304 static void
1305 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1306 {
1307         mlx5_wq_destroy(&cq->wq_ctrl);
1308 }
1309
1310 static int
1311 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1312 {
1313         struct mlx5_core_cq *mcq = &cq->mcq;
1314         void *in;
1315         void *cqc;
1316         int inlen;
1317         int irqn_not_used;
1318         int eqn;
1319         int err;
1320
1321         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1322             sizeof(u64) * cq->wq_ctrl.buf.npages;
1323         in = mlx5_vzalloc(inlen);
1324         if (in == NULL)
1325                 return (-ENOMEM);
1326
1327         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1328
1329         memcpy(cqc, param->cqc, sizeof(param->cqc));
1330
1331         mlx5_fill_page_array(&cq->wq_ctrl.buf,
1332             (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1333
1334         mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
1335
1336         MLX5_SET(cqc, cqc, c_eqn, eqn);
1337         MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1338         MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1339             PAGE_SHIFT);
1340         MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1341
1342         err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
1343
1344         kvfree(in);
1345
1346         if (err)
1347                 return (err);
1348
1349         mlx5e_cq_arm(cq);
1350
1351         return (0);
1352 }
1353
1354 static void
1355 mlx5e_disable_cq(struct mlx5e_cq *cq)
1356 {
1357
1358         mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
1359 }
1360
1361 int
1362 mlx5e_open_cq(struct mlx5e_priv *priv,
1363     struct mlx5e_cq_param *param,
1364     struct mlx5e_cq *cq,
1365     mlx5e_cq_comp_t *comp,
1366     int eq_ix)
1367 {
1368         int err;
1369
1370         err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
1371         if (err)
1372                 return (err);
1373
1374         err = mlx5e_enable_cq(cq, param, eq_ix);
1375         if (err)
1376                 goto err_destroy_cq;
1377
1378         return (0);
1379
1380 err_destroy_cq:
1381         mlx5e_destroy_cq(cq);
1382
1383         return (err);
1384 }
1385
1386 void
1387 mlx5e_close_cq(struct mlx5e_cq *cq)
1388 {
1389         mlx5e_disable_cq(cq);
1390         mlx5e_destroy_cq(cq);
1391 }
1392
1393 static int
1394 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1395     struct mlx5e_channel_param *cparam)
1396 {
1397         int err;
1398         int tc;
1399
1400         for (tc = 0; tc < c->num_tc; tc++) {
1401                 /* open completion queue */
1402                 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
1403                     &mlx5e_tx_cq_comp, c->ix);
1404                 if (err)
1405                         goto err_close_tx_cqs;
1406         }
1407         return (0);
1408
1409 err_close_tx_cqs:
1410         for (tc--; tc >= 0; tc--)
1411                 mlx5e_close_cq(&c->sq[tc].cq);
1412
1413         return (err);
1414 }
1415
1416 static void
1417 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1418 {
1419         int tc;
1420
1421         for (tc = 0; tc < c->num_tc; tc++)
1422                 mlx5e_close_cq(&c->sq[tc].cq);
1423 }
1424
1425 static int
1426 mlx5e_open_sqs(struct mlx5e_channel *c,
1427     struct mlx5e_channel_param *cparam)
1428 {
1429         int err;
1430         int tc;
1431
1432         for (tc = 0; tc < c->num_tc; tc++) {
1433                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1434                 if (err)
1435                         goto err_close_sqs;
1436         }
1437
1438         return (0);
1439
1440 err_close_sqs:
1441         for (tc--; tc >= 0; tc--)
1442                 mlx5e_close_sq_wait(&c->sq[tc]);
1443
1444         return (err);
1445 }
1446
1447 static void
1448 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
1449 {
1450         int tc;
1451
1452         for (tc = 0; tc < c->num_tc; tc++)
1453                 mlx5e_close_sq_wait(&c->sq[tc]);
1454 }
1455
1456 static void
1457 mlx5e_chan_mtx_init(struct mlx5e_channel *c)
1458 {
1459         int tc;
1460
1461         mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
1462
1463         callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
1464
1465         for (tc = 0; tc < c->num_tc; tc++) {
1466                 struct mlx5e_sq *sq = c->sq + tc;
1467
1468                 mtx_init(&sq->lock, "mlx5tx", MTX_NETWORK_LOCK, MTX_DEF);
1469                 mtx_init(&sq->comp_lock, "mlx5comp", MTX_NETWORK_LOCK,
1470                     MTX_DEF);
1471
1472                 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
1473
1474                 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1475
1476                 /* ensure the TX completion event factor is not zero */
1477                 if (sq->cev_factor == 0)
1478                         sq->cev_factor = 1;
1479         }
1480 }
1481
1482 static void
1483 mlx5e_chan_mtx_destroy(struct mlx5e_channel *c)
1484 {
1485         int tc;
1486
1487         mtx_destroy(&c->rq.mtx);
1488
1489         for (tc = 0; tc < c->num_tc; tc++) {
1490                 mtx_destroy(&c->sq[tc].lock);
1491                 mtx_destroy(&c->sq[tc].comp_lock);
1492         }
1493 }
1494
1495 static int
1496 mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1497     struct mlx5e_channel_param *cparam,
1498     struct mlx5e_channel *volatile *cp)
1499 {
1500         struct mlx5e_channel *c;
1501         int err;
1502
1503         c = malloc(sizeof(*c), M_MLX5EN, M_WAITOK | M_ZERO);
1504         c->priv = priv;
1505         c->ix = ix;
1506         c->cpu = 0;
1507         c->ifp = priv->ifp;
1508         c->mkey_be = cpu_to_be32(priv->mr.key);
1509         c->num_tc = priv->num_tc;
1510
1511         /* init mutexes */
1512         mlx5e_chan_mtx_init(c);
1513
1514         /* open transmit completion queue */
1515         err = mlx5e_open_tx_cqs(c, cparam);
1516         if (err)
1517                 goto err_free;
1518
1519         /* open receive completion queue */
1520         err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
1521             &mlx5e_rx_cq_comp, c->ix);
1522         if (err)
1523                 goto err_close_tx_cqs;
1524
1525         err = mlx5e_open_sqs(c, cparam);
1526         if (err)
1527                 goto err_close_rx_cq;
1528
1529         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1530         if (err)
1531                 goto err_close_sqs;
1532
1533         /* store channel pointer */
1534         *cp = c;
1535
1536         /* poll receive queue initially */
1537         c->rq.cq.mcq.comp(&c->rq.cq.mcq);
1538
1539         return (0);
1540
1541 err_close_sqs:
1542         mlx5e_close_sqs_wait(c);
1543
1544 err_close_rx_cq:
1545         mlx5e_close_cq(&c->rq.cq);
1546
1547 err_close_tx_cqs:
1548         mlx5e_close_tx_cqs(c);
1549
1550 err_free:
1551         /* destroy mutexes */
1552         mlx5e_chan_mtx_destroy(c);
1553         free(c, M_MLX5EN);
1554         return (err);
1555 }
1556
1557 static void
1558 mlx5e_close_channel(struct mlx5e_channel *volatile *pp)
1559 {
1560         struct mlx5e_channel *c = *pp;
1561
1562         /* check if channel is already closed */
1563         if (c == NULL)
1564                 return;
1565         mlx5e_close_rq(&c->rq);
1566 }
1567
1568 static void
1569 mlx5e_close_channel_wait(struct mlx5e_channel *volatile *pp)
1570 {
1571         struct mlx5e_channel *c = *pp;
1572
1573         /* check if channel is already closed */
1574         if (c == NULL)
1575                 return;
1576         /* ensure channel pointer is no longer used */
1577         *pp = NULL;
1578
1579         mlx5e_close_rq_wait(&c->rq);
1580         mlx5e_close_sqs_wait(c);
1581         mlx5e_close_cq(&c->rq.cq);
1582         mlx5e_close_tx_cqs(c);
1583         /* destroy mutexes */
1584         mlx5e_chan_mtx_destroy(c);
1585         free(c, M_MLX5EN);
1586 }
1587
1588 static void
1589 mlx5e_build_rq_param(struct mlx5e_priv *priv,
1590     struct mlx5e_rq_param *param)
1591 {
1592         void *rqc = param->rqc;
1593         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1594
1595         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1596         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1597         MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1598         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1599         MLX5_SET(wq, wq, pd, priv->pdn);
1600
1601         param->wq.buf_numa_node = 0;
1602         param->wq.db_numa_node = 0;
1603         param->wq.linear = 1;
1604 }
1605
1606 static void
1607 mlx5e_build_sq_param(struct mlx5e_priv *priv,
1608     struct mlx5e_sq_param *param)
1609 {
1610         void *sqc = param->sqc;
1611         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1612
1613         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1614         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1615         MLX5_SET(wq, wq, pd, priv->pdn);
1616
1617         param->wq.buf_numa_node = 0;
1618         param->wq.db_numa_node = 0;
1619         param->wq.linear = 1;
1620 }
1621
1622 static void
1623 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1624     struct mlx5e_cq_param *param)
1625 {
1626         void *cqc = param->cqc;
1627
1628         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1629 }
1630
1631 static void
1632 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1633     struct mlx5e_cq_param *param)
1634 {
1635         void *cqc = param->cqc;
1636
1637
1638         /*
1639          * TODO The sysctl to control on/off is a bool value for now, which means
1640          * we only support CSUM, once HASH is implemnted we'll need to address that.
1641          */
1642         if (priv->params.cqe_zipping_en) {
1643                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1644                 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
1645         }
1646
1647         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1648         MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1649         MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1650
1651         switch (priv->params.rx_cq_moderation_mode) {
1652         case 0:
1653                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1654                 break;
1655         default:
1656                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1657                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1658                 else
1659                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1660                 break;
1661         }
1662
1663         mlx5e_build_common_cq_param(priv, param);
1664 }
1665
1666 static void
1667 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1668     struct mlx5e_cq_param *param)
1669 {
1670         void *cqc = param->cqc;
1671
1672         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1673         MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
1674         MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
1675
1676         switch (priv->params.tx_cq_moderation_mode) {
1677         case 0:
1678                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1679                 break;
1680         default:
1681                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1682                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1683                 else
1684                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1685                 break;
1686         }
1687
1688         mlx5e_build_common_cq_param(priv, param);
1689 }
1690
1691 static void
1692 mlx5e_build_channel_param(struct mlx5e_priv *priv,
1693     struct mlx5e_channel_param *cparam)
1694 {
1695         memset(cparam, 0, sizeof(*cparam));
1696
1697         mlx5e_build_rq_param(priv, &cparam->rq);
1698         mlx5e_build_sq_param(priv, &cparam->sq);
1699         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1700         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1701 }
1702
1703 static int
1704 mlx5e_open_channels(struct mlx5e_priv *priv)
1705 {
1706         struct mlx5e_channel_param cparam;
1707         void *ptr;
1708         int err;
1709         int i;
1710         int j;
1711
1712         priv->channel = malloc(priv->params.num_channels *
1713             sizeof(struct mlx5e_channel *), M_MLX5EN, M_WAITOK | M_ZERO);
1714
1715         mlx5e_build_channel_param(priv, &cparam);
1716         for (i = 0; i < priv->params.num_channels; i++) {
1717                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1718                 if (err)
1719                         goto err_close_channels;
1720         }
1721
1722         for (j = 0; j < priv->params.num_channels; j++) {
1723                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1724                 if (err)
1725                         goto err_close_channels;
1726         }
1727
1728         return (0);
1729
1730 err_close_channels:
1731         for (i--; i >= 0; i--) {
1732                 mlx5e_close_channel(&priv->channel[i]);
1733                 mlx5e_close_channel_wait(&priv->channel[i]);
1734         }
1735
1736         /* remove "volatile" attribute from "channel" pointer */
1737         ptr = __DECONST(void *, priv->channel);
1738         priv->channel = NULL;
1739
1740         free(ptr, M_MLX5EN);
1741
1742         return (err);
1743 }
1744
1745 static void
1746 mlx5e_close_channels(struct mlx5e_priv *priv)
1747 {
1748         void *ptr;
1749         int i;
1750
1751         if (priv->channel == NULL)
1752                 return;
1753
1754         for (i = 0; i < priv->params.num_channels; i++)
1755                 mlx5e_close_channel(&priv->channel[i]);
1756         for (i = 0; i < priv->params.num_channels; i++)
1757                 mlx5e_close_channel_wait(&priv->channel[i]);
1758
1759         /* remove "volatile" attribute from "channel" pointer */
1760         ptr = __DECONST(void *, priv->channel);
1761         priv->channel = NULL;
1762
1763         free(ptr, M_MLX5EN);
1764 }
1765
1766 static int
1767 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
1768 {
1769         return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
1770             priv->params.tx_cq_moderation_usec,
1771             priv->params.tx_cq_moderation_pkts));
1772 }
1773
1774 static int
1775 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
1776 {
1777         return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
1778             priv->params.rx_cq_moderation_usec,
1779             priv->params.rx_cq_moderation_pkts));
1780 }
1781
1782 static int
1783 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1784 {
1785         int err;
1786         int i;
1787
1788         if (c == NULL)
1789                 return (EINVAL);
1790
1791         err = mlx5e_refresh_rq_params(priv, &c->rq);
1792         if (err)
1793                 goto done;
1794
1795         for (i = 0; i != c->num_tc; i++) {
1796                 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
1797                 if (err)
1798                         goto done;
1799         }
1800 done:
1801         return (err);
1802 }
1803
1804 int
1805 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
1806 {
1807         int i;
1808
1809         if (priv->channel == NULL)
1810                 return (EINVAL);
1811
1812         for (i = 0; i < priv->params.num_channels; i++) {
1813                 int err;
1814
1815                 err = mlx5e_refresh_channel_params_sub(priv, priv->channel[i]);
1816                 if (err)
1817                         return (err);
1818         }
1819         return (0);
1820 }
1821
1822 static int
1823 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
1824 {
1825         struct mlx5_core_dev *mdev = priv->mdev;
1826         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1827         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1828
1829         memset(in, 0, sizeof(in));
1830
1831         MLX5_SET(tisc, tisc, prio, tc);
1832         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1833
1834         return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
1835 }
1836
1837 static void
1838 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
1839 {
1840         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1841 }
1842
1843 static int
1844 mlx5e_open_tises(struct mlx5e_priv *priv)
1845 {
1846         int num_tc = priv->num_tc;
1847         int err;
1848         int tc;
1849
1850         for (tc = 0; tc < num_tc; tc++) {
1851                 err = mlx5e_open_tis(priv, tc);
1852                 if (err)
1853                         goto err_close_tises;
1854         }
1855
1856         return (0);
1857
1858 err_close_tises:
1859         for (tc--; tc >= 0; tc--)
1860                 mlx5e_close_tis(priv, tc);
1861
1862         return (err);
1863 }
1864
1865 static void
1866 mlx5e_close_tises(struct mlx5e_priv *priv)
1867 {
1868         int num_tc = priv->num_tc;
1869         int tc;
1870
1871         for (tc = 0; tc < num_tc; tc++)
1872                 mlx5e_close_tis(priv, tc);
1873 }
1874
1875 static int
1876 mlx5e_open_rqt(struct mlx5e_priv *priv)
1877 {
1878         struct mlx5_core_dev *mdev = priv->mdev;
1879         u32 *in;
1880         u32 out[MLX5_ST_SZ_DW(create_rqt_out)];
1881         void *rqtc;
1882         int inlen;
1883         int err;
1884         int sz;
1885         int i;
1886
1887         sz = 1 << priv->params.rx_hash_log_tbl_sz;
1888
1889         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1890         in = mlx5_vzalloc(inlen);
1891         if (in == NULL)
1892                 return (-ENOMEM);
1893         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1894
1895         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1896         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1897
1898         for (i = 0; i < sz; i++) {
1899                 int ix;
1900 #ifdef RSS
1901                 ix = rss_get_indirection_to_bucket(i);
1902 #else
1903                 ix = i;
1904 #endif
1905                 /* ensure we don't overflow */
1906                 ix %= priv->params.num_channels;
1907                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix]->rq.rqn);
1908         }
1909
1910         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1911
1912         memset(out, 0, sizeof(out));
1913         err = mlx5_cmd_exec_check_status(mdev, in, inlen, out, sizeof(out));
1914         if (!err)
1915                 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
1916
1917         kvfree(in);
1918
1919         return (err);
1920 }
1921
1922 static void
1923 mlx5e_close_rqt(struct mlx5e_priv *priv)
1924 {
1925         u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)];
1926         u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)];
1927
1928         memset(in, 0, sizeof(in));
1929
1930         MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
1931         MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
1932
1933         mlx5_cmd_exec_check_status(priv->mdev, in, sizeof(in), out,
1934             sizeof(out));
1935 }
1936
1937 static void
1938 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
1939 {
1940         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1941         __be32 *hkey;
1942
1943         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1944
1945 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1946
1947 #define MLX5_HASH_IP     (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1948                           MLX5_HASH_FIELD_SEL_DST_IP)
1949
1950 #define MLX5_HASH_ALL    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1951                           MLX5_HASH_FIELD_SEL_DST_IP   |\
1952                           MLX5_HASH_FIELD_SEL_L4_SPORT |\
1953                           MLX5_HASH_FIELD_SEL_L4_DPORT)
1954
1955 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
1956                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
1957                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1958
1959         if (priv->params.hw_lro_en) {
1960                 MLX5_SET(tirc, tirc, lro_enable_mask,
1961                     MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1962                     MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1963                 MLX5_SET(tirc, tirc, lro_max_msg_sz,
1964                     (priv->params.lro_wqe_sz -
1965                     ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1966                 /* TODO: add the option to choose timer value dynamically */
1967                 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1968                     MLX5_CAP_ETH(priv->mdev,
1969                     lro_timer_supported_periods[2]));
1970         }
1971
1972         /* setup parameters for hashing TIR type, if any */
1973         switch (tt) {
1974         case MLX5E_TT_ANY:
1975                 MLX5_SET(tirc, tirc, disp_type,
1976                     MLX5_TIRC_DISP_TYPE_DIRECT);
1977                 MLX5_SET(tirc, tirc, inline_rqn,
1978                     priv->channel[0]->rq.rqn);
1979                 break;
1980         default:
1981                 MLX5_SET(tirc, tirc, disp_type,
1982                     MLX5_TIRC_DISP_TYPE_INDIRECT);
1983                 MLX5_SET(tirc, tirc, indirect_table,
1984                     priv->rqtn);
1985                 MLX5_SET(tirc, tirc, rx_hash_fn,
1986                     MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
1987                 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1988 #ifdef RSS
1989                 /*
1990                  * The FreeBSD RSS implementation does currently not
1991                  * support symmetric Toeplitz hashes:
1992                  */
1993                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
1994                 rss_getkey((uint8_t *)hkey);
1995 #else
1996                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1997                 hkey[0] = cpu_to_be32(0xD181C62C);
1998                 hkey[1] = cpu_to_be32(0xF7F4DB5B);
1999                 hkey[2] = cpu_to_be32(0x1983A2FC);
2000                 hkey[3] = cpu_to_be32(0x943E1ADB);
2001                 hkey[4] = cpu_to_be32(0xD9389E6B);
2002                 hkey[5] = cpu_to_be32(0xD1039C2C);
2003                 hkey[6] = cpu_to_be32(0xA74499AD);
2004                 hkey[7] = cpu_to_be32(0x593D56D9);
2005                 hkey[8] = cpu_to_be32(0xF3253C06);
2006                 hkey[9] = cpu_to_be32(0x2ADC1FFC);
2007 #endif
2008                 break;
2009         }
2010
2011         switch (tt) {
2012         case MLX5E_TT_IPV4_TCP:
2013                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2014                     MLX5_L3_PROT_TYPE_IPV4);
2015                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2016                     MLX5_L4_PROT_TYPE_TCP);
2017 #ifdef RSS
2018                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2019                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2020                             MLX5_HASH_IP);
2021                 } else
2022 #endif
2023                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2024                     MLX5_HASH_ALL);
2025                 break;
2026
2027         case MLX5E_TT_IPV6_TCP:
2028                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2029                     MLX5_L3_PROT_TYPE_IPV6);
2030                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2031                     MLX5_L4_PROT_TYPE_TCP);
2032 #ifdef RSS
2033                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2034                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2035                             MLX5_HASH_IP);
2036                 } else
2037 #endif
2038                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2039                     MLX5_HASH_ALL);
2040                 break;
2041
2042         case MLX5E_TT_IPV4_UDP:
2043                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2044                     MLX5_L3_PROT_TYPE_IPV4);
2045                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2046                     MLX5_L4_PROT_TYPE_UDP);
2047 #ifdef RSS
2048                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2049                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2050                             MLX5_HASH_IP);
2051                 } else
2052 #endif
2053                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2054                     MLX5_HASH_ALL);
2055                 break;
2056
2057         case MLX5E_TT_IPV6_UDP:
2058                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2059                     MLX5_L3_PROT_TYPE_IPV6);
2060                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2061                     MLX5_L4_PROT_TYPE_UDP);
2062 #ifdef RSS
2063                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2064                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2065                             MLX5_HASH_IP);
2066                 } else
2067 #endif
2068                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2069                     MLX5_HASH_ALL);
2070                 break;
2071
2072         case MLX5E_TT_IPV4_IPSEC_AH:
2073                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2074                     MLX5_L3_PROT_TYPE_IPV4);
2075                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2076                     MLX5_HASH_IP_IPSEC_SPI);
2077                 break;
2078
2079         case MLX5E_TT_IPV6_IPSEC_AH:
2080                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2081                     MLX5_L3_PROT_TYPE_IPV6);
2082                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2083                     MLX5_HASH_IP_IPSEC_SPI);
2084                 break;
2085
2086         case MLX5E_TT_IPV4_IPSEC_ESP:
2087                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2088                     MLX5_L3_PROT_TYPE_IPV4);
2089                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2090                     MLX5_HASH_IP_IPSEC_SPI);
2091                 break;
2092
2093         case MLX5E_TT_IPV6_IPSEC_ESP:
2094                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2095                     MLX5_L3_PROT_TYPE_IPV6);
2096                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2097                     MLX5_HASH_IP_IPSEC_SPI);
2098                 break;
2099
2100         case MLX5E_TT_IPV4:
2101                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2102                     MLX5_L3_PROT_TYPE_IPV4);
2103                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2104                     MLX5_HASH_IP);
2105                 break;
2106
2107         case MLX5E_TT_IPV6:
2108                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2109                     MLX5_L3_PROT_TYPE_IPV6);
2110                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2111                     MLX5_HASH_IP);
2112                 break;
2113
2114         default:
2115                 break;
2116         }
2117 }
2118
2119 static int
2120 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2121 {
2122         struct mlx5_core_dev *mdev = priv->mdev;
2123         u32 *in;
2124         void *tirc;
2125         int inlen;
2126         int err;
2127
2128         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2129         in = mlx5_vzalloc(inlen);
2130         if (in == NULL)
2131                 return (-ENOMEM);
2132         tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2133
2134         mlx5e_build_tir_ctx(priv, tirc, tt);
2135
2136         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2137
2138         kvfree(in);
2139
2140         return (err);
2141 }
2142
2143 static void
2144 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2145 {
2146         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2147 }
2148
2149 static int
2150 mlx5e_open_tirs(struct mlx5e_priv *priv)
2151 {
2152         int err;
2153         int i;
2154
2155         for (i = 0; i < MLX5E_NUM_TT; i++) {
2156                 err = mlx5e_open_tir(priv, i);
2157                 if (err)
2158                         goto err_close_tirs;
2159         }
2160
2161         return (0);
2162
2163 err_close_tirs:
2164         for (i--; i >= 0; i--)
2165                 mlx5e_close_tir(priv, i);
2166
2167         return (err);
2168 }
2169
2170 static void
2171 mlx5e_close_tirs(struct mlx5e_priv *priv)
2172 {
2173         int i;
2174
2175         for (i = 0; i < MLX5E_NUM_TT; i++)
2176                 mlx5e_close_tir(priv, i);
2177 }
2178
2179 /*
2180  * SW MTU does not include headers,
2181  * HW MTU includes all headers and checksums.
2182  */
2183 static int
2184 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2185 {
2186         struct mlx5e_priv *priv = ifp->if_softc;
2187         struct mlx5_core_dev *mdev = priv->mdev;
2188         int hw_mtu;
2189         int err;
2190
2191         err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(sw_mtu));
2192         if (err) {
2193                 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n",
2194                     __func__, sw_mtu, err);
2195                 return (err);
2196         }
2197         err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2198         if (err) {
2199                 if_printf(ifp, "Query port MTU, after setting new "
2200                     "MTU value, failed\n");
2201         } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
2202                 err = -E2BIG,
2203                 if_printf(ifp, "Port MTU %d is smaller than "
2204                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2205         } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
2206                 err = -EINVAL;
2207                 if_printf(ifp, "Port MTU %d is bigger than "
2208                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2209         }
2210         ifp->if_mtu = sw_mtu;
2211         return (err);
2212 }
2213
2214 int
2215 mlx5e_open_locked(struct ifnet *ifp)
2216 {
2217         struct mlx5e_priv *priv = ifp->if_softc;
2218         int err;
2219         u16 set_id;
2220
2221         /* check if already opened */
2222         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2223                 return (0);
2224
2225 #ifdef RSS
2226         if (rss_getnumbuckets() > priv->params.num_channels) {
2227                 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than "
2228                     "channels(%u) available\n", rss_getnumbuckets(),
2229                     priv->params.num_channels);
2230         }
2231 #endif
2232         err = mlx5e_open_tises(priv);
2233         if (err) {
2234                 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n",
2235                     __func__, err);
2236                 return (err);
2237         }
2238         err = mlx5_vport_alloc_q_counter(priv->mdev,
2239             MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
2240         if (err) {
2241                 if_printf(priv->ifp,
2242                     "%s: mlx5_vport_alloc_q_counter failed: %d\n",
2243                     __func__, err);
2244                 goto err_close_tises;
2245         }
2246         /* store counter set ID */
2247         priv->counter_set_id = set_id;
2248
2249         err = mlx5e_open_channels(priv);
2250         if (err) {
2251                 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n",
2252                     __func__, err);
2253                 goto err_dalloc_q_counter;
2254         }
2255         err = mlx5e_open_rqt(priv);
2256         if (err) {
2257                 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n",
2258                     __func__, err);
2259                 goto err_close_channels;
2260         }
2261         err = mlx5e_open_tirs(priv);
2262         if (err) {
2263                 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n",
2264                     __func__, err);
2265                 goto err_close_rqls;
2266         }
2267         err = mlx5e_open_flow_table(priv);
2268         if (err) {
2269                 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n",
2270                     __func__, err);
2271                 goto err_close_tirs;
2272         }
2273         err = mlx5e_add_all_vlan_rules(priv);
2274         if (err) {
2275                 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
2276                     __func__, err);
2277                 goto err_close_flow_table;
2278         }
2279         set_bit(MLX5E_STATE_OPENED, &priv->state);
2280
2281         mlx5e_update_carrier(priv);
2282         mlx5e_set_rx_mode_core(priv);
2283
2284         return (0);
2285
2286 err_close_flow_table:
2287         mlx5e_close_flow_table(priv);
2288
2289 err_close_tirs:
2290         mlx5e_close_tirs(priv);
2291
2292 err_close_rqls:
2293         mlx5e_close_rqt(priv);
2294
2295 err_close_channels:
2296         mlx5e_close_channels(priv);
2297
2298 err_dalloc_q_counter:
2299         mlx5_vport_dealloc_q_counter(priv->mdev,
2300             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2301
2302 err_close_tises:
2303         mlx5e_close_tises(priv);
2304
2305         return (err);
2306 }
2307
2308 static void
2309 mlx5e_open(void *arg)
2310 {
2311         struct mlx5e_priv *priv = arg;
2312
2313         PRIV_LOCK(priv);
2314         if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
2315                 if_printf(priv->ifp,
2316                     "%s: Setting port status to up failed\n",
2317                     __func__);
2318
2319         mlx5e_open_locked(priv->ifp);
2320         priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
2321         PRIV_UNLOCK(priv);
2322 }
2323
2324 int
2325 mlx5e_close_locked(struct ifnet *ifp)
2326 {
2327         struct mlx5e_priv *priv = ifp->if_softc;
2328
2329         /* check if already closed */
2330         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2331                 return (0);
2332
2333         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2334
2335         mlx5e_set_rx_mode_core(priv);
2336         mlx5e_del_all_vlan_rules(priv);
2337         if_link_state_change(priv->ifp, LINK_STATE_DOWN);
2338         mlx5e_close_flow_table(priv);
2339         mlx5e_close_tirs(priv);
2340         mlx5e_close_rqt(priv);
2341         mlx5e_close_channels(priv);
2342         mlx5_vport_dealloc_q_counter(priv->mdev,
2343             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2344         mlx5e_close_tises(priv);
2345
2346         return (0);
2347 }
2348
2349 #if (__FreeBSD_version >= 1100000)
2350 static uint64_t
2351 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
2352 {
2353         struct mlx5e_priv *priv = ifp->if_softc;
2354         u64 retval;
2355
2356         /* PRIV_LOCK(priv); XXX not allowed */
2357         switch (cnt) {
2358         case IFCOUNTER_IPACKETS:
2359                 retval = priv->stats.vport.rx_packets;
2360                 break;
2361         case IFCOUNTER_IERRORS:
2362                 retval = priv->stats.vport.rx_error_packets;
2363                 break;
2364         case IFCOUNTER_IQDROPS:
2365                 retval = priv->stats.vport.rx_out_of_buffer;
2366                 break;
2367         case IFCOUNTER_OPACKETS:
2368                 retval = priv->stats.vport.tx_packets;
2369                 break;
2370         case IFCOUNTER_OERRORS:
2371                 retval = priv->stats.vport.tx_error_packets;
2372                 break;
2373         case IFCOUNTER_IBYTES:
2374                 retval = priv->stats.vport.rx_bytes;
2375                 break;
2376         case IFCOUNTER_OBYTES:
2377                 retval = priv->stats.vport.tx_bytes;
2378                 break;
2379         case IFCOUNTER_IMCASTS:
2380                 retval = priv->stats.vport.rx_multicast_packets;
2381                 break;
2382         case IFCOUNTER_OMCASTS:
2383                 retval = priv->stats.vport.tx_multicast_packets;
2384                 break;
2385         case IFCOUNTER_OQDROPS:
2386                 retval = priv->stats.vport.tx_queue_dropped;
2387                 break;
2388         default:
2389                 retval = if_get_counter_default(ifp, cnt);
2390                 break;
2391         }
2392         /* PRIV_UNLOCK(priv); XXX not allowed */
2393         return (retval);
2394 }
2395 #endif
2396
2397 static void
2398 mlx5e_set_rx_mode(struct ifnet *ifp)
2399 {
2400         struct mlx5e_priv *priv = ifp->if_softc;
2401
2402         schedule_work(&priv->set_rx_mode_work);
2403 }
2404
2405 static int
2406 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2407 {
2408         struct mlx5e_priv *priv;
2409         struct ifreq *ifr;
2410         struct ifi2creq i2c;
2411         int error = 0;
2412         int mask = 0;
2413         int size_read = 0;
2414         int module_num;
2415         int max_mtu;
2416         uint8_t read_addr;
2417
2418         priv = ifp->if_softc;
2419
2420         /* check if detaching */
2421         if (priv == NULL || priv->gone != 0)
2422                 return (ENXIO);
2423
2424         switch (command) {
2425         case SIOCSIFMTU:
2426                 ifr = (struct ifreq *)data;
2427
2428                 PRIV_LOCK(priv);
2429                 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
2430
2431                 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
2432                     ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
2433                         int was_opened;
2434
2435                         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2436                         if (was_opened)
2437                                 mlx5e_close_locked(ifp);
2438
2439                         /* set new MTU */
2440                         mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
2441
2442                         if (was_opened)
2443                                 mlx5e_open_locked(ifp);
2444                 } else {
2445                         error = EINVAL;
2446                         if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n",
2447                             MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
2448                 }
2449                 PRIV_UNLOCK(priv);
2450                 break;
2451         case SIOCSIFFLAGS:
2452                 if ((ifp->if_flags & IFF_UP) &&
2453                     (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2454                         mlx5e_set_rx_mode(ifp);
2455                         break;
2456                 }
2457                 PRIV_LOCK(priv);
2458                 if (ifp->if_flags & IFF_UP) {
2459                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2460                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2461                                         mlx5e_open_locked(ifp);
2462                                 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2463                                 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
2464                         }
2465                 } else {
2466                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2467                                 mlx5_set_port_status(priv->mdev,
2468                                     MLX5_PORT_DOWN);
2469                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2470                                         mlx5e_close_locked(ifp);
2471                                 mlx5e_update_carrier(priv);
2472                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2473                         }
2474                 }
2475                 PRIV_UNLOCK(priv);
2476                 break;
2477         case SIOCADDMULTI:
2478         case SIOCDELMULTI:
2479                 mlx5e_set_rx_mode(ifp);
2480                 break;
2481         case SIOCSIFMEDIA:
2482         case SIOCGIFMEDIA:
2483         case SIOCGIFXMEDIA:
2484                 ifr = (struct ifreq *)data;
2485                 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
2486                 break;
2487         case SIOCSIFCAP:
2488                 ifr = (struct ifreq *)data;
2489                 PRIV_LOCK(priv);
2490                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2491
2492                 if (mask & IFCAP_TXCSUM) {
2493                         ifp->if_capenable ^= IFCAP_TXCSUM;
2494                         ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2495
2496                         if (IFCAP_TSO4 & ifp->if_capenable &&
2497                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2498                                 ifp->if_capenable &= ~IFCAP_TSO4;
2499                                 ifp->if_hwassist &= ~CSUM_IP_TSO;
2500                                 if_printf(ifp,
2501                                     "tso4 disabled due to -txcsum.\n");
2502                         }
2503                 }
2504                 if (mask & IFCAP_TXCSUM_IPV6) {
2505                         ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
2506                         ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2507
2508                         if (IFCAP_TSO6 & ifp->if_capenable &&
2509                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2510                                 ifp->if_capenable &= ~IFCAP_TSO6;
2511                                 ifp->if_hwassist &= ~CSUM_IP6_TSO;
2512                                 if_printf(ifp,
2513                                     "tso6 disabled due to -txcsum6.\n");
2514                         }
2515                 }
2516                 if (mask & IFCAP_RXCSUM)
2517                         ifp->if_capenable ^= IFCAP_RXCSUM;
2518                 if (mask & IFCAP_RXCSUM_IPV6)
2519                         ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
2520                 if (mask & IFCAP_TSO4) {
2521                         if (!(IFCAP_TSO4 & ifp->if_capenable) &&
2522                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2523                                 if_printf(ifp, "enable txcsum first.\n");
2524                                 error = EAGAIN;
2525                                 goto out;
2526                         }
2527                         ifp->if_capenable ^= IFCAP_TSO4;
2528                         ifp->if_hwassist ^= CSUM_IP_TSO;
2529                 }
2530                 if (mask & IFCAP_TSO6) {
2531                         if (!(IFCAP_TSO6 & ifp->if_capenable) &&
2532                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2533                                 if_printf(ifp, "enable txcsum6 first.\n");
2534                                 error = EAGAIN;
2535                                 goto out;
2536                         }
2537                         ifp->if_capenable ^= IFCAP_TSO6;
2538                         ifp->if_hwassist ^= CSUM_IP6_TSO;
2539                 }
2540                 if (mask & IFCAP_VLAN_HWFILTER) {
2541                         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
2542                                 mlx5e_disable_vlan_filter(priv);
2543                         else
2544                                 mlx5e_enable_vlan_filter(priv);
2545
2546                         ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
2547                 }
2548                 if (mask & IFCAP_VLAN_HWTAGGING)
2549                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2550                 if (mask & IFCAP_WOL_MAGIC)
2551                         ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2552
2553                 VLAN_CAPABILITIES(ifp);
2554                 /* turn off LRO means also turn of HW LRO - if it's on */
2555                 if (mask & IFCAP_LRO) {
2556                         int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2557                         bool need_restart = false;
2558
2559                         ifp->if_capenable ^= IFCAP_LRO;
2560                         if (!(ifp->if_capenable & IFCAP_LRO)) {
2561                                 if (priv->params.hw_lro_en) {
2562                                         priv->params.hw_lro_en = false;
2563                                         need_restart = true;
2564                                         /* Not sure this is the correct way */
2565                                         priv->params_ethtool.hw_lro = priv->params.hw_lro_en;
2566                                 }
2567                         }
2568                         if (was_opened && need_restart) {
2569                                 mlx5e_close_locked(ifp);
2570                                 mlx5e_open_locked(ifp);
2571                         }
2572                 }
2573 out:
2574                 PRIV_UNLOCK(priv);
2575                 break;
2576
2577         case SIOCGI2C:
2578                 ifr = (struct ifreq *)data;
2579
2580                 /*
2581                  * Copy from the user-space address ifr_data to the
2582                  * kernel-space address i2c
2583                  */
2584                 error = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
2585                 if (error)
2586                         break;
2587
2588                 if (i2c.len > sizeof(i2c.data)) {
2589                         error = EINVAL;
2590                         break;
2591                 }
2592
2593                 PRIV_LOCK(priv);
2594                 /* Get module_num which is required for the query_eeprom */
2595                 error = mlx5_query_module_num(priv->mdev, &module_num);
2596                 if (error) {
2597                         if_printf(ifp, "Query module num failed, eeprom "
2598                             "reading is not supported\n");
2599                         error = EINVAL;
2600                         goto err_i2c;
2601                 }
2602                 /* Check if module is present before doing an access */
2603                 if (mlx5_query_module_status(priv->mdev, module_num) !=
2604                     MLX5_MODULE_STATUS_PLUGGED) {
2605                         error = EINVAL;
2606                         goto err_i2c;
2607                 }
2608                 /*
2609                  * Currently 0XA0 and 0xA2 are the only addresses permitted.
2610                  * The internal conversion is as follows:
2611                  */
2612                 if (i2c.dev_addr == 0xA0)
2613                         read_addr = MLX5E_I2C_ADDR_LOW;
2614                 else if (i2c.dev_addr == 0xA2)
2615                         read_addr = MLX5E_I2C_ADDR_HIGH;
2616                 else {
2617                         if_printf(ifp, "Query eeprom failed, "
2618                             "Invalid Address: %X\n", i2c.dev_addr);
2619                         error = EINVAL;
2620                         goto err_i2c;
2621                 }
2622                 error = mlx5_query_eeprom(priv->mdev,
2623                     read_addr, MLX5E_EEPROM_LOW_PAGE,
2624                     (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
2625                     (uint32_t *)i2c.data, &size_read);
2626                 if (error) {
2627                         if_printf(ifp, "Query eeprom failed, eeprom "
2628                             "reading is not supported\n");
2629                         error = EINVAL;
2630                         goto err_i2c;
2631                 }
2632
2633                 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
2634                         error = mlx5_query_eeprom(priv->mdev,
2635                             read_addr, MLX5E_EEPROM_LOW_PAGE,
2636                             (uint32_t)(i2c.offset + size_read),
2637                             (uint32_t)(i2c.len - size_read), module_num,
2638                             (uint32_t *)(i2c.data + size_read), &size_read);
2639                 }
2640                 if (error) {
2641                         if_printf(ifp, "Query eeprom failed, eeprom "
2642                             "reading is not supported\n");
2643                         error = EINVAL;
2644                         goto err_i2c;
2645                 }
2646
2647                 error = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
2648 err_i2c:
2649                 PRIV_UNLOCK(priv);
2650                 break;
2651
2652         default:
2653                 error = ether_ioctl(ifp, command, data);
2654                 break;
2655         }
2656         return (error);
2657 }
2658
2659 static int
2660 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2661 {
2662         /*
2663          * TODO: uncoment once FW really sets all these bits if
2664          * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
2665          * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
2666          * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
2667          * -ENOTSUPP;
2668          */
2669
2670         /* TODO: add more must-to-have features */
2671
2672         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2673                 return (-ENODEV);
2674
2675         return (0);
2676 }
2677
2678 static void
2679 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
2680     struct mlx5e_priv *priv,
2681     int num_comp_vectors)
2682 {
2683         /*
2684          * TODO: Consider link speed for setting "log_sq_size",
2685          * "log_rq_size" and "cq_moderation_xxx":
2686          */
2687         priv->params.log_sq_size =
2688             MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2689         priv->params.log_rq_size =
2690             MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2691         priv->params.rx_cq_moderation_usec =
2692             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
2693             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
2694             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2695         priv->params.rx_cq_moderation_mode =
2696             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
2697         priv->params.rx_cq_moderation_pkts =
2698             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2699         priv->params.tx_cq_moderation_usec =
2700             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2701         priv->params.tx_cq_moderation_pkts =
2702             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2703         priv->params.min_rx_wqes =
2704             MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
2705         priv->params.rx_hash_log_tbl_sz =
2706             (order_base_2(num_comp_vectors) >
2707             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
2708             order_base_2(num_comp_vectors) :
2709             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
2710         priv->params.num_tc = 1;
2711         priv->params.default_vlan_prio = 0;
2712         priv->counter_set_id = -1;
2713
2714         /*
2715          * hw lro is currently defaulted to off. when it won't anymore we
2716          * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
2717          */
2718         priv->params.hw_lro_en = false;
2719         priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2720
2721         priv->params.cqe_zipping_en = !!MLX5_CAP_GEN(mdev, cqe_compression);
2722
2723         priv->mdev = mdev;
2724         priv->params.num_channels = num_comp_vectors;
2725         priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
2726         priv->queue_mapping_channel_mask =
2727             roundup_pow_of_two(num_comp_vectors) - 1;
2728         priv->num_tc = priv->params.num_tc;
2729         priv->default_vlan_prio = priv->params.default_vlan_prio;
2730
2731         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2732         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2733         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2734 }
2735
2736 static int
2737 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2738     struct mlx5_core_mr *mr)
2739 {
2740         struct ifnet *ifp = priv->ifp;
2741         struct mlx5_core_dev *mdev = priv->mdev;
2742         struct mlx5_create_mkey_mbox_in *in;
2743         int err;
2744
2745         in = mlx5_vzalloc(sizeof(*in));
2746         if (in == NULL) {
2747                 if_printf(ifp, "%s: failed to allocate inbox\n", __func__);
2748                 return (-ENOMEM);
2749         }
2750         in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2751             MLX5_PERM_LOCAL_READ |
2752             MLX5_ACCESS_MODE_PA;
2753         in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2754         in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2755
2756         err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL,
2757             NULL);
2758         if (err)
2759                 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n",
2760                     __func__, err);
2761
2762         kvfree(in);
2763
2764         return (err);
2765 }
2766
2767 static const char *mlx5e_vport_stats_desc[] = {
2768         MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
2769 };
2770
2771 static const char *mlx5e_pport_stats_desc[] = {
2772         MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
2773 };
2774
2775 static void
2776 mlx5e_priv_mtx_init(struct mlx5e_priv *priv)
2777 {
2778         mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
2779         sx_init(&priv->state_lock, "mlx5state");
2780         callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
2781         MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
2782 }
2783
2784 static void
2785 mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv)
2786 {
2787         mtx_destroy(&priv->async_events_mtx);
2788         sx_destroy(&priv->state_lock);
2789 }
2790
2791 static int
2792 sysctl_firmware(SYSCTL_HANDLER_ARGS)
2793 {
2794         /*
2795          * %d.%d%.d the string format.
2796          * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
2797          * We need at most 5 chars to store that.
2798          * It also has: two "." and NULL at the end, which means we need 18
2799          * (5*3 + 3) chars at most.
2800          */
2801         char fw[18];
2802         struct mlx5e_priv *priv = arg1;
2803         int error;
2804
2805         snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
2806             fw_rev_sub(priv->mdev));
2807         error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
2808         return (error);
2809 }
2810
2811 static void
2812 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
2813 {
2814         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
2815             OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
2816             sysctl_firmware, "A", "HCA firmware version");
2817
2818         SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
2819             OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
2820             "Board ID");
2821 }
2822
2823 static void
2824 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
2825 {
2826 #if (__FreeBSD_version < 1100000)
2827         char path[64];
2828
2829 #endif
2830         /* Only receiving pauseframes is enabled by default */
2831         priv->params.tx_pauseframe_control = 0;
2832         priv->params.rx_pauseframe_control = 1;
2833
2834 #if (__FreeBSD_version < 1100000)
2835         /* compute path for sysctl */
2836         snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
2837             device_get_unit(priv->mdev->pdev->dev.bsddev));
2838
2839         /* try to fetch tunable, if any */
2840         TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
2841
2842         /* compute path for sysctl */
2843         snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
2844             device_get_unit(priv->mdev->pdev->dev.bsddev));
2845
2846         /* try to fetch tunable, if any */
2847         TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
2848 #endif
2849
2850         /* register pausframe SYSCTLs */
2851         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2852             OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
2853             &priv->params.tx_pauseframe_control, 0,
2854             "Set to enable TX pause frames. Clear to disable.");
2855
2856         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2857             OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
2858             &priv->params.rx_pauseframe_control, 0,
2859             "Set to enable RX pause frames. Clear to disable.");
2860
2861         /* range check */
2862         priv->params.tx_pauseframe_control =
2863             priv->params.tx_pauseframe_control ? 1 : 0;
2864         priv->params.rx_pauseframe_control =
2865             priv->params.rx_pauseframe_control ? 1 : 0;
2866
2867         /* update firmware */
2868         mlx5_set_port_pause(priv->mdev, 1,
2869             priv->params.rx_pauseframe_control,
2870             priv->params.tx_pauseframe_control);
2871 }
2872
2873 static void *
2874 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
2875 {
2876         static volatile int mlx5_en_unit;
2877         struct ifnet *ifp;
2878         struct mlx5e_priv *priv;
2879         u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
2880         struct sysctl_oid_list *child;
2881         int ncv = mdev->priv.eq_table.num_comp_vectors;
2882         char unit[16];
2883         int err;
2884         int i;
2885         u32 eth_proto_cap;
2886
2887         if (mlx5e_check_required_hca_cap(mdev)) {
2888                 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
2889                 return (NULL);
2890         }
2891         priv = malloc(sizeof(*priv), M_MLX5EN, M_WAITOK | M_ZERO);
2892         mlx5e_priv_mtx_init(priv);
2893
2894         ifp = priv->ifp = if_alloc(IFT_ETHER);
2895         if (ifp == NULL) {
2896                 mlx5_core_err(mdev, "if_alloc() failed\n");
2897                 goto err_free_priv;
2898         }
2899         ifp->if_softc = priv;
2900         if_initname(ifp, "mce", atomic_fetchadd_int(&mlx5_en_unit, 1));
2901         ifp->if_mtu = ETHERMTU;
2902         ifp->if_init = mlx5e_open;
2903         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2904         ifp->if_ioctl = mlx5e_ioctl;
2905         ifp->if_transmit = mlx5e_xmit;
2906         ifp->if_qflush = if_qflush;
2907 #if (__FreeBSD_version >= 1100000)
2908         ifp->if_get_counter = mlx5e_get_counter;
2909 #endif
2910         ifp->if_snd.ifq_maxlen = ifqmaxlen;
2911         /*
2912          * Set driver features
2913          */
2914         ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
2915         ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
2916         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
2917         ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
2918         ifp->if_capabilities |= IFCAP_LRO;
2919         ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
2920         ifp->if_capabilities |= IFCAP_HWSTATS;
2921
2922         /* set TSO limits so that we don't have to drop TX packets */
2923         ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
2924         ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
2925         ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
2926
2927         ifp->if_capenable = ifp->if_capabilities;
2928         ifp->if_hwassist = 0;
2929         if (ifp->if_capenable & IFCAP_TSO)
2930                 ifp->if_hwassist |= CSUM_TSO;
2931         if (ifp->if_capenable & IFCAP_TXCSUM)
2932                 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2933         if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
2934                 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2935
2936         /* ifnet sysctl tree */
2937         sysctl_ctx_init(&priv->sysctl_ctx);
2938         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
2939             OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
2940         if (priv->sysctl_ifnet == NULL) {
2941                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
2942                 goto err_free_sysctl;
2943         }
2944         snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
2945         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2946             OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
2947         if (priv->sysctl_ifnet == NULL) {
2948                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
2949                 goto err_free_sysctl;
2950         }
2951
2952         /* HW sysctl tree */
2953         child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
2954         priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
2955             OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
2956         if (priv->sysctl_hw == NULL) {
2957                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
2958                 goto err_free_sysctl;
2959         }
2960         mlx5e_build_ifp_priv(mdev, priv, ncv);
2961         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
2962         if (err) {
2963                 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n",
2964                     __func__, err);
2965                 goto err_free_sysctl;
2966         }
2967         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2968         if (err) {
2969                 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n",
2970                     __func__, err);
2971                 goto err_unmap_free_uar;
2972         }
2973         err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
2974         if (err) {
2975                 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n",
2976                     __func__, err);
2977                 goto err_dealloc_pd;
2978         }
2979         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
2980         if (err) {
2981                 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n",
2982                     __func__, err);
2983                 goto err_dealloc_transport_domain;
2984         }
2985         mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
2986
2987         /* check if we should generate a random MAC address */
2988         if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
2989             is_zero_ether_addr(dev_addr)) {
2990                 random_ether_addr(dev_addr);
2991                 if_printf(ifp, "Assigned random MAC address\n");
2992         }
2993
2994         /* set default MTU */
2995         mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
2996
2997         /* Set desc */
2998         device_set_desc(mdev->pdev->dev.bsddev, mlx5e_version);
2999
3000         /* Set default media status */
3001         priv->media_status_last = IFM_AVALID;
3002         priv->media_active_last = IFM_ETHER | IFM_AUTO |
3003             IFM_ETH_RXPAUSE | IFM_FDX;
3004
3005         /* setup default pauseframes configuration */
3006         mlx5e_setup_pauseframes(priv);
3007
3008         err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
3009         if (err) {
3010                 eth_proto_cap = 0;
3011                 if_printf(ifp, "%s: Query port media capability failed, %d\n",
3012                     __func__, err);
3013         }
3014
3015         /* Setup supported medias */
3016         ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
3017             mlx5e_media_change, mlx5e_media_status);
3018
3019         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
3020                 if (mlx5e_mode_table[i].baudrate == 0)
3021                         continue;
3022                 if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
3023                         ifmedia_add(&priv->media,
3024                             mlx5e_mode_table[i].subtype |
3025                             IFM_ETHER, 0, NULL);
3026                         ifmedia_add(&priv->media,
3027                             mlx5e_mode_table[i].subtype |
3028                             IFM_ETHER | IFM_FDX |
3029                             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3030                 }
3031         }
3032
3033         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
3034         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3035             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3036
3037         /* Set autoselect by default */
3038         ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3039             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
3040         ether_ifattach(ifp, dev_addr);
3041
3042         /* Register for VLAN events */
3043         priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
3044             mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
3045         priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
3046             mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
3047
3048         /* Link is down by default */
3049         if_link_state_change(ifp, LINK_STATE_DOWN);
3050
3051         mlx5e_enable_async_events(priv);
3052
3053         mlx5e_add_hw_stats(priv);
3054
3055         mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3056             "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
3057             priv->stats.vport.arg);
3058
3059         mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3060             "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
3061             priv->stats.pport.arg);
3062
3063         mlx5e_create_ethtool(priv);
3064
3065         mtx_lock(&priv->async_events_mtx);
3066         mlx5e_update_stats(priv);
3067         mtx_unlock(&priv->async_events_mtx);
3068
3069         return (priv);
3070
3071 err_dealloc_transport_domain:
3072         mlx5_dealloc_transport_domain(mdev, priv->tdn);
3073
3074 err_dealloc_pd:
3075         mlx5_core_dealloc_pd(mdev, priv->pdn);
3076
3077 err_unmap_free_uar:
3078         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3079
3080 err_free_sysctl:
3081         sysctl_ctx_free(&priv->sysctl_ctx);
3082
3083         if_free(ifp);
3084
3085 err_free_priv:
3086         mlx5e_priv_mtx_destroy(priv);
3087         free(priv, M_MLX5EN);
3088         return (NULL);
3089 }
3090
3091 static void
3092 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
3093 {
3094         struct mlx5e_priv *priv = vpriv;
3095         struct ifnet *ifp = priv->ifp;
3096
3097         /* don't allow more IOCTLs */
3098         priv->gone = 1;
3099
3100         /*
3101          * Clear the device description to avoid use after free,
3102          * because the bsddev is not destroyed when this module is
3103          * unloaded:
3104          */
3105         device_set_desc(mdev->pdev->dev.bsddev, NULL);
3106
3107         /* XXX wait a bit to allow IOCTL handlers to complete */
3108         pause("W", hz);
3109
3110         /* stop watchdog timer */
3111         callout_drain(&priv->watchdog);
3112
3113         if (priv->vlan_attach != NULL)
3114                 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
3115         if (priv->vlan_detach != NULL)
3116                 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
3117
3118         /* make sure device gets closed */
3119         PRIV_LOCK(priv);
3120         mlx5e_close_locked(ifp);
3121         PRIV_UNLOCK(priv);
3122
3123         /* unregister device */
3124         ifmedia_removeall(&priv->media);
3125         ether_ifdetach(ifp);
3126         if_free(ifp);
3127
3128         /* destroy all remaining sysctl nodes */
3129         if (priv->sysctl_debug)
3130                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
3131         sysctl_ctx_free(&priv->stats.vport.ctx);
3132         sysctl_ctx_free(&priv->stats.pport.ctx);
3133         sysctl_ctx_free(&priv->sysctl_ctx);
3134
3135         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
3136         mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
3137         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3138         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
3139         mlx5e_disable_async_events(priv);
3140         flush_scheduled_work();
3141         mlx5e_priv_mtx_destroy(priv);
3142         free(priv, M_MLX5EN);
3143 }
3144
3145 static void *
3146 mlx5e_get_ifp(void *vpriv)
3147 {
3148         struct mlx5e_priv *priv = vpriv;
3149
3150         return (priv->ifp);
3151 }
3152
3153 static struct mlx5_interface mlx5e_interface = {
3154         .add = mlx5e_create_ifp,
3155         .remove = mlx5e_destroy_ifp,
3156         .event = mlx5e_async_event,
3157         .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3158         .get_dev = mlx5e_get_ifp,
3159 };
3160
3161 void
3162 mlx5e_init(void)
3163 {
3164         mlx5_register_interface(&mlx5e_interface);
3165 }
3166
3167 void
3168 mlx5e_cleanup(void)
3169 {
3170         mlx5_unregister_interface(&mlx5e_interface);
3171 }
3172
3173 module_init_order(mlx5e_init, SI_ORDER_THIRD);
3174 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
3175
3176 #if (__FreeBSD_version >= 1100000)
3177 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
3178 #endif
3179 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
3180 MODULE_VERSION(mlx5en, 1);