sys/dev/mlx5/mlx5_en/mlx5_en_main.c

   1 /*-
   2  * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include "en.h"
  29
  30 #include <sys/sockio.h>
  31 #include <machine/atomic.h>
  32
  33 #ifndef ETH_DRIVER_VERSION
  34 #define ETH_DRIVER_VERSION      "3.5.0"
  35 #endif
  36 #define DRIVER_RELDATE  "November 2018"
  37
  38 static const char mlx5e_version[] = "mlx5en: Mellanox Ethernet driver "
  39         ETH_DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
  40
  41 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs);
  42
  43 struct mlx5e_channel_param {
  44         struct mlx5e_rq_param rq;
  45         struct mlx5e_sq_param sq;
  46         struct mlx5e_cq_param rx_cq;
  47         struct mlx5e_cq_param tx_cq;
  48 };
  49
  50 struct media {
  51         u32     subtype;
  52         u64     baudrate;
  53 };
  54
  55 static const struct media mlx5e_mode_table[MLX5E_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = {
  56
  57         [MLX5E_1000BASE_CX_SGMII][MLX5E_SGMII] = {
  58                 .subtype = IFM_1000_CX_SGMII,
  59                 .baudrate = IF_Mbps(1000ULL),
  60         },
  61         [MLX5E_1000BASE_KX][MLX5E_KX] = {
  62                 .subtype = IFM_1000_KX,
  63                 .baudrate = IF_Mbps(1000ULL),
  64         },
  65         [MLX5E_10GBASE_CX4][MLX5E_CX4] = {
  66                 .subtype = IFM_10G_CX4,
  67                 .baudrate = IF_Gbps(10ULL),
  68         },
  69         [MLX5E_10GBASE_KX4][MLX5E_KX4] = {
  70                 .subtype = IFM_10G_KX4,
  71                 .baudrate = IF_Gbps(10ULL),
  72         },
  73         [MLX5E_10GBASE_KR][MLX5E_KR] = {
  74                 .subtype = IFM_10G_KR,
  75                 .baudrate = IF_Gbps(10ULL),
  76         },
  77         [MLX5E_20GBASE_KR2][MLX5E_KR2] = {
  78                 .subtype = IFM_20G_KR2,
  79                 .baudrate = IF_Gbps(20ULL),
  80         },
  81         [MLX5E_40GBASE_CR4][MLX5E_CR4] = {
  82                 .subtype = IFM_40G_CR4,
  83                 .baudrate = IF_Gbps(40ULL),
  84         },
  85         [MLX5E_40GBASE_KR4][MLX5E_KR4] = {
  86                 .subtype = IFM_40G_KR4,
  87                 .baudrate = IF_Gbps(40ULL),
  88         },
  89         [MLX5E_56GBASE_R4][MLX5E_R] = {
  90                 .subtype = IFM_56G_R4,
  91                 .baudrate = IF_Gbps(56ULL),
  92         },
  93         [MLX5E_10GBASE_CR][MLX5E_CR1] = {
  94                 .subtype = IFM_10G_CR1,
  95                 .baudrate = IF_Gbps(10ULL),
  96         },
  97         [MLX5E_10GBASE_SR][MLX5E_SR] = {
  98                 .subtype = IFM_10G_SR,
  99                 .baudrate = IF_Gbps(10ULL),
 100         },
 101         [MLX5E_10GBASE_ER_LR][MLX5E_ER] = {
 102                 .subtype = IFM_10G_ER,
 103                 .baudrate = IF_Gbps(10ULL),
 104         },
 105         [MLX5E_10GBASE_ER_LR][MLX5E_LR] = {
 106                 .subtype = IFM_10G_LR,
 107                 .baudrate = IF_Gbps(10ULL),
 108         },
 109         [MLX5E_40GBASE_SR4][MLX5E_SR4] = {
 110                 .subtype = IFM_40G_SR4,
 111                 .baudrate = IF_Gbps(40ULL),
 112         },
 113         [MLX5E_40GBASE_LR4_ER4][MLX5E_LR4] = {
 114                 .subtype = IFM_40G_LR4,
 115                 .baudrate = IF_Gbps(40ULL),
 116         },
 117         [MLX5E_40GBASE_LR4_ER4][MLX5E_ER4] = {
 118                 .subtype = IFM_40G_ER4,
 119                 .baudrate = IF_Gbps(40ULL),
 120         },
 121         [MLX5E_100GBASE_CR4][MLX5E_CR4] = {
 122                 .subtype = IFM_100G_CR4,
 123                 .baudrate = IF_Gbps(100ULL),
 124         },
 125         [MLX5E_100GBASE_SR4][MLX5E_SR4] = {
 126                 .subtype = IFM_100G_SR4,
 127                 .baudrate = IF_Gbps(100ULL),
 128         },
 129         [MLX5E_100GBASE_KR4][MLX5E_KR4] = {
 130                 .subtype = IFM_100G_KR4,
 131                 .baudrate = IF_Gbps(100ULL),
 132         },
 133         [MLX5E_100GBASE_LR4][MLX5E_LR4] = {
 134                 .subtype = IFM_100G_LR4,
 135                 .baudrate = IF_Gbps(100ULL),
 136         },
 137         [MLX5E_100BASE_TX][MLX5E_TX] = {
 138                 .subtype = IFM_100_TX,
 139                 .baudrate = IF_Mbps(100ULL),
 140         },
 141         [MLX5E_1000BASE_T][MLX5E_T] = {
 142                 .subtype = IFM_1000_T,
 143                 .baudrate = IF_Mbps(1000ULL),
 144         },
 145         [MLX5E_10GBASE_T][MLX5E_T] = {
 146                 .subtype = IFM_10G_T,
 147                 .baudrate = IF_Gbps(10ULL),
 148         },
 149         [MLX5E_25GBASE_CR][MLX5E_CR] = {
 150                 .subtype = IFM_25G_CR,
 151                 .baudrate = IF_Gbps(25ULL),
 152         },
 153         [MLX5E_25GBASE_KR][MLX5E_KR] = {
 154                 .subtype = IFM_25G_KR,
 155                 .baudrate = IF_Gbps(25ULL),
 156         },
 157         [MLX5E_25GBASE_SR][MLX5E_SR] = {
 158                 .subtype = IFM_25G_SR,
 159                 .baudrate = IF_Gbps(25ULL),
 160         },
 161         [MLX5E_50GBASE_CR2][MLX5E_CR2] = {
 162                 .subtype = IFM_50G_CR2,
 163                 .baudrate = IF_Gbps(50ULL),
 164         },
 165         [MLX5E_50GBASE_KR2][MLX5E_KR2] = {
 166                 .subtype = IFM_50G_KR2,
 167                 .baudrate = IF_Gbps(50ULL),
 168         },
 169 };
 170
 171 static const struct media mlx5e_ext_mode_table[MLX5E_EXT_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = {
 172         [MLX5E_SGMII_100M][MLX5E_SGMII] = {
 173                 .subtype = IFM_100_SGMII,
 174                 .baudrate = IF_Mbps(100),
 175         },
 176         [MLX5E_1000BASE_X_SGMII][MLX5E_KX] = {
 177                 .subtype = IFM_1000_KX,
 178                 .baudrate = IF_Mbps(1000),
 179         },
 180         [MLX5E_1000BASE_X_SGMII][MLX5E_CX_SGMII] = {
 181                 .subtype = IFM_1000_CX_SGMII,
 182                 .baudrate = IF_Mbps(1000),
 183         },
 184         [MLX5E_1000BASE_X_SGMII][MLX5E_CX] = {
 185                 .subtype = IFM_1000_CX,
 186                 .baudrate = IF_Mbps(1000),
 187         },
 188         [MLX5E_1000BASE_X_SGMII][MLX5E_LX] = {
 189                 .subtype = IFM_1000_LX,
 190                 .baudrate = IF_Mbps(1000),
 191         },
 192         [MLX5E_1000BASE_X_SGMII][MLX5E_SX] = {
 193                 .subtype = IFM_1000_SX,
 194                 .baudrate = IF_Mbps(1000),
 195         },
 196         [MLX5E_1000BASE_X_SGMII][MLX5E_T] = {
 197                 .subtype = IFM_1000_T,
 198                 .baudrate = IF_Mbps(1000),
 199         },
 200         [MLX5E_5GBASE_R][MLX5E_T] = {
 201                 .subtype = IFM_5000_T,
 202                 .baudrate = IF_Mbps(5000),
 203         },
 204         [MLX5E_5GBASE_R][MLX5E_KR] = {
 205                 .subtype = IFM_5000_KR,
 206                 .baudrate = IF_Mbps(5000),
 207         },
 208         [MLX5E_5GBASE_R][MLX5E_KR1] = {
 209                 .subtype = IFM_5000_KR1,
 210                 .baudrate = IF_Mbps(5000),
 211         },
 212         [MLX5E_5GBASE_R][MLX5E_KR_S] = {
 213                 .subtype = IFM_5000_KR_S,
 214                 .baudrate = IF_Mbps(5000),
 215         },
 216         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_ER] = {
 217                 .subtype = IFM_10G_ER,
 218                 .baudrate = IF_Gbps(10ULL),
 219         },
 220         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_KR] = {
 221                 .subtype = IFM_10G_KR,
 222                 .baudrate = IF_Gbps(10ULL),
 223         },
 224         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_LR] = {
 225                 .subtype = IFM_10G_LR,
 226                 .baudrate = IF_Gbps(10ULL),
 227         },
 228         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_SR] = {
 229                 .subtype = IFM_10G_SR,
 230                 .baudrate = IF_Gbps(10ULL),
 231         },
 232         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_T] = {
 233                 .subtype = IFM_10G_T,
 234                 .baudrate = IF_Gbps(10ULL),
 235         },
 236         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_AOC] = {
 237                 .subtype = IFM_10G_AOC,
 238                 .baudrate = IF_Gbps(10ULL),
 239         },
 240         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CR1] = {
 241                 .subtype = IFM_10G_CR1,
 242                 .baudrate = IF_Gbps(10ULL),
 243         },
 244         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CR4] = {
 245                 .subtype = IFM_40G_CR4,
 246                 .baudrate = IF_Gbps(40ULL),
 247         },
 248         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_KR4] = {
 249                 .subtype = IFM_40G_KR4,
 250                 .baudrate = IF_Gbps(40ULL),
 251         },
 252         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_LR4] = {
 253                 .subtype = IFM_40G_LR4,
 254                 .baudrate = IF_Gbps(40ULL),
 255         },
 256         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_SR4] = {
 257                 .subtype = IFM_40G_SR4,
 258                 .baudrate = IF_Gbps(40ULL),
 259         },
 260         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_ER4] = {
 261                 .subtype = IFM_40G_ER4,
 262                 .baudrate = IF_Gbps(40ULL),
 263         },
 264
 265         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR] = {
 266                 .subtype = IFM_25G_CR,
 267                 .baudrate = IF_Gbps(25ULL),
 268         },
 269         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR] = {
 270                 .subtype = IFM_25G_KR,
 271                 .baudrate = IF_Gbps(25ULL),
 272         },
 273         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_SR] = {
 274                 .subtype = IFM_25G_SR,
 275                 .baudrate = IF_Gbps(25ULL),
 276         },
 277         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_ACC] = {
 278                 .subtype = IFM_25G_ACC,
 279                 .baudrate = IF_Gbps(25ULL),
 280         },
 281         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_AOC] = {
 282                 .subtype = IFM_25G_AOC,
 283                 .baudrate = IF_Gbps(25ULL),
 284         },
 285         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR1] = {
 286                 .subtype = IFM_25G_CR1,
 287                 .baudrate = IF_Gbps(25ULL),
 288         },
 289         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR_S] = {
 290                 .subtype = IFM_25G_CR_S,
 291                 .baudrate = IF_Gbps(25ULL),
 292         },
 293         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR1] = {
 294                 .subtype = IFM_5000_KR1,
 295                 .baudrate = IF_Gbps(25ULL),
 296         },
 297         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR_S] = {
 298                 .subtype = IFM_25G_KR_S,
 299                 .baudrate = IF_Gbps(25ULL),
 300         },
 301         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_LR] = {
 302                 .subtype = IFM_25G_LR,
 303                 .baudrate = IF_Gbps(25ULL),
 304         },
 305         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_T] = {
 306                 .subtype = IFM_25G_T,
 307                 .baudrate = IF_Gbps(25ULL),
 308         },
 309         [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CR2] = {
 310                 .subtype = IFM_50G_CR2,
 311                 .baudrate = IF_Gbps(50ULL),
 312         },
 313         [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_KR2] = {
 314                 .subtype = IFM_50G_KR2,
 315                 .baudrate = IF_Gbps(50ULL),
 316         },
 317         [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_SR2] = {
 318                 .subtype = IFM_50G_SR2,
 319                 .baudrate = IF_Gbps(50ULL),
 320         },
 321         [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_LR2] = {
 322                 .subtype = IFM_50G_LR2,
 323                 .baudrate = IF_Gbps(50ULL),
 324         },
 325         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_LR] = {
 326                 .subtype = IFM_50G_LR,
 327                 .baudrate = IF_Gbps(50ULL),
 328         },
 329         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_SR] = {
 330                 .subtype = IFM_50G_SR,
 331                 .baudrate = IF_Gbps(50ULL),
 332         },
 333         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CP] = {
 334                 .subtype = IFM_50G_CP,
 335                 .baudrate = IF_Gbps(50ULL),
 336         },
 337         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_FR] = {
 338                 .subtype = IFM_50G_FR,
 339                 .baudrate = IF_Gbps(50ULL),
 340         },
 341         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_KR_PAM4] = {
 342                 .subtype = IFM_50G_KR_PAM4,
 343                 .baudrate = IF_Gbps(50ULL),
 344         },
 345         [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CR4] = {
 346                 .subtype = IFM_100G_CR4,
 347                 .baudrate = IF_Gbps(100ULL),
 348         },
 349         [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_KR4] = {
 350                 .subtype = IFM_100G_KR4,
 351                 .baudrate = IF_Gbps(100ULL),
 352         },
 353         [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_LR4] = {
 354                 .subtype = IFM_100G_LR4,
 355                 .baudrate = IF_Gbps(100ULL),
 356         },
 357         [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_SR4] = {
 358                 .subtype = IFM_100G_SR4,
 359                 .baudrate = IF_Gbps(100ULL),
 360         },
 361         [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_SR2] = {
 362                 .subtype = IFM_100G_SR2,
 363                 .baudrate = IF_Gbps(100ULL),
 364         },
 365         [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CP2] = {
 366                 .subtype = IFM_100G_CP2,
 367                 .baudrate = IF_Gbps(100ULL),
 368         },
 369         [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_KR2_PAM4] = {
 370                 .subtype = IFM_100G_KR2_PAM4,
 371                 .baudrate = IF_Gbps(100ULL),
 372         },
 373         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_DR4] = {
 374                 .subtype = IFM_200G_DR4,
 375                 .baudrate = IF_Gbps(200ULL),
 376         },
 377         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_LR4] = {
 378                 .subtype = IFM_200G_LR4,
 379                 .baudrate = IF_Gbps(200ULL),
 380         },
 381         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_SR4] = {
 382                 .subtype = IFM_200G_SR4,
 383                 .baudrate = IF_Gbps(200ULL),
 384         },
 385         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_FR4] = {
 386                 .subtype = IFM_200G_FR4,
 387                 .baudrate = IF_Gbps(200ULL),
 388         },
 389         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CR4_PAM4] = {
 390                 .subtype = IFM_200G_CR4_PAM4,
 391                 .baudrate = IF_Gbps(200ULL),
 392         },
 393         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_KR4_PAM4] = {
 394                 .subtype = IFM_200G_KR4_PAM4,
 395                 .baudrate = IF_Gbps(200ULL),
 396         },
 397 };
 398
 399 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
 400
 401 static void
 402 mlx5e_update_carrier(struct mlx5e_priv *priv)
 403 {
 404         struct mlx5_core_dev *mdev = priv->mdev;
 405         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 406         u32 eth_proto_oper;
 407         int error;
 408         u8 port_state;
 409         u8 is_er_type;
 410         u8 i, j;
 411         bool ext;
 412         struct media media_entry = {};
 413
 414         port_state = mlx5_query_vport_state(mdev,
 415             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 416
 417         if (port_state == VPORT_STATE_UP) {
 418                 priv->media_status_last |= IFM_ACTIVE;
 419         } else {
 420                 priv->media_status_last &= ~IFM_ACTIVE;
 421                 priv->media_active_last = IFM_ETHER;
 422                 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
 423                 return;
 424         }
 425
 426         error = mlx5_query_port_ptys(mdev, out, sizeof(out),
 427             MLX5_PTYS_EN, 1);
 428         if (error) {
 429                 priv->media_active_last = IFM_ETHER;
 430                 priv->ifp->if_baudrate = 1;
 431                 if_printf(priv->ifp, "%s: query port ptys failed: "
 432                     "0x%x\n", __func__, error);
 433                 return;
 434         }
 435
 436         ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
 437         eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
 438             eth_proto_oper);
 439
 440         i = ilog2(eth_proto_oper);
 441
 442         for (j = 0; j != MLX5E_LINK_MODES_NUMBER; j++) {
 443                 media_entry = ext ? mlx5e_ext_mode_table[i][j] :
 444                     mlx5e_mode_table[i][j];
 445                 if (media_entry.baudrate != 0)
 446                         break;
 447         }
 448
 449         if (media_entry.subtype == 0) {
 450                 if_printf(priv->ifp, "%s: Could not find operational "
 451                     "media subtype\n", __func__);
 452                 return;
 453         }
 454
 455         switch (media_entry.subtype) {
 456         case IFM_10G_ER:
 457                 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
 458                 if (error != 0) {
 459                         if_printf(priv->ifp, "%s: query port pddr failed: %d\n",
 460                                   __func__, error);
 461                 }
 462                 if (error != 0 || is_er_type == 0)
 463                         media_entry.subtype = IFM_10G_LR;
 464                 break;
 465         case IFM_40G_LR4:
 466                 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
 467                 if (error != 0) {
 468                         if_printf(priv->ifp, "%s: query port pddr failed: %d\n",
 469                                   __func__, error);
 470                 }
 471                 if (error == 0 && is_er_type != 0)
 472                         media_entry.subtype = IFM_40G_ER4;
 473                 break;
 474         }
 475         priv->media_active_last = media_entry.subtype | IFM_ETHER | IFM_FDX;
 476         priv->ifp->if_baudrate = media_entry.baudrate;
 477
 478         if_link_state_change(priv->ifp, LINK_STATE_UP);
 479 }
 480
 481 static void
 482 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
 483 {
 484         struct mlx5e_priv *priv = dev->if_softc;
 485
 486         ifmr->ifm_status = priv->media_status_last;
 487         ifmr->ifm_active = priv->media_active_last |
 488             (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
 489             (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
 490
 491 }
 492
 493 static u32
 494 mlx5e_find_link_mode(u32 subtype, bool ext)
 495 {
 496         u32 i;
 497         u32 j;
 498         u32 link_mode = 0;
 499         u32 speeds_num = 0;
 500         struct media media_entry = {};
 501
 502         switch (subtype) {
 503         case IFM_10G_LR:
 504                 subtype = IFM_10G_ER;
 505                 break;
 506         case IFM_40G_ER4:
 507                 subtype = IFM_40G_LR4;
 508                 break;
 509         }
 510
 511         speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER :
 512             MLX5E_LINK_SPEEDS_NUMBER;
 513
 514         for (i = 0; i != speeds_num; i++) {
 515                 for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) {
 516                         media_entry = ext ? mlx5e_ext_mode_table[i][j] :
 517                             mlx5e_mode_table[i][j];
 518                         if (media_entry.baudrate == 0)
 519                                 continue;
 520                         if (media_entry.subtype == subtype) {
 521                                 link_mode |= MLX5E_PROT_MASK(i);
 522                         }
 523                 }
 524         }
 525
 526         return (link_mode);
 527 }
 528
 529 static int
 530 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv)
 531 {
 532         return (mlx5_set_port_pause_and_pfc(priv->mdev, 1,
 533             priv->params.rx_pauseframe_control,
 534             priv->params.tx_pauseframe_control,
 535             priv->params.rx_priority_flow_control,
 536             priv->params.tx_priority_flow_control));
 537 }
 538
 539 static int
 540 mlx5e_set_port_pfc(struct mlx5e_priv *priv)
 541 {
 542         int error;
 543
 544         if (priv->gone != 0) {
 545                 error = -ENXIO;
 546         } else if (priv->params.rx_pauseframe_control ||
 547             priv->params.tx_pauseframe_control) {
 548                 if_printf(priv->ifp,
 549                     "Global pauseframes must be disabled before "
 550                     "enabling PFC.\n");
 551                 error = -EINVAL;
 552         } else {
 553                 error = mlx5e_set_port_pause_and_pfc(priv);
 554         }
 555         return (error);
 556 }
 557
 558 static int
 559 mlx5e_media_change(struct ifnet *dev)
 560 {
 561         struct mlx5e_priv *priv = dev->if_softc;
 562         struct mlx5_core_dev *mdev = priv->mdev;
 563         u32 eth_proto_cap;
 564         u32 link_mode;
 565         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 566         int was_opened;
 567         int locked;
 568         int error;
 569         bool ext;
 570
 571         locked = PRIV_LOCKED(priv);
 572         if (!locked)
 573                 PRIV_LOCK(priv);
 574
 575         if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
 576                 error = EINVAL;
 577                 goto done;
 578         }
 579
 580         error = mlx5_query_port_ptys(mdev, out, sizeof(out),
 581             MLX5_PTYS_EN, 1);
 582         if (error != 0) {
 583                 if_printf(dev, "Query port media capability failed\n");
 584                 goto done;
 585         }
 586
 587         ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
 588         link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media), ext);
 589
 590         /* query supported capabilities */
 591         eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
 592             eth_proto_capability);
 593
 594         /* check for autoselect */
 595         if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
 596                 link_mode = eth_proto_cap;
 597                 if (link_mode == 0) {
 598                         if_printf(dev, "Port media capability is zero\n");
 599                         error = EINVAL;
 600                         goto done;
 601                 }
 602         } else {
 603                 link_mode = link_mode & eth_proto_cap;
 604                 if (link_mode == 0) {
 605                         if_printf(dev, "Not supported link mode requested\n");
 606                         error = EINVAL;
 607                         goto done;
 608                 }
 609         }
 610         if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
 611                 /* check if PFC is enabled */
 612                 if (priv->params.rx_priority_flow_control ||
 613                     priv->params.tx_priority_flow_control) {
 614                         if_printf(dev, "PFC must be disabled before enabling global pauseframes.\n");
 615                         error = EINVAL;
 616                         goto done;
 617                 }
 618         }
 619         /* update pauseframe control bits */
 620         priv->params.rx_pauseframe_control =
 621             (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
 622         priv->params.tx_pauseframe_control =
 623             (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
 624
 625         /* check if device is opened */
 626         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
 627
 628         /* reconfigure the hardware */
 629         mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
 630         mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN, ext);
 631         error = -mlx5e_set_port_pause_and_pfc(priv);
 632         if (was_opened)
 633                 mlx5_set_port_status(mdev, MLX5_PORT_UP);
 634
 635 done:
 636         if (!locked)
 637                 PRIV_UNLOCK(priv);
 638         return (error);
 639 }
 640
 641 static void
 642 mlx5e_update_carrier_work(struct work_struct *work)
 643 {
 644         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 645             update_carrier_work);
 646
 647         PRIV_LOCK(priv);
 648         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 649                 mlx5e_update_carrier(priv);
 650         PRIV_UNLOCK(priv);
 651 }
 652
 653 #define MLX5E_PCIE_PERF_GET_64(a,b,c,d,e,f)    \
 654         s_debug->c = MLX5_GET64(mpcnt_reg, out, counter_set.f.c);
 655
 656 #define MLX5E_PCIE_PERF_GET_32(a,b,c,d,e,f)    \
 657         s_debug->c = MLX5_GET(mpcnt_reg, out, counter_set.f.c);
 658
 659 static void
 660 mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
 661 {
 662         struct mlx5_core_dev *mdev = priv->mdev;
 663         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 664         const unsigned sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
 665         void *out;
 666         void *in;
 667         int err;
 668
 669         /* allocate firmware request structures */
 670         in = mlx5_vzalloc(sz);
 671         out = mlx5_vzalloc(sz);
 672         if (in == NULL || out == NULL)
 673                 goto free_out;
 674
 675         MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
 676         err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
 677         if (err != 0)
 678                 goto free_out;
 679
 680         MLX5E_PCIE_PERFORMANCE_COUNTERS_64(MLX5E_PCIE_PERF_GET_64)
 681         MLX5E_PCIE_PERFORMANCE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
 682
 683         MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP);
 684         err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
 685         if (err != 0)
 686                 goto free_out;
 687
 688         MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
 689
 690         MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_LANE_COUNTERS_GROUP);
 691         err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
 692         if (err != 0)
 693                 goto free_out;
 694
 695         MLX5E_PCIE_LANE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
 696
 697 free_out:
 698         /* free firmware request structures */
 699         kvfree(in);
 700         kvfree(out);
 701 }
 702
 703 /*
 704  * This function reads the physical port counters from the firmware
 705  * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
 706  * macros. The output is converted from big-endian 64-bit values into
 707  * host endian ones and stored in the "priv->stats.pport" structure.
 708  */
 709 static void
 710 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 711 {
 712         struct mlx5_core_dev *mdev = priv->mdev;
 713         struct mlx5e_pport_stats *s = &priv->stats.pport;
 714         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 715         u32 *in;
 716         u32 *out;
 717         const u64 *ptr;
 718         unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 719         unsigned x;
 720         unsigned y;
 721         unsigned z;
 722
 723         /* allocate firmware request structures */
 724         in = mlx5_vzalloc(sz);
 725         out = mlx5_vzalloc(sz);
 726         if (in == NULL || out == NULL)
 727                 goto free_out;
 728
 729         /*
 730          * Get pointer to the 64-bit counter set which is located at a
 731          * fixed offset in the output firmware request structure:
 732          */
 733         ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
 734
 735         MLX5_SET(ppcnt_reg, in, local_port, 1);
 736
 737         /* read IEEE802_3 counter group using predefined counter layout */
 738         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 739         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 740         for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM;
 741              x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
 742                 s->arg[y] = be64toh(ptr[x]);
 743
 744         /* read RFC2819 counter group using predefined counter layout */
 745         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 746         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 747         for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
 748                 s->arg[y] = be64toh(ptr[x]);
 749
 750         for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
 751             MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
 752                 s_debug->arg[y] = be64toh(ptr[x]);
 753
 754         /* read RFC2863 counter group using predefined counter layout */
 755         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 756         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 757         for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
 758                 s_debug->arg[y] = be64toh(ptr[x]);
 759
 760         /* read physical layer stats counter group using predefined counter layout */
 761         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 762         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 763         for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
 764                 s_debug->arg[y] = be64toh(ptr[x]);
 765
 766         /* read Extended Ethernet counter group using predefined counter layout */
 767         MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
 768         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 769         for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++)
 770                 s_debug->arg[y] = be64toh(ptr[x]);
 771
 772         /* read Extended Statistical Group */
 773         if (MLX5_CAP_GEN(mdev, pcam_reg) &&
 774             MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) &&
 775             MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) {
 776                 /* read Extended Statistical counter group using predefined counter layout */
 777                 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
 778                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 779
 780                 for (x = 0; x != MLX5E_PPORT_STATISTICAL_DEBUG_NUM; x++, y++)
 781                         s_debug->arg[y] = be64toh(ptr[x]);
 782         }
 783
 784         /* read PCIE counters */
 785         mlx5e_update_pcie_counters(priv);
 786
 787         /* read per-priority counters */
 788         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 789
 790         /* iterate all the priorities */
 791         for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) {
 792                 MLX5_SET(ppcnt_reg, in, prio_tc, z);
 793                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 794
 795                 /* read per priority stats counter group using predefined counter layout */
 796                 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM /
 797                     MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++)
 798                         s->arg[y] = be64toh(ptr[x]);
 799         }
 800
 801 free_out:
 802         /* free firmware request structures */
 803         kvfree(in);
 804         kvfree(out);
 805 }
 806
 807 static void
 808 mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv)
 809 {
 810         u32 out[MLX5_ST_SZ_DW(query_vnic_env_out)] = {};
 811         u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {};
 812
 813         if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
 814                 return;
 815
 816         MLX5_SET(query_vnic_env_in, in, opcode,
 817             MLX5_CMD_OP_QUERY_VNIC_ENV);
 818         MLX5_SET(query_vnic_env_in, in, op_mod, 0);
 819         MLX5_SET(query_vnic_env_in, in, other_vport, 0);
 820
 821         if (mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out)) != 0)
 822                 return;
 823
 824         priv->stats.vport.rx_steer_missed_packets =
 825             MLX5_GET64(query_vnic_env_out, out,
 826             vport_env.nic_receive_steering_discard);
 827 }
 828
 829 /*
 830  * This function is called regularly to collect all statistics
 831  * counters from the firmware. The values can be viewed through the
 832  * sysctl interface. Execution is serialized using the priv's global
 833  * configuration lock.
 834  */
 835 static void
 836 mlx5e_update_stats_locked(struct mlx5e_priv *priv)
 837 {
 838         struct mlx5_core_dev *mdev = priv->mdev;
 839         struct mlx5e_vport_stats *s = &priv->stats.vport;
 840         struct mlx5e_sq_stats *sq_stats;
 841         struct buf_ring *sq_br;
 842 #if (__FreeBSD_version < 1100000)
 843         struct ifnet *ifp = priv->ifp;
 844 #endif
 845
 846         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 847         u32 *out;
 848         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 849         u64 tso_packets = 0;
 850         u64 tso_bytes = 0;
 851         u64 tx_queue_dropped = 0;
 852         u64 tx_defragged = 0;
 853         u64 tx_offload_none = 0;
 854         u64 lro_packets = 0;
 855         u64 lro_bytes = 0;
 856         u64 sw_lro_queued = 0;
 857         u64 sw_lro_flushed = 0;
 858         u64 rx_csum_none = 0;
 859         u64 rx_wqe_err = 0;
 860         u64 rx_packets = 0;
 861         u64 rx_bytes = 0;
 862         u32 rx_out_of_buffer = 0;
 863         int i;
 864         int j;
 865
 866         out = mlx5_vzalloc(outlen);
 867         if (out == NULL)
 868                 goto free_out;
 869
 870         /* Collect firts the SW counters and then HW for consistency */
 871         for (i = 0; i < priv->params.num_channels; i++) {
 872                 struct mlx5e_channel *pch = priv->channel + i;
 873                 struct mlx5e_rq *rq = &pch->rq;
 874                 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats;
 875
 876                 /* collect stats from LRO */
 877                 rq_stats->sw_lro_queued = rq->lro.lro_queued;
 878                 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
 879                 sw_lro_queued += rq_stats->sw_lro_queued;
 880                 sw_lro_flushed += rq_stats->sw_lro_flushed;
 881                 lro_packets += rq_stats->lro_packets;
 882                 lro_bytes += rq_stats->lro_bytes;
 883                 rx_csum_none += rq_stats->csum_none;
 884                 rx_wqe_err += rq_stats->wqe_err;
 885                 rx_packets += rq_stats->packets;
 886                 rx_bytes += rq_stats->bytes;
 887
 888                 for (j = 0; j < priv->num_tc; j++) {
 889                         sq_stats = &pch->sq[j].stats;
 890                         sq_br = pch->sq[j].br;
 891
 892                         tso_packets += sq_stats->tso_packets;
 893                         tso_bytes += sq_stats->tso_bytes;
 894                         tx_queue_dropped += sq_stats->dropped;
 895                         if (sq_br != NULL)
 896                                 tx_queue_dropped += sq_br->br_drops;
 897                         tx_defragged += sq_stats->defragged;
 898                         tx_offload_none += sq_stats->csum_offload_none;
 899                 }
 900         }
 901
 902         /* update counters */
 903         s->tso_packets = tso_packets;
 904         s->tso_bytes = tso_bytes;
 905         s->tx_queue_dropped = tx_queue_dropped;
 906         s->tx_defragged = tx_defragged;
 907         s->lro_packets = lro_packets;
 908         s->lro_bytes = lro_bytes;
 909         s->sw_lro_queued = sw_lro_queued;
 910         s->sw_lro_flushed = sw_lro_flushed;
 911         s->rx_csum_none = rx_csum_none;
 912         s->rx_wqe_err = rx_wqe_err;
 913         s->rx_packets = rx_packets;
 914         s->rx_bytes = rx_bytes;
 915
 916         mlx5e_grp_vnic_env_update_stats(priv);
 917
 918         /* HW counters */
 919         memset(in, 0, sizeof(in));
 920
 921         MLX5_SET(query_vport_counter_in, in, opcode,
 922             MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 923         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 924         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 925
 926         memset(out, 0, outlen);
 927
 928         /* get number of out-of-buffer drops first */
 929         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 &&
 930             mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
 931             &rx_out_of_buffer) == 0) {
 932                 s->rx_out_of_buffer = rx_out_of_buffer;
 933         }
 934
 935         /* get port statistics */
 936         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen) == 0) {
 937 #define MLX5_GET_CTR(out, x) \
 938         MLX5_GET64(query_vport_counter_out, out, x)
 939
 940                 s->rx_error_packets =
 941                     MLX5_GET_CTR(out, received_errors.packets);
 942                 s->rx_error_bytes =
 943                     MLX5_GET_CTR(out, received_errors.octets);
 944                 s->tx_error_packets =
 945                     MLX5_GET_CTR(out, transmit_errors.packets);
 946                 s->tx_error_bytes =
 947                     MLX5_GET_CTR(out, transmit_errors.octets);
 948
 949                 s->rx_unicast_packets =
 950                     MLX5_GET_CTR(out, received_eth_unicast.packets);
 951                 s->rx_unicast_bytes =
 952                     MLX5_GET_CTR(out, received_eth_unicast.octets);
 953                 s->tx_unicast_packets =
 954                     MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 955                 s->tx_unicast_bytes =
 956                     MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 957
 958                 s->rx_multicast_packets =
 959                     MLX5_GET_CTR(out, received_eth_multicast.packets);
 960                 s->rx_multicast_bytes =
 961                     MLX5_GET_CTR(out, received_eth_multicast.octets);
 962                 s->tx_multicast_packets =
 963                     MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 964                 s->tx_multicast_bytes =
 965                     MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 966
 967                 s->rx_broadcast_packets =
 968                     MLX5_GET_CTR(out, received_eth_broadcast.packets);
 969                 s->rx_broadcast_bytes =
 970                     MLX5_GET_CTR(out, received_eth_broadcast.octets);
 971                 s->tx_broadcast_packets =
 972                     MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 973                 s->tx_broadcast_bytes =
 974                     MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 975
 976                 s->tx_packets = s->tx_unicast_packets +
 977                     s->tx_multicast_packets + s->tx_broadcast_packets;
 978                 s->tx_bytes = s->tx_unicast_bytes + s->tx_multicast_bytes +
 979                     s->tx_broadcast_bytes;
 980
 981                 /* Update calculated offload counters */
 982                 s->tx_csum_offload = s->tx_packets - tx_offload_none;
 983                 s->rx_csum_good = s->rx_packets - s->rx_csum_none;
 984         }
 985
 986         /* Get physical port counters */
 987         mlx5e_update_pport_counters(priv);
 988
 989         s->tx_jumbo_packets =
 990             priv->stats.port_stats_debug.tx_stat_p1519to2047octets +
 991             priv->stats.port_stats_debug.tx_stat_p2048to4095octets +
 992             priv->stats.port_stats_debug.tx_stat_p4096to8191octets +
 993             priv->stats.port_stats_debug.tx_stat_p8192to10239octets;
 994
 995 #if (__FreeBSD_version < 1100000)
 996         /* no get_counters interface in fbsd 10 */
 997         ifp->if_ipackets = s->rx_packets;
 998         ifp->if_ierrors = priv->stats.pport.in_range_len_errors +
 999             priv->stats.pport.out_of_range_len +
1000             priv->stats.pport.too_long_errors +
1001             priv->stats.pport.check_seq_err +
1002             priv->stats.pport.alignment_err;
1003         ifp->if_iqdrops = s->rx_out_of_buffer;
1004         ifp->if_opackets = s->tx_packets;
1005         ifp->if_oerrors = priv->stats.port_stats_debug.out_discards;
1006         ifp->if_snd.ifq_drops = s->tx_queue_dropped;
1007         ifp->if_ibytes = s->rx_bytes;
1008         ifp->if_obytes = s->tx_bytes;
1009         ifp->if_collisions =
1010             priv->stats.pport.collisions;
1011 #endif
1012
1013 free_out:
1014         kvfree(out);
1015
1016         /* Update diagnostics, if any */
1017         if (priv->params_ethtool.diag_pci_enable ||
1018             priv->params_ethtool.diag_general_enable) {
1019                 int error = mlx5_core_get_diagnostics_full(mdev,
1020                     priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL,
1021                     priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL);
1022                 if (error != 0)
1023                         if_printf(priv->ifp, "Failed reading diagnostics: %d\n", error);
1024         }
1025 }
1026
1027 static void
1028 mlx5e_update_stats_work(struct work_struct *work)
1029 {
1030         struct mlx5e_priv *priv;
1031
1032         priv  = container_of(work, struct mlx5e_priv, update_stats_work);
1033         PRIV_LOCK(priv);
1034         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
1035                 mlx5e_update_stats_locked(priv);
1036         PRIV_UNLOCK(priv);
1037 }
1038
1039 static void
1040 mlx5e_update_stats(void *arg)
1041 {
1042         struct mlx5e_priv *priv = arg;
1043
1044         queue_work(priv->wq, &priv->update_stats_work);
1045
1046         callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
1047 }
1048
1049 static void
1050 mlx5e_async_event_sub(struct mlx5e_priv *priv,
1051     enum mlx5_dev_event event)
1052 {
1053         switch (event) {
1054         case MLX5_DEV_EVENT_PORT_UP:
1055         case MLX5_DEV_EVENT_PORT_DOWN:
1056                 queue_work(priv->wq, &priv->update_carrier_work);
1057                 break;
1058
1059         default:
1060                 break;
1061         }
1062 }
1063
1064 static void
1065 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
1066     enum mlx5_dev_event event, unsigned long param)
1067 {
1068         struct mlx5e_priv *priv = vpriv;
1069
1070         mtx_lock(&priv->async_events_mtx);
1071         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
1072                 mlx5e_async_event_sub(priv, event);
1073         mtx_unlock(&priv->async_events_mtx);
1074 }
1075
1076 static void
1077 mlx5e_enable_async_events(struct mlx5e_priv *priv)
1078 {
1079         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
1080 }
1081
1082 static void
1083 mlx5e_disable_async_events(struct mlx5e_priv *priv)
1084 {
1085         mtx_lock(&priv->async_events_mtx);
1086         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
1087         mtx_unlock(&priv->async_events_mtx);
1088 }
1089
1090 static void mlx5e_calibration_callout(void *arg);
1091 static int mlx5e_calibration_duration = 20;
1092 static int mlx5e_fast_calibration = 1;
1093 static int mlx5e_normal_calibration = 30;
1094
1095 static SYSCTL_NODE(_hw_mlx5, OID_AUTO, calibr, CTLFLAG_RW, 0,
1096     "MLX5 timestamp calibration parameteres");
1097
1098 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, duration, CTLFLAG_RWTUN,
1099     &mlx5e_calibration_duration, 0,
1100     "Duration of initial calibration");
1101 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, fast, CTLFLAG_RWTUN,
1102     &mlx5e_fast_calibration, 0,
1103     "Recalibration interval during initial calibration");
1104 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, normal, CTLFLAG_RWTUN,
1105     &mlx5e_normal_calibration, 0,
1106     "Recalibration interval during normal operations");
1107
1108 /*
1109  * Ignites the calibration process.
1110  */
1111 static void
1112 mlx5e_reset_calibration_callout(struct mlx5e_priv *priv)
1113 {
1114
1115         if (priv->clbr_done == 0)
1116                 mlx5e_calibration_callout(priv);
1117         else
1118                 callout_reset_curcpu(&priv->tstmp_clbr, (priv->clbr_done <
1119                     mlx5e_calibration_duration ? mlx5e_fast_calibration :
1120                     mlx5e_normal_calibration) * hz, mlx5e_calibration_callout,
1121                     priv);
1122 }
1123
1124 static uint64_t
1125 mlx5e_timespec2usec(const struct timespec *ts)
1126 {
1127
1128         return ((uint64_t)ts->tv_sec * 1000000000 + ts->tv_nsec);
1129 }
1130
1131 static uint64_t
1132 mlx5e_hw_clock(struct mlx5e_priv *priv)
1133 {
1134         struct mlx5_init_seg *iseg;
1135         uint32_t hw_h, hw_h1, hw_l;
1136
1137         iseg = priv->mdev->iseg;
1138         do {
1139                 hw_h = ioread32be(&iseg->internal_timer_h);
1140                 hw_l = ioread32be(&iseg->internal_timer_l);
1141                 hw_h1 = ioread32be(&iseg->internal_timer_h);
1142         } while (hw_h1 != hw_h);
1143         return (((uint64_t)hw_h << 32) | hw_l);
1144 }
1145
1146 /*
1147  * The calibration callout, it runs either in the context of the
1148  * thread which enables calibration, or in callout.  It takes the
1149  * snapshot of system and adapter clocks, then advances the pointers to
1150  * the calibration point to allow rx path to read the consistent data
1151  * lockless.
1152  */
1153 static void
1154 mlx5e_calibration_callout(void *arg)
1155 {
1156         struct mlx5e_priv *priv;
1157         struct mlx5e_clbr_point *next, *curr;
1158         struct timespec ts;
1159         int clbr_curr_next;
1160
1161         priv = arg;
1162         curr = &priv->clbr_points[priv->clbr_curr];
1163         clbr_curr_next = priv->clbr_curr + 1;
1164         if (clbr_curr_next >= nitems(priv->clbr_points))
1165                 clbr_curr_next = 0;
1166         next = &priv->clbr_points[clbr_curr_next];
1167
1168         next->base_prev = curr->base_curr;
1169         next->clbr_hw_prev = curr->clbr_hw_curr;
1170
1171         next->clbr_hw_curr = mlx5e_hw_clock(priv);
1172         if (((next->clbr_hw_curr - curr->clbr_hw_curr) >> MLX5E_TSTMP_PREC) ==
1173             0) {
1174                 if (priv->clbr_done != 0) {
1175                         if_printf(priv->ifp, "HW failed tstmp frozen %#jx %#jx,"
1176                             "disabling\n",
1177                              next->clbr_hw_curr, curr->clbr_hw_prev);
1178                         priv->clbr_done = 0;
1179                 }
1180                 atomic_store_rel_int(&curr->clbr_gen, 0);
1181                 return;
1182         }
1183
1184         nanouptime(&ts);
1185         next->base_curr = mlx5e_timespec2usec(&ts);
1186
1187         curr->clbr_gen = 0;
1188         atomic_thread_fence_rel();
1189         priv->clbr_curr = clbr_curr_next;
1190         atomic_store_rel_int(&next->clbr_gen, ++(priv->clbr_gen));
1191
1192         if (priv->clbr_done < mlx5e_calibration_duration)
1193                 priv->clbr_done++;
1194         mlx5e_reset_calibration_callout(priv);
1195 }
1196
1197 static const char *mlx5e_rq_stats_desc[] = {
1198         MLX5E_RQ_STATS(MLX5E_STATS_DESC)
1199 };
1200
1201 static int
1202 mlx5e_create_rq(struct mlx5e_channel *c,
1203     struct mlx5e_rq_param *param,
1204     struct mlx5e_rq *rq)
1205 {
1206         struct mlx5e_priv *priv = c->priv;
1207         struct mlx5_core_dev *mdev = priv->mdev;
1208         char buffer[16];
1209         void *rqc = param->rqc;
1210         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1211         int wq_sz;
1212         int err;
1213         int i;
1214         u32 nsegs, wqe_sz;
1215
1216         err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
1217         if (err != 0)
1218                 goto done;
1219
1220         /* Create DMA descriptor TAG */
1221         if ((err = -bus_dma_tag_create(
1222             bus_get_dma_tag(mdev->pdev->dev.bsddev),
1223             1,                          /* any alignment */
1224             0,                          /* no boundary */
1225             BUS_SPACE_MAXADDR,          /* lowaddr */
1226             BUS_SPACE_MAXADDR,          /* highaddr */
1227             NULL, NULL,                 /* filter, filterarg */
1228             nsegs * MLX5E_MAX_RX_BYTES, /* maxsize */
1229             nsegs,                      /* nsegments */
1230             nsegs * MLX5E_MAX_RX_BYTES, /* maxsegsize */
1231             0,                          /* flags */
1232             NULL, NULL,                 /* lockfunc, lockfuncarg */
1233             &rq->dma_tag)))
1234                 goto done;
1235
1236         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1237             &rq->wq_ctrl);
1238         if (err)
1239                 goto err_free_dma_tag;
1240
1241         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
1242
1243         err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs);
1244         if (err != 0)
1245                 goto err_rq_wq_destroy;
1246
1247         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
1248
1249         err = -tcp_lro_init_args(&rq->lro, c->tag.m_snd_tag.ifp, TCP_LRO_ENTRIES, wq_sz);
1250         if (err)
1251                 goto err_rq_wq_destroy;
1252
1253         rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1254         for (i = 0; i != wq_sz; i++) {
1255                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
1256 #if (MLX5E_MAX_RX_SEGS == 1)
1257                 uint32_t byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
1258 #else
1259                 int j;
1260 #endif
1261
1262                 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
1263                 if (err != 0) {
1264                         while (i--)
1265                                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
1266                         goto err_rq_mbuf_free;
1267                 }
1268
1269                 /* set value for constant fields */
1270 #if (MLX5E_MAX_RX_SEGS == 1)
1271                 wqe->data[0].lkey = c->mkey_be;
1272                 wqe->data[0].byte_count = cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
1273 #else
1274                 for (j = 0; j < rq->nsegs; j++)
1275                         wqe->data[j].lkey = c->mkey_be;
1276 #endif
1277         }
1278
1279         INIT_WORK(&rq->dim.work, mlx5e_dim_work);
1280         if (priv->params.rx_cq_moderation_mode < 2) {
1281                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
1282         } else {
1283                 void *cqc = container_of(param,
1284                     struct mlx5e_channel_param, rq)->rx_cq.cqc;
1285
1286                 switch (MLX5_GET(cqc, cqc, cq_period_mode)) {
1287                 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
1288                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
1289                         break;
1290                 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
1291                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
1292                         break;
1293                 default:
1294                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
1295                         break;
1296                 }
1297         }
1298
1299         rq->ifp = c->tag.m_snd_tag.ifp;
1300         rq->channel = c;
1301         rq->ix = c->ix;
1302
1303         snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
1304         mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1305             buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
1306             rq->stats.arg);
1307         return (0);
1308
1309 err_rq_mbuf_free:
1310         free(rq->mbuf, M_MLX5EN);
1311         tcp_lro_free(&rq->lro);
1312 err_rq_wq_destroy:
1313         mlx5_wq_destroy(&rq->wq_ctrl);
1314 err_free_dma_tag:
1315         bus_dma_tag_destroy(rq->dma_tag);
1316 done:
1317         return (err);
1318 }
1319
1320 static void
1321 mlx5e_destroy_rq(struct mlx5e_rq *rq)
1322 {
1323         int wq_sz;
1324         int i;
1325
1326         /* destroy all sysctl nodes */
1327         sysctl_ctx_free(&rq->stats.ctx);
1328
1329         /* free leftover LRO packets, if any */
1330         tcp_lro_free(&rq->lro);
1331
1332         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
1333         for (i = 0; i != wq_sz; i++) {
1334                 if (rq->mbuf[i].mbuf != NULL) {
1335                         bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map);
1336                         m_freem(rq->mbuf[i].mbuf);
1337                 }
1338                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
1339         }
1340         free(rq->mbuf, M_MLX5EN);
1341         mlx5_wq_destroy(&rq->wq_ctrl);
1342 }
1343
1344 static int
1345 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
1346 {
1347         struct mlx5e_channel *c = rq->channel;
1348         struct mlx5e_priv *priv = c->priv;
1349         struct mlx5_core_dev *mdev = priv->mdev;
1350
1351         void *in;
1352         void *rqc;
1353         void *wq;
1354         int inlen;
1355         int err;
1356
1357         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
1358             sizeof(u64) * rq->wq_ctrl.buf.npages;
1359         in = mlx5_vzalloc(inlen);
1360         if (in == NULL)
1361                 return (-ENOMEM);
1362
1363         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1364         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1365
1366         memcpy(rqc, param->rqc, sizeof(param->rqc));
1367
1368         MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
1369         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1370         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1371         if (priv->counter_set_id >= 0)
1372                 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
1373         MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
1374             PAGE_SHIFT);
1375         MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
1376
1377         mlx5_fill_page_array(&rq->wq_ctrl.buf,
1378             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1379
1380         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
1381
1382         kvfree(in);
1383
1384         return (err);
1385 }
1386
1387 static int
1388 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
1389 {
1390         struct mlx5e_channel *c = rq->channel;
1391         struct mlx5e_priv *priv = c->priv;
1392         struct mlx5_core_dev *mdev = priv->mdev;
1393
1394         void *in;
1395         void *rqc;
1396         int inlen;
1397         int err;
1398
1399         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1400         in = mlx5_vzalloc(inlen);
1401         if (in == NULL)
1402                 return (-ENOMEM);
1403
1404         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1405
1406         MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
1407         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
1408         MLX5_SET(rqc, rqc, state, next_state);
1409
1410         err = mlx5_core_modify_rq(mdev, in, inlen);
1411
1412         kvfree(in);
1413
1414         return (err);
1415 }
1416
1417 static void
1418 mlx5e_disable_rq(struct mlx5e_rq *rq)
1419 {
1420         struct mlx5e_channel *c = rq->channel;
1421         struct mlx5e_priv *priv = c->priv;
1422         struct mlx5_core_dev *mdev = priv->mdev;
1423
1424         mlx5_core_destroy_rq(mdev, rq->rqn);
1425 }
1426
1427 static int
1428 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
1429 {
1430         struct mlx5e_channel *c = rq->channel;
1431         struct mlx5e_priv *priv = c->priv;
1432         struct mlx5_wq_ll *wq = &rq->wq;
1433         int i;
1434
1435         for (i = 0; i < 1000; i++) {
1436                 if (wq->cur_sz >= priv->params.min_rx_wqes)
1437                         return (0);
1438
1439                 msleep(4);
1440         }
1441         return (-ETIMEDOUT);
1442 }
1443
1444 static int
1445 mlx5e_open_rq(struct mlx5e_channel *c,
1446     struct mlx5e_rq_param *param,
1447     struct mlx5e_rq *rq)
1448 {
1449         int err;
1450
1451         err = mlx5e_create_rq(c, param, rq);
1452         if (err)
1453                 return (err);
1454
1455         err = mlx5e_enable_rq(rq, param);
1456         if (err)
1457                 goto err_destroy_rq;
1458
1459         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1460         if (err)
1461                 goto err_disable_rq;
1462
1463         c->rq.enabled = 1;
1464
1465         return (0);
1466
1467 err_disable_rq:
1468         mlx5e_disable_rq(rq);
1469 err_destroy_rq:
1470         mlx5e_destroy_rq(rq);
1471
1472         return (err);
1473 }
1474
1475 static void
1476 mlx5e_close_rq(struct mlx5e_rq *rq)
1477 {
1478         mtx_lock(&rq->mtx);
1479         rq->enabled = 0;
1480         callout_stop(&rq->watchdog);
1481         mtx_unlock(&rq->mtx);
1482
1483         callout_drain(&rq->watchdog);
1484
1485         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
1486 }
1487
1488 static void
1489 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
1490 {
1491
1492         mlx5e_disable_rq(rq);
1493         mlx5e_close_cq(&rq->cq);
1494         cancel_work_sync(&rq->dim.work);
1495         mlx5e_destroy_rq(rq);
1496 }
1497
1498 void
1499 mlx5e_free_sq_db(struct mlx5e_sq *sq)
1500 {
1501         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1502         int x;
1503
1504         for (x = 0; x != wq_sz; x++) {
1505                 if (sq->mbuf[x].mbuf != NULL) {
1506                         bus_dmamap_unload(sq->dma_tag, sq->mbuf[x].dma_map);
1507                         m_freem(sq->mbuf[x].mbuf);
1508                 }
1509                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1510         }
1511         free(sq->mbuf, M_MLX5EN);
1512 }
1513
1514 int
1515 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
1516 {
1517         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1518         int err;
1519         int x;
1520
1521         sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1522
1523         /* Create DMA descriptor MAPs */
1524         for (x = 0; x != wq_sz; x++) {
1525                 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
1526                 if (err != 0) {
1527                         while (x--)
1528                                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1529                         free(sq->mbuf, M_MLX5EN);
1530                         return (err);
1531                 }
1532         }
1533         return (0);
1534 }
1535
1536 static const char *mlx5e_sq_stats_desc[] = {
1537         MLX5E_SQ_STATS(MLX5E_STATS_DESC)
1538 };
1539
1540 void
1541 mlx5e_update_sq_inline(struct mlx5e_sq *sq)
1542 {
1543         sq->max_inline = sq->priv->params.tx_max_inline;
1544         sq->min_inline_mode = sq->priv->params.tx_min_inline_mode;
1545
1546         /*
1547          * Check if trust state is DSCP or if inline mode is NONE which
1548          * indicates CX-5 or newer hardware.
1549          */
1550         if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP ||
1551             sq->min_inline_mode == MLX5_INLINE_MODE_NONE) {
1552                 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert))
1553                         sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN;
1554                 else
1555                         sq->min_insert_caps = MLX5E_INSERT_NON_VLAN;
1556         } else {
1557                 sq->min_insert_caps = 0;
1558         }
1559 }
1560
1561 static void
1562 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1563 {
1564         int i;
1565
1566         for (i = 0; i != c->num_tc; i++) {
1567                 mtx_lock(&c->sq[i].lock);
1568                 mlx5e_update_sq_inline(&c->sq[i]);
1569                 mtx_unlock(&c->sq[i].lock);
1570         }
1571 }
1572
1573 void
1574 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv)
1575 {
1576         int i;
1577
1578         /* check if channels are closed */
1579         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
1580                 return;
1581
1582         for (i = 0; i < priv->params.num_channels; i++)
1583                 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]);
1584 }
1585
1586 static int
1587 mlx5e_create_sq(struct mlx5e_channel *c,
1588     int tc,
1589     struct mlx5e_sq_param *param,
1590     struct mlx5e_sq *sq)
1591 {
1592         struct mlx5e_priv *priv = c->priv;
1593         struct mlx5_core_dev *mdev = priv->mdev;
1594         char buffer[16];
1595         void *sqc = param->sqc;
1596         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1597         int err;
1598
1599         /* Create DMA descriptor TAG */
1600         if ((err = -bus_dma_tag_create(
1601             bus_get_dma_tag(mdev->pdev->dev.bsddev),
1602             1,                          /* any alignment */
1603             0,                          /* no boundary */
1604             BUS_SPACE_MAXADDR,          /* lowaddr */
1605             BUS_SPACE_MAXADDR,          /* highaddr */
1606             NULL, NULL,                 /* filter, filterarg */
1607             MLX5E_MAX_TX_PAYLOAD_SIZE,  /* maxsize */
1608             MLX5E_MAX_TX_MBUF_FRAGS,    /* nsegments */
1609             MLX5E_MAX_TX_MBUF_SIZE,     /* maxsegsize */
1610             0,                          /* flags */
1611             NULL, NULL,                 /* lockfunc, lockfuncarg */
1612             &sq->dma_tag)))
1613                 goto done;
1614
1615         err = mlx5_alloc_map_uar(mdev, &sq->uar);
1616         if (err)
1617                 goto err_free_dma_tag;
1618
1619         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
1620             &sq->wq_ctrl);
1621         if (err)
1622                 goto err_unmap_free_uar;
1623
1624         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1625         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1626
1627         err = mlx5e_alloc_sq_db(sq);
1628         if (err)
1629                 goto err_sq_wq_destroy;
1630
1631         sq->mkey_be = c->mkey_be;
1632         sq->ifp = priv->ifp;
1633         sq->priv = priv;
1634         sq->tc = tc;
1635
1636         mlx5e_update_sq_inline(sq);
1637
1638         snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1639         mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1640             buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1641             sq->stats.arg);
1642
1643         return (0);
1644
1645 err_sq_wq_destroy:
1646         mlx5_wq_destroy(&sq->wq_ctrl);
1647
1648 err_unmap_free_uar:
1649         mlx5_unmap_free_uar(mdev, &sq->uar);
1650
1651 err_free_dma_tag:
1652         bus_dma_tag_destroy(sq->dma_tag);
1653 done:
1654         return (err);
1655 }
1656
1657 static void
1658 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1659 {
1660         /* destroy all sysctl nodes */
1661         sysctl_ctx_free(&sq->stats.ctx);
1662
1663         mlx5e_free_sq_db(sq);
1664         mlx5_wq_destroy(&sq->wq_ctrl);
1665         mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1666 }
1667
1668 int
1669 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1670     int tis_num)
1671 {
1672         void *in;
1673         void *sqc;
1674         void *wq;
1675         int inlen;
1676         int err;
1677
1678         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1679             sizeof(u64) * sq->wq_ctrl.buf.npages;
1680         in = mlx5_vzalloc(inlen);
1681         if (in == NULL)
1682                 return (-ENOMEM);
1683
1684         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1685         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1686
1687         memcpy(sqc, param->sqc, sizeof(param->sqc));
1688
1689         MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1690         MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1691         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1692         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1693         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1694
1695         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1696         MLX5_SET(wq, wq, uar_page, sq->uar.index);
1697         MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1698             PAGE_SHIFT);
1699         MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1700
1701         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1702             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1703
1704         err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1705
1706         kvfree(in);
1707
1708         return (err);
1709 }
1710
1711 int
1712 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1713 {
1714         void *in;
1715         void *sqc;
1716         int inlen;
1717         int err;
1718
1719         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1720         in = mlx5_vzalloc(inlen);
1721         if (in == NULL)
1722                 return (-ENOMEM);
1723
1724         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1725
1726         MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1727         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1728         MLX5_SET(sqc, sqc, state, next_state);
1729
1730         err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1731
1732         kvfree(in);
1733
1734         return (err);
1735 }
1736
1737 void
1738 mlx5e_disable_sq(struct mlx5e_sq *sq)
1739 {
1740
1741         mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1742 }
1743
1744 static int
1745 mlx5e_open_sq(struct mlx5e_channel *c,
1746     int tc,
1747     struct mlx5e_sq_param *param,
1748     struct mlx5e_sq *sq)
1749 {
1750         int err;
1751
1752         err = mlx5e_create_sq(c, tc, param, sq);
1753         if (err)
1754                 return (err);
1755
1756         err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1757         if (err)
1758                 goto err_destroy_sq;
1759
1760         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1761         if (err)
1762                 goto err_disable_sq;
1763
1764         WRITE_ONCE(sq->running, 1);
1765
1766         return (0);
1767
1768 err_disable_sq:
1769         mlx5e_disable_sq(sq);
1770 err_destroy_sq:
1771         mlx5e_destroy_sq(sq);
1772
1773         return (err);
1774 }
1775
1776 static void
1777 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1778 {
1779         /* fill up remainder with NOPs */
1780         while (sq->cev_counter != 0) {
1781                 while (!mlx5e_sq_has_room_for(sq, 1)) {
1782                         if (can_sleep != 0) {
1783                                 mtx_unlock(&sq->lock);
1784                                 msleep(4);
1785                                 mtx_lock(&sq->lock);
1786                         } else {
1787                                 goto done;
1788                         }
1789                 }
1790                 /* send a single NOP */
1791                 mlx5e_send_nop(sq, 1);
1792                 atomic_thread_fence_rel();
1793         }
1794 done:
1795         /* Check if we need to write the doorbell */
1796         if (likely(sq->doorbell.d64 != 0)) {
1797                 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1798                 sq->doorbell.d64 = 0;
1799         }
1800 }
1801
1802 void
1803 mlx5e_sq_cev_timeout(void *arg)
1804 {
1805         struct mlx5e_sq *sq = arg;
1806
1807         mtx_assert(&sq->lock, MA_OWNED);
1808
1809         /* check next state */
1810         switch (sq->cev_next_state) {
1811         case MLX5E_CEV_STATE_SEND_NOPS:
1812                 /* fill TX ring with NOPs, if any */
1813                 mlx5e_sq_send_nops_locked(sq, 0);
1814
1815                 /* check if completed */
1816                 if (sq->cev_counter == 0) {
1817                         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1818                         return;
1819                 }
1820                 break;
1821         default:
1822                 /* send NOPs on next timeout */
1823                 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1824                 break;
1825         }
1826
1827         /* restart timer */
1828         callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1829 }
1830
1831 void
1832 mlx5e_drain_sq(struct mlx5e_sq *sq)
1833 {
1834         int error;
1835         struct mlx5_core_dev *mdev= sq->priv->mdev;
1836
1837         /*
1838          * Check if already stopped.
1839          *
1840          * NOTE: Serialization of this function is managed by the
1841          * caller ensuring the priv's state lock is locked or in case
1842          * of rate limit support, a single thread manages drain and
1843          * resume of SQs. The "running" variable can therefore safely
1844          * be read without any locks.
1845          */
1846         if (READ_ONCE(sq->running) == 0)
1847                 return;
1848
1849         /* don't put more packets into the SQ */
1850         WRITE_ONCE(sq->running, 0);
1851
1852         /* serialize access to DMA rings */
1853         mtx_lock(&sq->lock);
1854
1855         /* teardown event factor timer, if any */
1856         sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1857         callout_stop(&sq->cev_callout);
1858
1859         /* send dummy NOPs in order to flush the transmit ring */
1860         mlx5e_sq_send_nops_locked(sq, 1);
1861         mtx_unlock(&sq->lock);
1862
1863         /* make sure it is safe to free the callout */
1864         callout_drain(&sq->cev_callout);
1865
1866         /* wait till SQ is empty or link is down */
1867         mtx_lock(&sq->lock);
1868         while (sq->cc != sq->pc &&
1869             (sq->priv->media_status_last & IFM_ACTIVE) != 0 &&
1870             mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1871                 mtx_unlock(&sq->lock);
1872                 msleep(1);
1873                 sq->cq.mcq.comp(&sq->cq.mcq);
1874                 mtx_lock(&sq->lock);
1875         }
1876         mtx_unlock(&sq->lock);
1877
1878         /* error out remaining requests */
1879         error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1880         if (error != 0) {
1881                 if_printf(sq->ifp,
1882                     "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error);
1883         }
1884
1885         /* wait till SQ is empty */
1886         mtx_lock(&sq->lock);
1887         while (sq->cc != sq->pc &&
1888                mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1889                 mtx_unlock(&sq->lock);
1890                 msleep(1);
1891                 sq->cq.mcq.comp(&sq->cq.mcq);
1892                 mtx_lock(&sq->lock);
1893         }
1894         mtx_unlock(&sq->lock);
1895 }
1896
1897 static void
1898 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1899 {
1900
1901         mlx5e_drain_sq(sq);
1902         mlx5e_disable_sq(sq);
1903         mlx5e_destroy_sq(sq);
1904 }
1905
1906 static int
1907 mlx5e_create_cq(struct mlx5e_priv *priv,
1908     struct mlx5e_cq_param *param,
1909     struct mlx5e_cq *cq,
1910     mlx5e_cq_comp_t *comp,
1911     int eq_ix)
1912 {
1913         struct mlx5_core_dev *mdev = priv->mdev;
1914         struct mlx5_core_cq *mcq = &cq->mcq;
1915         int eqn_not_used;
1916         int irqn;
1917         int err;
1918         u32 i;
1919
1920         param->wq.buf_numa_node = 0;
1921         param->wq.db_numa_node = 0;
1922
1923         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1924             &cq->wq_ctrl);
1925         if (err)
1926                 return (err);
1927
1928         mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1929
1930         mcq->cqe_sz = 64;
1931         mcq->set_ci_db = cq->wq_ctrl.db.db;
1932         mcq->arm_db = cq->wq_ctrl.db.db + 1;
1933         *mcq->set_ci_db = 0;
1934         *mcq->arm_db = 0;
1935         mcq->vector = eq_ix;
1936         mcq->comp = comp;
1937         mcq->event = mlx5e_cq_error_event;
1938         mcq->irqn = irqn;
1939         mcq->uar = &priv->cq_uar;
1940
1941         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1942                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1943
1944                 cqe->op_own = 0xf1;
1945         }
1946
1947         cq->priv = priv;
1948
1949         return (0);
1950 }
1951
1952 static void
1953 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1954 {
1955         mlx5_wq_destroy(&cq->wq_ctrl);
1956 }
1957
1958 static int
1959 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1960 {
1961         struct mlx5_core_cq *mcq = &cq->mcq;
1962         void *in;
1963         void *cqc;
1964         int inlen;
1965         int irqn_not_used;
1966         int eqn;
1967         int err;
1968
1969         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1970             sizeof(u64) * cq->wq_ctrl.buf.npages;
1971         in = mlx5_vzalloc(inlen);
1972         if (in == NULL)
1973                 return (-ENOMEM);
1974
1975         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1976
1977         memcpy(cqc, param->cqc, sizeof(param->cqc));
1978
1979         mlx5_fill_page_array(&cq->wq_ctrl.buf,
1980             (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1981
1982         mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
1983
1984         MLX5_SET(cqc, cqc, c_eqn, eqn);
1985         MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1986         MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1987             PAGE_SHIFT);
1988         MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1989
1990         err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
1991
1992         kvfree(in);
1993
1994         if (err)
1995                 return (err);
1996
1997         mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock));
1998
1999         return (0);
2000 }
2001
2002 static void
2003 mlx5e_disable_cq(struct mlx5e_cq *cq)
2004 {
2005
2006         mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
2007 }
2008
2009 int
2010 mlx5e_open_cq(struct mlx5e_priv *priv,
2011     struct mlx5e_cq_param *param,
2012     struct mlx5e_cq *cq,
2013     mlx5e_cq_comp_t *comp,
2014     int eq_ix)
2015 {
2016         int err;
2017
2018         err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
2019         if (err)
2020                 return (err);
2021
2022         err = mlx5e_enable_cq(cq, param, eq_ix);
2023         if (err)
2024                 goto err_destroy_cq;
2025
2026         return (0);
2027
2028 err_destroy_cq:
2029         mlx5e_destroy_cq(cq);
2030
2031         return (err);
2032 }
2033
2034 void
2035 mlx5e_close_cq(struct mlx5e_cq *cq)
2036 {
2037         mlx5e_disable_cq(cq);
2038         mlx5e_destroy_cq(cq);
2039 }
2040
2041 static int
2042 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
2043     struct mlx5e_channel_param *cparam)
2044 {
2045         int err;
2046         int tc;
2047
2048         for (tc = 0; tc < c->num_tc; tc++) {
2049                 /* open completion queue */
2050                 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
2051                     &mlx5e_tx_cq_comp, c->ix);
2052                 if (err)
2053                         goto err_close_tx_cqs;
2054         }
2055         return (0);
2056
2057 err_close_tx_cqs:
2058         for (tc--; tc >= 0; tc--)
2059                 mlx5e_close_cq(&c->sq[tc].cq);
2060
2061         return (err);
2062 }
2063
2064 static void
2065 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
2066 {
2067         int tc;
2068
2069         for (tc = 0; tc < c->num_tc; tc++)
2070                 mlx5e_close_cq(&c->sq[tc].cq);
2071 }
2072
2073 static int
2074 mlx5e_open_sqs(struct mlx5e_channel *c,
2075     struct mlx5e_channel_param *cparam)
2076 {
2077         int err;
2078         int tc;
2079
2080         for (tc = 0; tc < c->num_tc; tc++) {
2081                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
2082                 if (err)
2083                         goto err_close_sqs;
2084         }
2085
2086         return (0);
2087
2088 err_close_sqs:
2089         for (tc--; tc >= 0; tc--)
2090                 mlx5e_close_sq_wait(&c->sq[tc]);
2091
2092         return (err);
2093 }
2094
2095 static void
2096 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
2097 {
2098         int tc;
2099
2100         for (tc = 0; tc < c->num_tc; tc++)
2101                 mlx5e_close_sq_wait(&c->sq[tc]);
2102 }
2103
2104 static void
2105 mlx5e_chan_mtx_init(struct mlx5e_channel *c)
2106 {
2107         int tc;
2108
2109         mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
2110
2111         callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
2112
2113         for (tc = 0; tc < c->num_tc; tc++) {
2114                 struct mlx5e_sq *sq = c->sq + tc;
2115
2116                 mtx_init(&sq->lock, "mlx5tx",
2117                     MTX_NETWORK_LOCK " TX", MTX_DEF);
2118                 mtx_init(&sq->comp_lock, "mlx5comp",
2119                     MTX_NETWORK_LOCK " TX", MTX_DEF);
2120
2121                 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
2122
2123                 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
2124
2125                 /* ensure the TX completion event factor is not zero */
2126                 if (sq->cev_factor == 0)
2127                         sq->cev_factor = 1;
2128         }
2129 }
2130
2131 static void
2132 mlx5e_chan_mtx_destroy(struct mlx5e_channel *c)
2133 {
2134         int tc;
2135
2136         mtx_destroy(&c->rq.mtx);
2137
2138         for (tc = 0; tc < c->num_tc; tc++) {
2139                 mtx_destroy(&c->sq[tc].lock);
2140                 mtx_destroy(&c->sq[tc].comp_lock);
2141         }
2142 }
2143
2144 static int
2145 mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
2146     struct mlx5e_channel_param *cparam,
2147     struct mlx5e_channel *c)
2148 {
2149         int err;
2150
2151         memset(c, 0, sizeof(*c));
2152
2153         c->priv = priv;
2154         c->ix = ix;
2155         /* setup send tag */
2156         c->tag.m_snd_tag.ifp = priv->ifp;
2157         c->tag.type = IF_SND_TAG_TYPE_UNLIMITED;
2158         c->mkey_be = cpu_to_be32(priv->mr.key);
2159         c->num_tc = priv->num_tc;
2160
2161         /* init mutexes */
2162         mlx5e_chan_mtx_init(c);
2163
2164         /* open transmit completion queue */
2165         err = mlx5e_open_tx_cqs(c, cparam);
2166         if (err)
2167                 goto err_free;
2168
2169         /* open receive completion queue */
2170         err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
2171             &mlx5e_rx_cq_comp, c->ix);
2172         if (err)
2173                 goto err_close_tx_cqs;
2174
2175         err = mlx5e_open_sqs(c, cparam);
2176         if (err)
2177                 goto err_close_rx_cq;
2178
2179         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
2180         if (err)
2181                 goto err_close_sqs;
2182
2183         /* poll receive queue initially */
2184         c->rq.cq.mcq.comp(&c->rq.cq.mcq);
2185
2186         return (0);
2187
2188 err_close_sqs:
2189         mlx5e_close_sqs_wait(c);
2190
2191 err_close_rx_cq:
2192         mlx5e_close_cq(&c->rq.cq);
2193
2194 err_close_tx_cqs:
2195         mlx5e_close_tx_cqs(c);
2196
2197 err_free:
2198         /* destroy mutexes */
2199         mlx5e_chan_mtx_destroy(c);
2200         return (err);
2201 }
2202
2203 static void
2204 mlx5e_close_channel(struct mlx5e_channel *c)
2205 {
2206         mlx5e_close_rq(&c->rq);
2207 }
2208
2209 static void
2210 mlx5e_close_channel_wait(struct mlx5e_channel *c)
2211 {
2212         mlx5e_close_rq_wait(&c->rq);
2213         mlx5e_close_sqs_wait(c);
2214         mlx5e_close_tx_cqs(c);
2215         /* destroy mutexes */
2216         mlx5e_chan_mtx_destroy(c);
2217 }
2218
2219 static int
2220 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs)
2221 {
2222         u32 r, n;
2223
2224         r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz :
2225             MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
2226         if (r > MJUM16BYTES)
2227                 return (-ENOMEM);
2228
2229         if (r > MJUM9BYTES)
2230                 r = MJUM16BYTES;
2231         else if (r > MJUMPAGESIZE)
2232                 r = MJUM9BYTES;
2233         else if (r > MCLBYTES)
2234                 r = MJUMPAGESIZE;
2235         else
2236                 r = MCLBYTES;
2237
2238         /*
2239          * n + 1 must be a power of two, because stride size must be.
2240          * Stride size is 16 * (n + 1), as the first segment is
2241          * control.
2242          */
2243         for (n = howmany(r, MLX5E_MAX_RX_BYTES); !powerof2(n + 1); n++)
2244                 ;
2245
2246         *wqe_sz = r;
2247         *nsegs = n;
2248         return (0);
2249 }
2250
2251 static void
2252 mlx5e_build_rq_param(struct mlx5e_priv *priv,
2253     struct mlx5e_rq_param *param)
2254 {
2255         void *rqc = param->rqc;
2256         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2257         u32 wqe_sz, nsegs;
2258
2259         mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
2260         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
2261         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2262         MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) +
2263             nsegs * sizeof(struct mlx5_wqe_data_seg)));
2264         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
2265         MLX5_SET(wq, wq, pd, priv->pdn);
2266
2267         param->wq.buf_numa_node = 0;
2268         param->wq.db_numa_node = 0;
2269         param->wq.linear = 1;
2270 }
2271
2272 static void
2273 mlx5e_build_sq_param(struct mlx5e_priv *priv,
2274     struct mlx5e_sq_param *param)
2275 {
2276         void *sqc = param->sqc;
2277         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2278
2279         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
2280         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2281         MLX5_SET(wq, wq, pd, priv->pdn);
2282
2283         param->wq.buf_numa_node = 0;
2284         param->wq.db_numa_node = 0;
2285         param->wq.linear = 1;
2286 }
2287
2288 static void
2289 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2290     struct mlx5e_cq_param *param)
2291 {
2292         void *cqc = param->cqc;
2293
2294         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
2295 }
2296
2297 static void
2298 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr)
2299 {
2300
2301         *ptr = net_dim_get_profile(mode, MLX5E_DIM_DEFAULT_PROFILE);
2302
2303         /* apply LRO restrictions */
2304         if (priv->params.hw_lro_en &&
2305             ptr->pkts > MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO) {
2306                 ptr->pkts = MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO;
2307         }
2308 }
2309
2310 static void
2311 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2312     struct mlx5e_cq_param *param)
2313 {
2314         struct net_dim_cq_moder curr;
2315         void *cqc = param->cqc;
2316
2317         /*
2318          * We use MLX5_CQE_FORMAT_HASH because the RX hash mini CQE
2319          * format is more beneficial for FreeBSD use case.
2320          *
2321          * Adding support for MLX5_CQE_FORMAT_CSUM will require changes
2322          * in mlx5e_decompress_cqe.
2323          */
2324         if (priv->params.cqe_zipping_en) {
2325                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_HASH);
2326                 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
2327         }
2328
2329         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
2330
2331         switch (priv->params.rx_cq_moderation_mode) {
2332         case 0:
2333                 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
2334                 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
2335                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2336                 break;
2337         case 1:
2338                 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
2339                 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
2340                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2341                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2342                 else
2343                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2344                 break;
2345         case 2:
2346                 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr);
2347                 MLX5_SET(cqc, cqc, cq_period, curr.usec);
2348                 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
2349                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2350                 break;
2351         case 3:
2352                 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr);
2353                 MLX5_SET(cqc, cqc, cq_period, curr.usec);
2354                 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
2355                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2356                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2357                 else
2358                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2359                 break;
2360         default:
2361                 break;
2362         }
2363
2364         mlx5e_dim_build_cq_param(priv, param);
2365
2366         mlx5e_build_common_cq_param(priv, param);
2367 }
2368
2369 static void
2370 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2371     struct mlx5e_cq_param *param)
2372 {
2373         void *cqc = param->cqc;
2374
2375         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
2376         MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
2377         MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
2378
2379         switch (priv->params.tx_cq_moderation_mode) {
2380         case 0:
2381                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2382                 break;
2383         default:
2384                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2385                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2386                 else
2387                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2388                 break;
2389         }
2390
2391         mlx5e_build_common_cq_param(priv, param);
2392 }
2393
2394 static void
2395 mlx5e_build_channel_param(struct mlx5e_priv *priv,
2396     struct mlx5e_channel_param *cparam)
2397 {
2398         memset(cparam, 0, sizeof(*cparam));
2399
2400         mlx5e_build_rq_param(priv, &cparam->rq);
2401         mlx5e_build_sq_param(priv, &cparam->sq);
2402         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
2403         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
2404 }
2405
2406 static int
2407 mlx5e_open_channels(struct mlx5e_priv *priv)
2408 {
2409         struct mlx5e_channel_param cparam;
2410         int err;
2411         int i;
2412         int j;
2413
2414         mlx5e_build_channel_param(priv, &cparam);
2415         for (i = 0; i < priv->params.num_channels; i++) {
2416                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
2417                 if (err)
2418                         goto err_close_channels;
2419         }
2420
2421         for (j = 0; j < priv->params.num_channels; j++) {
2422                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j].rq);
2423                 if (err)
2424                         goto err_close_channels;
2425         }
2426         return (0);
2427
2428 err_close_channels:
2429         while (i--) {
2430                 mlx5e_close_channel(&priv->channel[i]);
2431                 mlx5e_close_channel_wait(&priv->channel[i]);
2432         }
2433         return (err);
2434 }
2435
2436 static void
2437 mlx5e_close_channels(struct mlx5e_priv *priv)
2438 {
2439         int i;
2440
2441         for (i = 0; i < priv->params.num_channels; i++)
2442                 mlx5e_close_channel(&priv->channel[i]);
2443         for (i = 0; i < priv->params.num_channels; i++)
2444                 mlx5e_close_channel_wait(&priv->channel[i]);
2445 }
2446
2447 static int
2448 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
2449 {
2450
2451         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2452                 uint8_t cq_mode;
2453
2454                 switch (priv->params.tx_cq_moderation_mode) {
2455                 case 0:
2456                 case 2:
2457                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2458                         break;
2459                 default:
2460                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2461                         break;
2462                 }
2463
2464                 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq,
2465                     priv->params.tx_cq_moderation_usec,
2466                     priv->params.tx_cq_moderation_pkts,
2467                     cq_mode));
2468         }
2469
2470         return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
2471             priv->params.tx_cq_moderation_usec,
2472             priv->params.tx_cq_moderation_pkts));
2473 }
2474
2475 static int
2476 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
2477 {
2478
2479         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2480                 uint8_t cq_mode;
2481                 uint8_t dim_mode;
2482                 int retval;
2483
2484                 switch (priv->params.rx_cq_moderation_mode) {
2485                 case 0:
2486                 case 2:
2487                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2488                         dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2489                         break;
2490                 default:
2491                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2492                         dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
2493                         break;
2494                 }
2495
2496                 /* tear down dynamic interrupt moderation */
2497                 mtx_lock(&rq->mtx);
2498                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
2499                 mtx_unlock(&rq->mtx);
2500
2501                 /* wait for dynamic interrupt moderation work task, if any */
2502                 cancel_work_sync(&rq->dim.work);
2503
2504                 if (priv->params.rx_cq_moderation_mode >= 2) {
2505                         struct net_dim_cq_moder curr;
2506
2507                         mlx5e_get_default_profile(priv, dim_mode, &curr);
2508
2509                         retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2510                             curr.usec, curr.pkts, cq_mode);
2511
2512                         /* set dynamic interrupt moderation mode and zero defaults */
2513                         mtx_lock(&rq->mtx);
2514                         rq->dim.mode = dim_mode;
2515                         rq->dim.state = 0;
2516                         rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE;
2517                         mtx_unlock(&rq->mtx);
2518                 } else {
2519                         retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2520                             priv->params.rx_cq_moderation_usec,
2521                             priv->params.rx_cq_moderation_pkts,
2522                             cq_mode);
2523                 }
2524                 return (retval);
2525         }
2526
2527         return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
2528             priv->params.rx_cq_moderation_usec,
2529             priv->params.rx_cq_moderation_pkts));
2530 }
2531
2532 static int
2533 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
2534 {
2535         int err;
2536         int i;
2537
2538         err = mlx5e_refresh_rq_params(priv, &c->rq);
2539         if (err)
2540                 goto done;
2541
2542         for (i = 0; i != c->num_tc; i++) {
2543                 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
2544                 if (err)
2545                         goto done;
2546         }
2547 done:
2548         return (err);
2549 }
2550
2551 int
2552 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
2553 {
2554         int i;
2555
2556         /* check if channels are closed */
2557         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2558                 return (EINVAL);
2559
2560         for (i = 0; i < priv->params.num_channels; i++) {
2561                 int err;
2562
2563                 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]);
2564                 if (err)
2565                         return (err);
2566         }
2567         return (0);
2568 }
2569
2570 static int
2571 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
2572 {
2573         struct mlx5_core_dev *mdev = priv->mdev;
2574         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
2575         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2576
2577         memset(in, 0, sizeof(in));
2578
2579         MLX5_SET(tisc, tisc, prio, tc);
2580         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
2581
2582         return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
2583 }
2584
2585 static void
2586 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
2587 {
2588         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2589 }
2590
2591 static int
2592 mlx5e_open_tises(struct mlx5e_priv *priv)
2593 {
2594         int num_tc = priv->num_tc;
2595         int err;
2596         int tc;
2597
2598         for (tc = 0; tc < num_tc; tc++) {
2599                 err = mlx5e_open_tis(priv, tc);
2600                 if (err)
2601                         goto err_close_tises;
2602         }
2603
2604         return (0);
2605
2606 err_close_tises:
2607         for (tc--; tc >= 0; tc--)
2608                 mlx5e_close_tis(priv, tc);
2609
2610         return (err);
2611 }
2612
2613 static void
2614 mlx5e_close_tises(struct mlx5e_priv *priv)
2615 {
2616         int num_tc = priv->num_tc;
2617         int tc;
2618
2619         for (tc = 0; tc < num_tc; tc++)
2620                 mlx5e_close_tis(priv, tc);
2621 }
2622
2623 static int
2624 mlx5e_open_rqt(struct mlx5e_priv *priv)
2625 {
2626         struct mlx5_core_dev *mdev = priv->mdev;
2627         u32 *in;
2628         u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
2629         void *rqtc;
2630         int inlen;
2631         int err;
2632         int sz;
2633         int i;
2634
2635         sz = 1 << priv->params.rx_hash_log_tbl_sz;
2636
2637         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2638         in = mlx5_vzalloc(inlen);
2639         if (in == NULL)
2640                 return (-ENOMEM);
2641         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2642
2643         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2644         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2645
2646         for (i = 0; i < sz; i++) {
2647                 int ix = i;
2648 #ifdef RSS
2649                 ix = rss_get_indirection_to_bucket(ix);
2650 #endif
2651                 /* ensure we don't overflow */
2652                 ix %= priv->params.num_channels;
2653
2654                 /* apply receive side scaling stride, if any */
2655                 ix -= ix % (int)priv->params.channels_rsss;
2656
2657                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn);
2658         }
2659
2660         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
2661
2662         err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
2663         if (!err)
2664                 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
2665
2666         kvfree(in);
2667
2668         return (err);
2669 }
2670
2671 static void
2672 mlx5e_close_rqt(struct mlx5e_priv *priv)
2673 {
2674         u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0};
2675         u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0};
2676
2677         MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
2678         MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
2679
2680         mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out));
2681 }
2682
2683 static void
2684 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
2685 {
2686         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2687         __be32 *hkey;
2688
2689         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2690
2691 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2692
2693 #define MLX5_HASH_IP     (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2694                           MLX5_HASH_FIELD_SEL_DST_IP)
2695
2696 #define MLX5_HASH_ALL    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2697                           MLX5_HASH_FIELD_SEL_DST_IP   |\
2698                           MLX5_HASH_FIELD_SEL_L4_SPORT |\
2699                           MLX5_HASH_FIELD_SEL_L4_DPORT)
2700
2701 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2702                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2703                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2704
2705         if (priv->params.hw_lro_en) {
2706                 MLX5_SET(tirc, tirc, lro_enable_mask,
2707                     MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2708                     MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2709                 MLX5_SET(tirc, tirc, lro_max_msg_sz,
2710                     (priv->params.lro_wqe_sz -
2711                     ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2712                 /* TODO: add the option to choose timer value dynamically */
2713                 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
2714                     MLX5_CAP_ETH(priv->mdev,
2715                     lro_timer_supported_periods[2]));
2716         }
2717
2718         /* setup parameters for hashing TIR type, if any */
2719         switch (tt) {
2720         case MLX5E_TT_ANY:
2721                 MLX5_SET(tirc, tirc, disp_type,
2722                     MLX5_TIRC_DISP_TYPE_DIRECT);
2723                 MLX5_SET(tirc, tirc, inline_rqn,
2724                     priv->channel[0].rq.rqn);
2725                 break;
2726         default:
2727                 MLX5_SET(tirc, tirc, disp_type,
2728                     MLX5_TIRC_DISP_TYPE_INDIRECT);
2729                 MLX5_SET(tirc, tirc, indirect_table,
2730                     priv->rqtn);
2731                 MLX5_SET(tirc, tirc, rx_hash_fn,
2732                     MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
2733                 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
2734 #ifdef RSS
2735                 /*
2736                  * The FreeBSD RSS implementation does currently not
2737                  * support symmetric Toeplitz hashes:
2738                  */
2739                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
2740                 rss_getkey((uint8_t *)hkey);
2741 #else
2742                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2743                 hkey[0] = cpu_to_be32(0xD181C62C);
2744                 hkey[1] = cpu_to_be32(0xF7F4DB5B);
2745                 hkey[2] = cpu_to_be32(0x1983A2FC);
2746                 hkey[3] = cpu_to_be32(0x943E1ADB);
2747                 hkey[4] = cpu_to_be32(0xD9389E6B);
2748                 hkey[5] = cpu_to_be32(0xD1039C2C);
2749                 hkey[6] = cpu_to_be32(0xA74499AD);
2750                 hkey[7] = cpu_to_be32(0x593D56D9);
2751                 hkey[8] = cpu_to_be32(0xF3253C06);
2752                 hkey[9] = cpu_to_be32(0x2ADC1FFC);
2753 #endif
2754                 break;
2755         }
2756
2757         switch (tt) {
2758         case MLX5E_TT_IPV4_TCP:
2759                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2760                     MLX5_L3_PROT_TYPE_IPV4);
2761                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2762                     MLX5_L4_PROT_TYPE_TCP);
2763 #ifdef RSS
2764                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2765                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2766                             MLX5_HASH_IP);
2767                 } else
2768 #endif
2769                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2770                     MLX5_HASH_ALL);
2771                 break;
2772
2773         case MLX5E_TT_IPV6_TCP:
2774                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2775                     MLX5_L3_PROT_TYPE_IPV6);
2776                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2777                     MLX5_L4_PROT_TYPE_TCP);
2778 #ifdef RSS
2779                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2780                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2781                             MLX5_HASH_IP);
2782                 } else
2783 #endif
2784                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2785                     MLX5_HASH_ALL);
2786                 break;
2787
2788         case MLX5E_TT_IPV4_UDP:
2789                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2790                     MLX5_L3_PROT_TYPE_IPV4);
2791                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2792                     MLX5_L4_PROT_TYPE_UDP);
2793 #ifdef RSS
2794                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2795                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2796                             MLX5_HASH_IP);
2797                 } else
2798 #endif
2799                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2800                     MLX5_HASH_ALL);
2801                 break;
2802
2803         case MLX5E_TT_IPV6_UDP:
2804                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2805                     MLX5_L3_PROT_TYPE_IPV6);
2806                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2807                     MLX5_L4_PROT_TYPE_UDP);
2808 #ifdef RSS
2809                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2810                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2811                             MLX5_HASH_IP);
2812                 } else
2813 #endif
2814                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2815                     MLX5_HASH_ALL);
2816                 break;
2817
2818         case MLX5E_TT_IPV4_IPSEC_AH:
2819                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2820                     MLX5_L3_PROT_TYPE_IPV4);
2821                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2822                     MLX5_HASH_IP_IPSEC_SPI);
2823                 break;
2824
2825         case MLX5E_TT_IPV6_IPSEC_AH:
2826                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2827                     MLX5_L3_PROT_TYPE_IPV6);
2828                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2829                     MLX5_HASH_IP_IPSEC_SPI);
2830                 break;
2831
2832         case MLX5E_TT_IPV4_IPSEC_ESP:
2833                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2834                     MLX5_L3_PROT_TYPE_IPV4);
2835                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2836                     MLX5_HASH_IP_IPSEC_SPI);
2837                 break;
2838
2839         case MLX5E_TT_IPV6_IPSEC_ESP:
2840                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2841                     MLX5_L3_PROT_TYPE_IPV6);
2842                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2843                     MLX5_HASH_IP_IPSEC_SPI);
2844                 break;
2845
2846         case MLX5E_TT_IPV4:
2847                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2848                     MLX5_L3_PROT_TYPE_IPV4);
2849                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2850                     MLX5_HASH_IP);
2851                 break;
2852
2853         case MLX5E_TT_IPV6:
2854                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2855                     MLX5_L3_PROT_TYPE_IPV6);
2856                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2857                     MLX5_HASH_IP);
2858                 break;
2859
2860         default:
2861                 break;
2862         }
2863 }
2864
2865 static int
2866 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2867 {
2868         struct mlx5_core_dev *mdev = priv->mdev;
2869         u32 *in;
2870         void *tirc;
2871         int inlen;
2872         int err;
2873
2874         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2875         in = mlx5_vzalloc(inlen);
2876         if (in == NULL)
2877                 return (-ENOMEM);
2878         tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2879
2880         mlx5e_build_tir_ctx(priv, tirc, tt);
2881
2882         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2883
2884         kvfree(in);
2885
2886         return (err);
2887 }
2888
2889 static void
2890 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2891 {
2892         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2893 }
2894
2895 static int
2896 mlx5e_open_tirs(struct mlx5e_priv *priv)
2897 {
2898         int err;
2899         int i;
2900
2901         for (i = 0; i < MLX5E_NUM_TT; i++) {
2902                 err = mlx5e_open_tir(priv, i);
2903                 if (err)
2904                         goto err_close_tirs;
2905         }
2906
2907         return (0);
2908
2909 err_close_tirs:
2910         for (i--; i >= 0; i--)
2911                 mlx5e_close_tir(priv, i);
2912
2913         return (err);
2914 }
2915
2916 static void
2917 mlx5e_close_tirs(struct mlx5e_priv *priv)
2918 {
2919         int i;
2920
2921         for (i = 0; i < MLX5E_NUM_TT; i++)
2922                 mlx5e_close_tir(priv, i);
2923 }
2924
2925 /*
2926  * SW MTU does not include headers,
2927  * HW MTU includes all headers and checksums.
2928  */
2929 static int
2930 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2931 {
2932         struct mlx5e_priv *priv = ifp->if_softc;
2933         struct mlx5_core_dev *mdev = priv->mdev;
2934         int hw_mtu;
2935         int err;
2936
2937         hw_mtu = MLX5E_SW2HW_MTU(sw_mtu);
2938
2939         err = mlx5_set_port_mtu(mdev, hw_mtu);
2940         if (err) {
2941                 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n",
2942                     __func__, sw_mtu, err);
2943                 return (err);
2944         }
2945
2946         /* Update vport context MTU */
2947         err = mlx5_set_vport_mtu(mdev, hw_mtu);
2948         if (err) {
2949                 if_printf(ifp, "%s: Failed updating vport context with MTU size, err=%d\n",
2950                     __func__, err);
2951         }
2952
2953         ifp->if_mtu = sw_mtu;
2954
2955         err = mlx5_query_vport_mtu(mdev, &hw_mtu);
2956         if (err || !hw_mtu) {
2957                 /* fallback to port oper mtu */
2958                 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2959         }
2960         if (err) {
2961                 if_printf(ifp, "Query port MTU, after setting new "
2962                     "MTU value, failed\n");
2963                 return (err);
2964         } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
2965                 err = -E2BIG,
2966                 if_printf(ifp, "Port MTU %d is smaller than "
2967                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2968         } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
2969                 err = -EINVAL;
2970                 if_printf(ifp, "Port MTU %d is bigger than "
2971                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2972         }
2973         priv->params_ethtool.hw_mtu = hw_mtu;
2974
2975         return (err);
2976 }
2977
2978 int
2979 mlx5e_open_locked(struct ifnet *ifp)
2980 {
2981         struct mlx5e_priv *priv = ifp->if_softc;
2982         int err;
2983         u16 set_id;
2984
2985         /* check if already opened */
2986         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2987                 return (0);
2988
2989 #ifdef RSS
2990         if (rss_getnumbuckets() > priv->params.num_channels) {
2991                 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than "
2992                     "channels(%u) available\n", rss_getnumbuckets(),
2993                     priv->params.num_channels);
2994         }
2995 #endif
2996         err = mlx5e_open_tises(priv);
2997         if (err) {
2998                 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n",
2999                     __func__, err);
3000                 return (err);
3001         }
3002         err = mlx5_vport_alloc_q_counter(priv->mdev,
3003             MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
3004         if (err) {
3005                 if_printf(priv->ifp,
3006                     "%s: mlx5_vport_alloc_q_counter failed: %d\n",
3007                     __func__, err);
3008                 goto err_close_tises;
3009         }
3010         /* store counter set ID */
3011         priv->counter_set_id = set_id;
3012
3013         err = mlx5e_open_channels(priv);
3014         if (err) {
3015                 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n",
3016                     __func__, err);
3017                 goto err_dalloc_q_counter;
3018         }
3019         err = mlx5e_open_rqt(priv);
3020         if (err) {
3021                 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n",
3022                     __func__, err);
3023                 goto err_close_channels;
3024         }
3025         err = mlx5e_open_tirs(priv);
3026         if (err) {
3027                 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n",
3028                     __func__, err);
3029                 goto err_close_rqls;
3030         }
3031         err = mlx5e_open_flow_table(priv);
3032         if (err) {
3033                 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n",
3034                     __func__, err);
3035                 goto err_close_tirs;
3036         }
3037         err = mlx5e_add_all_vlan_rules(priv);
3038         if (err) {
3039                 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
3040                     __func__, err);
3041                 goto err_close_flow_table;
3042         }
3043         set_bit(MLX5E_STATE_OPENED, &priv->state);
3044
3045         mlx5e_update_carrier(priv);
3046         mlx5e_set_rx_mode_core(priv);
3047
3048         return (0);
3049
3050 err_close_flow_table:
3051         mlx5e_close_flow_table(priv);
3052
3053 err_close_tirs:
3054         mlx5e_close_tirs(priv);
3055
3056 err_close_rqls:
3057         mlx5e_close_rqt(priv);
3058
3059 err_close_channels:
3060         mlx5e_close_channels(priv);
3061
3062 err_dalloc_q_counter:
3063         mlx5_vport_dealloc_q_counter(priv->mdev,
3064             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
3065
3066 err_close_tises:
3067         mlx5e_close_tises(priv);
3068
3069         return (err);
3070 }
3071
3072 static void
3073 mlx5e_open(void *arg)
3074 {
3075         struct mlx5e_priv *priv = arg;
3076
3077         PRIV_LOCK(priv);
3078         if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
3079                 if_printf(priv->ifp,
3080                     "%s: Setting port status to up failed\n",
3081                     __func__);
3082
3083         mlx5e_open_locked(priv->ifp);
3084         priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
3085         PRIV_UNLOCK(priv);
3086 }
3087
3088 int
3089 mlx5e_close_locked(struct ifnet *ifp)
3090 {
3091         struct mlx5e_priv *priv = ifp->if_softc;
3092
3093         /* check if already closed */
3094         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3095                 return (0);
3096
3097         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3098
3099         mlx5e_set_rx_mode_core(priv);
3100         mlx5e_del_all_vlan_rules(priv);
3101         if_link_state_change(priv->ifp, LINK_STATE_DOWN);
3102         mlx5e_close_flow_table(priv);
3103         mlx5e_close_tirs(priv);
3104         mlx5e_close_rqt(priv);
3105         mlx5e_close_channels(priv);
3106         mlx5_vport_dealloc_q_counter(priv->mdev,
3107             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
3108         mlx5e_close_tises(priv);
3109
3110         return (0);
3111 }
3112
3113 #if (__FreeBSD_version >= 1100000)
3114 static uint64_t
3115 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
3116 {
3117         struct mlx5e_priv *priv = ifp->if_softc;
3118         u64 retval;
3119
3120         /* PRIV_LOCK(priv); XXX not allowed */
3121         switch (cnt) {
3122         case IFCOUNTER_IPACKETS:
3123                 retval = priv->stats.vport.rx_packets;
3124                 break;
3125         case IFCOUNTER_IERRORS:
3126                 retval = priv->stats.pport.in_range_len_errors +
3127                     priv->stats.pport.out_of_range_len +
3128                     priv->stats.pport.too_long_errors +
3129                     priv->stats.pport.check_seq_err +
3130                     priv->stats.pport.alignment_err;
3131                 break;
3132         case IFCOUNTER_IQDROPS:
3133                 retval = priv->stats.vport.rx_out_of_buffer;
3134                 break;
3135         case IFCOUNTER_OPACKETS:
3136                 retval = priv->stats.vport.tx_packets;
3137                 break;
3138         case IFCOUNTER_OERRORS:
3139                 retval = priv->stats.port_stats_debug.out_discards;
3140                 break;
3141         case IFCOUNTER_IBYTES:
3142                 retval = priv->stats.vport.rx_bytes;
3143                 break;
3144         case IFCOUNTER_OBYTES:
3145                 retval = priv->stats.vport.tx_bytes;
3146                 break;
3147         case IFCOUNTER_IMCASTS:
3148                 retval = priv->stats.vport.rx_multicast_packets;
3149                 break;
3150         case IFCOUNTER_OMCASTS:
3151                 retval = priv->stats.vport.tx_multicast_packets;
3152                 break;
3153         case IFCOUNTER_OQDROPS:
3154                 retval = priv->stats.vport.tx_queue_dropped;
3155                 break;
3156         case IFCOUNTER_COLLISIONS:
3157                 retval = priv->stats.pport.collisions;
3158                 break;
3159         default:
3160                 retval = if_get_counter_default(ifp, cnt);
3161                 break;
3162         }
3163         /* PRIV_UNLOCK(priv); XXX not allowed */
3164         return (retval);
3165 }
3166 #endif
3167
3168 static void
3169 mlx5e_set_rx_mode(struct ifnet *ifp)
3170 {
3171         struct mlx5e_priv *priv = ifp->if_softc;
3172
3173         queue_work(priv->wq, &priv->set_rx_mode_work);
3174 }
3175
3176 static int
3177 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3178 {
3179         struct mlx5e_priv *priv;
3180         struct ifreq *ifr;
3181         struct ifi2creq i2c;
3182         int error = 0;
3183         int mask = 0;
3184         int size_read = 0;
3185         int module_status;
3186         int module_num;
3187         int max_mtu;
3188         uint8_t read_addr;
3189
3190         priv = ifp->if_softc;
3191
3192         /* check if detaching */
3193         if (priv == NULL || priv->gone != 0)
3194                 return (ENXIO);
3195
3196         switch (command) {
3197         case SIOCSIFMTU:
3198                 ifr = (struct ifreq *)data;
3199
3200                 PRIV_LOCK(priv);
3201                 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
3202
3203                 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
3204                     ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
3205                         int was_opened;
3206
3207                         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3208                         if (was_opened)
3209                                 mlx5e_close_locked(ifp);
3210
3211                         /* set new MTU */
3212                         mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
3213
3214                         if (was_opened)
3215                                 mlx5e_open_locked(ifp);
3216                 } else {
3217                         error = EINVAL;
3218                         if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n",
3219                             MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
3220                 }
3221                 PRIV_UNLOCK(priv);
3222                 break;
3223         case SIOCSIFFLAGS:
3224                 if ((ifp->if_flags & IFF_UP) &&
3225                     (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3226                         mlx5e_set_rx_mode(ifp);
3227                         break;
3228                 }
3229                 PRIV_LOCK(priv);
3230                 if (ifp->if_flags & IFF_UP) {
3231                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
3232                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3233                                         mlx5e_open_locked(ifp);
3234                                 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3235                                 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
3236                         }
3237                 } else {
3238                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3239                                 mlx5_set_port_status(priv->mdev,
3240                                     MLX5_PORT_DOWN);
3241                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
3242                                         mlx5e_close_locked(ifp);
3243                                 mlx5e_update_carrier(priv);
3244                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3245                         }
3246                 }
3247                 PRIV_UNLOCK(priv);
3248                 break;
3249         case SIOCADDMULTI:
3250         case SIOCDELMULTI:
3251                 mlx5e_set_rx_mode(ifp);
3252                 break;
3253         case SIOCSIFMEDIA:
3254         case SIOCGIFMEDIA:
3255         case SIOCGIFXMEDIA:
3256                 ifr = (struct ifreq *)data;
3257                 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
3258                 break;
3259         case SIOCSIFCAP:
3260                 ifr = (struct ifreq *)data;
3261                 PRIV_LOCK(priv);
3262                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3263
3264                 if (mask & IFCAP_TXCSUM) {
3265                         ifp->if_capenable ^= IFCAP_TXCSUM;
3266                         ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
3267
3268                         if (IFCAP_TSO4 & ifp->if_capenable &&
3269                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
3270                                 ifp->if_capenable &= ~IFCAP_TSO4;
3271                                 ifp->if_hwassist &= ~CSUM_IP_TSO;
3272                                 if_printf(ifp,
3273                                     "tso4 disabled due to -txcsum.\n");
3274                         }
3275                 }
3276                 if (mask & IFCAP_TXCSUM_IPV6) {
3277                         ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
3278                         ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3279
3280                         if (IFCAP_TSO6 & ifp->if_capenable &&
3281                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
3282                                 ifp->if_capenable &= ~IFCAP_TSO6;
3283                                 ifp->if_hwassist &= ~CSUM_IP6_TSO;
3284                                 if_printf(ifp,
3285                                     "tso6 disabled due to -txcsum6.\n");
3286                         }
3287                 }
3288                 if (mask & IFCAP_RXCSUM)
3289                         ifp->if_capenable ^= IFCAP_RXCSUM;
3290                 if (mask & IFCAP_RXCSUM_IPV6)
3291                         ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
3292                 if (mask & IFCAP_TSO4) {
3293                         if (!(IFCAP_TSO4 & ifp->if_capenable) &&
3294                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
3295                                 if_printf(ifp, "enable txcsum first.\n");
3296                                 error = EAGAIN;
3297                                 goto out;
3298                         }
3299                         ifp->if_capenable ^= IFCAP_TSO4;
3300                         ifp->if_hwassist ^= CSUM_IP_TSO;
3301                 }
3302                 if (mask & IFCAP_TSO6) {
3303                         if (!(IFCAP_TSO6 & ifp->if_capenable) &&
3304                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
3305                                 if_printf(ifp, "enable txcsum6 first.\n");
3306                                 error = EAGAIN;
3307                                 goto out;
3308                         }
3309                         ifp->if_capenable ^= IFCAP_TSO6;
3310                         ifp->if_hwassist ^= CSUM_IP6_TSO;
3311                 }
3312                 if (mask & IFCAP_VLAN_HWFILTER) {
3313                         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
3314                                 mlx5e_disable_vlan_filter(priv);
3315                         else
3316                                 mlx5e_enable_vlan_filter(priv);
3317
3318                         ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
3319                 }
3320                 if (mask & IFCAP_VLAN_HWTAGGING)
3321                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
3322                 if (mask & IFCAP_WOL_MAGIC)
3323                         ifp->if_capenable ^= IFCAP_WOL_MAGIC;
3324
3325                 VLAN_CAPABILITIES(ifp);
3326                 /* turn off LRO means also turn of HW LRO - if it's on */
3327                 if (mask & IFCAP_LRO) {
3328                         int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3329                         bool need_restart = false;
3330
3331                         ifp->if_capenable ^= IFCAP_LRO;
3332
3333                         /* figure out if updating HW LRO is needed */
3334                         if (!(ifp->if_capenable & IFCAP_LRO)) {
3335                                 if (priv->params.hw_lro_en) {
3336                                         priv->params.hw_lro_en = false;
3337                                         need_restart = true;
3338                                 }
3339                         } else {
3340                                 if (priv->params.hw_lro_en == false &&
3341                                     priv->params_ethtool.hw_lro != 0) {
3342                                         priv->params.hw_lro_en = true;
3343                                         need_restart = true;
3344                                 }
3345                         }
3346                         if (was_opened && need_restart) {
3347                                 mlx5e_close_locked(ifp);
3348                                 mlx5e_open_locked(ifp);
3349                         }
3350                 }
3351                 if (mask & IFCAP_HWRXTSTMP) {
3352                         ifp->if_capenable ^= IFCAP_HWRXTSTMP;
3353                         if (ifp->if_capenable & IFCAP_HWRXTSTMP) {
3354                                 if (priv->clbr_done == 0)
3355                                         mlx5e_reset_calibration_callout(priv);
3356                         } else {
3357                                 callout_drain(&priv->tstmp_clbr);
3358                                 priv->clbr_done = 0;
3359                         }
3360                 }
3361 out:
3362                 PRIV_UNLOCK(priv);
3363                 break;
3364
3365         case SIOCGI2C:
3366                 ifr = (struct ifreq *)data;
3367
3368                 /*
3369                  * Copy from the user-space address ifr_data to the
3370                  * kernel-space address i2c
3371                  */
3372                 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
3373                 if (error)
3374                         break;
3375
3376                 if (i2c.len > sizeof(i2c.data)) {
3377                         error = EINVAL;
3378                         break;
3379                 }
3380
3381                 PRIV_LOCK(priv);
3382                 /* Get module_num which is required for the query_eeprom */
3383                 error = mlx5_query_module_num(priv->mdev, &module_num);
3384                 if (error) {
3385                         if_printf(ifp, "Query module num failed, eeprom "
3386                             "reading is not supported\n");
3387                         error = EINVAL;
3388                         goto err_i2c;
3389                 }
3390                 /* Check if module is present before doing an access */
3391                 module_status = mlx5_query_module_status(priv->mdev, module_num);
3392                 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED &&
3393                     module_status != MLX5_MODULE_STATUS_PLUGGED_DISABLED) {
3394                         error = EINVAL;
3395                         goto err_i2c;
3396                 }
3397                 /*
3398                  * Currently 0XA0 and 0xA2 are the only addresses permitted.
3399                  * The internal conversion is as follows:
3400                  */
3401                 if (i2c.dev_addr == 0xA0)
3402                         read_addr = MLX5E_I2C_ADDR_LOW;
3403                 else if (i2c.dev_addr == 0xA2)
3404                         read_addr = MLX5E_I2C_ADDR_HIGH;
3405                 else {
3406                         if_printf(ifp, "Query eeprom failed, "
3407                             "Invalid Address: %X\n", i2c.dev_addr);
3408                         error = EINVAL;
3409                         goto err_i2c;
3410                 }
3411                 error = mlx5_query_eeprom(priv->mdev,
3412                     read_addr, MLX5E_EEPROM_LOW_PAGE,
3413                     (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
3414                     (uint32_t *)i2c.data, &size_read);
3415                 if (error) {
3416                         if_printf(ifp, "Query eeprom failed, eeprom "
3417                             "reading is not supported\n");
3418                         error = EINVAL;
3419                         goto err_i2c;
3420                 }
3421
3422                 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
3423                         error = mlx5_query_eeprom(priv->mdev,
3424                             read_addr, MLX5E_EEPROM_LOW_PAGE,
3425                             (uint32_t)(i2c.offset + size_read),
3426                             (uint32_t)(i2c.len - size_read), module_num,
3427                             (uint32_t *)(i2c.data + size_read), &size_read);
3428                 }
3429                 if (error) {
3430                         if_printf(ifp, "Query eeprom failed, eeprom "
3431                             "reading is not supported\n");
3432                         error = EINVAL;
3433                         goto err_i2c;
3434                 }
3435
3436                 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
3437 err_i2c:
3438                 PRIV_UNLOCK(priv);
3439                 break;
3440
3441         default:
3442                 error = ether_ioctl(ifp, command, data);
3443                 break;
3444         }
3445         return (error);
3446 }
3447
3448 static int
3449 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3450 {
3451         /*
3452          * TODO: uncoment once FW really sets all these bits if
3453          * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
3454          * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
3455          * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
3456          * -ENOTSUPP;
3457          */
3458
3459         /* TODO: add more must-to-have features */
3460
3461         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3462                 return (-ENODEV);
3463
3464         return (0);
3465 }
3466
3467 static u16
3468 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3469 {
3470         uint32_t bf_buf_size = (1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U;
3471
3472         bf_buf_size -= sizeof(struct mlx5e_tx_wqe) - 2;
3473
3474         /* verify against driver hardware limit */
3475         if (bf_buf_size > MLX5E_MAX_TX_INLINE)
3476                 bf_buf_size = MLX5E_MAX_TX_INLINE;
3477
3478         return (bf_buf_size);
3479 }
3480
3481 static int
3482 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
3483     struct mlx5e_priv *priv,
3484     int num_comp_vectors)
3485 {
3486         int err;
3487
3488         /*
3489          * TODO: Consider link speed for setting "log_sq_size",
3490          * "log_rq_size" and "cq_moderation_xxx":
3491          */
3492         priv->params.log_sq_size =
3493             MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3494         priv->params.log_rq_size =
3495             MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3496         priv->params.rx_cq_moderation_usec =
3497             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3498             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
3499             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3500         priv->params.rx_cq_moderation_mode =
3501             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
3502         priv->params.rx_cq_moderation_pkts =
3503             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3504         priv->params.tx_cq_moderation_usec =
3505             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3506         priv->params.tx_cq_moderation_pkts =
3507             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3508         priv->params.min_rx_wqes =
3509             MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
3510         priv->params.rx_hash_log_tbl_sz =
3511             (order_base_2(num_comp_vectors) >
3512             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
3513             order_base_2(num_comp_vectors) :
3514             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
3515         priv->params.num_tc = 1;
3516         priv->params.default_vlan_prio = 0;
3517         priv->counter_set_id = -1;
3518         priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3519
3520         err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3521         if (err)
3522                 return (err);
3523
3524         /*
3525          * hw lro is currently defaulted to off. when it won't anymore we
3526          * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
3527          */
3528         priv->params.hw_lro_en = false;
3529         priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3530
3531         /*
3532          * CQE zipping is currently defaulted to off. when it won't
3533          * anymore we will consider the HW capability:
3534          * "!!MLX5_CAP_GEN(mdev, cqe_compression)"
3535          */
3536         priv->params.cqe_zipping_en = false;
3537
3538         priv->mdev = mdev;
3539         priv->params.num_channels = num_comp_vectors;
3540         priv->params.channels_rsss = 1;
3541         priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
3542         priv->queue_mapping_channel_mask =
3543             roundup_pow_of_two(num_comp_vectors) - 1;
3544         priv->num_tc = priv->params.num_tc;
3545         priv->default_vlan_prio = priv->params.default_vlan_prio;
3546
3547         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3548         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3549         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3550
3551         return (0);
3552 }
3553
3554 static int
3555 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
3556                   struct mlx5_core_mr *mkey)
3557 {
3558         struct ifnet *ifp = priv->ifp;
3559         struct mlx5_core_dev *mdev = priv->mdev;
3560         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3561         void *mkc;
3562         u32 *in;
3563         int err;
3564
3565         in = mlx5_vzalloc(inlen);
3566         if (in == NULL) {
3567                 if_printf(ifp, "%s: failed to allocate inbox\n", __func__);
3568                 return (-ENOMEM);
3569         }
3570
3571         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3572         MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA);
3573         MLX5_SET(mkc, mkc, lw, 1);
3574         MLX5_SET(mkc, mkc, lr, 1);
3575
3576         MLX5_SET(mkc, mkc, pd, pdn);
3577         MLX5_SET(mkc, mkc, length64, 1);
3578         MLX5_SET(mkc, mkc, qpn, 0xffffff);
3579
3580         err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
3581         if (err)
3582                 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n",
3583                     __func__, err);
3584
3585         kvfree(in);
3586         return (err);
3587 }
3588
3589 static const char *mlx5e_vport_stats_desc[] = {
3590         MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
3591 };
3592
3593 static const char *mlx5e_pport_stats_desc[] = {
3594         MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
3595 };
3596
3597 static void
3598 mlx5e_priv_mtx_init(struct mlx5e_priv *priv)
3599 {
3600         mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
3601         sx_init(&priv->state_lock, "mlx5state");
3602         callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
3603         MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
3604 }
3605
3606 static void
3607 mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv)
3608 {
3609         mtx_destroy(&priv->async_events_mtx);
3610         sx_destroy(&priv->state_lock);
3611 }
3612
3613 static int
3614 sysctl_firmware(SYSCTL_HANDLER_ARGS)
3615 {
3616         /*
3617          * %d.%d%.d the string format.
3618          * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
3619          * We need at most 5 chars to store that.
3620          * It also has: two "." and NULL at the end, which means we need 18
3621          * (5*3 + 3) chars at most.
3622          */
3623         char fw[18];
3624         struct mlx5e_priv *priv = arg1;
3625         int error;
3626
3627         snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
3628             fw_rev_sub(priv->mdev));
3629         error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
3630         return (error);
3631 }
3632
3633 static void
3634 mlx5e_disable_tx_dma(struct mlx5e_channel *ch)
3635 {
3636         int i;
3637
3638         for (i = 0; i < ch->num_tc; i++)
3639                 mlx5e_drain_sq(&ch->sq[i]);
3640 }
3641
3642 static void
3643 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq)
3644 {
3645
3646         sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP);
3647         sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8);
3648         mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
3649         sq->doorbell.d64 = 0;
3650 }
3651
3652 void
3653 mlx5e_resume_sq(struct mlx5e_sq *sq)
3654 {
3655         int err;
3656
3657         /* check if already enabled */
3658         if (READ_ONCE(sq->running) != 0)
3659                 return;
3660
3661         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR,
3662             MLX5_SQC_STATE_RST);
3663         if (err != 0) {
3664                 if_printf(sq->ifp,
3665                     "mlx5e_modify_sq() from ERR to RST failed: %d\n", err);
3666         }
3667
3668         sq->cc = 0;
3669         sq->pc = 0;
3670
3671         /* reset doorbell prior to moving from RST to RDY */
3672         mlx5e_reset_sq_doorbell_record(sq);
3673
3674         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST,
3675             MLX5_SQC_STATE_RDY);
3676         if (err != 0) {
3677                 if_printf(sq->ifp,
3678                     "mlx5e_modify_sq() from RST to RDY failed: %d\n", err);
3679         }
3680
3681         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
3682         WRITE_ONCE(sq->running, 1);
3683 }
3684
3685 static void
3686 mlx5e_enable_tx_dma(struct mlx5e_channel *ch)
3687 {
3688         int i;
3689
3690         for (i = 0; i < ch->num_tc; i++)
3691                 mlx5e_resume_sq(&ch->sq[i]);
3692 }
3693
3694 static void
3695 mlx5e_disable_rx_dma(struct mlx5e_channel *ch)
3696 {
3697         struct mlx5e_rq *rq = &ch->rq;
3698         int err;
3699
3700         mtx_lock(&rq->mtx);
3701         rq->enabled = 0;
3702         callout_stop(&rq->watchdog);
3703         mtx_unlock(&rq->mtx);
3704
3705         callout_drain(&rq->watchdog);
3706
3707         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
3708         if (err != 0) {
3709                 if_printf(rq->ifp,
3710                     "mlx5e_modify_rq() from RDY to RST failed: %d\n", err);
3711         }
3712
3713         while (!mlx5_wq_ll_is_empty(&rq->wq)) {
3714                 msleep(1);
3715                 rq->cq.mcq.comp(&rq->cq.mcq);
3716         }
3717
3718         /*
3719          * Transitioning into RST state will allow the FW to track less ERR state queues,
3720          * thus reducing the recv queue flushing time
3721          */
3722         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST);
3723         if (err != 0) {
3724                 if_printf(rq->ifp,
3725                     "mlx5e_modify_rq() from ERR to RST failed: %d\n", err);
3726         }
3727 }
3728
3729 static void
3730 mlx5e_enable_rx_dma(struct mlx5e_channel *ch)
3731 {
3732         struct mlx5e_rq *rq = &ch->rq;
3733         int err;
3734
3735         rq->wq.wqe_ctr = 0;
3736         mlx5_wq_ll_update_db_record(&rq->wq);
3737         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3738         if (err != 0) {
3739                 if_printf(rq->ifp,
3740                     "mlx5e_modify_rq() from RST to RDY failed: %d\n", err);
3741         }
3742
3743         rq->enabled = 1;
3744
3745         rq->cq.mcq.comp(&rq->cq.mcq);
3746 }
3747
3748 void
3749 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value)
3750 {
3751         int i;
3752
3753         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3754                 return;
3755
3756         for (i = 0; i < priv->params.num_channels; i++) {
3757                 if (value)
3758                         mlx5e_disable_tx_dma(&priv->channel[i]);
3759                 else
3760                         mlx5e_enable_tx_dma(&priv->channel[i]);
3761         }
3762 }
3763
3764 void
3765 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value)
3766 {
3767         int i;
3768
3769         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3770                 return;
3771
3772         for (i = 0; i < priv->params.num_channels; i++) {
3773                 if (value)
3774                         mlx5e_disable_rx_dma(&priv->channel[i]);
3775                 else
3776                         mlx5e_enable_rx_dma(&priv->channel[i]);
3777         }
3778 }
3779
3780 static void
3781 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
3782 {
3783         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3784             OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
3785             sysctl_firmware, "A", "HCA firmware version");
3786
3787         SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3788             OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
3789             "Board ID");
3790 }
3791
3792 static int
3793 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3794 {
3795         struct mlx5e_priv *priv = arg1;
3796         uint8_t temp[MLX5E_MAX_PRIORITY];
3797         uint32_t tx_pfc;
3798         int err;
3799         int i;
3800
3801         PRIV_LOCK(priv);
3802
3803         tx_pfc = priv->params.tx_priority_flow_control;
3804
3805         for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3806                 temp[i] = (tx_pfc >> i) & 1;
3807
3808         err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3809         if (err || !req->newptr)
3810                 goto done;
3811         err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3812         if (err)
3813                 goto done;
3814
3815         priv->params.tx_priority_flow_control = 0;
3816
3817         /* range check input value */
3818         for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3819                 if (temp[i] > 1) {
3820                         err = ERANGE;
3821                         goto done;
3822                 }
3823                 priv->params.tx_priority_flow_control |= (temp[i] << i);
3824         }
3825
3826         /* check if update is required */
3827         if (tx_pfc != priv->params.tx_priority_flow_control)
3828                 err = -mlx5e_set_port_pfc(priv);
3829 done:
3830         if (err != 0)
3831                 priv->params.tx_priority_flow_control= tx_pfc;
3832         PRIV_UNLOCK(priv);
3833
3834         return (err);
3835 }
3836
3837 static int
3838 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3839 {
3840         struct mlx5e_priv *priv = arg1;
3841         uint8_t temp[MLX5E_MAX_PRIORITY];
3842         uint32_t rx_pfc;
3843         int err;
3844         int i;
3845
3846         PRIV_LOCK(priv);
3847
3848         rx_pfc = priv->params.rx_priority_flow_control;
3849
3850         for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3851                 temp[i] = (rx_pfc >> i) & 1;
3852
3853         err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3854         if (err || !req->newptr)
3855                 goto done;
3856         err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3857         if (err)
3858                 goto done;
3859
3860         priv->params.rx_priority_flow_control = 0;
3861
3862         /* range check input value */
3863         for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3864                 if (temp[i] > 1) {
3865                         err = ERANGE;
3866                         goto done;
3867                 }
3868                 priv->params.rx_priority_flow_control |= (temp[i] << i);
3869         }
3870
3871         /* check if update is required */
3872         if (rx_pfc != priv->params.rx_priority_flow_control)
3873                 err = -mlx5e_set_port_pfc(priv);
3874 done:
3875         if (err != 0)
3876                 priv->params.rx_priority_flow_control= rx_pfc;
3877         PRIV_UNLOCK(priv);
3878
3879         return (err);
3880 }
3881
3882 static void
3883 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
3884 {
3885 #if (__FreeBSD_version < 1100000)
3886         char path[96];
3887 #endif
3888         int error;
3889
3890         /* enable pauseframes by default */
3891         priv->params.tx_pauseframe_control = 1;
3892         priv->params.rx_pauseframe_control = 1;
3893
3894         /* disable ports flow control, PFC, by default */
3895         priv->params.tx_priority_flow_control = 0;
3896         priv->params.rx_priority_flow_control = 0;
3897
3898 #if (__FreeBSD_version < 1100000)
3899         /* compute path for sysctl */
3900         snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
3901             device_get_unit(priv->mdev->pdev->dev.bsddev));
3902
3903         /* try to fetch tunable, if any */
3904         TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
3905
3906         /* compute path for sysctl */
3907         snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
3908             device_get_unit(priv->mdev->pdev->dev.bsddev));
3909
3910         /* try to fetch tunable, if any */
3911         TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
3912 #endif
3913
3914         /* register pauseframe SYSCTLs */
3915         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3916             OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
3917             &priv->params.tx_pauseframe_control, 0,
3918             "Set to enable TX pause frames. Clear to disable.");
3919
3920         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3921             OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
3922             &priv->params.rx_pauseframe_control, 0,
3923             "Set to enable RX pause frames. Clear to disable.");
3924
3925         /* register priority flow control, PFC, SYSCTLs */
3926         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3927             OID_AUTO, "tx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
3928             CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_tx_priority_flow_control, "CU",
3929             "Set to enable TX ports flow control frames for priorities 0..7. Clear to disable.");
3930
3931         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3932             OID_AUTO, "rx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
3933             CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_rx_priority_flow_control, "CU",
3934             "Set to enable RX ports flow control frames for priorities 0..7. Clear to disable.");
3935
3936         PRIV_LOCK(priv);
3937
3938         /* range check */
3939         priv->params.tx_pauseframe_control =
3940             priv->params.tx_pauseframe_control ? 1 : 0;
3941         priv->params.rx_pauseframe_control =
3942             priv->params.rx_pauseframe_control ? 1 : 0;
3943
3944         /* update firmware */
3945         error = mlx5e_set_port_pause_and_pfc(priv);
3946         if (error == -EINVAL) {
3947                 if_printf(priv->ifp,
3948                     "Global pauseframes must be disabled before enabling PFC.\n");
3949                 priv->params.rx_priority_flow_control = 0;
3950                 priv->params.tx_priority_flow_control = 0;
3951
3952                 /* update firmware */
3953                 (void) mlx5e_set_port_pause_and_pfc(priv);
3954         }
3955         PRIV_UNLOCK(priv);
3956 }
3957
3958 static int
3959 mlx5e_ul_snd_tag_alloc(struct ifnet *ifp,
3960     union if_snd_tag_alloc_params *params,
3961     struct m_snd_tag **ppmt)
3962 {
3963         struct mlx5e_priv *priv;
3964         struct mlx5e_channel *pch;
3965
3966         priv = ifp->if_softc;
3967
3968         if (unlikely(priv->gone || params->hdr.flowtype == M_HASHTYPE_NONE)) {
3969                 return (EOPNOTSUPP);
3970         } else {
3971                 /* keep this code synced with mlx5e_select_queue() */
3972                 u32 ch = priv->params.num_channels;
3973 #ifdef RSS
3974                 u32 temp;
3975
3976                 if (rss_hash2bucket(params->hdr.flowid,
3977                     params->hdr.flowtype, &temp) == 0)
3978                         ch = temp % ch;
3979                 else
3980 #endif
3981                         ch = (params->hdr.flowid % 128) % ch;
3982
3983                 /*
3984                  * NOTE: The channels array is only freed at detach
3985                  * and it safe to return a pointer to the send tag
3986                  * inside the channels structure as long as we
3987                  * reference the priv.
3988                  */
3989                 pch = priv->channel + ch;
3990
3991                 /* check if send queue is not running */
3992                 if (unlikely(pch->sq[0].running == 0))
3993                         return (ENXIO);
3994                 mlx5e_ref_channel(priv);
3995                 *ppmt = &pch->tag.m_snd_tag;
3996                 return (0);
3997         }
3998 }
3999
4000 static int
4001 mlx5e_ul_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
4002 {
4003         struct mlx5e_channel *pch =
4004             container_of(pmt, struct mlx5e_channel, tag.m_snd_tag);
4005
4006         params->unlimited.max_rate = -1ULL;
4007         params->unlimited.queue_level = mlx5e_sq_queue_level(&pch->sq[0]);
4008         return (0);
4009 }
4010
4011 static void
4012 mlx5e_ul_snd_tag_free(struct m_snd_tag *pmt)
4013 {
4014         struct mlx5e_channel *pch =
4015             container_of(pmt, struct mlx5e_channel, tag.m_snd_tag);
4016
4017         mlx5e_unref_channel(pch->priv);
4018 }
4019
4020 static int
4021 mlx5e_snd_tag_alloc(struct ifnet *ifp,
4022     union if_snd_tag_alloc_params *params,
4023     struct m_snd_tag **ppmt)
4024 {
4025
4026         switch (params->hdr.type) {
4027 #ifdef RATELIMIT
4028         case IF_SND_TAG_TYPE_RATE_LIMIT:
4029                 return (mlx5e_rl_snd_tag_alloc(ifp, params, ppmt));
4030 #endif
4031         case IF_SND_TAG_TYPE_UNLIMITED:
4032                 return (mlx5e_ul_snd_tag_alloc(ifp, params, ppmt));
4033         default:
4034                 return (EOPNOTSUPP);
4035         }
4036 }
4037
4038 static int
4039 mlx5e_snd_tag_modify(struct m_snd_tag *pmt, union if_snd_tag_modify_params *params)
4040 {
4041         struct mlx5e_snd_tag *tag =
4042             container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
4043
4044         switch (tag->type) {
4045 #ifdef RATELIMIT
4046         case IF_SND_TAG_TYPE_RATE_LIMIT:
4047                 return (mlx5e_rl_snd_tag_modify(pmt, params));
4048 #endif
4049         case IF_SND_TAG_TYPE_UNLIMITED:
4050         default:
4051                 return (EOPNOTSUPP);
4052         }
4053 }
4054
4055 static int
4056 mlx5e_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
4057 {
4058         struct mlx5e_snd_tag *tag =
4059             container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
4060
4061         switch (tag->type) {
4062 #ifdef RATELIMIT
4063         case IF_SND_TAG_TYPE_RATE_LIMIT:
4064                 return (mlx5e_rl_snd_tag_query(pmt, params));
4065 #endif
4066         case IF_SND_TAG_TYPE_UNLIMITED:
4067                 return (mlx5e_ul_snd_tag_query(pmt, params));
4068         default:
4069                 return (EOPNOTSUPP);
4070         }
4071 }
4072
4073 static void
4074 mlx5e_snd_tag_free(struct m_snd_tag *pmt)
4075 {
4076         struct mlx5e_snd_tag *tag =
4077             container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
4078
4079         switch (tag->type) {
4080 #ifdef RATELIMIT
4081         case IF_SND_TAG_TYPE_RATE_LIMIT:
4082                 mlx5e_rl_snd_tag_free(pmt);
4083                 break;
4084 #endif
4085         case IF_SND_TAG_TYPE_UNLIMITED:
4086                 mlx5e_ul_snd_tag_free(pmt);
4087                 break;
4088         default:
4089                 break;
4090         }
4091 }
4092
4093 static void *
4094 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
4095 {
4096         struct ifnet *ifp;
4097         struct mlx5e_priv *priv;
4098         u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
4099         u8 connector_type;
4100         struct sysctl_oid_list *child;
4101         int ncv = mdev->priv.eq_table.num_comp_vectors;
4102         char unit[16];
4103         int err;
4104         int i,j;
4105         u32 eth_proto_cap;
4106         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
4107         bool ext = 0;
4108         u32 speeds_num;
4109         struct media media_entry = {};
4110
4111         if (mlx5e_check_required_hca_cap(mdev)) {
4112                 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
4113                 return (NULL);
4114         }
4115         /*
4116          * Try to allocate the priv and make room for worst-case
4117          * number of channel structures:
4118          */
4119         priv = malloc(sizeof(*priv) +
4120             (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors),
4121             M_MLX5EN, M_WAITOK | M_ZERO);
4122         mlx5e_priv_mtx_init(priv);
4123
4124         ifp = priv->ifp = if_alloc(IFT_ETHER);
4125         if (ifp == NULL) {
4126                 mlx5_core_err(mdev, "if_alloc() failed\n");
4127                 goto err_free_priv;
4128         }
4129         ifp->if_softc = priv;
4130         if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev));
4131         ifp->if_mtu = ETHERMTU;
4132         ifp->if_init = mlx5e_open;
4133         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
4134         ifp->if_ioctl = mlx5e_ioctl;
4135         ifp->if_transmit = mlx5e_xmit;
4136         ifp->if_qflush = if_qflush;
4137 #if (__FreeBSD_version >= 1100000)
4138         ifp->if_get_counter = mlx5e_get_counter;
4139 #endif
4140         ifp->if_snd.ifq_maxlen = ifqmaxlen;
4141         /*
4142          * Set driver features
4143          */
4144         ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
4145         ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
4146         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
4147         ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
4148         ifp->if_capabilities |= IFCAP_LRO;
4149         ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
4150         ifp->if_capabilities |= IFCAP_HWSTATS | IFCAP_HWRXTSTMP;
4151         ifp->if_capabilities |= IFCAP_TXRTLMT;
4152         ifp->if_snd_tag_alloc = mlx5e_snd_tag_alloc;
4153         ifp->if_snd_tag_free = mlx5e_snd_tag_free;
4154         ifp->if_snd_tag_modify = mlx5e_snd_tag_modify;
4155         ifp->if_snd_tag_query = mlx5e_snd_tag_query;
4156
4157         /* set TSO limits so that we don't have to drop TX packets */
4158         ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
4159         ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
4160         ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
4161
4162         ifp->if_capenable = ifp->if_capabilities;
4163         ifp->if_hwassist = 0;
4164         if (ifp->if_capenable & IFCAP_TSO)
4165                 ifp->if_hwassist |= CSUM_TSO;
4166         if (ifp->if_capenable & IFCAP_TXCSUM)
4167                 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
4168         if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
4169                 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
4170
4171         /* ifnet sysctl tree */
4172         sysctl_ctx_init(&priv->sysctl_ctx);
4173         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
4174             OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
4175         if (priv->sysctl_ifnet == NULL) {
4176                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4177                 goto err_free_sysctl;
4178         }
4179         snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
4180         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4181             OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
4182         if (priv->sysctl_ifnet == NULL) {
4183                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4184                 goto err_free_sysctl;
4185         }
4186
4187         /* HW sysctl tree */
4188         child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
4189         priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
4190             OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
4191         if (priv->sysctl_hw == NULL) {
4192                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4193                 goto err_free_sysctl;
4194         }
4195
4196         err = mlx5e_build_ifp_priv(mdev, priv, ncv);
4197         if (err) {
4198                 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err);
4199                 goto err_free_sysctl;
4200         }
4201
4202         /* reuse mlx5core's watchdog workqueue */
4203         priv->wq = mdev->priv.health.wq_watchdog;
4204
4205         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
4206         if (err) {
4207                 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n",
4208                     __func__, err);
4209                 goto err_free_wq;
4210         }
4211         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
4212         if (err) {
4213                 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n",
4214                     __func__, err);
4215                 goto err_unmap_free_uar;
4216         }
4217         err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
4218         if (err) {
4219                 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n",
4220                     __func__, err);
4221                 goto err_dealloc_pd;
4222         }
4223         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
4224         if (err) {
4225                 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n",
4226                     __func__, err);
4227                 goto err_dealloc_transport_domain;
4228         }
4229         mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
4230
4231         /* check if we should generate a random MAC address */
4232         if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
4233             is_zero_ether_addr(dev_addr)) {
4234                 random_ether_addr(dev_addr);
4235                 if_printf(ifp, "Assigned random MAC address\n");
4236         }
4237 #ifdef RATELIMIT
4238         err = mlx5e_rl_init(priv);
4239         if (err) {
4240                 if_printf(ifp, "%s: mlx5e_rl_init failed, %d\n",
4241                     __func__, err);
4242                 goto err_create_mkey;
4243         }
4244 #endif
4245
4246         /* set default MTU */
4247         mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
4248
4249         /* Set default media status */
4250         priv->media_status_last = IFM_AVALID;
4251         priv->media_active_last = IFM_ETHER | IFM_AUTO |
4252             IFM_ETH_RXPAUSE | IFM_FDX;
4253
4254         /* setup default pauseframes configuration */
4255         mlx5e_setup_pauseframes(priv);
4256
4257         /* Setup supported medias */
4258         //TODO: If we failed to query ptys is it ok to proceed??
4259         if (!mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1)) {
4260                 ext = MLX5_CAP_PCAM_FEATURE(mdev,
4261                     ptys_extended_ethernet);
4262                 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
4263                     eth_proto_capability);
4264                 if (MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type))
4265                         connector_type = MLX5_GET(ptys_reg, out,
4266                             connector_type);
4267         } else {
4268                 eth_proto_cap = 0;
4269                 if_printf(ifp, "%s: Query port media capability failed,"
4270                     " %d\n", __func__, err);
4271         }
4272
4273         ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
4274             mlx5e_media_change, mlx5e_media_status);
4275
4276         speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER : MLX5E_LINK_SPEEDS_NUMBER;
4277         for (i = 0; i != speeds_num; i++) {
4278                 for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) {
4279                         media_entry = ext ? mlx5e_ext_mode_table[i][j] :
4280                             mlx5e_mode_table[i][j];
4281                         if (media_entry.baudrate == 0)
4282                                 continue;
4283                         if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
4284                                 ifmedia_add(&priv->media,
4285                                     media_entry.subtype |
4286                                     IFM_ETHER, 0, NULL);
4287                                 ifmedia_add(&priv->media,
4288                                     media_entry.subtype |
4289                                     IFM_ETHER | IFM_FDX |
4290                                     IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
4291                         }
4292                 }
4293         }
4294
4295         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
4296         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
4297             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
4298
4299         /* Set autoselect by default */
4300         ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
4301             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
4302         ether_ifattach(ifp, dev_addr);
4303
4304         /* Register for VLAN events */
4305         priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
4306             mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
4307         priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
4308             mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
4309
4310         /* Link is down by default */
4311         if_link_state_change(ifp, LINK_STATE_DOWN);
4312
4313         mlx5e_enable_async_events(priv);
4314
4315         mlx5e_add_hw_stats(priv);
4316
4317         mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4318             "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
4319             priv->stats.vport.arg);
4320
4321         mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4322             "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
4323             priv->stats.pport.arg);
4324
4325         mlx5e_create_ethtool(priv);
4326
4327         mtx_lock(&priv->async_events_mtx);
4328         mlx5e_update_stats(priv);
4329         mtx_unlock(&priv->async_events_mtx);
4330
4331         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4332             OID_AUTO, "rx_clbr_done", CTLFLAG_RD,
4333             &priv->clbr_done, 0,
4334             "RX timestamps calibration state");
4335         callout_init(&priv->tstmp_clbr, CALLOUT_DIRECT);
4336         mlx5e_reset_calibration_callout(priv);
4337
4338         return (priv);
4339
4340 #ifdef RATELIMIT
4341 err_create_mkey:
4342         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
4343 #endif
4344 err_dealloc_transport_domain:
4345         mlx5_dealloc_transport_domain(mdev, priv->tdn);
4346
4347 err_dealloc_pd:
4348         mlx5_core_dealloc_pd(mdev, priv->pdn);
4349
4350 err_unmap_free_uar:
4351         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
4352
4353 err_free_wq:
4354         flush_workqueue(priv->wq);
4355
4356 err_free_sysctl:
4357         sysctl_ctx_free(&priv->sysctl_ctx);
4358         if (priv->sysctl_debug)
4359                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4360         if_free(ifp);
4361
4362 err_free_priv:
4363         mlx5e_priv_mtx_destroy(priv);
4364         free(priv, M_MLX5EN);
4365         return (NULL);
4366 }
4367
4368 static void
4369 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
4370 {
4371         struct mlx5e_priv *priv = vpriv;
4372         struct ifnet *ifp = priv->ifp;
4373
4374         /* don't allow more IOCTLs */
4375         priv->gone = 1;
4376
4377         /* XXX wait a bit to allow IOCTL handlers to complete */
4378         pause("W", hz);
4379
4380 #ifdef RATELIMIT
4381         /*
4382          * The kernel can have reference(s) via the m_snd_tag's into
4383          * the ratelimit channels, and these must go away before
4384          * detaching:
4385          */
4386         while (READ_ONCE(priv->rl.stats.tx_active_connections) != 0) {
4387                 if_printf(priv->ifp, "Waiting for all ratelimit connections "
4388                     "to terminate\n");
4389                 pause("W", hz);
4390         }
4391 #endif
4392         /* stop watchdog timer */
4393         callout_drain(&priv->watchdog);
4394
4395         callout_drain(&priv->tstmp_clbr);
4396
4397         if (priv->vlan_attach != NULL)
4398                 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
4399         if (priv->vlan_detach != NULL)
4400                 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
4401
4402         /* make sure device gets closed */
4403         PRIV_LOCK(priv);
4404         mlx5e_close_locked(ifp);
4405         PRIV_UNLOCK(priv);
4406
4407         /* wait for all unlimited send tags to go away */
4408         while (priv->channel_refs != 0) {
4409                 if_printf(priv->ifp, "Waiting for all unlimited connections "
4410                     "to terminate\n");
4411                 pause("W", hz);
4412         }
4413
4414         /* unregister device */
4415         ifmedia_removeall(&priv->media);
4416         ether_ifdetach(ifp);
4417         if_free(ifp);
4418
4419 #ifdef RATELIMIT
4420         mlx5e_rl_cleanup(priv);
4421 #endif
4422         /* destroy all remaining sysctl nodes */
4423         sysctl_ctx_free(&priv->stats.vport.ctx);
4424         sysctl_ctx_free(&priv->stats.pport.ctx);
4425         if (priv->sysctl_debug)
4426                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4427         sysctl_ctx_free(&priv->sysctl_ctx);
4428
4429         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
4430         mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
4431         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
4432         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
4433         mlx5e_disable_async_events(priv);
4434         flush_workqueue(priv->wq);
4435         mlx5e_priv_mtx_destroy(priv);
4436         free(priv, M_MLX5EN);
4437 }
4438
4439 static void *
4440 mlx5e_get_ifp(void *vpriv)
4441 {
4442         struct mlx5e_priv *priv = vpriv;
4443
4444         return (priv->ifp);
4445 }
4446
4447 static struct mlx5_interface mlx5e_interface = {
4448         .add = mlx5e_create_ifp,
4449         .remove = mlx5e_destroy_ifp,
4450         .event = mlx5e_async_event,
4451         .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4452         .get_dev = mlx5e_get_ifp,
4453 };
4454
4455 void
4456 mlx5e_init(void)
4457 {
4458         mlx5_register_interface(&mlx5e_interface);
4459 }
4460
4461 void
4462 mlx5e_cleanup(void)
4463 {
4464         mlx5_unregister_interface(&mlx5e_interface);
4465 }
4466
4467 static void
4468 mlx5e_show_version(void __unused *arg)
4469 {
4470
4471         printf("%s", mlx5e_version);
4472 }
4473 SYSINIT(mlx5e_show_version, SI_SUB_DRIVERS, SI_ORDER_ANY, mlx5e_show_version, NULL);
4474
4475 module_init_order(mlx5e_init, SI_ORDER_THIRD);
4476 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
4477
4478 #if (__FreeBSD_version >= 1100000)
4479 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
4480 #endif
4481 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
4482 MODULE_VERSION(mlx5en, 1);