sys/dev/mlx5/mlx5_en/mlx5_en_main.c

   1 /*-
   2  * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include "en.h"
  29
  30 #include <sys/sockio.h>
  31 #include <machine/atomic.h>
  32
  33 #ifndef ETH_DRIVER_VERSION
  34 #define ETH_DRIVER_VERSION      "3.5.0"
  35 #endif
  36 #define DRIVER_RELDATE  "November 2018"
  37
  38 static const char mlx5e_version[] = "mlx5en: Mellanox Ethernet driver "
  39         ETH_DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
  40
  41 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs);
  42
  43 struct mlx5e_channel_param {
  44         struct mlx5e_rq_param rq;
  45         struct mlx5e_sq_param sq;
  46         struct mlx5e_cq_param rx_cq;
  47         struct mlx5e_cq_param tx_cq;
  48 };
  49
  50 static const struct {
  51         u32     subtype;
  52         u64     baudrate;
  53 }       mlx5e_mode_table[MLX5E_LINK_MODES_NUMBER] = {
  54
  55         [MLX5E_1000BASE_CX_SGMII] = {
  56                 .subtype = IFM_1000_CX_SGMII,
  57                 .baudrate = IF_Mbps(1000ULL),
  58         },
  59         [MLX5E_1000BASE_KX] = {
  60                 .subtype = IFM_1000_KX,
  61                 .baudrate = IF_Mbps(1000ULL),
  62         },
  63         [MLX5E_10GBASE_CX4] = {
  64                 .subtype = IFM_10G_CX4,
  65                 .baudrate = IF_Gbps(10ULL),
  66         },
  67         [MLX5E_10GBASE_KX4] = {
  68                 .subtype = IFM_10G_KX4,
  69                 .baudrate = IF_Gbps(10ULL),
  70         },
  71         [MLX5E_10GBASE_KR] = {
  72                 .subtype = IFM_10G_KR,
  73                 .baudrate = IF_Gbps(10ULL),
  74         },
  75         [MLX5E_20GBASE_KR2] = {
  76                 .subtype = IFM_20G_KR2,
  77                 .baudrate = IF_Gbps(20ULL),
  78         },
  79         [MLX5E_40GBASE_CR4] = {
  80                 .subtype = IFM_40G_CR4,
  81                 .baudrate = IF_Gbps(40ULL),
  82         },
  83         [MLX5E_40GBASE_KR4] = {
  84                 .subtype = IFM_40G_KR4,
  85                 .baudrate = IF_Gbps(40ULL),
  86         },
  87         [MLX5E_56GBASE_R4] = {
  88                 .subtype = IFM_56G_R4,
  89                 .baudrate = IF_Gbps(56ULL),
  90         },
  91         [MLX5E_10GBASE_CR] = {
  92                 .subtype = IFM_10G_CR1,
  93                 .baudrate = IF_Gbps(10ULL),
  94         },
  95         [MLX5E_10GBASE_SR] = {
  96                 .subtype = IFM_10G_SR,
  97                 .baudrate = IF_Gbps(10ULL),
  98         },
  99         [MLX5E_10GBASE_ER] = {
 100                 .subtype = IFM_10G_ER,
 101                 .baudrate = IF_Gbps(10ULL),
 102         },
 103         [MLX5E_40GBASE_SR4] = {
 104                 .subtype = IFM_40G_SR4,
 105                 .baudrate = IF_Gbps(40ULL),
 106         },
 107         [MLX5E_40GBASE_LR4] = {
 108                 .subtype = IFM_40G_LR4,
 109                 .baudrate = IF_Gbps(40ULL),
 110         },
 111         [MLX5E_100GBASE_CR4] = {
 112                 .subtype = IFM_100G_CR4,
 113                 .baudrate = IF_Gbps(100ULL),
 114         },
 115         [MLX5E_100GBASE_SR4] = {
 116                 .subtype = IFM_100G_SR4,
 117                 .baudrate = IF_Gbps(100ULL),
 118         },
 119         [MLX5E_100GBASE_KR4] = {
 120                 .subtype = IFM_100G_KR4,
 121                 .baudrate = IF_Gbps(100ULL),
 122         },
 123         [MLX5E_100GBASE_LR4] = {
 124                 .subtype = IFM_100G_LR4,
 125                 .baudrate = IF_Gbps(100ULL),
 126         },
 127         [MLX5E_100BASE_TX] = {
 128                 .subtype = IFM_100_TX,
 129                 .baudrate = IF_Mbps(100ULL),
 130         },
 131         [MLX5E_1000BASE_T] = {
 132                 .subtype = IFM_1000_T,
 133                 .baudrate = IF_Mbps(1000ULL),
 134         },
 135         [MLX5E_10GBASE_T] = {
 136                 .subtype = IFM_10G_T,
 137                 .baudrate = IF_Gbps(10ULL),
 138         },
 139         [MLX5E_25GBASE_CR] = {
 140                 .subtype = IFM_25G_CR,
 141                 .baudrate = IF_Gbps(25ULL),
 142         },
 143         [MLX5E_25GBASE_KR] = {
 144                 .subtype = IFM_25G_KR,
 145                 .baudrate = IF_Gbps(25ULL),
 146         },
 147         [MLX5E_25GBASE_SR] = {
 148                 .subtype = IFM_25G_SR,
 149                 .baudrate = IF_Gbps(25ULL),
 150         },
 151         [MLX5E_50GBASE_CR2] = {
 152                 .subtype = IFM_50G_CR2,
 153                 .baudrate = IF_Gbps(50ULL),
 154         },
 155         [MLX5E_50GBASE_KR2] = {
 156                 .subtype = IFM_50G_KR2,
 157                 .baudrate = IF_Gbps(50ULL),
 158         },
 159 };
 160
 161 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
 162
 163 static void
 164 mlx5e_update_carrier(struct mlx5e_priv *priv)
 165 {
 166         struct mlx5_core_dev *mdev = priv->mdev;
 167         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 168         u32 eth_proto_oper;
 169         int error;
 170         u8 port_state;
 171         u8 is_er_type;
 172         u8 i;
 173
 174         port_state = mlx5_query_vport_state(mdev,
 175             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 176
 177         if (port_state == VPORT_STATE_UP) {
 178                 priv->media_status_last |= IFM_ACTIVE;
 179         } else {
 180                 priv->media_status_last &= ~IFM_ACTIVE;
 181                 priv->media_active_last = IFM_ETHER;
 182                 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
 183                 return;
 184         }
 185
 186         error = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
 187         if (error) {
 188                 priv->media_active_last = IFM_ETHER;
 189                 priv->ifp->if_baudrate = 1;
 190                 if_printf(priv->ifp, "%s: query port ptys failed: 0x%x\n",
 191                     __func__, error);
 192                 return;
 193         }
 194         eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
 195
 196         for (i = 0; i != MLX5E_LINK_MODES_NUMBER; i++) {
 197                 if (mlx5e_mode_table[i].baudrate == 0)
 198                         continue;
 199                 if (MLX5E_PROT_MASK(i) & eth_proto_oper) {
 200                         u32 subtype = mlx5e_mode_table[i].subtype;
 201
 202                         priv->ifp->if_baudrate =
 203                             mlx5e_mode_table[i].baudrate;
 204
 205                         switch (subtype) {
 206                         case IFM_10G_ER:
 207                                 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
 208                                 if (error != 0) {
 209                                         if_printf(priv->ifp, "%s: query port pddr failed: %d\n",
 210                                             __func__, error);
 211                                 }
 212                                 if (error != 0 || is_er_type == 0)
 213                                         subtype = IFM_10G_LR;
 214                                 break;
 215                         case IFM_40G_LR4:
 216                                 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
 217                                 if (error != 0) {
 218                                         if_printf(priv->ifp, "%s: query port pddr failed: %d\n",
 219                                             __func__, error);
 220                                 }
 221                                 if (error == 0 && is_er_type != 0)
 222                                         subtype = IFM_40G_ER4;
 223                                 break;
 224                         }
 225                         priv->media_active_last = subtype | IFM_ETHER | IFM_FDX;
 226                         break;
 227                 }
 228         }
 229         if_link_state_change(priv->ifp, LINK_STATE_UP);
 230 }
 231
 232 static void
 233 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
 234 {
 235         struct mlx5e_priv *priv = dev->if_softc;
 236
 237         ifmr->ifm_status = priv->media_status_last;
 238         ifmr->ifm_active = priv->media_active_last |
 239             (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
 240             (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
 241
 242 }
 243
 244 static u32
 245 mlx5e_find_link_mode(u32 subtype)
 246 {
 247         u32 i;
 248         u32 link_mode = 0;
 249
 250         switch (subtype) {
 251         case IFM_10G_LR:
 252                 subtype = IFM_10G_ER;
 253                 break;
 254         case IFM_40G_ER4:
 255                 subtype = IFM_40G_LR4;
 256                 break;
 257         }
 258
 259         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
 260                 if (mlx5e_mode_table[i].baudrate == 0)
 261                         continue;
 262                 if (mlx5e_mode_table[i].subtype == subtype)
 263                         link_mode |= MLX5E_PROT_MASK(i);
 264         }
 265
 266         return (link_mode);
 267 }
 268
 269 static int
 270 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv)
 271 {
 272         return (mlx5_set_port_pause_and_pfc(priv->mdev, 1,
 273             priv->params.rx_pauseframe_control,
 274             priv->params.tx_pauseframe_control,
 275             priv->params.rx_priority_flow_control,
 276             priv->params.tx_priority_flow_control));
 277 }
 278
 279 static int
 280 mlx5e_set_port_pfc(struct mlx5e_priv *priv)
 281 {
 282         int error;
 283
 284         if (priv->params.rx_pauseframe_control ||
 285             priv->params.tx_pauseframe_control) {
 286                 if_printf(priv->ifp,
 287                     "Global pauseframes must be disabled before enabling PFC.\n");
 288                 error = -EINVAL;
 289         } else {
 290                 error = mlx5e_set_port_pause_and_pfc(priv);
 291         }
 292         return (error);
 293 }
 294
 295 static int
 296 mlx5e_media_change(struct ifnet *dev)
 297 {
 298         struct mlx5e_priv *priv = dev->if_softc;
 299         struct mlx5_core_dev *mdev = priv->mdev;
 300         u32 eth_proto_cap;
 301         u32 link_mode;
 302         int was_opened;
 303         int locked;
 304         int error;
 305
 306         locked = PRIV_LOCKED(priv);
 307         if (!locked)
 308                 PRIV_LOCK(priv);
 309
 310         if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
 311                 error = EINVAL;
 312                 goto done;
 313         }
 314         link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media));
 315
 316         /* query supported capabilities */
 317         error = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
 318         if (error != 0) {
 319                 if_printf(dev, "Query port media capability failed\n");
 320                 goto done;
 321         }
 322         /* check for autoselect */
 323         if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
 324                 link_mode = eth_proto_cap;
 325                 if (link_mode == 0) {
 326                         if_printf(dev, "Port media capability is zero\n");
 327                         error = EINVAL;
 328                         goto done;
 329                 }
 330         } else {
 331                 link_mode = link_mode & eth_proto_cap;
 332                 if (link_mode == 0) {
 333                         if_printf(dev, "Not supported link mode requested\n");
 334                         error = EINVAL;
 335                         goto done;
 336                 }
 337         }
 338         if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
 339                 /* check if PFC is enabled */
 340                 if (priv->params.rx_priority_flow_control ||
 341                     priv->params.tx_priority_flow_control) {
 342                         if_printf(dev, "PFC must be disabled before enabling global pauseframes.\n");
 343                         error = EINVAL;
 344                         goto done;
 345                 }
 346         }
 347         /* update pauseframe control bits */
 348         priv->params.rx_pauseframe_control =
 349             (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
 350         priv->params.tx_pauseframe_control =
 351             (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
 352
 353         /* check if device is opened */
 354         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
 355
 356         /* reconfigure the hardware */
 357         mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
 358         mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN);
 359         error = -mlx5e_set_port_pause_and_pfc(priv);
 360         if (was_opened)
 361                 mlx5_set_port_status(mdev, MLX5_PORT_UP);
 362
 363 done:
 364         if (!locked)
 365                 PRIV_UNLOCK(priv);
 366         return (error);
 367 }
 368
 369 static void
 370 mlx5e_update_carrier_work(struct work_struct *work)
 371 {
 372         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 373             update_carrier_work);
 374
 375         PRIV_LOCK(priv);
 376         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 377                 mlx5e_update_carrier(priv);
 378         PRIV_UNLOCK(priv);
 379 }
 380
 381 /*
 382  * This function reads the physical port counters from the firmware
 383  * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
 384  * macros. The output is converted from big-endian 64-bit values into
 385  * host endian ones and stored in the "priv->stats.pport" structure.
 386  */
 387 static void
 388 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 389 {
 390         struct mlx5_core_dev *mdev = priv->mdev;
 391         struct mlx5e_pport_stats *s = &priv->stats.pport;
 392         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 393         u32 *in;
 394         u32 *out;
 395         const u64 *ptr;
 396         unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 397         unsigned x;
 398         unsigned y;
 399         unsigned z;
 400
 401         /* allocate firmware request structures */
 402         in = mlx5_vzalloc(sz);
 403         out = mlx5_vzalloc(sz);
 404         if (in == NULL || out == NULL)
 405                 goto free_out;
 406
 407         /*
 408          * Get pointer to the 64-bit counter set which is located at a
 409          * fixed offset in the output firmware request structure:
 410          */
 411         ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
 412
 413         MLX5_SET(ppcnt_reg, in, local_port, 1);
 414
 415         /* read IEEE802_3 counter group using predefined counter layout */
 416         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 417         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 418         for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM;
 419              x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
 420                 s->arg[y] = be64toh(ptr[x]);
 421
 422         /* read RFC2819 counter group using predefined counter layout */
 423         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 424         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 425         for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
 426                 s->arg[y] = be64toh(ptr[x]);
 427         for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
 428             MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
 429                 s_debug->arg[y] = be64toh(ptr[x]);
 430
 431         /* read RFC2863 counter group using predefined counter layout */
 432         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 433         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 434         for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
 435                 s_debug->arg[y] = be64toh(ptr[x]);
 436
 437         /* read physical layer stats counter group using predefined counter layout */
 438         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 439         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 440         for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
 441                 s_debug->arg[y] = be64toh(ptr[x]);
 442
 443         /* read Extended Ethernet counter group using predefined counter layout */
 444         MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
 445         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 446         for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++)
 447                 s_debug->arg[y] = be64toh(ptr[x]);
 448
 449         /* read per-priority counters */
 450         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 451
 452         /* iterate all the priorities */
 453         for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) {
 454                 MLX5_SET(ppcnt_reg, in, prio_tc, z);
 455                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 456
 457                 /* read per priority stats counter group using predefined counter layout */
 458                 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM /
 459                     MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++)
 460                         s->arg[y] = be64toh(ptr[x]);
 461         }
 462
 463 free_out:
 464         /* free firmware request structures */
 465         kvfree(in);
 466         kvfree(out);
 467 }
 468
 469 /*
 470  * This function is called regularly to collect all statistics
 471  * counters from the firmware. The values can be viewed through the
 472  * sysctl interface. Execution is serialized using the priv's global
 473  * configuration lock.
 474  */
 475 static void
 476 mlx5e_update_stats_work(struct work_struct *work)
 477 {
 478         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 479             update_stats_work);
 480         struct mlx5_core_dev *mdev = priv->mdev;
 481         struct mlx5e_vport_stats *s = &priv->stats.vport;
 482         struct mlx5e_sq_stats *sq_stats;
 483         struct buf_ring *sq_br;
 484 #if (__FreeBSD_version < 1100000)
 485         struct ifnet *ifp = priv->ifp;
 486 #endif
 487
 488         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 489         u32 *out;
 490         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 491         u64 tso_packets = 0;
 492         u64 tso_bytes = 0;
 493         u64 tx_queue_dropped = 0;
 494         u64 tx_defragged = 0;
 495         u64 tx_offload_none = 0;
 496         u64 lro_packets = 0;
 497         u64 lro_bytes = 0;
 498         u64 sw_lro_queued = 0;
 499         u64 sw_lro_flushed = 0;
 500         u64 rx_csum_none = 0;
 501         u64 rx_wqe_err = 0;
 502         u32 rx_out_of_buffer = 0;
 503         int i;
 504         int j;
 505
 506         PRIV_LOCK(priv);
 507         out = mlx5_vzalloc(outlen);
 508         if (out == NULL)
 509                 goto free_out;
 510         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
 511                 goto free_out;
 512
 513         /* Collect firts the SW counters and then HW for consistency */
 514         for (i = 0; i < priv->params.num_channels; i++) {
 515                 struct mlx5e_channel *pch = priv->channel + i;
 516                 struct mlx5e_rq *rq = &pch->rq;
 517                 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats;
 518
 519                 /* collect stats from LRO */
 520                 rq_stats->sw_lro_queued = rq->lro.lro_queued;
 521                 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
 522                 sw_lro_queued += rq_stats->sw_lro_queued;
 523                 sw_lro_flushed += rq_stats->sw_lro_flushed;
 524                 lro_packets += rq_stats->lro_packets;
 525                 lro_bytes += rq_stats->lro_bytes;
 526                 rx_csum_none += rq_stats->csum_none;
 527                 rx_wqe_err += rq_stats->wqe_err;
 528
 529                 for (j = 0; j < priv->num_tc; j++) {
 530                         sq_stats = &pch->sq[j].stats;
 531                         sq_br = pch->sq[j].br;
 532
 533                         tso_packets += sq_stats->tso_packets;
 534                         tso_bytes += sq_stats->tso_bytes;
 535                         tx_queue_dropped += sq_stats->dropped;
 536                         if (sq_br != NULL)
 537                                 tx_queue_dropped += sq_br->br_drops;
 538                         tx_defragged += sq_stats->defragged;
 539                         tx_offload_none += sq_stats->csum_offload_none;
 540                 }
 541         }
 542
 543         /* update counters */
 544         s->tso_packets = tso_packets;
 545         s->tso_bytes = tso_bytes;
 546         s->tx_queue_dropped = tx_queue_dropped;
 547         s->tx_defragged = tx_defragged;
 548         s->lro_packets = lro_packets;
 549         s->lro_bytes = lro_bytes;
 550         s->sw_lro_queued = sw_lro_queued;
 551         s->sw_lro_flushed = sw_lro_flushed;
 552         s->rx_csum_none = rx_csum_none;
 553         s->rx_wqe_err = rx_wqe_err;
 554
 555         /* HW counters */
 556         memset(in, 0, sizeof(in));
 557
 558         MLX5_SET(query_vport_counter_in, in, opcode,
 559             MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 560         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 561         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 562
 563         memset(out, 0, outlen);
 564
 565         /* get number of out-of-buffer drops first */
 566         if (mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
 567             &rx_out_of_buffer))
 568                 goto free_out;
 569
 570         /* accumulate difference into a 64-bit counter */
 571         s->rx_out_of_buffer += (u64)(u32)(rx_out_of_buffer - s->rx_out_of_buffer_prev);
 572         s->rx_out_of_buffer_prev = rx_out_of_buffer;
 573
 574         /* get port statistics */
 575         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
 576                 goto free_out;
 577
 578 #define MLX5_GET_CTR(out, x) \
 579         MLX5_GET64(query_vport_counter_out, out, x)
 580
 581         s->rx_error_packets =
 582             MLX5_GET_CTR(out, received_errors.packets);
 583         s->rx_error_bytes =
 584             MLX5_GET_CTR(out, received_errors.octets);
 585         s->tx_error_packets =
 586             MLX5_GET_CTR(out, transmit_errors.packets);
 587         s->tx_error_bytes =
 588             MLX5_GET_CTR(out, transmit_errors.octets);
 589
 590         s->rx_unicast_packets =
 591             MLX5_GET_CTR(out, received_eth_unicast.packets);
 592         s->rx_unicast_bytes =
 593             MLX5_GET_CTR(out, received_eth_unicast.octets);
 594         s->tx_unicast_packets =
 595             MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 596         s->tx_unicast_bytes =
 597             MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 598
 599         s->rx_multicast_packets =
 600             MLX5_GET_CTR(out, received_eth_multicast.packets);
 601         s->rx_multicast_bytes =
 602             MLX5_GET_CTR(out, received_eth_multicast.octets);
 603         s->tx_multicast_packets =
 604             MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 605         s->tx_multicast_bytes =
 606             MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 607
 608         s->rx_broadcast_packets =
 609             MLX5_GET_CTR(out, received_eth_broadcast.packets);
 610         s->rx_broadcast_bytes =
 611             MLX5_GET_CTR(out, received_eth_broadcast.octets);
 612         s->tx_broadcast_packets =
 613             MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 614         s->tx_broadcast_bytes =
 615             MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 616
 617         s->rx_packets =
 618             s->rx_unicast_packets +
 619             s->rx_multicast_packets +
 620             s->rx_broadcast_packets -
 621             s->rx_out_of_buffer;
 622         s->rx_bytes =
 623             s->rx_unicast_bytes +
 624             s->rx_multicast_bytes +
 625             s->rx_broadcast_bytes;
 626         s->tx_packets =
 627             s->tx_unicast_packets +
 628             s->tx_multicast_packets +
 629             s->tx_broadcast_packets;
 630         s->tx_bytes =
 631             s->tx_unicast_bytes +
 632             s->tx_multicast_bytes +
 633             s->tx_broadcast_bytes;
 634
 635         /* Update calculated offload counters */
 636         s->tx_csum_offload = s->tx_packets - tx_offload_none;
 637         s->rx_csum_good = s->rx_packets - s->rx_csum_none;
 638
 639         /* Get physical port counters */
 640         mlx5e_update_pport_counters(priv);
 641
 642         s->tx_jumbo_packets =
 643             priv->stats.port_stats_debug.tx_stat_p1519to2047octets +
 644             priv->stats.port_stats_debug.tx_stat_p2048to4095octets +
 645             priv->stats.port_stats_debug.tx_stat_p4096to8191octets +
 646             priv->stats.port_stats_debug.tx_stat_p8192to10239octets;
 647
 648 #if (__FreeBSD_version < 1100000)
 649         /* no get_counters interface in fbsd 10 */
 650         ifp->if_ipackets = s->rx_packets;
 651         ifp->if_ierrors = s->rx_error_packets +
 652             priv->stats.pport.alignment_err +
 653             priv->stats.pport.check_seq_err +
 654             priv->stats.pport.crc_align_errors +
 655             priv->stats.pport.in_range_len_errors +
 656             priv->stats.pport.jabbers +
 657             priv->stats.pport.out_of_range_len +
 658             priv->stats.pport.oversize_pkts +
 659             priv->stats.pport.symbol_err +
 660             priv->stats.pport.too_long_errors +
 661             priv->stats.pport.undersize_pkts +
 662             priv->stats.pport.unsupported_op_rx;
 663         ifp->if_iqdrops = s->rx_out_of_buffer +
 664             priv->stats.pport.drop_events;
 665         ifp->if_opackets = s->tx_packets;
 666         ifp->if_oerrors = s->tx_error_packets;
 667         ifp->if_snd.ifq_drops = s->tx_queue_dropped;
 668         ifp->if_ibytes = s->rx_bytes;
 669         ifp->if_obytes = s->tx_bytes;
 670         ifp->if_collisions =
 671             priv->stats.pport.collisions;
 672 #endif
 673
 674 free_out:
 675         kvfree(out);
 676
 677         /* Update diagnostics, if any */
 678         if (priv->params_ethtool.diag_pci_enable ||
 679             priv->params_ethtool.diag_general_enable) {
 680                 int error = mlx5_core_get_diagnostics_full(mdev,
 681                     priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL,
 682                     priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL);
 683                 if (error != 0)
 684                         if_printf(priv->ifp, "Failed reading diagnostics: %d\n", error);
 685         }
 686         PRIV_UNLOCK(priv);
 687 }
 688
 689 static void
 690 mlx5e_update_stats(void *arg)
 691 {
 692         struct mlx5e_priv *priv = arg;
 693
 694         queue_work(priv->wq, &priv->update_stats_work);
 695
 696         callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
 697 }
 698
 699 static void
 700 mlx5e_async_event_sub(struct mlx5e_priv *priv,
 701     enum mlx5_dev_event event)
 702 {
 703         switch (event) {
 704         case MLX5_DEV_EVENT_PORT_UP:
 705         case MLX5_DEV_EVENT_PORT_DOWN:
 706                 queue_work(priv->wq, &priv->update_carrier_work);
 707                 break;
 708
 709         default:
 710                 break;
 711         }
 712 }
 713
 714 static void
 715 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 716     enum mlx5_dev_event event, unsigned long param)
 717 {
 718         struct mlx5e_priv *priv = vpriv;
 719
 720         mtx_lock(&priv->async_events_mtx);
 721         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 722                 mlx5e_async_event_sub(priv, event);
 723         mtx_unlock(&priv->async_events_mtx);
 724 }
 725
 726 static void
 727 mlx5e_enable_async_events(struct mlx5e_priv *priv)
 728 {
 729         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 730 }
 731
 732 static void
 733 mlx5e_disable_async_events(struct mlx5e_priv *priv)
 734 {
 735         mtx_lock(&priv->async_events_mtx);
 736         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 737         mtx_unlock(&priv->async_events_mtx);
 738 }
 739
 740 static void mlx5e_calibration_callout(void *arg);
 741 static int mlx5e_calibration_duration = 20;
 742 static int mlx5e_fast_calibration = 1;
 743 static int mlx5e_normal_calibration = 30;
 744
 745 static SYSCTL_NODE(_hw_mlx5, OID_AUTO, calibr, CTLFLAG_RW, 0,
 746     "MLX5 timestamp calibration parameteres");
 747
 748 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, duration, CTLFLAG_RWTUN,
 749     &mlx5e_calibration_duration, 0,
 750     "Duration of initial calibration");
 751 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, fast, CTLFLAG_RWTUN,
 752     &mlx5e_fast_calibration, 0,
 753     "Recalibration interval during initial calibration");
 754 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, normal, CTLFLAG_RWTUN,
 755     &mlx5e_normal_calibration, 0,
 756     "Recalibration interval during normal operations");
 757
 758 /*
 759  * Ignites the calibration process.
 760  */
 761 static void
 762 mlx5e_reset_calibration_callout(struct mlx5e_priv *priv)
 763 {
 764
 765         if (priv->clbr_done == 0)
 766                 mlx5e_calibration_callout(priv);
 767         else
 768                 callout_reset_curcpu(&priv->tstmp_clbr, (priv->clbr_done <
 769                     mlx5e_calibration_duration ? mlx5e_fast_calibration :
 770                     mlx5e_normal_calibration) * hz, mlx5e_calibration_callout,
 771                     priv);
 772 }
 773
 774 static uint64_t
 775 mlx5e_timespec2usec(const struct timespec *ts)
 776 {
 777
 778         return ((uint64_t)ts->tv_sec * 1000000000 + ts->tv_nsec);
 779 }
 780
 781 static uint64_t
 782 mlx5e_hw_clock(struct mlx5e_priv *priv)
 783 {
 784         struct mlx5_init_seg *iseg;
 785         uint32_t hw_h, hw_h1, hw_l;
 786
 787         iseg = priv->mdev->iseg;
 788         do {
 789                 hw_h = ioread32be(&iseg->internal_timer_h);
 790                 hw_l = ioread32be(&iseg->internal_timer_l);
 791                 hw_h1 = ioread32be(&iseg->internal_timer_h);
 792         } while (hw_h1 != hw_h);
 793         return (((uint64_t)hw_h << 32) | hw_l);
 794 }
 795
 796 /*
 797  * The calibration callout, it runs either in the context of the
 798  * thread which enables calibration, or in callout.  It takes the
 799  * snapshot of system and adapter clocks, then advances the pointers to
 800  * the calibration point to allow rx path to read the consistent data
 801  * lockless.
 802  */
 803 static void
 804 mlx5e_calibration_callout(void *arg)
 805 {
 806         struct mlx5e_priv *priv;
 807         struct mlx5e_clbr_point *next, *curr;
 808         struct timespec ts;
 809         int clbr_curr_next;
 810
 811         priv = arg;
 812         curr = &priv->clbr_points[priv->clbr_curr];
 813         clbr_curr_next = priv->clbr_curr + 1;
 814         if (clbr_curr_next >= nitems(priv->clbr_points))
 815                 clbr_curr_next = 0;
 816         next = &priv->clbr_points[clbr_curr_next];
 817
 818         next->base_prev = curr->base_curr;
 819         next->clbr_hw_prev = curr->clbr_hw_curr;
 820
 821         next->clbr_hw_curr = mlx5e_hw_clock(priv);
 822         if (((next->clbr_hw_curr - curr->clbr_hw_prev) >> MLX5E_TSTMP_PREC) ==
 823             0) {
 824                 if_printf(priv->ifp, "HW failed tstmp frozen %#jx %#jx,"
 825                     "disabling\n", next->clbr_hw_curr, curr->clbr_hw_prev);
 826                 priv->clbr_done = 0;
 827                 return;
 828         }
 829
 830         nanouptime(&ts);
 831         next->base_curr = mlx5e_timespec2usec(&ts);
 832
 833         curr->clbr_gen = 0;
 834         atomic_thread_fence_rel();
 835         priv->clbr_curr = clbr_curr_next;
 836         atomic_store_rel_int(&next->clbr_gen, ++(priv->clbr_gen));
 837
 838         if (priv->clbr_done < mlx5e_calibration_duration)
 839                 priv->clbr_done++;
 840         mlx5e_reset_calibration_callout(priv);
 841 }
 842
 843 static const char *mlx5e_rq_stats_desc[] = {
 844         MLX5E_RQ_STATS(MLX5E_STATS_DESC)
 845 };
 846
 847 static int
 848 mlx5e_create_rq(struct mlx5e_channel *c,
 849     struct mlx5e_rq_param *param,
 850     struct mlx5e_rq *rq)
 851 {
 852         struct mlx5e_priv *priv = c->priv;
 853         struct mlx5_core_dev *mdev = priv->mdev;
 854         char buffer[16];
 855         void *rqc = param->rqc;
 856         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 857         int wq_sz;
 858         int err;
 859         int i;
 860         u32 nsegs, wqe_sz;
 861
 862         err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
 863         if (err != 0)
 864                 goto done;
 865
 866         /* Create DMA descriptor TAG */
 867         if ((err = -bus_dma_tag_create(
 868             bus_get_dma_tag(mdev->pdev->dev.bsddev),
 869             1,                          /* any alignment */
 870             0,                          /* no boundary */
 871             BUS_SPACE_MAXADDR,          /* lowaddr */
 872             BUS_SPACE_MAXADDR,          /* highaddr */
 873             NULL, NULL,                 /* filter, filterarg */
 874             nsegs * MLX5E_MAX_RX_BYTES, /* maxsize */
 875             nsegs,                      /* nsegments */
 876             nsegs * MLX5E_MAX_RX_BYTES, /* maxsegsize */
 877             0,                          /* flags */
 878             NULL, NULL,                 /* lockfunc, lockfuncarg */
 879             &rq->dma_tag)))
 880                 goto done;
 881
 882         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 883             &rq->wq_ctrl);
 884         if (err)
 885                 goto err_free_dma_tag;
 886
 887         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 888
 889         err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs);
 890         if (err != 0)
 891                 goto err_rq_wq_destroy;
 892
 893         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 894
 895         err = -tcp_lro_init_args(&rq->lro, c->tag.m_snd_tag.ifp, TCP_LRO_ENTRIES, wq_sz);
 896         if (err)
 897                 goto err_rq_wq_destroy;
 898
 899         rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
 900         for (i = 0; i != wq_sz; i++) {
 901                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 902 #if (MLX5E_MAX_RX_SEGS == 1)
 903                 uint32_t byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 904 #else
 905                 int j;
 906 #endif
 907
 908                 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
 909                 if (err != 0) {
 910                         while (i--)
 911                                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 912                         goto err_rq_mbuf_free;
 913                 }
 914
 915                 /* set value for constant fields */
 916 #if (MLX5E_MAX_RX_SEGS == 1)
 917                 wqe->data[0].lkey = c->mkey_be;
 918                 wqe->data[0].byte_count = cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
 919 #else
 920                 for (j = 0; j < rq->nsegs; j++)
 921                         wqe->data[j].lkey = c->mkey_be;
 922 #endif
 923         }
 924
 925         INIT_WORK(&rq->dim.work, mlx5e_dim_work);
 926         if (priv->params.rx_cq_moderation_mode < 2) {
 927                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
 928         } else {
 929                 void *cqc = container_of(param,
 930                     struct mlx5e_channel_param, rq)->rx_cq.cqc;
 931
 932                 switch (MLX5_GET(cqc, cqc, cq_period_mode)) {
 933                 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 934                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 935                         break;
 936                 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 937                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 938                         break;
 939                 default:
 940                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
 941                         break;
 942                 }
 943         }
 944
 945         rq->ifp = c->tag.m_snd_tag.ifp;
 946         rq->channel = c;
 947         rq->ix = c->ix;
 948
 949         snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
 950         mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
 951             buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
 952             rq->stats.arg);
 953         return (0);
 954
 955 err_rq_mbuf_free:
 956         free(rq->mbuf, M_MLX5EN);
 957         tcp_lro_free(&rq->lro);
 958 err_rq_wq_destroy:
 959         mlx5_wq_destroy(&rq->wq_ctrl);
 960 err_free_dma_tag:
 961         bus_dma_tag_destroy(rq->dma_tag);
 962 done:
 963         return (err);
 964 }
 965
 966 static void
 967 mlx5e_destroy_rq(struct mlx5e_rq *rq)
 968 {
 969         int wq_sz;
 970         int i;
 971
 972         /* destroy all sysctl nodes */
 973         sysctl_ctx_free(&rq->stats.ctx);
 974
 975         /* free leftover LRO packets, if any */
 976         tcp_lro_free(&rq->lro);
 977
 978         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 979         for (i = 0; i != wq_sz; i++) {
 980                 if (rq->mbuf[i].mbuf != NULL) {
 981                         bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map);
 982                         m_freem(rq->mbuf[i].mbuf);
 983                 }
 984                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 985         }
 986         free(rq->mbuf, M_MLX5EN);
 987         mlx5_wq_destroy(&rq->wq_ctrl);
 988 }
 989
 990 static int
 991 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 992 {
 993         struct mlx5e_channel *c = rq->channel;
 994         struct mlx5e_priv *priv = c->priv;
 995         struct mlx5_core_dev *mdev = priv->mdev;
 996
 997         void *in;
 998         void *rqc;
 999         void *wq;
1000         int inlen;
1001         int err;
1002
1003         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
1004             sizeof(u64) * rq->wq_ctrl.buf.npages;
1005         in = mlx5_vzalloc(inlen);
1006         if (in == NULL)
1007                 return (-ENOMEM);
1008
1009         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1010         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1011
1012         memcpy(rqc, param->rqc, sizeof(param->rqc));
1013
1014         MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
1015         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1016         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1017         if (priv->counter_set_id >= 0)
1018                 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
1019         MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
1020             PAGE_SHIFT);
1021         MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
1022
1023         mlx5_fill_page_array(&rq->wq_ctrl.buf,
1024             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1025
1026         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
1027
1028         kvfree(in);
1029
1030         return (err);
1031 }
1032
1033 static int
1034 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
1035 {
1036         struct mlx5e_channel *c = rq->channel;
1037         struct mlx5e_priv *priv = c->priv;
1038         struct mlx5_core_dev *mdev = priv->mdev;
1039
1040         void *in;
1041         void *rqc;
1042         int inlen;
1043         int err;
1044
1045         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1046         in = mlx5_vzalloc(inlen);
1047         if (in == NULL)
1048                 return (-ENOMEM);
1049
1050         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1051
1052         MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
1053         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
1054         MLX5_SET(rqc, rqc, state, next_state);
1055
1056         err = mlx5_core_modify_rq(mdev, in, inlen);
1057
1058         kvfree(in);
1059
1060         return (err);
1061 }
1062
1063 static void
1064 mlx5e_disable_rq(struct mlx5e_rq *rq)
1065 {
1066         struct mlx5e_channel *c = rq->channel;
1067         struct mlx5e_priv *priv = c->priv;
1068         struct mlx5_core_dev *mdev = priv->mdev;
1069
1070         mlx5_core_destroy_rq(mdev, rq->rqn);
1071 }
1072
1073 static int
1074 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
1075 {
1076         struct mlx5e_channel *c = rq->channel;
1077         struct mlx5e_priv *priv = c->priv;
1078         struct mlx5_wq_ll *wq = &rq->wq;
1079         int i;
1080
1081         for (i = 0; i < 1000; i++) {
1082                 if (wq->cur_sz >= priv->params.min_rx_wqes)
1083                         return (0);
1084
1085                 msleep(4);
1086         }
1087         return (-ETIMEDOUT);
1088 }
1089
1090 static int
1091 mlx5e_open_rq(struct mlx5e_channel *c,
1092     struct mlx5e_rq_param *param,
1093     struct mlx5e_rq *rq)
1094 {
1095         int err;
1096
1097         err = mlx5e_create_rq(c, param, rq);
1098         if (err)
1099                 return (err);
1100
1101         err = mlx5e_enable_rq(rq, param);
1102         if (err)
1103                 goto err_destroy_rq;
1104
1105         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1106         if (err)
1107                 goto err_disable_rq;
1108
1109         c->rq.enabled = 1;
1110
1111         return (0);
1112
1113 err_disable_rq:
1114         mlx5e_disable_rq(rq);
1115 err_destroy_rq:
1116         mlx5e_destroy_rq(rq);
1117
1118         return (err);
1119 }
1120
1121 static void
1122 mlx5e_close_rq(struct mlx5e_rq *rq)
1123 {
1124         mtx_lock(&rq->mtx);
1125         rq->enabled = 0;
1126         callout_stop(&rq->watchdog);
1127         mtx_unlock(&rq->mtx);
1128
1129         callout_drain(&rq->watchdog);
1130
1131         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
1132 }
1133
1134 static void
1135 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
1136 {
1137         struct mlx5_core_dev *mdev = rq->channel->priv->mdev;
1138
1139         /* wait till RQ is empty */
1140         while (!mlx5_wq_ll_is_empty(&rq->wq) &&
1141                (mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR)) {
1142                 msleep(4);
1143                 rq->cq.mcq.comp(&rq->cq.mcq);
1144         }
1145
1146         cancel_work_sync(&rq->dim.work);
1147         mlx5e_disable_rq(rq);
1148         mlx5e_destroy_rq(rq);
1149 }
1150
1151 void
1152 mlx5e_free_sq_db(struct mlx5e_sq *sq)
1153 {
1154         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1155         int x;
1156
1157         for (x = 0; x != wq_sz; x++)
1158                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1159         free(sq->mbuf, M_MLX5EN);
1160 }
1161
1162 int
1163 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
1164 {
1165         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1166         int err;
1167         int x;
1168
1169         sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1170
1171         /* Create DMA descriptor MAPs */
1172         for (x = 0; x != wq_sz; x++) {
1173                 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
1174                 if (err != 0) {
1175                         while (x--)
1176                                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1177                         free(sq->mbuf, M_MLX5EN);
1178                         return (err);
1179                 }
1180         }
1181         return (0);
1182 }
1183
1184 static const char *mlx5e_sq_stats_desc[] = {
1185         MLX5E_SQ_STATS(MLX5E_STATS_DESC)
1186 };
1187
1188 void
1189 mlx5e_update_sq_inline(struct mlx5e_sq *sq)
1190 {
1191         sq->max_inline = sq->priv->params.tx_max_inline;
1192         sq->min_inline_mode = sq->priv->params.tx_min_inline_mode;
1193
1194         /*
1195          * Check if trust state is DSCP or if inline mode is NONE which
1196          * indicates CX-5 or newer hardware.
1197          */
1198         if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP ||
1199             sq->min_inline_mode == MLX5_INLINE_MODE_NONE) {
1200                 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert))
1201                         sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN;
1202                 else
1203                         sq->min_insert_caps = MLX5E_INSERT_NON_VLAN;
1204         } else {
1205                 sq->min_insert_caps = 0;
1206         }
1207 }
1208
1209 static void
1210 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1211 {
1212         int i;
1213
1214         for (i = 0; i != c->num_tc; i++) {
1215                 mtx_lock(&c->sq[i].lock);
1216                 mlx5e_update_sq_inline(&c->sq[i]);
1217                 mtx_unlock(&c->sq[i].lock);
1218         }
1219 }
1220
1221 void
1222 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv)
1223 {
1224         int i;
1225
1226         /* check if channels are closed */
1227         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
1228                 return;
1229
1230         for (i = 0; i < priv->params.num_channels; i++)
1231                 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]);
1232 }
1233
1234 static int
1235 mlx5e_create_sq(struct mlx5e_channel *c,
1236     int tc,
1237     struct mlx5e_sq_param *param,
1238     struct mlx5e_sq *sq)
1239 {
1240         struct mlx5e_priv *priv = c->priv;
1241         struct mlx5_core_dev *mdev = priv->mdev;
1242         char buffer[16];
1243         void *sqc = param->sqc;
1244         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1245         int err;
1246
1247         /* Create DMA descriptor TAG */
1248         if ((err = -bus_dma_tag_create(
1249             bus_get_dma_tag(mdev->pdev->dev.bsddev),
1250             1,                          /* any alignment */
1251             0,                          /* no boundary */
1252             BUS_SPACE_MAXADDR,          /* lowaddr */
1253             BUS_SPACE_MAXADDR,          /* highaddr */
1254             NULL, NULL,                 /* filter, filterarg */
1255             MLX5E_MAX_TX_PAYLOAD_SIZE,  /* maxsize */
1256             MLX5E_MAX_TX_MBUF_FRAGS,    /* nsegments */
1257             MLX5E_MAX_TX_MBUF_SIZE,     /* maxsegsize */
1258             0,                          /* flags */
1259             NULL, NULL,                 /* lockfunc, lockfuncarg */
1260             &sq->dma_tag)))
1261                 goto done;
1262
1263         err = mlx5_alloc_map_uar(mdev, &sq->uar);
1264         if (err)
1265                 goto err_free_dma_tag;
1266
1267         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
1268             &sq->wq_ctrl);
1269         if (err)
1270                 goto err_unmap_free_uar;
1271
1272         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1273         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1274
1275         err = mlx5e_alloc_sq_db(sq);
1276         if (err)
1277                 goto err_sq_wq_destroy;
1278
1279         sq->mkey_be = c->mkey_be;
1280         sq->ifp = priv->ifp;
1281         sq->priv = priv;
1282         sq->tc = tc;
1283
1284         mlx5e_update_sq_inline(sq);
1285
1286         snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1287         mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1288             buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1289             sq->stats.arg);
1290
1291         return (0);
1292
1293 err_sq_wq_destroy:
1294         mlx5_wq_destroy(&sq->wq_ctrl);
1295
1296 err_unmap_free_uar:
1297         mlx5_unmap_free_uar(mdev, &sq->uar);
1298
1299 err_free_dma_tag:
1300         bus_dma_tag_destroy(sq->dma_tag);
1301 done:
1302         return (err);
1303 }
1304
1305 static void
1306 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1307 {
1308         /* destroy all sysctl nodes */
1309         sysctl_ctx_free(&sq->stats.ctx);
1310
1311         mlx5e_free_sq_db(sq);
1312         mlx5_wq_destroy(&sq->wq_ctrl);
1313         mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1314 }
1315
1316 int
1317 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1318     int tis_num)
1319 {
1320         void *in;
1321         void *sqc;
1322         void *wq;
1323         int inlen;
1324         int err;
1325
1326         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1327             sizeof(u64) * sq->wq_ctrl.buf.npages;
1328         in = mlx5_vzalloc(inlen);
1329         if (in == NULL)
1330                 return (-ENOMEM);
1331
1332         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1333         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1334
1335         memcpy(sqc, param->sqc, sizeof(param->sqc));
1336
1337         MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1338         MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1339         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1340         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1341         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1342
1343         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1344         MLX5_SET(wq, wq, uar_page, sq->uar.index);
1345         MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1346             PAGE_SHIFT);
1347         MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1348
1349         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1350             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1351
1352         err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1353
1354         kvfree(in);
1355
1356         return (err);
1357 }
1358
1359 int
1360 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1361 {
1362         void *in;
1363         void *sqc;
1364         int inlen;
1365         int err;
1366
1367         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1368         in = mlx5_vzalloc(inlen);
1369         if (in == NULL)
1370                 return (-ENOMEM);
1371
1372         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1373
1374         MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1375         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1376         MLX5_SET(sqc, sqc, state, next_state);
1377
1378         err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1379
1380         kvfree(in);
1381
1382         return (err);
1383 }
1384
1385 void
1386 mlx5e_disable_sq(struct mlx5e_sq *sq)
1387 {
1388
1389         mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1390 }
1391
1392 static int
1393 mlx5e_open_sq(struct mlx5e_channel *c,
1394     int tc,
1395     struct mlx5e_sq_param *param,
1396     struct mlx5e_sq *sq)
1397 {
1398         int err;
1399
1400         err = mlx5e_create_sq(c, tc, param, sq);
1401         if (err)
1402                 return (err);
1403
1404         err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1405         if (err)
1406                 goto err_destroy_sq;
1407
1408         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1409         if (err)
1410                 goto err_disable_sq;
1411
1412         WRITE_ONCE(sq->running, 1);
1413
1414         return (0);
1415
1416 err_disable_sq:
1417         mlx5e_disable_sq(sq);
1418 err_destroy_sq:
1419         mlx5e_destroy_sq(sq);
1420
1421         return (err);
1422 }
1423
1424 static void
1425 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1426 {
1427         /* fill up remainder with NOPs */
1428         while (sq->cev_counter != 0) {
1429                 while (!mlx5e_sq_has_room_for(sq, 1)) {
1430                         if (can_sleep != 0) {
1431                                 mtx_unlock(&sq->lock);
1432                                 msleep(4);
1433                                 mtx_lock(&sq->lock);
1434                         } else {
1435                                 goto done;
1436                         }
1437                 }
1438                 /* send a single NOP */
1439                 mlx5e_send_nop(sq, 1);
1440                 atomic_thread_fence_rel();
1441         }
1442 done:
1443         /* Check if we need to write the doorbell */
1444         if (likely(sq->doorbell.d64 != 0)) {
1445                 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1446                 sq->doorbell.d64 = 0;
1447         }
1448 }
1449
1450 void
1451 mlx5e_sq_cev_timeout(void *arg)
1452 {
1453         struct mlx5e_sq *sq = arg;
1454
1455         mtx_assert(&sq->lock, MA_OWNED);
1456
1457         /* check next state */
1458         switch (sq->cev_next_state) {
1459         case MLX5E_CEV_STATE_SEND_NOPS:
1460                 /* fill TX ring with NOPs, if any */
1461                 mlx5e_sq_send_nops_locked(sq, 0);
1462
1463                 /* check if completed */
1464                 if (sq->cev_counter == 0) {
1465                         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1466                         return;
1467                 }
1468                 break;
1469         default:
1470                 /* send NOPs on next timeout */
1471                 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1472                 break;
1473         }
1474
1475         /* restart timer */
1476         callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1477 }
1478
1479 void
1480 mlx5e_drain_sq(struct mlx5e_sq *sq)
1481 {
1482         int error;
1483         struct mlx5_core_dev *mdev= sq->priv->mdev;
1484
1485         /*
1486          * Check if already stopped.
1487          *
1488          * NOTE: Serialization of this function is managed by the
1489          * caller ensuring the priv's state lock is locked or in case
1490          * of rate limit support, a single thread manages drain and
1491          * resume of SQs. The "running" variable can therefore safely
1492          * be read without any locks.
1493          */
1494         if (READ_ONCE(sq->running) == 0)
1495                 return;
1496
1497         /* don't put more packets into the SQ */
1498         WRITE_ONCE(sq->running, 0);
1499
1500         /* serialize access to DMA rings */
1501         mtx_lock(&sq->lock);
1502
1503         /* teardown event factor timer, if any */
1504         sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1505         callout_stop(&sq->cev_callout);
1506
1507         /* send dummy NOPs in order to flush the transmit ring */
1508         mlx5e_sq_send_nops_locked(sq, 1);
1509         mtx_unlock(&sq->lock);
1510
1511         /* make sure it is safe to free the callout */
1512         callout_drain(&sq->cev_callout);
1513
1514         /* wait till SQ is empty or link is down */
1515         mtx_lock(&sq->lock);
1516         while (sq->cc != sq->pc &&
1517             (sq->priv->media_status_last & IFM_ACTIVE) != 0 &&
1518             mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1519                 mtx_unlock(&sq->lock);
1520                 msleep(1);
1521                 sq->cq.mcq.comp(&sq->cq.mcq);
1522                 mtx_lock(&sq->lock);
1523         }
1524         mtx_unlock(&sq->lock);
1525
1526         /* error out remaining requests */
1527         error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1528         if (error != 0) {
1529                 if_printf(sq->ifp,
1530                     "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error);
1531         }
1532
1533         /* wait till SQ is empty */
1534         mtx_lock(&sq->lock);
1535         while (sq->cc != sq->pc &&
1536                mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1537                 mtx_unlock(&sq->lock);
1538                 msleep(1);
1539                 sq->cq.mcq.comp(&sq->cq.mcq);
1540                 mtx_lock(&sq->lock);
1541         }
1542         mtx_unlock(&sq->lock);
1543 }
1544
1545 static void
1546 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1547 {
1548
1549         mlx5e_drain_sq(sq);
1550         mlx5e_disable_sq(sq);
1551         mlx5e_destroy_sq(sq);
1552 }
1553
1554 static int
1555 mlx5e_create_cq(struct mlx5e_priv *priv,
1556     struct mlx5e_cq_param *param,
1557     struct mlx5e_cq *cq,
1558     mlx5e_cq_comp_t *comp,
1559     int eq_ix)
1560 {
1561         struct mlx5_core_dev *mdev = priv->mdev;
1562         struct mlx5_core_cq *mcq = &cq->mcq;
1563         int eqn_not_used;
1564         int irqn;
1565         int err;
1566         u32 i;
1567
1568         param->wq.buf_numa_node = 0;
1569         param->wq.db_numa_node = 0;
1570
1571         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1572             &cq->wq_ctrl);
1573         if (err)
1574                 return (err);
1575
1576         mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1577
1578         mcq->cqe_sz = 64;
1579         mcq->set_ci_db = cq->wq_ctrl.db.db;
1580         mcq->arm_db = cq->wq_ctrl.db.db + 1;
1581         *mcq->set_ci_db = 0;
1582         *mcq->arm_db = 0;
1583         mcq->vector = eq_ix;
1584         mcq->comp = comp;
1585         mcq->event = mlx5e_cq_error_event;
1586         mcq->irqn = irqn;
1587         mcq->uar = &priv->cq_uar;
1588
1589         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1590                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1591
1592                 cqe->op_own = 0xf1;
1593         }
1594
1595         cq->priv = priv;
1596
1597         return (0);
1598 }
1599
1600 static void
1601 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1602 {
1603         mlx5_wq_destroy(&cq->wq_ctrl);
1604 }
1605
1606 static int
1607 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1608 {
1609         struct mlx5_core_cq *mcq = &cq->mcq;
1610         void *in;
1611         void *cqc;
1612         int inlen;
1613         int irqn_not_used;
1614         int eqn;
1615         int err;
1616
1617         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1618             sizeof(u64) * cq->wq_ctrl.buf.npages;
1619         in = mlx5_vzalloc(inlen);
1620         if (in == NULL)
1621                 return (-ENOMEM);
1622
1623         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1624
1625         memcpy(cqc, param->cqc, sizeof(param->cqc));
1626
1627         mlx5_fill_page_array(&cq->wq_ctrl.buf,
1628             (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1629
1630         mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
1631
1632         MLX5_SET(cqc, cqc, c_eqn, eqn);
1633         MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1634         MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1635             PAGE_SHIFT);
1636         MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1637
1638         err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
1639
1640         kvfree(in);
1641
1642         if (err)
1643                 return (err);
1644
1645         mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock));
1646
1647         return (0);
1648 }
1649
1650 static void
1651 mlx5e_disable_cq(struct mlx5e_cq *cq)
1652 {
1653
1654         mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
1655 }
1656
1657 int
1658 mlx5e_open_cq(struct mlx5e_priv *priv,
1659     struct mlx5e_cq_param *param,
1660     struct mlx5e_cq *cq,
1661     mlx5e_cq_comp_t *comp,
1662     int eq_ix)
1663 {
1664         int err;
1665
1666         err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
1667         if (err)
1668                 return (err);
1669
1670         err = mlx5e_enable_cq(cq, param, eq_ix);
1671         if (err)
1672                 goto err_destroy_cq;
1673
1674         return (0);
1675
1676 err_destroy_cq:
1677         mlx5e_destroy_cq(cq);
1678
1679         return (err);
1680 }
1681
1682 void
1683 mlx5e_close_cq(struct mlx5e_cq *cq)
1684 {
1685         mlx5e_disable_cq(cq);
1686         mlx5e_destroy_cq(cq);
1687 }
1688
1689 static int
1690 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1691     struct mlx5e_channel_param *cparam)
1692 {
1693         int err;
1694         int tc;
1695
1696         for (tc = 0; tc < c->num_tc; tc++) {
1697                 /* open completion queue */
1698                 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
1699                     &mlx5e_tx_cq_comp, c->ix);
1700                 if (err)
1701                         goto err_close_tx_cqs;
1702         }
1703         return (0);
1704
1705 err_close_tx_cqs:
1706         for (tc--; tc >= 0; tc--)
1707                 mlx5e_close_cq(&c->sq[tc].cq);
1708
1709         return (err);
1710 }
1711
1712 static void
1713 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1714 {
1715         int tc;
1716
1717         for (tc = 0; tc < c->num_tc; tc++)
1718                 mlx5e_close_cq(&c->sq[tc].cq);
1719 }
1720
1721 static int
1722 mlx5e_open_sqs(struct mlx5e_channel *c,
1723     struct mlx5e_channel_param *cparam)
1724 {
1725         int err;
1726         int tc;
1727
1728         for (tc = 0; tc < c->num_tc; tc++) {
1729                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1730                 if (err)
1731                         goto err_close_sqs;
1732         }
1733
1734         return (0);
1735
1736 err_close_sqs:
1737         for (tc--; tc >= 0; tc--)
1738                 mlx5e_close_sq_wait(&c->sq[tc]);
1739
1740         return (err);
1741 }
1742
1743 static void
1744 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
1745 {
1746         int tc;
1747
1748         for (tc = 0; tc < c->num_tc; tc++)
1749                 mlx5e_close_sq_wait(&c->sq[tc]);
1750 }
1751
1752 static void
1753 mlx5e_chan_mtx_init(struct mlx5e_channel *c)
1754 {
1755         int tc;
1756
1757         mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
1758
1759         callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
1760
1761         for (tc = 0; tc < c->num_tc; tc++) {
1762                 struct mlx5e_sq *sq = c->sq + tc;
1763
1764                 mtx_init(&sq->lock, "mlx5tx",
1765                     MTX_NETWORK_LOCK " TX", MTX_DEF);
1766                 mtx_init(&sq->comp_lock, "mlx5comp",
1767                     MTX_NETWORK_LOCK " TX", MTX_DEF);
1768
1769                 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
1770
1771                 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1772
1773                 /* ensure the TX completion event factor is not zero */
1774                 if (sq->cev_factor == 0)
1775                         sq->cev_factor = 1;
1776         }
1777 }
1778
1779 static void
1780 mlx5e_chan_mtx_destroy(struct mlx5e_channel *c)
1781 {
1782         int tc;
1783
1784         mtx_destroy(&c->rq.mtx);
1785
1786         for (tc = 0; tc < c->num_tc; tc++) {
1787                 mtx_destroy(&c->sq[tc].lock);
1788                 mtx_destroy(&c->sq[tc].comp_lock);
1789         }
1790 }
1791
1792 static int
1793 mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1794     struct mlx5e_channel_param *cparam,
1795     struct mlx5e_channel *c)
1796 {
1797         int err;
1798
1799         memset(c, 0, sizeof(*c));
1800
1801         c->priv = priv;
1802         c->ix = ix;
1803         /* setup send tag */
1804         c->tag.m_snd_tag.ifp = priv->ifp;
1805         c->tag.type = IF_SND_TAG_TYPE_UNLIMITED;
1806         c->mkey_be = cpu_to_be32(priv->mr.key);
1807         c->num_tc = priv->num_tc;
1808
1809         /* init mutexes */
1810         mlx5e_chan_mtx_init(c);
1811
1812         /* open transmit completion queue */
1813         err = mlx5e_open_tx_cqs(c, cparam);
1814         if (err)
1815                 goto err_free;
1816
1817         /* open receive completion queue */
1818         err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
1819             &mlx5e_rx_cq_comp, c->ix);
1820         if (err)
1821                 goto err_close_tx_cqs;
1822
1823         err = mlx5e_open_sqs(c, cparam);
1824         if (err)
1825                 goto err_close_rx_cq;
1826
1827         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1828         if (err)
1829                 goto err_close_sqs;
1830
1831         /* poll receive queue initially */
1832         c->rq.cq.mcq.comp(&c->rq.cq.mcq);
1833
1834         return (0);
1835
1836 err_close_sqs:
1837         mlx5e_close_sqs_wait(c);
1838
1839 err_close_rx_cq:
1840         mlx5e_close_cq(&c->rq.cq);
1841
1842 err_close_tx_cqs:
1843         mlx5e_close_tx_cqs(c);
1844
1845 err_free:
1846         /* destroy mutexes */
1847         mlx5e_chan_mtx_destroy(c);
1848         return (err);
1849 }
1850
1851 static void
1852 mlx5e_close_channel(struct mlx5e_channel *c)
1853 {
1854         mlx5e_close_rq(&c->rq);
1855 }
1856
1857 static void
1858 mlx5e_close_channel_wait(struct mlx5e_channel *c)
1859 {
1860         mlx5e_close_rq_wait(&c->rq);
1861         mlx5e_close_sqs_wait(c);
1862         mlx5e_close_cq(&c->rq.cq);
1863         mlx5e_close_tx_cqs(c);
1864         /* destroy mutexes */
1865         mlx5e_chan_mtx_destroy(c);
1866 }
1867
1868 static int
1869 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs)
1870 {
1871         u32 r, n;
1872
1873         r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz :
1874             MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
1875         if (r > MJUM16BYTES)
1876                 return (-ENOMEM);
1877
1878         if (r > MJUM9BYTES)
1879                 r = MJUM16BYTES;
1880         else if (r > MJUMPAGESIZE)
1881                 r = MJUM9BYTES;
1882         else if (r > MCLBYTES)
1883                 r = MJUMPAGESIZE;
1884         else
1885                 r = MCLBYTES;
1886
1887         /*
1888          * n + 1 must be a power of two, because stride size must be.
1889          * Stride size is 16 * (n + 1), as the first segment is
1890          * control.
1891          */
1892         for (n = howmany(r, MLX5E_MAX_RX_BYTES); !powerof2(n + 1); n++)
1893                 ;
1894
1895         *wqe_sz = r;
1896         *nsegs = n;
1897         return (0);
1898 }
1899
1900 static void
1901 mlx5e_build_rq_param(struct mlx5e_priv *priv,
1902     struct mlx5e_rq_param *param)
1903 {
1904         void *rqc = param->rqc;
1905         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1906         u32 wqe_sz, nsegs;
1907
1908         mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
1909         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1910         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1911         MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) +
1912             nsegs * sizeof(struct mlx5_wqe_data_seg)));
1913         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1914         MLX5_SET(wq, wq, pd, priv->pdn);
1915
1916         param->wq.buf_numa_node = 0;
1917         param->wq.db_numa_node = 0;
1918         param->wq.linear = 1;
1919 }
1920
1921 static void
1922 mlx5e_build_sq_param(struct mlx5e_priv *priv,
1923     struct mlx5e_sq_param *param)
1924 {
1925         void *sqc = param->sqc;
1926         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1927
1928         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1929         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1930         MLX5_SET(wq, wq, pd, priv->pdn);
1931
1932         param->wq.buf_numa_node = 0;
1933         param->wq.db_numa_node = 0;
1934         param->wq.linear = 1;
1935 }
1936
1937 static void
1938 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1939     struct mlx5e_cq_param *param)
1940 {
1941         void *cqc = param->cqc;
1942
1943         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1944 }
1945
1946 static void
1947 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr)
1948 {
1949
1950         *ptr = net_dim_get_profile(mode, MLX5E_DIM_DEFAULT_PROFILE);
1951
1952         /* apply LRO restrictions */
1953         if (priv->params.hw_lro_en &&
1954             ptr->pkts > MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO) {
1955                 ptr->pkts = MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO;
1956         }
1957 }
1958
1959 static void
1960 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1961     struct mlx5e_cq_param *param)
1962 {
1963         struct net_dim_cq_moder curr;
1964         void *cqc = param->cqc;
1965
1966
1967         /*
1968          * TODO The sysctl to control on/off is a bool value for now, which means
1969          * we only support CSUM, once HASH is implemnted we'll need to address that.
1970          */
1971         if (priv->params.cqe_zipping_en) {
1972                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1973                 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
1974         }
1975
1976         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1977
1978         switch (priv->params.rx_cq_moderation_mode) {
1979         case 0:
1980                 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1981                 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1982                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1983                 break;
1984         case 1:
1985                 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1986                 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1987                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1988                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1989                 else
1990                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1991                 break;
1992         case 2:
1993                 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr);
1994                 MLX5_SET(cqc, cqc, cq_period, curr.usec);
1995                 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
1996                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1997                 break;
1998         case 3:
1999                 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr);
2000                 MLX5_SET(cqc, cqc, cq_period, curr.usec);
2001                 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
2002                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2003                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2004                 else
2005                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2006                 break;
2007         default:
2008                 break;
2009         }
2010
2011         mlx5e_dim_build_cq_param(priv, param);
2012
2013         mlx5e_build_common_cq_param(priv, param);
2014 }
2015
2016 static void
2017 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2018     struct mlx5e_cq_param *param)
2019 {
2020         void *cqc = param->cqc;
2021
2022         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
2023         MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
2024         MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
2025
2026         switch (priv->params.tx_cq_moderation_mode) {
2027         case 0:
2028                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2029                 break;
2030         default:
2031                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2032                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2033                 else
2034                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2035                 break;
2036         }
2037
2038         mlx5e_build_common_cq_param(priv, param);
2039 }
2040
2041 static void
2042 mlx5e_build_channel_param(struct mlx5e_priv *priv,
2043     struct mlx5e_channel_param *cparam)
2044 {
2045         memset(cparam, 0, sizeof(*cparam));
2046
2047         mlx5e_build_rq_param(priv, &cparam->rq);
2048         mlx5e_build_sq_param(priv, &cparam->sq);
2049         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
2050         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
2051 }
2052
2053 static int
2054 mlx5e_open_channels(struct mlx5e_priv *priv)
2055 {
2056         struct mlx5e_channel_param cparam;
2057         int err;
2058         int i;
2059         int j;
2060
2061         mlx5e_build_channel_param(priv, &cparam);
2062         for (i = 0; i < priv->params.num_channels; i++) {
2063                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
2064                 if (err)
2065                         goto err_close_channels;
2066         }
2067
2068         for (j = 0; j < priv->params.num_channels; j++) {
2069                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j].rq);
2070                 if (err)
2071                         goto err_close_channels;
2072         }
2073         return (0);
2074
2075 err_close_channels:
2076         while (i--) {
2077                 mlx5e_close_channel(&priv->channel[i]);
2078                 mlx5e_close_channel_wait(&priv->channel[i]);
2079         }
2080         return (err);
2081 }
2082
2083 static void
2084 mlx5e_close_channels(struct mlx5e_priv *priv)
2085 {
2086         int i;
2087
2088         for (i = 0; i < priv->params.num_channels; i++)
2089                 mlx5e_close_channel(&priv->channel[i]);
2090         for (i = 0; i < priv->params.num_channels; i++)
2091                 mlx5e_close_channel_wait(&priv->channel[i]);
2092 }
2093
2094 static int
2095 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
2096 {
2097
2098         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2099                 uint8_t cq_mode;
2100
2101                 switch (priv->params.tx_cq_moderation_mode) {
2102                 case 0:
2103                 case 2:
2104                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2105                         break;
2106                 default:
2107                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2108                         break;
2109                 }
2110
2111                 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq,
2112                     priv->params.tx_cq_moderation_usec,
2113                     priv->params.tx_cq_moderation_pkts,
2114                     cq_mode));
2115         }
2116
2117         return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
2118             priv->params.tx_cq_moderation_usec,
2119             priv->params.tx_cq_moderation_pkts));
2120 }
2121
2122 static int
2123 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
2124 {
2125
2126         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2127                 uint8_t cq_mode;
2128                 uint8_t dim_mode;
2129                 int retval;
2130
2131                 switch (priv->params.rx_cq_moderation_mode) {
2132                 case 0:
2133                 case 2:
2134                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2135                         dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2136                         break;
2137                 default:
2138                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2139                         dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
2140                         break;
2141                 }
2142
2143                 /* tear down dynamic interrupt moderation */
2144                 mtx_lock(&rq->mtx);
2145                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
2146                 mtx_unlock(&rq->mtx);
2147
2148                 /* wait for dynamic interrupt moderation work task, if any */
2149                 cancel_work_sync(&rq->dim.work);
2150
2151                 if (priv->params.rx_cq_moderation_mode >= 2) {
2152                         struct net_dim_cq_moder curr;
2153
2154                         mlx5e_get_default_profile(priv, dim_mode, &curr);
2155
2156                         retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2157                             curr.usec, curr.pkts, cq_mode);
2158
2159                         /* set dynamic interrupt moderation mode and zero defaults */
2160                         mtx_lock(&rq->mtx);
2161                         rq->dim.mode = dim_mode;
2162                         rq->dim.state = 0;
2163                         rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE;
2164                         mtx_unlock(&rq->mtx);
2165                 } else {
2166                         retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2167                             priv->params.rx_cq_moderation_usec,
2168                             priv->params.rx_cq_moderation_pkts,
2169                             cq_mode);
2170                 }
2171                 return (retval);
2172         }
2173
2174         return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
2175             priv->params.rx_cq_moderation_usec,
2176             priv->params.rx_cq_moderation_pkts));
2177 }
2178
2179 static int
2180 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
2181 {
2182         int err;
2183         int i;
2184
2185         err = mlx5e_refresh_rq_params(priv, &c->rq);
2186         if (err)
2187                 goto done;
2188
2189         for (i = 0; i != c->num_tc; i++) {
2190                 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
2191                 if (err)
2192                         goto done;
2193         }
2194 done:
2195         return (err);
2196 }
2197
2198 int
2199 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
2200 {
2201         int i;
2202
2203         /* check if channels are closed */
2204         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2205                 return (EINVAL);
2206
2207         for (i = 0; i < priv->params.num_channels; i++) {
2208                 int err;
2209
2210                 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]);
2211                 if (err)
2212                         return (err);
2213         }
2214         return (0);
2215 }
2216
2217 static int
2218 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
2219 {
2220         struct mlx5_core_dev *mdev = priv->mdev;
2221         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
2222         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2223
2224         memset(in, 0, sizeof(in));
2225
2226         MLX5_SET(tisc, tisc, prio, tc);
2227         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
2228
2229         return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
2230 }
2231
2232 static void
2233 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
2234 {
2235         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2236 }
2237
2238 static int
2239 mlx5e_open_tises(struct mlx5e_priv *priv)
2240 {
2241         int num_tc = priv->num_tc;
2242         int err;
2243         int tc;
2244
2245         for (tc = 0; tc < num_tc; tc++) {
2246                 err = mlx5e_open_tis(priv, tc);
2247                 if (err)
2248                         goto err_close_tises;
2249         }
2250
2251         return (0);
2252
2253 err_close_tises:
2254         for (tc--; tc >= 0; tc--)
2255                 mlx5e_close_tis(priv, tc);
2256
2257         return (err);
2258 }
2259
2260 static void
2261 mlx5e_close_tises(struct mlx5e_priv *priv)
2262 {
2263         int num_tc = priv->num_tc;
2264         int tc;
2265
2266         for (tc = 0; tc < num_tc; tc++)
2267                 mlx5e_close_tis(priv, tc);
2268 }
2269
2270 static int
2271 mlx5e_open_rqt(struct mlx5e_priv *priv)
2272 {
2273         struct mlx5_core_dev *mdev = priv->mdev;
2274         u32 *in;
2275         u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
2276         void *rqtc;
2277         int inlen;
2278         int err;
2279         int sz;
2280         int i;
2281
2282         sz = 1 << priv->params.rx_hash_log_tbl_sz;
2283
2284         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2285         in = mlx5_vzalloc(inlen);
2286         if (in == NULL)
2287                 return (-ENOMEM);
2288         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2289
2290         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2291         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2292
2293         for (i = 0; i < sz; i++) {
2294                 int ix = i;
2295 #ifdef RSS
2296                 ix = rss_get_indirection_to_bucket(ix);
2297 #endif
2298                 /* ensure we don't overflow */
2299                 ix %= priv->params.num_channels;
2300
2301                 /* apply receive side scaling stride, if any */
2302                 ix -= ix % (int)priv->params.channels_rsss;
2303
2304                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn);
2305         }
2306
2307         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
2308
2309         err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
2310         if (!err)
2311                 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
2312
2313         kvfree(in);
2314
2315         return (err);
2316 }
2317
2318 static void
2319 mlx5e_close_rqt(struct mlx5e_priv *priv)
2320 {
2321         u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0};
2322         u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0};
2323
2324         MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
2325         MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
2326
2327         mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out));
2328 }
2329
2330 static void
2331 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
2332 {
2333         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2334         __be32 *hkey;
2335
2336         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2337
2338 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2339
2340 #define MLX5_HASH_IP     (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2341                           MLX5_HASH_FIELD_SEL_DST_IP)
2342
2343 #define MLX5_HASH_ALL    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2344                           MLX5_HASH_FIELD_SEL_DST_IP   |\
2345                           MLX5_HASH_FIELD_SEL_L4_SPORT |\
2346                           MLX5_HASH_FIELD_SEL_L4_DPORT)
2347
2348 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2349                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2350                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2351
2352         if (priv->params.hw_lro_en) {
2353                 MLX5_SET(tirc, tirc, lro_enable_mask,
2354                     MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2355                     MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2356                 MLX5_SET(tirc, tirc, lro_max_msg_sz,
2357                     (priv->params.lro_wqe_sz -
2358                     ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2359                 /* TODO: add the option to choose timer value dynamically */
2360                 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
2361                     MLX5_CAP_ETH(priv->mdev,
2362                     lro_timer_supported_periods[2]));
2363         }
2364
2365         /* setup parameters for hashing TIR type, if any */
2366         switch (tt) {
2367         case MLX5E_TT_ANY:
2368                 MLX5_SET(tirc, tirc, disp_type,
2369                     MLX5_TIRC_DISP_TYPE_DIRECT);
2370                 MLX5_SET(tirc, tirc, inline_rqn,
2371                     priv->channel[0].rq.rqn);
2372                 break;
2373         default:
2374                 MLX5_SET(tirc, tirc, disp_type,
2375                     MLX5_TIRC_DISP_TYPE_INDIRECT);
2376                 MLX5_SET(tirc, tirc, indirect_table,
2377                     priv->rqtn);
2378                 MLX5_SET(tirc, tirc, rx_hash_fn,
2379                     MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
2380                 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
2381 #ifdef RSS
2382                 /*
2383                  * The FreeBSD RSS implementation does currently not
2384                  * support symmetric Toeplitz hashes:
2385                  */
2386                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
2387                 rss_getkey((uint8_t *)hkey);
2388 #else
2389                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2390                 hkey[0] = cpu_to_be32(0xD181C62C);
2391                 hkey[1] = cpu_to_be32(0xF7F4DB5B);
2392                 hkey[2] = cpu_to_be32(0x1983A2FC);
2393                 hkey[3] = cpu_to_be32(0x943E1ADB);
2394                 hkey[4] = cpu_to_be32(0xD9389E6B);
2395                 hkey[5] = cpu_to_be32(0xD1039C2C);
2396                 hkey[6] = cpu_to_be32(0xA74499AD);
2397                 hkey[7] = cpu_to_be32(0x593D56D9);
2398                 hkey[8] = cpu_to_be32(0xF3253C06);
2399                 hkey[9] = cpu_to_be32(0x2ADC1FFC);
2400 #endif
2401                 break;
2402         }
2403
2404         switch (tt) {
2405         case MLX5E_TT_IPV4_TCP:
2406                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2407                     MLX5_L3_PROT_TYPE_IPV4);
2408                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2409                     MLX5_L4_PROT_TYPE_TCP);
2410 #ifdef RSS
2411                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2412                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2413                             MLX5_HASH_IP);
2414                 } else
2415 #endif
2416                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2417                     MLX5_HASH_ALL);
2418                 break;
2419
2420         case MLX5E_TT_IPV6_TCP:
2421                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2422                     MLX5_L3_PROT_TYPE_IPV6);
2423                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2424                     MLX5_L4_PROT_TYPE_TCP);
2425 #ifdef RSS
2426                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2427                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2428                             MLX5_HASH_IP);
2429                 } else
2430 #endif
2431                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2432                     MLX5_HASH_ALL);
2433                 break;
2434
2435         case MLX5E_TT_IPV4_UDP:
2436                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2437                     MLX5_L3_PROT_TYPE_IPV4);
2438                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2439                     MLX5_L4_PROT_TYPE_UDP);
2440 #ifdef RSS
2441                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2442                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2443                             MLX5_HASH_IP);
2444                 } else
2445 #endif
2446                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2447                     MLX5_HASH_ALL);
2448                 break;
2449
2450         case MLX5E_TT_IPV6_UDP:
2451                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2452                     MLX5_L3_PROT_TYPE_IPV6);
2453                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2454                     MLX5_L4_PROT_TYPE_UDP);
2455 #ifdef RSS
2456                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2457                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2458                             MLX5_HASH_IP);
2459                 } else
2460 #endif
2461                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2462                     MLX5_HASH_ALL);
2463                 break;
2464
2465         case MLX5E_TT_IPV4_IPSEC_AH:
2466                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2467                     MLX5_L3_PROT_TYPE_IPV4);
2468                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2469                     MLX5_HASH_IP_IPSEC_SPI);
2470                 break;
2471
2472         case MLX5E_TT_IPV6_IPSEC_AH:
2473                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2474                     MLX5_L3_PROT_TYPE_IPV6);
2475                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2476                     MLX5_HASH_IP_IPSEC_SPI);
2477                 break;
2478
2479         case MLX5E_TT_IPV4_IPSEC_ESP:
2480                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2481                     MLX5_L3_PROT_TYPE_IPV4);
2482                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2483                     MLX5_HASH_IP_IPSEC_SPI);
2484                 break;
2485
2486         case MLX5E_TT_IPV6_IPSEC_ESP:
2487                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2488                     MLX5_L3_PROT_TYPE_IPV6);
2489                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2490                     MLX5_HASH_IP_IPSEC_SPI);
2491                 break;
2492
2493         case MLX5E_TT_IPV4:
2494                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2495                     MLX5_L3_PROT_TYPE_IPV4);
2496                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2497                     MLX5_HASH_IP);
2498                 break;
2499
2500         case MLX5E_TT_IPV6:
2501                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2502                     MLX5_L3_PROT_TYPE_IPV6);
2503                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2504                     MLX5_HASH_IP);
2505                 break;
2506
2507         default:
2508                 break;
2509         }
2510 }
2511
2512 static int
2513 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2514 {
2515         struct mlx5_core_dev *mdev = priv->mdev;
2516         u32 *in;
2517         void *tirc;
2518         int inlen;
2519         int err;
2520
2521         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2522         in = mlx5_vzalloc(inlen);
2523         if (in == NULL)
2524                 return (-ENOMEM);
2525         tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2526
2527         mlx5e_build_tir_ctx(priv, tirc, tt);
2528
2529         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2530
2531         kvfree(in);
2532
2533         return (err);
2534 }
2535
2536 static void
2537 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2538 {
2539         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2540 }
2541
2542 static int
2543 mlx5e_open_tirs(struct mlx5e_priv *priv)
2544 {
2545         int err;
2546         int i;
2547
2548         for (i = 0; i < MLX5E_NUM_TT; i++) {
2549                 err = mlx5e_open_tir(priv, i);
2550                 if (err)
2551                         goto err_close_tirs;
2552         }
2553
2554         return (0);
2555
2556 err_close_tirs:
2557         for (i--; i >= 0; i--)
2558                 mlx5e_close_tir(priv, i);
2559
2560         return (err);
2561 }
2562
2563 static void
2564 mlx5e_close_tirs(struct mlx5e_priv *priv)
2565 {
2566         int i;
2567
2568         for (i = 0; i < MLX5E_NUM_TT; i++)
2569                 mlx5e_close_tir(priv, i);
2570 }
2571
2572 /*
2573  * SW MTU does not include headers,
2574  * HW MTU includes all headers and checksums.
2575  */
2576 static int
2577 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2578 {
2579         struct mlx5e_priv *priv = ifp->if_softc;
2580         struct mlx5_core_dev *mdev = priv->mdev;
2581         int hw_mtu;
2582         int err;
2583
2584         hw_mtu = MLX5E_SW2HW_MTU(sw_mtu);
2585
2586         err = mlx5_set_port_mtu(mdev, hw_mtu);
2587         if (err) {
2588                 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n",
2589                     __func__, sw_mtu, err);
2590                 return (err);
2591         }
2592
2593         /* Update vport context MTU */
2594         err = mlx5_set_vport_mtu(mdev, hw_mtu);
2595         if (err) {
2596                 if_printf(ifp, "%s: Failed updating vport context with MTU size, err=%d\n",
2597                     __func__, err);
2598         }
2599
2600         ifp->if_mtu = sw_mtu;
2601
2602         err = mlx5_query_vport_mtu(mdev, &hw_mtu);
2603         if (err || !hw_mtu) {
2604                 /* fallback to port oper mtu */
2605                 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2606         }
2607         if (err) {
2608                 if_printf(ifp, "Query port MTU, after setting new "
2609                     "MTU value, failed\n");
2610                 return (err);
2611         } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
2612                 err = -E2BIG,
2613                 if_printf(ifp, "Port MTU %d is smaller than "
2614                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2615         } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
2616                 err = -EINVAL;
2617                 if_printf(ifp, "Port MTU %d is bigger than "
2618                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2619         }
2620         priv->params_ethtool.hw_mtu = hw_mtu;
2621
2622         return (err);
2623 }
2624
2625 int
2626 mlx5e_open_locked(struct ifnet *ifp)
2627 {
2628         struct mlx5e_priv *priv = ifp->if_softc;
2629         int err;
2630         u16 set_id;
2631
2632         /* check if already opened */
2633         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2634                 return (0);
2635
2636 #ifdef RSS
2637         if (rss_getnumbuckets() > priv->params.num_channels) {
2638                 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than "
2639                     "channels(%u) available\n", rss_getnumbuckets(),
2640                     priv->params.num_channels);
2641         }
2642 #endif
2643         err = mlx5e_open_tises(priv);
2644         if (err) {
2645                 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n",
2646                     __func__, err);
2647                 return (err);
2648         }
2649         err = mlx5_vport_alloc_q_counter(priv->mdev,
2650             MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
2651         if (err) {
2652                 if_printf(priv->ifp,
2653                     "%s: mlx5_vport_alloc_q_counter failed: %d\n",
2654                     __func__, err);
2655                 goto err_close_tises;
2656         }
2657         /* store counter set ID */
2658         priv->counter_set_id = set_id;
2659
2660         err = mlx5e_open_channels(priv);
2661         if (err) {
2662                 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n",
2663                     __func__, err);
2664                 goto err_dalloc_q_counter;
2665         }
2666         err = mlx5e_open_rqt(priv);
2667         if (err) {
2668                 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n",
2669                     __func__, err);
2670                 goto err_close_channels;
2671         }
2672         err = mlx5e_open_tirs(priv);
2673         if (err) {
2674                 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n",
2675                     __func__, err);
2676                 goto err_close_rqls;
2677         }
2678         err = mlx5e_open_flow_table(priv);
2679         if (err) {
2680                 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n",
2681                     __func__, err);
2682                 goto err_close_tirs;
2683         }
2684         err = mlx5e_add_all_vlan_rules(priv);
2685         if (err) {
2686                 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
2687                     __func__, err);
2688                 goto err_close_flow_table;
2689         }
2690         set_bit(MLX5E_STATE_OPENED, &priv->state);
2691
2692         mlx5e_update_carrier(priv);
2693         mlx5e_set_rx_mode_core(priv);
2694
2695         return (0);
2696
2697 err_close_flow_table:
2698         mlx5e_close_flow_table(priv);
2699
2700 err_close_tirs:
2701         mlx5e_close_tirs(priv);
2702
2703 err_close_rqls:
2704         mlx5e_close_rqt(priv);
2705
2706 err_close_channels:
2707         mlx5e_close_channels(priv);
2708
2709 err_dalloc_q_counter:
2710         mlx5_vport_dealloc_q_counter(priv->mdev,
2711             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2712
2713 err_close_tises:
2714         mlx5e_close_tises(priv);
2715
2716         return (err);
2717 }
2718
2719 static void
2720 mlx5e_open(void *arg)
2721 {
2722         struct mlx5e_priv *priv = arg;
2723
2724         PRIV_LOCK(priv);
2725         if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
2726                 if_printf(priv->ifp,
2727                     "%s: Setting port status to up failed\n",
2728                     __func__);
2729
2730         mlx5e_open_locked(priv->ifp);
2731         priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
2732         PRIV_UNLOCK(priv);
2733 }
2734
2735 int
2736 mlx5e_close_locked(struct ifnet *ifp)
2737 {
2738         struct mlx5e_priv *priv = ifp->if_softc;
2739
2740         /* check if already closed */
2741         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2742                 return (0);
2743
2744         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2745
2746         mlx5e_set_rx_mode_core(priv);
2747         mlx5e_del_all_vlan_rules(priv);
2748         if_link_state_change(priv->ifp, LINK_STATE_DOWN);
2749         mlx5e_close_flow_table(priv);
2750         mlx5e_close_tirs(priv);
2751         mlx5e_close_rqt(priv);
2752         mlx5e_close_channels(priv);
2753         mlx5_vport_dealloc_q_counter(priv->mdev,
2754             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2755         mlx5e_close_tises(priv);
2756
2757         return (0);
2758 }
2759
2760 #if (__FreeBSD_version >= 1100000)
2761 static uint64_t
2762 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
2763 {
2764         struct mlx5e_priv *priv = ifp->if_softc;
2765         u64 retval;
2766
2767         /* PRIV_LOCK(priv); XXX not allowed */
2768         switch (cnt) {
2769         case IFCOUNTER_IPACKETS:
2770                 retval = priv->stats.vport.rx_packets;
2771                 break;
2772         case IFCOUNTER_IERRORS:
2773                 retval = priv->stats.vport.rx_error_packets +
2774                     priv->stats.pport.alignment_err +
2775                     priv->stats.pport.check_seq_err +
2776                     priv->stats.pport.crc_align_errors +
2777                     priv->stats.pport.in_range_len_errors +
2778                     priv->stats.pport.jabbers +
2779                     priv->stats.pport.out_of_range_len +
2780                     priv->stats.pport.oversize_pkts +
2781                     priv->stats.pport.symbol_err +
2782                     priv->stats.pport.too_long_errors +
2783                     priv->stats.pport.undersize_pkts +
2784                     priv->stats.pport.unsupported_op_rx;
2785                 break;
2786         case IFCOUNTER_IQDROPS:
2787                 retval = priv->stats.vport.rx_out_of_buffer +
2788                     priv->stats.pport.drop_events;
2789                 break;
2790         case IFCOUNTER_OPACKETS:
2791                 retval = priv->stats.vport.tx_packets;
2792                 break;
2793         case IFCOUNTER_OERRORS:
2794                 retval = priv->stats.vport.tx_error_packets;
2795                 break;
2796         case IFCOUNTER_IBYTES:
2797                 retval = priv->stats.vport.rx_bytes;
2798                 break;
2799         case IFCOUNTER_OBYTES:
2800                 retval = priv->stats.vport.tx_bytes;
2801                 break;
2802         case IFCOUNTER_IMCASTS:
2803                 retval = priv->stats.vport.rx_multicast_packets;
2804                 break;
2805         case IFCOUNTER_OMCASTS:
2806                 retval = priv->stats.vport.tx_multicast_packets;
2807                 break;
2808         case IFCOUNTER_OQDROPS:
2809                 retval = priv->stats.vport.tx_queue_dropped;
2810                 break;
2811         case IFCOUNTER_COLLISIONS:
2812                 retval = priv->stats.pport.collisions;
2813                 break;
2814         default:
2815                 retval = if_get_counter_default(ifp, cnt);
2816                 break;
2817         }
2818         /* PRIV_UNLOCK(priv); XXX not allowed */
2819         return (retval);
2820 }
2821 #endif
2822
2823 static void
2824 mlx5e_set_rx_mode(struct ifnet *ifp)
2825 {
2826         struct mlx5e_priv *priv = ifp->if_softc;
2827
2828         queue_work(priv->wq, &priv->set_rx_mode_work);
2829 }
2830
2831 static int
2832 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2833 {
2834         struct mlx5e_priv *priv;
2835         struct ifreq *ifr;
2836         struct ifi2creq i2c;
2837         int error = 0;
2838         int mask = 0;
2839         int size_read = 0;
2840         int module_status;
2841         int module_num;
2842         int max_mtu;
2843         uint8_t read_addr;
2844
2845         priv = ifp->if_softc;
2846
2847         /* check if detaching */
2848         if (priv == NULL || priv->gone != 0)
2849                 return (ENXIO);
2850
2851         switch (command) {
2852         case SIOCSIFMTU:
2853                 ifr = (struct ifreq *)data;
2854
2855                 PRIV_LOCK(priv);
2856                 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
2857
2858                 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
2859                     ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
2860                         int was_opened;
2861
2862                         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2863                         if (was_opened)
2864                                 mlx5e_close_locked(ifp);
2865
2866                         /* set new MTU */
2867                         mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
2868
2869                         if (was_opened)
2870                                 mlx5e_open_locked(ifp);
2871                 } else {
2872                         error = EINVAL;
2873                         if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n",
2874                             MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
2875                 }
2876                 PRIV_UNLOCK(priv);
2877                 break;
2878         case SIOCSIFFLAGS:
2879                 if ((ifp->if_flags & IFF_UP) &&
2880                     (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2881                         mlx5e_set_rx_mode(ifp);
2882                         break;
2883                 }
2884                 PRIV_LOCK(priv);
2885                 if (ifp->if_flags & IFF_UP) {
2886                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2887                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2888                                         mlx5e_open_locked(ifp);
2889                                 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2890                                 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
2891                         }
2892                 } else {
2893                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2894                                 mlx5_set_port_status(priv->mdev,
2895                                     MLX5_PORT_DOWN);
2896                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2897                                         mlx5e_close_locked(ifp);
2898                                 mlx5e_update_carrier(priv);
2899                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2900                         }
2901                 }
2902                 PRIV_UNLOCK(priv);
2903                 break;
2904         case SIOCADDMULTI:
2905         case SIOCDELMULTI:
2906                 mlx5e_set_rx_mode(ifp);
2907                 break;
2908         case SIOCSIFMEDIA:
2909         case SIOCGIFMEDIA:
2910         case SIOCGIFXMEDIA:
2911                 ifr = (struct ifreq *)data;
2912                 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
2913                 break;
2914         case SIOCSIFCAP:
2915                 ifr = (struct ifreq *)data;
2916                 PRIV_LOCK(priv);
2917                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2918
2919                 if (mask & IFCAP_TXCSUM) {
2920                         ifp->if_capenable ^= IFCAP_TXCSUM;
2921                         ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2922
2923                         if (IFCAP_TSO4 & ifp->if_capenable &&
2924                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2925                                 ifp->if_capenable &= ~IFCAP_TSO4;
2926                                 ifp->if_hwassist &= ~CSUM_IP_TSO;
2927                                 if_printf(ifp,
2928                                     "tso4 disabled due to -txcsum.\n");
2929                         }
2930                 }
2931                 if (mask & IFCAP_TXCSUM_IPV6) {
2932                         ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
2933                         ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2934
2935                         if (IFCAP_TSO6 & ifp->if_capenable &&
2936                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2937                                 ifp->if_capenable &= ~IFCAP_TSO6;
2938                                 ifp->if_hwassist &= ~CSUM_IP6_TSO;
2939                                 if_printf(ifp,
2940                                     "tso6 disabled due to -txcsum6.\n");
2941                         }
2942                 }
2943                 if (mask & IFCAP_RXCSUM)
2944                         ifp->if_capenable ^= IFCAP_RXCSUM;
2945                 if (mask & IFCAP_RXCSUM_IPV6)
2946                         ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
2947                 if (mask & IFCAP_TSO4) {
2948                         if (!(IFCAP_TSO4 & ifp->if_capenable) &&
2949                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2950                                 if_printf(ifp, "enable txcsum first.\n");
2951                                 error = EAGAIN;
2952                                 goto out;
2953                         }
2954                         ifp->if_capenable ^= IFCAP_TSO4;
2955                         ifp->if_hwassist ^= CSUM_IP_TSO;
2956                 }
2957                 if (mask & IFCAP_TSO6) {
2958                         if (!(IFCAP_TSO6 & ifp->if_capenable) &&
2959                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2960                                 if_printf(ifp, "enable txcsum6 first.\n");
2961                                 error = EAGAIN;
2962                                 goto out;
2963                         }
2964                         ifp->if_capenable ^= IFCAP_TSO6;
2965                         ifp->if_hwassist ^= CSUM_IP6_TSO;
2966                 }
2967                 if (mask & IFCAP_VLAN_HWFILTER) {
2968                         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
2969                                 mlx5e_disable_vlan_filter(priv);
2970                         else
2971                                 mlx5e_enable_vlan_filter(priv);
2972
2973                         ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
2974                 }
2975                 if (mask & IFCAP_VLAN_HWTAGGING)
2976                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2977                 if (mask & IFCAP_WOL_MAGIC)
2978                         ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2979
2980                 VLAN_CAPABILITIES(ifp);
2981                 /* turn off LRO means also turn of HW LRO - if it's on */
2982                 if (mask & IFCAP_LRO) {
2983                         int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2984                         bool need_restart = false;
2985
2986                         ifp->if_capenable ^= IFCAP_LRO;
2987
2988                         /* figure out if updating HW LRO is needed */
2989                         if (!(ifp->if_capenable & IFCAP_LRO)) {
2990                                 if (priv->params.hw_lro_en) {
2991                                         priv->params.hw_lro_en = false;
2992                                         need_restart = true;
2993                                 }
2994                         } else {
2995                                 if (priv->params.hw_lro_en == false &&
2996                                     priv->params_ethtool.hw_lro != 0) {
2997                                         priv->params.hw_lro_en = true;
2998                                         need_restart = true;
2999                                 }
3000                         }
3001                         if (was_opened && need_restart) {
3002                                 mlx5e_close_locked(ifp);
3003                                 mlx5e_open_locked(ifp);
3004                         }
3005                 }
3006                 if (mask & IFCAP_HWRXTSTMP) {
3007                         ifp->if_capenable ^= IFCAP_HWRXTSTMP;
3008                         if (ifp->if_capenable & IFCAP_HWRXTSTMP) {
3009                                 if (priv->clbr_done == 0)
3010                                         mlx5e_reset_calibration_callout(priv);
3011                         } else {
3012                                 callout_drain(&priv->tstmp_clbr);
3013                                 priv->clbr_done = 0;
3014                         }
3015                 }
3016 out:
3017                 PRIV_UNLOCK(priv);
3018                 break;
3019
3020         case SIOCGI2C:
3021                 ifr = (struct ifreq *)data;
3022
3023                 /*
3024                  * Copy from the user-space address ifr_data to the
3025                  * kernel-space address i2c
3026                  */
3027                 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
3028                 if (error)
3029                         break;
3030
3031                 if (i2c.len > sizeof(i2c.data)) {
3032                         error = EINVAL;
3033                         break;
3034                 }
3035
3036                 PRIV_LOCK(priv);
3037                 /* Get module_num which is required for the query_eeprom */
3038                 error = mlx5_query_module_num(priv->mdev, &module_num);
3039                 if (error) {
3040                         if_printf(ifp, "Query module num failed, eeprom "
3041                             "reading is not supported\n");
3042                         error = EINVAL;
3043                         goto err_i2c;
3044                 }
3045                 /* Check if module is present before doing an access */
3046                 module_status = mlx5_query_module_status(priv->mdev, module_num);
3047                 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED &&
3048                     module_status != MLX5_MODULE_STATUS_PLUGGED_DISABLED) {
3049                         error = EINVAL;
3050                         goto err_i2c;
3051                 }
3052                 /*
3053                  * Currently 0XA0 and 0xA2 are the only addresses permitted.
3054                  * The internal conversion is as follows:
3055                  */
3056                 if (i2c.dev_addr == 0xA0)
3057                         read_addr = MLX5E_I2C_ADDR_LOW;
3058                 else if (i2c.dev_addr == 0xA2)
3059                         read_addr = MLX5E_I2C_ADDR_HIGH;
3060                 else {
3061                         if_printf(ifp, "Query eeprom failed, "
3062                             "Invalid Address: %X\n", i2c.dev_addr);
3063                         error = EINVAL;
3064                         goto err_i2c;
3065                 }
3066                 error = mlx5_query_eeprom(priv->mdev,
3067                     read_addr, MLX5E_EEPROM_LOW_PAGE,
3068                     (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
3069                     (uint32_t *)i2c.data, &size_read);
3070                 if (error) {
3071                         if_printf(ifp, "Query eeprom failed, eeprom "
3072                             "reading is not supported\n");
3073                         error = EINVAL;
3074                         goto err_i2c;
3075                 }
3076
3077                 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
3078                         error = mlx5_query_eeprom(priv->mdev,
3079                             read_addr, MLX5E_EEPROM_LOW_PAGE,
3080                             (uint32_t)(i2c.offset + size_read),
3081                             (uint32_t)(i2c.len - size_read), module_num,
3082                             (uint32_t *)(i2c.data + size_read), &size_read);
3083                 }
3084                 if (error) {
3085                         if_printf(ifp, "Query eeprom failed, eeprom "
3086                             "reading is not supported\n");
3087                         error = EINVAL;
3088                         goto err_i2c;
3089                 }
3090
3091                 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
3092 err_i2c:
3093                 PRIV_UNLOCK(priv);
3094                 break;
3095
3096         default:
3097                 error = ether_ioctl(ifp, command, data);
3098                 break;
3099         }
3100         return (error);
3101 }
3102
3103 static int
3104 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3105 {
3106         /*
3107          * TODO: uncoment once FW really sets all these bits if
3108          * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
3109          * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
3110          * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
3111          * -ENOTSUPP;
3112          */
3113
3114         /* TODO: add more must-to-have features */
3115
3116         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3117                 return (-ENODEV);
3118
3119         return (0);
3120 }
3121
3122 static u16
3123 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3124 {
3125         uint32_t bf_buf_size = (1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U;
3126
3127         bf_buf_size -= sizeof(struct mlx5e_tx_wqe) - 2;
3128
3129         /* verify against driver hardware limit */
3130         if (bf_buf_size > MLX5E_MAX_TX_INLINE)
3131                 bf_buf_size = MLX5E_MAX_TX_INLINE;
3132
3133         return (bf_buf_size);
3134 }
3135
3136 static int
3137 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
3138     struct mlx5e_priv *priv,
3139     int num_comp_vectors)
3140 {
3141         int err;
3142
3143         /*
3144          * TODO: Consider link speed for setting "log_sq_size",
3145          * "log_rq_size" and "cq_moderation_xxx":
3146          */
3147         priv->params.log_sq_size =
3148             MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3149         priv->params.log_rq_size =
3150             MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3151         priv->params.rx_cq_moderation_usec =
3152             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3153             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
3154             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3155         priv->params.rx_cq_moderation_mode =
3156             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
3157         priv->params.rx_cq_moderation_pkts =
3158             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3159         priv->params.tx_cq_moderation_usec =
3160             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3161         priv->params.tx_cq_moderation_pkts =
3162             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3163         priv->params.min_rx_wqes =
3164             MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
3165         priv->params.rx_hash_log_tbl_sz =
3166             (order_base_2(num_comp_vectors) >
3167             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
3168             order_base_2(num_comp_vectors) :
3169             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
3170         priv->params.num_tc = 1;
3171         priv->params.default_vlan_prio = 0;
3172         priv->counter_set_id = -1;
3173         priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3174
3175         err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3176         if (err)
3177                 return (err);
3178
3179         /*
3180          * hw lro is currently defaulted to off. when it won't anymore we
3181          * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
3182          */
3183         priv->params.hw_lro_en = false;
3184         priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3185
3186         priv->params.cqe_zipping_en = !!MLX5_CAP_GEN(mdev, cqe_compression);
3187
3188         priv->mdev = mdev;
3189         priv->params.num_channels = num_comp_vectors;
3190         priv->params.channels_rsss = 1;
3191         priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
3192         priv->queue_mapping_channel_mask =
3193             roundup_pow_of_two(num_comp_vectors) - 1;
3194         priv->num_tc = priv->params.num_tc;
3195         priv->default_vlan_prio = priv->params.default_vlan_prio;
3196
3197         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3198         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3199         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3200
3201         return (0);
3202 }
3203
3204 static int
3205 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
3206                   struct mlx5_core_mr *mkey)
3207 {
3208         struct ifnet *ifp = priv->ifp;
3209         struct mlx5_core_dev *mdev = priv->mdev;
3210         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3211         void *mkc;
3212         u32 *in;
3213         int err;
3214
3215         in = mlx5_vzalloc(inlen);
3216         if (in == NULL) {
3217                 if_printf(ifp, "%s: failed to allocate inbox\n", __func__);
3218                 return (-ENOMEM);
3219         }
3220
3221         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3222         MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA);
3223         MLX5_SET(mkc, mkc, lw, 1);
3224         MLX5_SET(mkc, mkc, lr, 1);
3225
3226         MLX5_SET(mkc, mkc, pd, pdn);
3227         MLX5_SET(mkc, mkc, length64, 1);
3228         MLX5_SET(mkc, mkc, qpn, 0xffffff);
3229
3230         err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
3231         if (err)
3232                 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n",
3233                     __func__, err);
3234
3235         kvfree(in);
3236         return (err);
3237 }
3238
3239 static const char *mlx5e_vport_stats_desc[] = {
3240         MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
3241 };
3242
3243 static const char *mlx5e_pport_stats_desc[] = {
3244         MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
3245 };
3246
3247 static void
3248 mlx5e_priv_mtx_init(struct mlx5e_priv *priv)
3249 {
3250         mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
3251         sx_init(&priv->state_lock, "mlx5state");
3252         callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
3253         MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
3254 }
3255
3256 static void
3257 mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv)
3258 {
3259         mtx_destroy(&priv->async_events_mtx);
3260         sx_destroy(&priv->state_lock);
3261 }
3262
3263 static int
3264 sysctl_firmware(SYSCTL_HANDLER_ARGS)
3265 {
3266         /*
3267          * %d.%d%.d the string format.
3268          * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
3269          * We need at most 5 chars to store that.
3270          * It also has: two "." and NULL at the end, which means we need 18
3271          * (5*3 + 3) chars at most.
3272          */
3273         char fw[18];
3274         struct mlx5e_priv *priv = arg1;
3275         int error;
3276
3277         snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
3278             fw_rev_sub(priv->mdev));
3279         error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
3280         return (error);
3281 }
3282
3283 static void
3284 mlx5e_disable_tx_dma(struct mlx5e_channel *ch)
3285 {
3286         int i;
3287
3288         for (i = 0; i < ch->num_tc; i++)
3289                 mlx5e_drain_sq(&ch->sq[i]);
3290 }
3291
3292 static void
3293 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq)
3294 {
3295
3296         sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP);
3297         sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8);
3298         mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
3299         sq->doorbell.d64 = 0;
3300 }
3301
3302 void
3303 mlx5e_resume_sq(struct mlx5e_sq *sq)
3304 {
3305         int err;
3306
3307         /* check if already enabled */
3308         if (READ_ONCE(sq->running) != 0)
3309                 return;
3310
3311         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR,
3312             MLX5_SQC_STATE_RST);
3313         if (err != 0) {
3314                 if_printf(sq->ifp,
3315                     "mlx5e_modify_sq() from ERR to RST failed: %d\n", err);
3316         }
3317
3318         sq->cc = 0;
3319         sq->pc = 0;
3320
3321         /* reset doorbell prior to moving from RST to RDY */
3322         mlx5e_reset_sq_doorbell_record(sq);
3323
3324         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST,
3325             MLX5_SQC_STATE_RDY);
3326         if (err != 0) {
3327                 if_printf(sq->ifp,
3328                     "mlx5e_modify_sq() from RST to RDY failed: %d\n", err);
3329         }
3330
3331         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
3332         WRITE_ONCE(sq->running, 1);
3333 }
3334
3335 static void
3336 mlx5e_enable_tx_dma(struct mlx5e_channel *ch)
3337 {
3338         int i;
3339
3340         for (i = 0; i < ch->num_tc; i++)
3341                 mlx5e_resume_sq(&ch->sq[i]);
3342 }
3343
3344 static void
3345 mlx5e_disable_rx_dma(struct mlx5e_channel *ch)
3346 {
3347         struct mlx5e_rq *rq = &ch->rq;
3348         int err;
3349
3350         mtx_lock(&rq->mtx);
3351         rq->enabled = 0;
3352         callout_stop(&rq->watchdog);
3353         mtx_unlock(&rq->mtx);
3354
3355         callout_drain(&rq->watchdog);
3356
3357         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
3358         if (err != 0) {
3359                 if_printf(rq->ifp,
3360                     "mlx5e_modify_rq() from RDY to RST failed: %d\n", err);
3361         }
3362
3363         while (!mlx5_wq_ll_is_empty(&rq->wq)) {
3364                 msleep(1);
3365                 rq->cq.mcq.comp(&rq->cq.mcq);
3366         }
3367
3368         /*
3369          * Transitioning into RST state will allow the FW to track less ERR state queues,
3370          * thus reducing the recv queue flushing time
3371          */
3372         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST);
3373         if (err != 0) {
3374                 if_printf(rq->ifp,
3375                     "mlx5e_modify_rq() from ERR to RST failed: %d\n", err);
3376         }
3377 }
3378
3379 static void
3380 mlx5e_enable_rx_dma(struct mlx5e_channel *ch)
3381 {
3382         struct mlx5e_rq *rq = &ch->rq;
3383         int err;
3384
3385         rq->wq.wqe_ctr = 0;
3386         mlx5_wq_ll_update_db_record(&rq->wq);
3387         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3388         if (err != 0) {
3389                 if_printf(rq->ifp,
3390                     "mlx5e_modify_rq() from RST to RDY failed: %d\n", err);
3391         }
3392
3393         rq->enabled = 1;
3394
3395         rq->cq.mcq.comp(&rq->cq.mcq);
3396 }
3397
3398 void
3399 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value)
3400 {
3401         int i;
3402
3403         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3404                 return;
3405
3406         for (i = 0; i < priv->params.num_channels; i++) {
3407                 if (value)
3408                         mlx5e_disable_tx_dma(&priv->channel[i]);
3409                 else
3410                         mlx5e_enable_tx_dma(&priv->channel[i]);
3411         }
3412 }
3413
3414 void
3415 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value)
3416 {
3417         int i;
3418
3419         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3420                 return;
3421
3422         for (i = 0; i < priv->params.num_channels; i++) {
3423                 if (value)
3424                         mlx5e_disable_rx_dma(&priv->channel[i]);
3425                 else
3426                         mlx5e_enable_rx_dma(&priv->channel[i]);
3427         }
3428 }
3429
3430 static void
3431 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
3432 {
3433         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3434             OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
3435             sysctl_firmware, "A", "HCA firmware version");
3436
3437         SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3438             OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
3439             "Board ID");
3440 }
3441
3442 static int
3443 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3444 {
3445         struct mlx5e_priv *priv = arg1;
3446         uint32_t tx_pfc;
3447         uint32_t value;
3448         int error;
3449
3450         PRIV_LOCK(priv);
3451
3452         tx_pfc = priv->params.tx_priority_flow_control;
3453
3454         /* get current value */
3455         value = (tx_pfc >> arg2) & 1;
3456
3457         error = sysctl_handle_32(oidp, &value, 0, req);
3458
3459         /* range check value */
3460         if (value != 0)
3461                 priv->params.tx_priority_flow_control |= (1 << arg2);
3462         else
3463                 priv->params.tx_priority_flow_control &= ~(1 << arg2);
3464
3465         /* check if update is required */
3466         if (error == 0 && priv->gone == 0 &&
3467             tx_pfc != priv->params.tx_priority_flow_control) {
3468                 error = -mlx5e_set_port_pfc(priv);
3469                 /* restore previous value */
3470                 if (error != 0)
3471                         priv->params.tx_priority_flow_control= tx_pfc;
3472         }
3473         PRIV_UNLOCK(priv);
3474
3475         return (error);
3476 }
3477
3478 static int
3479 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3480 {
3481         struct mlx5e_priv *priv = arg1;
3482         uint32_t rx_pfc;
3483         uint32_t value;
3484         int error;
3485
3486         PRIV_LOCK(priv);
3487
3488         rx_pfc = priv->params.rx_priority_flow_control;
3489
3490         /* get current value */
3491         value = (rx_pfc >> arg2) & 1;
3492
3493         error = sysctl_handle_32(oidp, &value, 0, req);
3494
3495         /* range check value */
3496         if (value != 0)
3497                 priv->params.rx_priority_flow_control |= (1 << arg2);
3498         else
3499                 priv->params.rx_priority_flow_control &= ~(1 << arg2);
3500
3501         /* check if update is required */
3502         if (error == 0 && priv->gone == 0 &&
3503             rx_pfc != priv->params.rx_priority_flow_control) {
3504                 error = -mlx5e_set_port_pfc(priv);
3505                 /* restore previous value */
3506                 if (error != 0)
3507                         priv->params.rx_priority_flow_control= rx_pfc;
3508         }
3509         PRIV_UNLOCK(priv);
3510
3511         return (error);
3512 }
3513
3514 static void
3515 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
3516 {
3517         unsigned int x;
3518         char path[96];
3519         int error;
3520
3521         /* enable pauseframes by default */
3522         priv->params.tx_pauseframe_control = 1;
3523         priv->params.rx_pauseframe_control = 1;
3524
3525         /* disable ports flow control, PFC, by default */
3526         priv->params.tx_priority_flow_control = 0;
3527         priv->params.rx_priority_flow_control = 0;
3528
3529 #if (__FreeBSD_version < 1100000)
3530         /* compute path for sysctl */
3531         snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
3532             device_get_unit(priv->mdev->pdev->dev.bsddev));
3533
3534         /* try to fetch tunable, if any */
3535         TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
3536
3537         /* compute path for sysctl */
3538         snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
3539             device_get_unit(priv->mdev->pdev->dev.bsddev));
3540
3541         /* try to fetch tunable, if any */
3542         TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
3543
3544         for (x = 0; x != 8; x++) {
3545
3546                 /* compute path for sysctl */
3547                 snprintf(path, sizeof(path), "dev.mce.%d.tx_priority_flow_control_%u",
3548                     device_get_unit(priv->mdev->pdev->dev.bsddev), x);
3549
3550                 /* try to fetch tunable, if any */
3551                 if (TUNABLE_INT_FETCH(path, &value) == 0 && value != 0)
3552                         priv->params.tx_priority_flow_control |= 1 << x;
3553
3554                 /* compute path for sysctl */
3555                 snprintf(path, sizeof(path), "dev.mce.%d.rx_priority_flow_control_%u",
3556                     device_get_unit(priv->mdev->pdev->dev.bsddev), x);
3557
3558                 /* try to fetch tunable, if any */
3559                 if (TUNABLE_INT_FETCH(path, &value) == 0 && value != 0)
3560                         priv->params.rx_priority_flow_control |= 1 << x;
3561         }
3562 #endif
3563
3564         /* register pauseframe SYSCTLs */
3565         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3566             OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
3567             &priv->params.tx_pauseframe_control, 0,
3568             "Set to enable TX pause frames. Clear to disable.");
3569
3570         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3571             OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
3572             &priv->params.rx_pauseframe_control, 0,
3573             "Set to enable RX pause frames. Clear to disable.");
3574
3575         /* register priority_flow control, PFC, SYSCTLs */
3576         for (x = 0; x != 8; x++) {
3577                 snprintf(path, sizeof(path), "tx_priority_flow_control_%u", x);
3578
3579                 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3580                     OID_AUTO, path, CTLTYPE_UINT | CTLFLAG_RWTUN |
3581                     CTLFLAG_MPSAFE, priv, x, &mlx5e_sysctl_tx_priority_flow_control, "IU",
3582                     "Set to enable TX ports flow control frames for given priority. Clear to disable.");
3583
3584                 snprintf(path, sizeof(path), "rx_priority_flow_control_%u", x);
3585
3586                 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3587                     OID_AUTO, path, CTLTYPE_UINT | CTLFLAG_RWTUN |
3588                     CTLFLAG_MPSAFE, priv, x, &mlx5e_sysctl_rx_priority_flow_control, "IU",
3589                     "Set to enable RX ports flow control frames for given priority. Clear to disable.");
3590         }
3591
3592         PRIV_LOCK(priv);
3593
3594         /* range check */
3595         priv->params.tx_pauseframe_control =
3596             priv->params.tx_pauseframe_control ? 1 : 0;
3597         priv->params.rx_pauseframe_control =
3598             priv->params.rx_pauseframe_control ? 1 : 0;
3599
3600         /* update firmware */
3601         error = mlx5e_set_port_pause_and_pfc(priv);
3602         if (error == -EINVAL) {
3603                 if_printf(priv->ifp,
3604                     "Global pauseframes must be disabled before enabling PFC.\n");
3605                 priv->params.rx_priority_flow_control = 0;
3606                 priv->params.tx_priority_flow_control = 0;
3607
3608                 /* update firmware */
3609                 (void) mlx5e_set_port_pause_and_pfc(priv);
3610         }
3611         PRIV_UNLOCK(priv);
3612 }
3613
3614 static int
3615 mlx5e_ul_snd_tag_alloc(struct ifnet *ifp,
3616     union if_snd_tag_alloc_params *params,
3617     struct m_snd_tag **ppmt)
3618 {
3619         struct mlx5e_priv *priv;
3620         struct mlx5e_channel *pch;
3621
3622         priv = ifp->if_softc;
3623
3624         if (unlikely(priv->gone || params->hdr.flowtype == M_HASHTYPE_NONE)) {
3625                 return (EOPNOTSUPP);
3626         } else {
3627                 /* keep this code synced with mlx5e_select_queue() */
3628                 u32 ch = priv->params.num_channels;
3629 #ifdef RSS
3630                 u32 temp;
3631
3632                 if (rss_hash2bucket(params->hdr.flowid,
3633                     params->hdr.flowtype, &temp) == 0)
3634                         ch = temp % ch;
3635                 else
3636 #endif
3637                         ch = (params->hdr.flowid % 128) % ch;
3638
3639                 /*
3640                  * NOTE: The channels array is only freed at detach
3641                  * and it safe to return a pointer to the send tag
3642                  * inside the channels structure as long as we
3643                  * reference the priv.
3644                  */
3645                 pch = priv->channel + ch;
3646
3647                 /* check if send queue is not running */
3648                 if (unlikely(pch->sq[0].running == 0))
3649                         return (ENXIO);
3650                 mlx5e_ref_channel(priv);
3651                 *ppmt = &pch->tag.m_snd_tag;
3652                 return (0);
3653         }
3654 }
3655
3656 static int
3657 mlx5e_ul_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
3658 {
3659         struct mlx5e_channel *pch =
3660             container_of(pmt, struct mlx5e_channel, tag.m_snd_tag);
3661
3662         params->unlimited.max_rate = -1ULL;
3663         params->unlimited.queue_level = mlx5e_sq_queue_level(&pch->sq[0]);
3664         return (0);
3665 }
3666
3667 static void
3668 mlx5e_ul_snd_tag_free(struct m_snd_tag *pmt)
3669 {
3670         struct mlx5e_channel *pch =
3671             container_of(pmt, struct mlx5e_channel, tag.m_snd_tag);
3672
3673         mlx5e_unref_channel(pch->priv);
3674 }
3675
3676 static int
3677 mlx5e_snd_tag_alloc(struct ifnet *ifp,
3678     union if_snd_tag_alloc_params *params,
3679     struct m_snd_tag **ppmt)
3680 {
3681
3682         switch (params->hdr.type) {
3683 #ifdef RATELIMIT
3684         case IF_SND_TAG_TYPE_RATE_LIMIT:
3685                 return (mlx5e_rl_snd_tag_alloc(ifp, params, ppmt));
3686 #endif
3687         case IF_SND_TAG_TYPE_UNLIMITED:
3688                 return (mlx5e_ul_snd_tag_alloc(ifp, params, ppmt));
3689         default:
3690                 return (EOPNOTSUPP);
3691         }
3692 }
3693
3694 static int
3695 mlx5e_snd_tag_modify(struct m_snd_tag *pmt, union if_snd_tag_modify_params *params)
3696 {
3697         struct mlx5e_snd_tag *tag =
3698             container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
3699
3700         switch (tag->type) {
3701 #ifdef RATELIMIT
3702         case IF_SND_TAG_TYPE_RATE_LIMIT:
3703                 return (mlx5e_rl_snd_tag_modify(pmt, params));
3704 #endif
3705         case IF_SND_TAG_TYPE_UNLIMITED:
3706         default:
3707                 return (EOPNOTSUPP);
3708         }
3709 }
3710
3711 static int
3712 mlx5e_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
3713 {
3714         struct mlx5e_snd_tag *tag =
3715             container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
3716
3717         switch (tag->type) {
3718 #ifdef RATELIMIT
3719         case IF_SND_TAG_TYPE_RATE_LIMIT:
3720                 return (mlx5e_rl_snd_tag_query(pmt, params));
3721 #endif
3722         case IF_SND_TAG_TYPE_UNLIMITED:
3723                 return (mlx5e_ul_snd_tag_query(pmt, params));
3724         default:
3725                 return (EOPNOTSUPP);
3726         }
3727 }
3728
3729 static void
3730 mlx5e_snd_tag_free(struct m_snd_tag *pmt)
3731 {
3732         struct mlx5e_snd_tag *tag =
3733             container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
3734
3735         switch (tag->type) {
3736 #ifdef RATELIMIT
3737         case IF_SND_TAG_TYPE_RATE_LIMIT:
3738                 mlx5e_rl_snd_tag_free(pmt);
3739                 break;
3740 #endif
3741         case IF_SND_TAG_TYPE_UNLIMITED:
3742                 mlx5e_ul_snd_tag_free(pmt);
3743                 break;
3744         default:
3745                 break;
3746         }
3747 }
3748
3749 static void *
3750 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
3751 {
3752         struct ifnet *ifp;
3753         struct mlx5e_priv *priv;
3754         u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
3755         struct sysctl_oid_list *child;
3756         int ncv = mdev->priv.eq_table.num_comp_vectors;
3757         char unit[16];
3758         struct pfil_head_args pa;
3759         int err;
3760         int i;
3761         u32 eth_proto_cap;
3762
3763         if (mlx5e_check_required_hca_cap(mdev)) {
3764                 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
3765                 return (NULL);
3766         }
3767         /*
3768          * Try to allocate the priv and make room for worst-case
3769          * number of channel structures:
3770          */
3771         priv = malloc(sizeof(*priv) +
3772             (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors),
3773             M_MLX5EN, M_WAITOK | M_ZERO);
3774         mlx5e_priv_mtx_init(priv);
3775
3776         ifp = priv->ifp = if_alloc_dev(IFT_ETHER, mdev->pdev->dev.bsddev);
3777         if (ifp == NULL) {
3778                 mlx5_core_err(mdev, "if_alloc() failed\n");
3779                 goto err_free_priv;
3780         }
3781         ifp->if_softc = priv;
3782         if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev));
3783         ifp->if_mtu = ETHERMTU;
3784         ifp->if_init = mlx5e_open;
3785         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
3786         ifp->if_ioctl = mlx5e_ioctl;
3787         ifp->if_transmit = mlx5e_xmit;
3788         ifp->if_qflush = if_qflush;
3789 #if (__FreeBSD_version >= 1100000)
3790         ifp->if_get_counter = mlx5e_get_counter;
3791 #endif
3792         ifp->if_snd.ifq_maxlen = ifqmaxlen;
3793         /*
3794          * Set driver features
3795          */
3796         ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
3797         ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
3798         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
3799         ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
3800         ifp->if_capabilities |= IFCAP_LRO;
3801         ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
3802         ifp->if_capabilities |= IFCAP_HWSTATS | IFCAP_HWRXTSTMP;
3803         ifp->if_capabilities |= IFCAP_TXRTLMT;
3804         ifp->if_snd_tag_alloc = mlx5e_snd_tag_alloc;
3805         ifp->if_snd_tag_free = mlx5e_snd_tag_free;
3806         ifp->if_snd_tag_modify = mlx5e_snd_tag_modify;
3807         ifp->if_snd_tag_query = mlx5e_snd_tag_query;
3808
3809         /* set TSO limits so that we don't have to drop TX packets */
3810         ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
3811         ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
3812         ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
3813
3814         ifp->if_capenable = ifp->if_capabilities;
3815         ifp->if_hwassist = 0;
3816         if (ifp->if_capenable & IFCAP_TSO)
3817                 ifp->if_hwassist |= CSUM_TSO;
3818         if (ifp->if_capenable & IFCAP_TXCSUM)
3819                 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
3820         if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
3821                 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3822
3823         /* ifnet sysctl tree */
3824         sysctl_ctx_init(&priv->sysctl_ctx);
3825         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
3826             OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
3827         if (priv->sysctl_ifnet == NULL) {
3828                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3829                 goto err_free_sysctl;
3830         }
3831         snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
3832         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3833             OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
3834         if (priv->sysctl_ifnet == NULL) {
3835                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3836                 goto err_free_sysctl;
3837         }
3838
3839         /* HW sysctl tree */
3840         child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
3841         priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
3842             OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
3843         if (priv->sysctl_hw == NULL) {
3844                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3845                 goto err_free_sysctl;
3846         }
3847
3848         err = mlx5e_build_ifp_priv(mdev, priv, ncv);
3849         if (err) {
3850                 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err);
3851                 goto err_free_sysctl;
3852         }
3853
3854         snprintf(unit, sizeof(unit), "mce%u_wq",
3855             device_get_unit(mdev->pdev->dev.bsddev));
3856         priv->wq = alloc_workqueue(unit, 0, 1);
3857         if (priv->wq == NULL) {
3858                 if_printf(ifp, "%s: alloc_workqueue failed\n", __func__);
3859                 goto err_free_sysctl;
3860         }
3861
3862         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
3863         if (err) {
3864                 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n",
3865                     __func__, err);
3866                 goto err_free_wq;
3867         }
3868         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
3869         if (err) {
3870                 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n",
3871                     __func__, err);
3872                 goto err_unmap_free_uar;
3873         }
3874         err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
3875         if (err) {
3876                 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n",
3877                     __func__, err);
3878                 goto err_dealloc_pd;
3879         }
3880         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
3881         if (err) {
3882                 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n",
3883                     __func__, err);
3884                 goto err_dealloc_transport_domain;
3885         }
3886         mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
3887
3888         /* check if we should generate a random MAC address */
3889         if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
3890             is_zero_ether_addr(dev_addr)) {
3891                 random_ether_addr(dev_addr);
3892                 if_printf(ifp, "Assigned random MAC address\n");
3893         }
3894 #ifdef RATELIMIT
3895         err = mlx5e_rl_init(priv);
3896         if (err) {
3897                 if_printf(ifp, "%s: mlx5e_rl_init failed, %d\n",
3898                     __func__, err);
3899                 goto err_create_mkey;
3900         }
3901 #endif
3902
3903         /* set default MTU */
3904         mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
3905
3906         /* Set default media status */
3907         priv->media_status_last = IFM_AVALID;
3908         priv->media_active_last = IFM_ETHER | IFM_AUTO |
3909             IFM_ETH_RXPAUSE | IFM_FDX;
3910
3911         /* setup default pauseframes configuration */
3912         mlx5e_setup_pauseframes(priv);
3913
3914         err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
3915         if (err) {
3916                 eth_proto_cap = 0;
3917                 if_printf(ifp, "%s: Query port media capability failed, %d\n",
3918                     __func__, err);
3919         }
3920
3921         /* Setup supported medias */
3922         ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
3923             mlx5e_media_change, mlx5e_media_status);
3924
3925         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
3926                 if (mlx5e_mode_table[i].baudrate == 0)
3927                         continue;
3928                 if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
3929                         ifmedia_add(&priv->media,
3930                             mlx5e_mode_table[i].subtype |
3931                             IFM_ETHER, 0, NULL);
3932                         ifmedia_add(&priv->media,
3933                             mlx5e_mode_table[i].subtype |
3934                             IFM_ETHER | IFM_FDX |
3935                             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3936                 }
3937         }
3938
3939         /* Additional supported medias */
3940         ifmedia_add(&priv->media, IFM_10G_LR | IFM_ETHER, 0, NULL);
3941         ifmedia_add(&priv->media, IFM_10G_LR |
3942             IFM_ETHER | IFM_FDX |
3943             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3944
3945         ifmedia_add(&priv->media, IFM_40G_ER4 | IFM_ETHER, 0, NULL);
3946         ifmedia_add(&priv->media, IFM_40G_ER4 |
3947             IFM_ETHER | IFM_FDX |
3948             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3949
3950         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
3951         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3952             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3953
3954         /* Set autoselect by default */
3955         ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3956             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
3957         ether_ifattach(ifp, dev_addr);
3958
3959         /* Register for VLAN events */
3960         priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
3961             mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
3962         priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
3963             mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
3964
3965         /* Link is down by default */
3966         if_link_state_change(ifp, LINK_STATE_DOWN);
3967
3968         mlx5e_enable_async_events(priv);
3969
3970         mlx5e_add_hw_stats(priv);
3971
3972         mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3973             "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
3974             priv->stats.vport.arg);
3975
3976         mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3977             "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
3978             priv->stats.pport.arg);
3979
3980         mlx5e_create_ethtool(priv);
3981
3982         mtx_lock(&priv->async_events_mtx);
3983         mlx5e_update_stats(priv);
3984         mtx_unlock(&priv->async_events_mtx);
3985
3986         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3987             OID_AUTO, "rx_clbr_done", CTLFLAG_RD,
3988             &priv->clbr_done, 0,
3989             "RX timestamps calibration state");
3990         callout_init(&priv->tstmp_clbr, CALLOUT_DIRECT);
3991         mlx5e_reset_calibration_callout(priv);
3992
3993         pa.pa_version = PFIL_VERSION;
3994         pa.pa_flags = PFIL_IN;
3995         pa.pa_type = PFIL_TYPE_ETHERNET;
3996         pa.pa_headname = ifp->if_xname;
3997         priv->pfil = pfil_head_register(&pa);
3998
3999         return (priv);
4000
4001 #ifdef RATELIMIT
4002 err_create_mkey:
4003         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
4004 #endif
4005 err_dealloc_transport_domain:
4006         mlx5_dealloc_transport_domain(mdev, priv->tdn);
4007
4008 err_dealloc_pd:
4009         mlx5_core_dealloc_pd(mdev, priv->pdn);
4010
4011 err_unmap_free_uar:
4012         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
4013
4014 err_free_wq:
4015         destroy_workqueue(priv->wq);
4016
4017 err_free_sysctl:
4018         sysctl_ctx_free(&priv->sysctl_ctx);
4019         if (priv->sysctl_debug)
4020                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4021         if_free(ifp);
4022
4023 err_free_priv:
4024         mlx5e_priv_mtx_destroy(priv);
4025         free(priv, M_MLX5EN);
4026         return (NULL);
4027 }
4028
4029 static void
4030 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
4031 {
4032         struct mlx5e_priv *priv = vpriv;
4033         struct ifnet *ifp = priv->ifp;
4034
4035         /* don't allow more IOCTLs */
4036         priv->gone = 1;
4037
4038         /* XXX wait a bit to allow IOCTL handlers to complete */
4039         pause("W", hz);
4040
4041 #ifdef RATELIMIT
4042         /*
4043          * The kernel can have reference(s) via the m_snd_tag's into
4044          * the ratelimit channels, and these must go away before
4045          * detaching:
4046          */
4047         while (READ_ONCE(priv->rl.stats.tx_active_connections) != 0) {
4048                 if_printf(priv->ifp, "Waiting for all ratelimit connections "
4049                     "to terminate\n");
4050                 pause("W", hz);
4051         }
4052 #endif
4053         /* stop watchdog timer */
4054         callout_drain(&priv->watchdog);
4055
4056         callout_drain(&priv->tstmp_clbr);
4057
4058         if (priv->vlan_attach != NULL)
4059                 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
4060         if (priv->vlan_detach != NULL)
4061                 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
4062
4063         /* make sure device gets closed */
4064         PRIV_LOCK(priv);
4065         mlx5e_close_locked(ifp);
4066         PRIV_UNLOCK(priv);
4067
4068         /* wait for all unlimited send tags to go away */
4069         while (priv->channel_refs != 0) {
4070                 if_printf(priv->ifp, "Waiting for all unlimited connections "
4071                     "to terminate\n");
4072                 pause("W", hz);
4073         }
4074
4075         /* deregister pfil */
4076         if (priv->pfil != NULL) {
4077                 pfil_head_unregister(priv->pfil);
4078                 priv->pfil = NULL;
4079         }
4080
4081         /* unregister device */
4082         ifmedia_removeall(&priv->media);
4083         ether_ifdetach(ifp);
4084         if_free(ifp);
4085
4086 #ifdef RATELIMIT
4087         mlx5e_rl_cleanup(priv);
4088 #endif
4089         /* destroy all remaining sysctl nodes */
4090         sysctl_ctx_free(&priv->stats.vport.ctx);
4091         sysctl_ctx_free(&priv->stats.pport.ctx);
4092         if (priv->sysctl_debug)
4093                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4094         sysctl_ctx_free(&priv->sysctl_ctx);
4095
4096         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
4097         mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
4098         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
4099         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
4100         mlx5e_disable_async_events(priv);
4101         destroy_workqueue(priv->wq);
4102         mlx5e_priv_mtx_destroy(priv);
4103         free(priv, M_MLX5EN);
4104 }
4105
4106 static void *
4107 mlx5e_get_ifp(void *vpriv)
4108 {
4109         struct mlx5e_priv *priv = vpriv;
4110
4111         return (priv->ifp);
4112 }
4113
4114 static struct mlx5_interface mlx5e_interface = {
4115         .add = mlx5e_create_ifp,
4116         .remove = mlx5e_destroy_ifp,
4117         .event = mlx5e_async_event,
4118         .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4119         .get_dev = mlx5e_get_ifp,
4120 };
4121
4122 void
4123 mlx5e_init(void)
4124 {
4125         mlx5_register_interface(&mlx5e_interface);
4126 }
4127
4128 void
4129 mlx5e_cleanup(void)
4130 {
4131         mlx5_unregister_interface(&mlx5e_interface);
4132 }
4133
4134 static void
4135 mlx5e_show_version(void __unused *arg)
4136 {
4137
4138         printf("%s", mlx5e_version);
4139 }
4140 SYSINIT(mlx5e_show_version, SI_SUB_DRIVERS, SI_ORDER_ANY, mlx5e_show_version, NULL);
4141
4142 module_init_order(mlx5e_init, SI_ORDER_THIRD);
4143 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
4144
4145 #if (__FreeBSD_version >= 1100000)
4146 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
4147 #endif
4148 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
4149 MODULE_VERSION(mlx5en, 1);