sys/dev/mlx5/mlx5_en/mlx5_en_main.c

   1 /*-
   2  * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include "opt_kern_tls.h"
  29
  30 #include "en.h"
  31
  32 #include <sys/eventhandler.h>
  33 #include <sys/sockio.h>
  34 #include <machine/atomic.h>
  35
  36 #include <net/debugnet.h>
  37
  38 #ifndef ETH_DRIVER_VERSION
  39 #define ETH_DRIVER_VERSION      "3.5.2"
  40 #endif
  41 #define DRIVER_RELDATE  "September 2019"
  42
  43 static const char mlx5e_version[] = "mlx5en: Mellanox Ethernet driver "
  44         ETH_DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
  45
  46 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs);
  47
  48 struct mlx5e_channel_param {
  49         struct mlx5e_rq_param rq;
  50         struct mlx5e_sq_param sq;
  51         struct mlx5e_cq_param rx_cq;
  52         struct mlx5e_cq_param tx_cq;
  53 };
  54
  55 struct media {
  56         u32     subtype;
  57         u64     baudrate;
  58 };
  59
  60 static const struct media mlx5e_mode_table[MLX5E_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = {
  61
  62         [MLX5E_1000BASE_CX_SGMII][MLX5E_SGMII] = {
  63                 .subtype = IFM_1000_CX_SGMII,
  64                 .baudrate = IF_Mbps(1000ULL),
  65         },
  66         [MLX5E_1000BASE_KX][MLX5E_KX] = {
  67                 .subtype = IFM_1000_KX,
  68                 .baudrate = IF_Mbps(1000ULL),
  69         },
  70         [MLX5E_10GBASE_CX4][MLX5E_CX4] = {
  71                 .subtype = IFM_10G_CX4,
  72                 .baudrate = IF_Gbps(10ULL),
  73         },
  74         [MLX5E_10GBASE_KX4][MLX5E_KX4] = {
  75                 .subtype = IFM_10G_KX4,
  76                 .baudrate = IF_Gbps(10ULL),
  77         },
  78         [MLX5E_10GBASE_KR][MLX5E_KR] = {
  79                 .subtype = IFM_10G_KR,
  80                 .baudrate = IF_Gbps(10ULL),
  81         },
  82         [MLX5E_20GBASE_KR2][MLX5E_KR2] = {
  83                 .subtype = IFM_20G_KR2,
  84                 .baudrate = IF_Gbps(20ULL),
  85         },
  86         [MLX5E_40GBASE_CR4][MLX5E_CR4] = {
  87                 .subtype = IFM_40G_CR4,
  88                 .baudrate = IF_Gbps(40ULL),
  89         },
  90         [MLX5E_40GBASE_KR4][MLX5E_KR4] = {
  91                 .subtype = IFM_40G_KR4,
  92                 .baudrate = IF_Gbps(40ULL),
  93         },
  94         [MLX5E_56GBASE_R4][MLX5E_R] = {
  95                 .subtype = IFM_56G_R4,
  96                 .baudrate = IF_Gbps(56ULL),
  97         },
  98         [MLX5E_10GBASE_CR][MLX5E_CR1] = {
  99                 .subtype = IFM_10G_CR1,
 100                 .baudrate = IF_Gbps(10ULL),
 101         },
 102         [MLX5E_10GBASE_SR][MLX5E_SR] = {
 103                 .subtype = IFM_10G_SR,
 104                 .baudrate = IF_Gbps(10ULL),
 105         },
 106         [MLX5E_10GBASE_ER_LR][MLX5E_ER] = {
 107                 .subtype = IFM_10G_ER,
 108                 .baudrate = IF_Gbps(10ULL),
 109         },
 110         [MLX5E_10GBASE_ER_LR][MLX5E_LR] = {
 111                 .subtype = IFM_10G_LR,
 112                 .baudrate = IF_Gbps(10ULL),
 113         },
 114         [MLX5E_40GBASE_SR4][MLX5E_SR4] = {
 115                 .subtype = IFM_40G_SR4,
 116                 .baudrate = IF_Gbps(40ULL),
 117         },
 118         [MLX5E_40GBASE_LR4_ER4][MLX5E_LR4] = {
 119                 .subtype = IFM_40G_LR4,
 120                 .baudrate = IF_Gbps(40ULL),
 121         },
 122         [MLX5E_40GBASE_LR4_ER4][MLX5E_ER4] = {
 123                 .subtype = IFM_40G_ER4,
 124                 .baudrate = IF_Gbps(40ULL),
 125         },
 126         [MLX5E_100GBASE_CR4][MLX5E_CR4] = {
 127                 .subtype = IFM_100G_CR4,
 128                 .baudrate = IF_Gbps(100ULL),
 129         },
 130         [MLX5E_100GBASE_SR4][MLX5E_SR4] = {
 131                 .subtype = IFM_100G_SR4,
 132                 .baudrate = IF_Gbps(100ULL),
 133         },
 134         [MLX5E_100GBASE_KR4][MLX5E_KR4] = {
 135                 .subtype = IFM_100G_KR4,
 136                 .baudrate = IF_Gbps(100ULL),
 137         },
 138         [MLX5E_100GBASE_LR4][MLX5E_LR4] = {
 139                 .subtype = IFM_100G_LR4,
 140                 .baudrate = IF_Gbps(100ULL),
 141         },
 142         [MLX5E_100BASE_TX][MLX5E_TX] = {
 143                 .subtype = IFM_100_TX,
 144                 .baudrate = IF_Mbps(100ULL),
 145         },
 146         [MLX5E_1000BASE_T][MLX5E_T] = {
 147                 .subtype = IFM_1000_T,
 148                 .baudrate = IF_Mbps(1000ULL),
 149         },
 150         [MLX5E_10GBASE_T][MLX5E_T] = {
 151                 .subtype = IFM_10G_T,
 152                 .baudrate = IF_Gbps(10ULL),
 153         },
 154         [MLX5E_25GBASE_CR][MLX5E_CR] = {
 155                 .subtype = IFM_25G_CR,
 156                 .baudrate = IF_Gbps(25ULL),
 157         },
 158         [MLX5E_25GBASE_KR][MLX5E_KR] = {
 159                 .subtype = IFM_25G_KR,
 160                 .baudrate = IF_Gbps(25ULL),
 161         },
 162         [MLX5E_25GBASE_SR][MLX5E_SR] = {
 163                 .subtype = IFM_25G_SR,
 164                 .baudrate = IF_Gbps(25ULL),
 165         },
 166         [MLX5E_50GBASE_CR2][MLX5E_CR2] = {
 167                 .subtype = IFM_50G_CR2,
 168                 .baudrate = IF_Gbps(50ULL),
 169         },
 170         [MLX5E_50GBASE_KR2][MLX5E_KR2] = {
 171                 .subtype = IFM_50G_KR2,
 172                 .baudrate = IF_Gbps(50ULL),
 173         },
 174         [MLX5E_50GBASE_KR4][MLX5E_KR4] = {
 175                 .subtype = IFM_50G_KR4,
 176                 .baudrate = IF_Gbps(50ULL),
 177         },
 178 };
 179
 180 static const struct media mlx5e_ext_mode_table[MLX5E_EXT_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = {
 181         [MLX5E_SGMII_100M][MLX5E_SGMII] = {
 182                 .subtype = IFM_100_SGMII,
 183                 .baudrate = IF_Mbps(100),
 184         },
 185         [MLX5E_1000BASE_X_SGMII][MLX5E_KX] = {
 186                 .subtype = IFM_1000_KX,
 187                 .baudrate = IF_Mbps(1000),
 188         },
 189         [MLX5E_1000BASE_X_SGMII][MLX5E_CX_SGMII] = {
 190                 .subtype = IFM_1000_CX_SGMII,
 191                 .baudrate = IF_Mbps(1000),
 192         },
 193         [MLX5E_1000BASE_X_SGMII][MLX5E_CX] = {
 194                 .subtype = IFM_1000_CX,
 195                 .baudrate = IF_Mbps(1000),
 196         },
 197         [MLX5E_1000BASE_X_SGMII][MLX5E_LX] = {
 198                 .subtype = IFM_1000_LX,
 199                 .baudrate = IF_Mbps(1000),
 200         },
 201         [MLX5E_1000BASE_X_SGMII][MLX5E_SX] = {
 202                 .subtype = IFM_1000_SX,
 203                 .baudrate = IF_Mbps(1000),
 204         },
 205         [MLX5E_1000BASE_X_SGMII][MLX5E_T] = {
 206                 .subtype = IFM_1000_T,
 207                 .baudrate = IF_Mbps(1000),
 208         },
 209         [MLX5E_5GBASE_R][MLX5E_T] = {
 210                 .subtype = IFM_5000_T,
 211                 .baudrate = IF_Mbps(5000),
 212         },
 213         [MLX5E_5GBASE_R][MLX5E_KR] = {
 214                 .subtype = IFM_5000_KR,
 215                 .baudrate = IF_Mbps(5000),
 216         },
 217         [MLX5E_5GBASE_R][MLX5E_KR1] = {
 218                 .subtype = IFM_5000_KR1,
 219                 .baudrate = IF_Mbps(5000),
 220         },
 221         [MLX5E_5GBASE_R][MLX5E_KR_S] = {
 222                 .subtype = IFM_5000_KR_S,
 223                 .baudrate = IF_Mbps(5000),
 224         },
 225         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_ER] = {
 226                 .subtype = IFM_10G_ER,
 227                 .baudrate = IF_Gbps(10ULL),
 228         },
 229         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_KR] = {
 230                 .subtype = IFM_10G_KR,
 231                 .baudrate = IF_Gbps(10ULL),
 232         },
 233         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_LR] = {
 234                 .subtype = IFM_10G_LR,
 235                 .baudrate = IF_Gbps(10ULL),
 236         },
 237         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_SR] = {
 238                 .subtype = IFM_10G_SR,
 239                 .baudrate = IF_Gbps(10ULL),
 240         },
 241         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_T] = {
 242                 .subtype = IFM_10G_T,
 243                 .baudrate = IF_Gbps(10ULL),
 244         },
 245         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_AOC] = {
 246                 .subtype = IFM_10G_AOC,
 247                 .baudrate = IF_Gbps(10ULL),
 248         },
 249         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CR1] = {
 250                 .subtype = IFM_10G_CR1,
 251                 .baudrate = IF_Gbps(10ULL),
 252         },
 253         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CR4] = {
 254                 .subtype = IFM_40G_CR4,
 255                 .baudrate = IF_Gbps(40ULL),
 256         },
 257         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_KR4] = {
 258                 .subtype = IFM_40G_KR4,
 259                 .baudrate = IF_Gbps(40ULL),
 260         },
 261         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_LR4] = {
 262                 .subtype = IFM_40G_LR4,
 263                 .baudrate = IF_Gbps(40ULL),
 264         },
 265         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_SR4] = {
 266                 .subtype = IFM_40G_SR4,
 267                 .baudrate = IF_Gbps(40ULL),
 268         },
 269         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_ER4] = {
 270                 .subtype = IFM_40G_ER4,
 271                 .baudrate = IF_Gbps(40ULL),
 272         },
 273
 274         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR] = {
 275                 .subtype = IFM_25G_CR,
 276                 .baudrate = IF_Gbps(25ULL),
 277         },
 278         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR] = {
 279                 .subtype = IFM_25G_KR,
 280                 .baudrate = IF_Gbps(25ULL),
 281         },
 282         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_SR] = {
 283                 .subtype = IFM_25G_SR,
 284                 .baudrate = IF_Gbps(25ULL),
 285         },
 286         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_ACC] = {
 287                 .subtype = IFM_25G_ACC,
 288                 .baudrate = IF_Gbps(25ULL),
 289         },
 290         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_AOC] = {
 291                 .subtype = IFM_25G_AOC,
 292                 .baudrate = IF_Gbps(25ULL),
 293         },
 294         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR1] = {
 295                 .subtype = IFM_25G_CR1,
 296                 .baudrate = IF_Gbps(25ULL),
 297         },
 298         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR_S] = {
 299                 .subtype = IFM_25G_CR_S,
 300                 .baudrate = IF_Gbps(25ULL),
 301         },
 302         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR1] = {
 303                 .subtype = IFM_5000_KR1,
 304                 .baudrate = IF_Gbps(25ULL),
 305         },
 306         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR_S] = {
 307                 .subtype = IFM_25G_KR_S,
 308                 .baudrate = IF_Gbps(25ULL),
 309         },
 310         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_LR] = {
 311                 .subtype = IFM_25G_LR,
 312                 .baudrate = IF_Gbps(25ULL),
 313         },
 314         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_T] = {
 315                 .subtype = IFM_25G_T,
 316                 .baudrate = IF_Gbps(25ULL),
 317         },
 318         [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CR2] = {
 319                 .subtype = IFM_50G_CR2,
 320                 .baudrate = IF_Gbps(50ULL),
 321         },
 322         [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_KR2] = {
 323                 .subtype = IFM_50G_KR2,
 324                 .baudrate = IF_Gbps(50ULL),
 325         },
 326         [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_KR4] = {
 327                 .subtype = IFM_50G_KR4,
 328                 .baudrate = IF_Gbps(50ULL),
 329         },
 330         [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_SR2] = {
 331                 .subtype = IFM_50G_SR2,
 332                 .baudrate = IF_Gbps(50ULL),
 333         },
 334         [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_LR2] = {
 335                 .subtype = IFM_50G_LR2,
 336                 .baudrate = IF_Gbps(50ULL),
 337         },
 338         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_LR] = {
 339                 .subtype = IFM_50G_LR,
 340                 .baudrate = IF_Gbps(50ULL),
 341         },
 342         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_SR] = {
 343                 .subtype = IFM_50G_SR,
 344                 .baudrate = IF_Gbps(50ULL),
 345         },
 346         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CP] = {
 347                 .subtype = IFM_50G_CP,
 348                 .baudrate = IF_Gbps(50ULL),
 349         },
 350         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_FR] = {
 351                 .subtype = IFM_50G_FR,
 352                 .baudrate = IF_Gbps(50ULL),
 353         },
 354         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_KR_PAM4] = {
 355                 .subtype = IFM_50G_KR_PAM4,
 356                 .baudrate = IF_Gbps(50ULL),
 357         },
 358         [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CR4] = {
 359                 .subtype = IFM_100G_CR4,
 360                 .baudrate = IF_Gbps(100ULL),
 361         },
 362         [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_KR4] = {
 363                 .subtype = IFM_100G_KR4,
 364                 .baudrate = IF_Gbps(100ULL),
 365         },
 366         [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_LR4] = {
 367                 .subtype = IFM_100G_LR4,
 368                 .baudrate = IF_Gbps(100ULL),
 369         },
 370         [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_SR4] = {
 371                 .subtype = IFM_100G_SR4,
 372                 .baudrate = IF_Gbps(100ULL),
 373         },
 374         [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_SR2] = {
 375                 .subtype = IFM_100G_SR2,
 376                 .baudrate = IF_Gbps(100ULL),
 377         },
 378         [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CP2] = {
 379                 .subtype = IFM_100G_CP2,
 380                 .baudrate = IF_Gbps(100ULL),
 381         },
 382         [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_KR2_PAM4] = {
 383                 .subtype = IFM_100G_KR2_PAM4,
 384                 .baudrate = IF_Gbps(100ULL),
 385         },
 386         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_DR4] = {
 387                 .subtype = IFM_200G_DR4,
 388                 .baudrate = IF_Gbps(200ULL),
 389         },
 390         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_LR4] = {
 391                 .subtype = IFM_200G_LR4,
 392                 .baudrate = IF_Gbps(200ULL),
 393         },
 394         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_SR4] = {
 395                 .subtype = IFM_200G_SR4,
 396                 .baudrate = IF_Gbps(200ULL),
 397         },
 398         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_FR4] = {
 399                 .subtype = IFM_200G_FR4,
 400                 .baudrate = IF_Gbps(200ULL),
 401         },
 402         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CR4_PAM4] = {
 403                 .subtype = IFM_200G_CR4_PAM4,
 404                 .baudrate = IF_Gbps(200ULL),
 405         },
 406         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_KR4_PAM4] = {
 407                 .subtype = IFM_200G_KR4_PAM4,
 408                 .baudrate = IF_Gbps(200ULL),
 409         },
 410 };
 411
 412 DEBUGNET_DEFINE(mlx5_en);
 413
 414 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
 415
 416 static void
 417 mlx5e_update_carrier(struct mlx5e_priv *priv)
 418 {
 419         struct mlx5_core_dev *mdev = priv->mdev;
 420         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 421         u32 eth_proto_oper;
 422         int error;
 423         u8 port_state;
 424         u8 is_er_type;
 425         u8 i, j;
 426         bool ext;
 427         struct media media_entry = {};
 428
 429         port_state = mlx5_query_vport_state(mdev,
 430             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 431
 432         if (port_state == VPORT_STATE_UP) {
 433                 priv->media_status_last |= IFM_ACTIVE;
 434         } else {
 435                 priv->media_status_last &= ~IFM_ACTIVE;
 436                 priv->media_active_last = IFM_ETHER;
 437                 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
 438                 return;
 439         }
 440
 441         error = mlx5_query_port_ptys(mdev, out, sizeof(out),
 442             MLX5_PTYS_EN, 1);
 443         if (error) {
 444                 priv->media_active_last = IFM_ETHER;
 445                 priv->ifp->if_baudrate = 1;
 446                 mlx5_en_err(priv->ifp, "query port ptys failed: 0x%x\n",
 447                     error);
 448                 return;
 449         }
 450
 451         ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
 452         eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
 453             eth_proto_oper);
 454
 455         i = ilog2(eth_proto_oper);
 456
 457         for (j = 0; j != MLX5E_LINK_MODES_NUMBER; j++) {
 458                 media_entry = ext ? mlx5e_ext_mode_table[i][j] :
 459                     mlx5e_mode_table[i][j];
 460                 if (media_entry.baudrate != 0)
 461                         break;
 462         }
 463
 464         if (media_entry.subtype == 0) {
 465                 mlx5_en_err(priv->ifp,
 466                     "Could not find operational media subtype\n");
 467                 return;
 468         }
 469
 470         switch (media_entry.subtype) {
 471         case IFM_10G_ER:
 472                 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
 473                 if (error != 0) {
 474                         mlx5_en_err(priv->ifp,
 475                             "query port pddr failed: %d\n", error);
 476                 }
 477                 if (error != 0 || is_er_type == 0)
 478                         media_entry.subtype = IFM_10G_LR;
 479                 break;
 480         case IFM_40G_LR4:
 481                 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
 482                 if (error != 0) {
 483                         mlx5_en_err(priv->ifp,
 484                             "query port pddr failed: %d\n", error);
 485                 }
 486                 if (error == 0 && is_er_type != 0)
 487                         media_entry.subtype = IFM_40G_ER4;
 488                 break;
 489         }
 490         priv->media_active_last = media_entry.subtype | IFM_ETHER | IFM_FDX;
 491         priv->ifp->if_baudrate = media_entry.baudrate;
 492
 493         if_link_state_change(priv->ifp, LINK_STATE_UP);
 494 }
 495
 496 static void
 497 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
 498 {
 499         struct mlx5e_priv *priv = dev->if_softc;
 500
 501         ifmr->ifm_status = priv->media_status_last;
 502         ifmr->ifm_active = priv->media_active_last |
 503             (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
 504             (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
 505
 506 }
 507
 508 static u32
 509 mlx5e_find_link_mode(u32 subtype, bool ext)
 510 {
 511         u32 i;
 512         u32 j;
 513         u32 link_mode = 0;
 514         u32 speeds_num = 0;
 515         struct media media_entry = {};
 516
 517         switch (subtype) {
 518         case IFM_10G_LR:
 519                 subtype = IFM_10G_ER;
 520                 break;
 521         case IFM_40G_ER4:
 522                 subtype = IFM_40G_LR4;
 523                 break;
 524         }
 525
 526         speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER :
 527             MLX5E_LINK_SPEEDS_NUMBER;
 528
 529         for (i = 0; i != speeds_num; i++) {
 530                 for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) {
 531                         media_entry = ext ? mlx5e_ext_mode_table[i][j] :
 532                             mlx5e_mode_table[i][j];
 533                         if (media_entry.baudrate == 0)
 534                                 continue;
 535                         if (media_entry.subtype == subtype) {
 536                                 link_mode |= MLX5E_PROT_MASK(i);
 537                         }
 538                 }
 539         }
 540
 541         return (link_mode);
 542 }
 543
 544 static int
 545 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv)
 546 {
 547         return (mlx5_set_port_pause_and_pfc(priv->mdev, 1,
 548             priv->params.rx_pauseframe_control,
 549             priv->params.tx_pauseframe_control,
 550             priv->params.rx_priority_flow_control,
 551             priv->params.tx_priority_flow_control));
 552 }
 553
 554 static int
 555 mlx5e_set_port_pfc(struct mlx5e_priv *priv)
 556 {
 557         int error;
 558
 559         if (priv->gone != 0) {
 560                 error = -ENXIO;
 561         } else if (priv->params.rx_pauseframe_control ||
 562             priv->params.tx_pauseframe_control) {
 563                 mlx5_en_err(priv->ifp,
 564                     "Global pauseframes must be disabled before enabling PFC.\n");
 565                 error = -EINVAL;
 566         } else {
 567                 error = mlx5e_set_port_pause_and_pfc(priv);
 568         }
 569         return (error);
 570 }
 571
 572 static int
 573 mlx5e_media_change(struct ifnet *dev)
 574 {
 575         struct mlx5e_priv *priv = dev->if_softc;
 576         struct mlx5_core_dev *mdev = priv->mdev;
 577         u32 eth_proto_cap;
 578         u32 link_mode;
 579         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 580         int was_opened;
 581         int locked;
 582         int error;
 583         bool ext;
 584
 585         locked = PRIV_LOCKED(priv);
 586         if (!locked)
 587                 PRIV_LOCK(priv);
 588
 589         if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
 590                 error = EINVAL;
 591                 goto done;
 592         }
 593
 594         error = mlx5_query_port_ptys(mdev, out, sizeof(out),
 595             MLX5_PTYS_EN, 1);
 596         if (error != 0) {
 597                 mlx5_en_err(dev, "Query port media capability failed\n");
 598                 goto done;
 599         }
 600
 601         ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
 602         link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media), ext);
 603
 604         /* query supported capabilities */
 605         eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
 606             eth_proto_capability);
 607
 608         /* check for autoselect */
 609         if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
 610                 link_mode = eth_proto_cap;
 611                 if (link_mode == 0) {
 612                         mlx5_en_err(dev, "Port media capability is zero\n");
 613                         error = EINVAL;
 614                         goto done;
 615                 }
 616         } else {
 617                 link_mode = link_mode & eth_proto_cap;
 618                 if (link_mode == 0) {
 619                         mlx5_en_err(dev, "Not supported link mode requested\n");
 620                         error = EINVAL;
 621                         goto done;
 622                 }
 623         }
 624         if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
 625                 /* check if PFC is enabled */
 626                 if (priv->params.rx_priority_flow_control ||
 627                     priv->params.tx_priority_flow_control) {
 628                         mlx5_en_err(dev, "PFC must be disabled before enabling global pauseframes.\n");
 629                         error = EINVAL;
 630                         goto done;
 631                 }
 632         }
 633         /* update pauseframe control bits */
 634         priv->params.rx_pauseframe_control =
 635             (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
 636         priv->params.tx_pauseframe_control =
 637             (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
 638
 639         /* check if device is opened */
 640         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
 641
 642         /* reconfigure the hardware */
 643         mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
 644         mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN, ext);
 645         error = -mlx5e_set_port_pause_and_pfc(priv);
 646         if (was_opened)
 647                 mlx5_set_port_status(mdev, MLX5_PORT_UP);
 648
 649 done:
 650         if (!locked)
 651                 PRIV_UNLOCK(priv);
 652         return (error);
 653 }
 654
 655 static void
 656 mlx5e_update_carrier_work(struct work_struct *work)
 657 {
 658         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 659             update_carrier_work);
 660
 661         PRIV_LOCK(priv);
 662         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 663                 mlx5e_update_carrier(priv);
 664         PRIV_UNLOCK(priv);
 665 }
 666
 667 #define MLX5E_PCIE_PERF_GET_64(a,b,c,d,e,f)    \
 668         s_debug->c = MLX5_GET64(mpcnt_reg, out, counter_set.f.c);
 669
 670 #define MLX5E_PCIE_PERF_GET_32(a,b,c,d,e,f)    \
 671         s_debug->c = MLX5_GET(mpcnt_reg, out, counter_set.f.c);
 672
 673 static void
 674 mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
 675 {
 676         struct mlx5_core_dev *mdev = priv->mdev;
 677         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 678         const unsigned sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
 679         void *out;
 680         void *in;
 681         int err;
 682
 683         /* allocate firmware request structures */
 684         in = mlx5_vzalloc(sz);
 685         out = mlx5_vzalloc(sz);
 686         if (in == NULL || out == NULL)
 687                 goto free_out;
 688
 689         MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
 690         err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
 691         if (err != 0)
 692                 goto free_out;
 693
 694         MLX5E_PCIE_PERFORMANCE_COUNTERS_64(MLX5E_PCIE_PERF_GET_64)
 695         MLX5E_PCIE_PERFORMANCE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
 696
 697         MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP);
 698         err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
 699         if (err != 0)
 700                 goto free_out;
 701
 702         MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
 703
 704         MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_LANE_COUNTERS_GROUP);
 705         err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
 706         if (err != 0)
 707                 goto free_out;
 708
 709         MLX5E_PCIE_LANE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
 710
 711 free_out:
 712         /* free firmware request structures */
 713         kvfree(in);
 714         kvfree(out);
 715 }
 716
 717 /*
 718  * This function reads the physical port counters from the firmware
 719  * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
 720  * macros. The output is converted from big-endian 64-bit values into
 721  * host endian ones and stored in the "priv->stats.pport" structure.
 722  */
 723 static void
 724 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 725 {
 726         struct mlx5_core_dev *mdev = priv->mdev;
 727         struct mlx5e_pport_stats *s = &priv->stats.pport;
 728         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 729         u32 *in;
 730         u32 *out;
 731         const u64 *ptr;
 732         unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 733         unsigned x;
 734         unsigned y;
 735         unsigned z;
 736
 737         /* allocate firmware request structures */
 738         in = mlx5_vzalloc(sz);
 739         out = mlx5_vzalloc(sz);
 740         if (in == NULL || out == NULL)
 741                 goto free_out;
 742
 743         /*
 744          * Get pointer to the 64-bit counter set which is located at a
 745          * fixed offset in the output firmware request structure:
 746          */
 747         ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
 748
 749         MLX5_SET(ppcnt_reg, in, local_port, 1);
 750
 751         /* read IEEE802_3 counter group using predefined counter layout */
 752         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 753         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 754         for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM;
 755              x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
 756                 s->arg[y] = be64toh(ptr[x]);
 757
 758         /* read RFC2819 counter group using predefined counter layout */
 759         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 760         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 761         for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
 762                 s->arg[y] = be64toh(ptr[x]);
 763
 764         for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
 765             MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
 766                 s_debug->arg[y] = be64toh(ptr[x]);
 767
 768         /* read RFC2863 counter group using predefined counter layout */
 769         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 770         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 771         for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
 772                 s_debug->arg[y] = be64toh(ptr[x]);
 773
 774         /* read physical layer stats counter group using predefined counter layout */
 775         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 776         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 777         for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
 778                 s_debug->arg[y] = be64toh(ptr[x]);
 779
 780         /* read Extended Ethernet counter group using predefined counter layout */
 781         MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
 782         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 783         for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++)
 784                 s_debug->arg[y] = be64toh(ptr[x]);
 785
 786         /* read Extended Statistical Group */
 787         if (MLX5_CAP_GEN(mdev, pcam_reg) &&
 788             MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) &&
 789             MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) {
 790                 /* read Extended Statistical counter group using predefined counter layout */
 791                 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
 792                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 793
 794                 for (x = 0; x != MLX5E_PPORT_STATISTICAL_DEBUG_NUM; x++, y++)
 795                         s_debug->arg[y] = be64toh(ptr[x]);
 796         }
 797
 798         /* read PCIE counters */
 799         mlx5e_update_pcie_counters(priv);
 800
 801         /* read per-priority counters */
 802         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 803
 804         /* iterate all the priorities */
 805         for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) {
 806                 MLX5_SET(ppcnt_reg, in, prio_tc, z);
 807                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 808
 809                 /* read per priority stats counter group using predefined counter layout */
 810                 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM /
 811                     MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++)
 812                         s->arg[y] = be64toh(ptr[x]);
 813         }
 814
 815 free_out:
 816         /* free firmware request structures */
 817         kvfree(in);
 818         kvfree(out);
 819 }
 820
 821 static void
 822 mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv)
 823 {
 824         u32 out[MLX5_ST_SZ_DW(query_vnic_env_out)] = {};
 825         u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {};
 826
 827         if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
 828                 return;
 829
 830         MLX5_SET(query_vnic_env_in, in, opcode,
 831             MLX5_CMD_OP_QUERY_VNIC_ENV);
 832         MLX5_SET(query_vnic_env_in, in, op_mod, 0);
 833         MLX5_SET(query_vnic_env_in, in, other_vport, 0);
 834
 835         if (mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out)) != 0)
 836                 return;
 837
 838         priv->stats.vport.rx_steer_missed_packets =
 839             MLX5_GET64(query_vnic_env_out, out,
 840             vport_env.nic_receive_steering_discard);
 841 }
 842
 843 /*
 844  * This function is called regularly to collect all statistics
 845  * counters from the firmware. The values can be viewed through the
 846  * sysctl interface. Execution is serialized using the priv's global
 847  * configuration lock.
 848  */
 849 static void
 850 mlx5e_update_stats_locked(struct mlx5e_priv *priv)
 851 {
 852         struct mlx5_core_dev *mdev = priv->mdev;
 853         struct mlx5e_vport_stats *s = &priv->stats.vport;
 854         struct mlx5e_sq_stats *sq_stats;
 855 #if (__FreeBSD_version < 1100000)
 856         struct ifnet *ifp = priv->ifp;
 857 #endif
 858
 859         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 860         u32 *out;
 861         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 862         u64 tso_packets = 0;
 863         u64 tso_bytes = 0;
 864         u64 tx_queue_dropped = 0;
 865         u64 tx_defragged = 0;
 866         u64 tx_offload_none = 0;
 867         u64 lro_packets = 0;
 868         u64 lro_bytes = 0;
 869         u64 sw_lro_queued = 0;
 870         u64 sw_lro_flushed = 0;
 871         u64 rx_csum_none = 0;
 872         u64 rx_wqe_err = 0;
 873         u64 rx_packets = 0;
 874         u64 rx_bytes = 0;
 875         u32 rx_out_of_buffer = 0;
 876         int error;
 877         int i;
 878         int j;
 879
 880         out = mlx5_vzalloc(outlen);
 881         if (out == NULL)
 882                 goto free_out;
 883
 884         /* Collect firts the SW counters and then HW for consistency */
 885         for (i = 0; i < priv->params.num_channels; i++) {
 886                 struct mlx5e_channel *pch = priv->channel + i;
 887                 struct mlx5e_rq *rq = &pch->rq;
 888                 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats;
 889
 890                 /* collect stats from LRO */
 891                 rq_stats->sw_lro_queued = rq->lro.lro_queued;
 892                 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
 893                 sw_lro_queued += rq_stats->sw_lro_queued;
 894                 sw_lro_flushed += rq_stats->sw_lro_flushed;
 895                 lro_packets += rq_stats->lro_packets;
 896                 lro_bytes += rq_stats->lro_bytes;
 897                 rx_csum_none += rq_stats->csum_none;
 898                 rx_wqe_err += rq_stats->wqe_err;
 899                 rx_packets += rq_stats->packets;
 900                 rx_bytes += rq_stats->bytes;
 901
 902                 for (j = 0; j < priv->num_tc; j++) {
 903                         sq_stats = &pch->sq[j].stats;
 904
 905                         tso_packets += sq_stats->tso_packets;
 906                         tso_bytes += sq_stats->tso_bytes;
 907                         tx_queue_dropped += sq_stats->dropped;
 908                         tx_queue_dropped += sq_stats->enobuf;
 909                         tx_defragged += sq_stats->defragged;
 910                         tx_offload_none += sq_stats->csum_offload_none;
 911                 }
 912         }
 913
 914         /* update counters */
 915         s->tso_packets = tso_packets;
 916         s->tso_bytes = tso_bytes;
 917         s->tx_queue_dropped = tx_queue_dropped;
 918         s->tx_defragged = tx_defragged;
 919         s->lro_packets = lro_packets;
 920         s->lro_bytes = lro_bytes;
 921         s->sw_lro_queued = sw_lro_queued;
 922         s->sw_lro_flushed = sw_lro_flushed;
 923         s->rx_csum_none = rx_csum_none;
 924         s->rx_wqe_err = rx_wqe_err;
 925         s->rx_packets = rx_packets;
 926         s->rx_bytes = rx_bytes;
 927
 928         mlx5e_grp_vnic_env_update_stats(priv);
 929
 930         /* HW counters */
 931         memset(in, 0, sizeof(in));
 932
 933         MLX5_SET(query_vport_counter_in, in, opcode,
 934             MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 935         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 936         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 937
 938         memset(out, 0, outlen);
 939
 940         /* get number of out-of-buffer drops first */
 941         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 &&
 942             mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
 943             &rx_out_of_buffer) == 0) {
 944                 s->rx_out_of_buffer = rx_out_of_buffer;
 945         }
 946
 947         /* get port statistics */
 948         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen) == 0) {
 949 #define MLX5_GET_CTR(out, x) \
 950         MLX5_GET64(query_vport_counter_out, out, x)
 951
 952                 s->rx_error_packets =
 953                     MLX5_GET_CTR(out, received_errors.packets);
 954                 s->rx_error_bytes =
 955                     MLX5_GET_CTR(out, received_errors.octets);
 956                 s->tx_error_packets =
 957                     MLX5_GET_CTR(out, transmit_errors.packets);
 958                 s->tx_error_bytes =
 959                     MLX5_GET_CTR(out, transmit_errors.octets);
 960
 961                 s->rx_unicast_packets =
 962                     MLX5_GET_CTR(out, received_eth_unicast.packets);
 963                 s->rx_unicast_bytes =
 964                     MLX5_GET_CTR(out, received_eth_unicast.octets);
 965                 s->tx_unicast_packets =
 966                     MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 967                 s->tx_unicast_bytes =
 968                     MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 969
 970                 s->rx_multicast_packets =
 971                     MLX5_GET_CTR(out, received_eth_multicast.packets);
 972                 s->rx_multicast_bytes =
 973                     MLX5_GET_CTR(out, received_eth_multicast.octets);
 974                 s->tx_multicast_packets =
 975                     MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 976                 s->tx_multicast_bytes =
 977                     MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 978
 979                 s->rx_broadcast_packets =
 980                     MLX5_GET_CTR(out, received_eth_broadcast.packets);
 981                 s->rx_broadcast_bytes =
 982                     MLX5_GET_CTR(out, received_eth_broadcast.octets);
 983                 s->tx_broadcast_packets =
 984                     MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 985                 s->tx_broadcast_bytes =
 986                     MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 987
 988                 s->tx_packets = s->tx_unicast_packets +
 989                     s->tx_multicast_packets + s->tx_broadcast_packets;
 990                 s->tx_bytes = s->tx_unicast_bytes + s->tx_multicast_bytes +
 991                     s->tx_broadcast_bytes;
 992
 993                 /* Update calculated offload counters */
 994                 s->tx_csum_offload = s->tx_packets - tx_offload_none;
 995                 s->rx_csum_good = s->rx_packets - s->rx_csum_none;
 996         }
 997
 998         /* Get physical port counters */
 999         mlx5e_update_pport_counters(priv);
1000
1001         s->tx_jumbo_packets =
1002             priv->stats.port_stats_debug.tx_stat_p1519to2047octets +
1003             priv->stats.port_stats_debug.tx_stat_p2048to4095octets +
1004             priv->stats.port_stats_debug.tx_stat_p4096to8191octets +
1005             priv->stats.port_stats_debug.tx_stat_p8192to10239octets;
1006
1007 #if (__FreeBSD_version < 1100000)
1008         /* no get_counters interface in fbsd 10 */
1009         ifp->if_ipackets = s->rx_packets;
1010         ifp->if_ierrors = priv->stats.pport.in_range_len_errors +
1011             priv->stats.pport.out_of_range_len +
1012             priv->stats.pport.too_long_errors +
1013             priv->stats.pport.check_seq_err +
1014             priv->stats.pport.alignment_err;
1015         ifp->if_iqdrops = s->rx_out_of_buffer;
1016         ifp->if_opackets = s->tx_packets;
1017         ifp->if_oerrors = priv->stats.port_stats_debug.out_discards;
1018         ifp->if_snd.ifq_drops = s->tx_queue_dropped;
1019         ifp->if_ibytes = s->rx_bytes;
1020         ifp->if_obytes = s->tx_bytes;
1021         ifp->if_collisions =
1022             priv->stats.pport.collisions;
1023 #endif
1024
1025 free_out:
1026         kvfree(out);
1027
1028         /* Update diagnostics, if any */
1029         if (priv->params_ethtool.diag_pci_enable ||
1030             priv->params_ethtool.diag_general_enable) {
1031                 error = mlx5_core_get_diagnostics_full(mdev,
1032                     priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL,
1033                     priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL);
1034                 if (error != 0)
1035                         mlx5_en_err(priv->ifp,
1036                             "Failed reading diagnostics: %d\n", error);
1037         }
1038
1039         /* Update FEC, if any */
1040         error = mlx5e_fec_update(priv);
1041         if (error != 0 && error != EOPNOTSUPP) {
1042                 mlx5_en_err(priv->ifp,
1043                     "Updating FEC failed: %d\n", error);
1044         }
1045
1046         /* Update temperature, if any */
1047         if (priv->params_ethtool.hw_num_temp != 0) {
1048                 error = mlx5e_hw_temperature_update(priv);
1049                 if (error != 0 && error != EOPNOTSUPP) {
1050                         mlx5_en_err(priv->ifp,
1051                             "Updating temperature failed: %d\n", error);
1052                 }
1053         }
1054 }
1055
1056 static void
1057 mlx5e_update_stats_work(struct work_struct *work)
1058 {
1059         struct mlx5e_priv *priv;
1060
1061         priv = container_of(work, struct mlx5e_priv, update_stats_work);
1062         PRIV_LOCK(priv);
1063         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 &&
1064             !test_bit(MLX5_INTERFACE_STATE_TEARDOWN, &priv->mdev->intf_state))
1065                 mlx5e_update_stats_locked(priv);
1066         PRIV_UNLOCK(priv);
1067 }
1068
1069 static void
1070 mlx5e_update_stats(void *arg)
1071 {
1072         struct mlx5e_priv *priv = arg;
1073
1074         queue_work(priv->wq, &priv->update_stats_work);
1075
1076         callout_reset(&priv->watchdog, hz / 4, &mlx5e_update_stats, priv);
1077 }
1078
1079 static void
1080 mlx5e_async_event_sub(struct mlx5e_priv *priv,
1081     enum mlx5_dev_event event)
1082 {
1083         switch (event) {
1084         case MLX5_DEV_EVENT_PORT_UP:
1085         case MLX5_DEV_EVENT_PORT_DOWN:
1086                 queue_work(priv->wq, &priv->update_carrier_work);
1087                 break;
1088
1089         default:
1090                 break;
1091         }
1092 }
1093
1094 static void
1095 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
1096     enum mlx5_dev_event event, unsigned long param)
1097 {
1098         struct mlx5e_priv *priv = vpriv;
1099
1100         mtx_lock(&priv->async_events_mtx);
1101         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
1102                 mlx5e_async_event_sub(priv, event);
1103         mtx_unlock(&priv->async_events_mtx);
1104 }
1105
1106 static void
1107 mlx5e_enable_async_events(struct mlx5e_priv *priv)
1108 {
1109         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
1110 }
1111
1112 static void
1113 mlx5e_disable_async_events(struct mlx5e_priv *priv)
1114 {
1115         mtx_lock(&priv->async_events_mtx);
1116         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
1117         mtx_unlock(&priv->async_events_mtx);
1118 }
1119
1120 static void mlx5e_calibration_callout(void *arg);
1121 static int mlx5e_calibration_duration = 20;
1122 static int mlx5e_fast_calibration = 1;
1123 static int mlx5e_normal_calibration = 30;
1124
1125 static SYSCTL_NODE(_hw_mlx5, OID_AUTO, calibr, CTLFLAG_RW | CTLFLAG_MPSAFE, 0,
1126     "MLX5 timestamp calibration parameteres");
1127
1128 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, duration, CTLFLAG_RWTUN,
1129     &mlx5e_calibration_duration, 0,
1130     "Duration of initial calibration");
1131 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, fast, CTLFLAG_RWTUN,
1132     &mlx5e_fast_calibration, 0,
1133     "Recalibration interval during initial calibration");
1134 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, normal, CTLFLAG_RWTUN,
1135     &mlx5e_normal_calibration, 0,
1136     "Recalibration interval during normal operations");
1137
1138 /*
1139  * Ignites the calibration process.
1140  */
1141 static void
1142 mlx5e_reset_calibration_callout(struct mlx5e_priv *priv)
1143 {
1144
1145         if (priv->clbr_done == 0)
1146                 mlx5e_calibration_callout(priv);
1147         else
1148                 callout_reset_curcpu(&priv->tstmp_clbr, (priv->clbr_done <
1149                     mlx5e_calibration_duration ? mlx5e_fast_calibration :
1150                     mlx5e_normal_calibration) * hz, mlx5e_calibration_callout,
1151                     priv);
1152 }
1153
1154 static uint64_t
1155 mlx5e_timespec2usec(const struct timespec *ts)
1156 {
1157
1158         return ((uint64_t)ts->tv_sec * 1000000000 + ts->tv_nsec);
1159 }
1160
1161 static uint64_t
1162 mlx5e_hw_clock(struct mlx5e_priv *priv)
1163 {
1164         struct mlx5_init_seg *iseg;
1165         uint32_t hw_h, hw_h1, hw_l;
1166
1167         iseg = priv->mdev->iseg;
1168         do {
1169                 hw_h = ioread32be(&iseg->internal_timer_h);
1170                 hw_l = ioread32be(&iseg->internal_timer_l);
1171                 hw_h1 = ioread32be(&iseg->internal_timer_h);
1172         } while (hw_h1 != hw_h);
1173         return (((uint64_t)hw_h << 32) | hw_l);
1174 }
1175
1176 /*
1177  * The calibration callout, it runs either in the context of the
1178  * thread which enables calibration, or in callout.  It takes the
1179  * snapshot of system and adapter clocks, then advances the pointers to
1180  * the calibration point to allow rx path to read the consistent data
1181  * lockless.
1182  */
1183 static void
1184 mlx5e_calibration_callout(void *arg)
1185 {
1186         struct mlx5e_priv *priv;
1187         struct mlx5e_clbr_point *next, *curr;
1188         struct timespec ts;
1189         int clbr_curr_next;
1190
1191         priv = arg;
1192         curr = &priv->clbr_points[priv->clbr_curr];
1193         clbr_curr_next = priv->clbr_curr + 1;
1194         if (clbr_curr_next >= nitems(priv->clbr_points))
1195                 clbr_curr_next = 0;
1196         next = &priv->clbr_points[clbr_curr_next];
1197
1198         next->base_prev = curr->base_curr;
1199         next->clbr_hw_prev = curr->clbr_hw_curr;
1200
1201         next->clbr_hw_curr = mlx5e_hw_clock(priv);
1202         if (((next->clbr_hw_curr - curr->clbr_hw_curr) >> MLX5E_TSTMP_PREC) ==
1203             0) {
1204                 if (priv->clbr_done != 0) {
1205                         mlx5_en_err(priv->ifp,
1206                             "HW failed tstmp frozen %#jx %#jx, disabling\n",
1207                              next->clbr_hw_curr, curr->clbr_hw_prev);
1208                         priv->clbr_done = 0;
1209                 }
1210                 atomic_store_rel_int(&curr->clbr_gen, 0);
1211                 return;
1212         }
1213
1214         nanouptime(&ts);
1215         next->base_curr = mlx5e_timespec2usec(&ts);
1216
1217         curr->clbr_gen = 0;
1218         atomic_thread_fence_rel();
1219         priv->clbr_curr = clbr_curr_next;
1220         atomic_store_rel_int(&next->clbr_gen, ++(priv->clbr_gen));
1221
1222         if (priv->clbr_done < mlx5e_calibration_duration)
1223                 priv->clbr_done++;
1224         mlx5e_reset_calibration_callout(priv);
1225 }
1226
1227 static const char *mlx5e_rq_stats_desc[] = {
1228         MLX5E_RQ_STATS(MLX5E_STATS_DESC)
1229 };
1230
1231 static int
1232 mlx5e_create_rq(struct mlx5e_channel *c,
1233     struct mlx5e_rq_param *param,
1234     struct mlx5e_rq *rq)
1235 {
1236         struct mlx5e_priv *priv = c->priv;
1237         struct mlx5_core_dev *mdev = priv->mdev;
1238         char buffer[16];
1239         void *rqc = param->rqc;
1240         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1241         int wq_sz;
1242         int err;
1243         int i;
1244         u32 nsegs, wqe_sz;
1245
1246         err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
1247         if (err != 0)
1248                 goto done;
1249
1250         /* Create DMA descriptor TAG */
1251         if ((err = -bus_dma_tag_create(
1252             bus_get_dma_tag(mdev->pdev->dev.bsddev),
1253             1,                          /* any alignment */
1254             0,                          /* no boundary */
1255             BUS_SPACE_MAXADDR,          /* lowaddr */
1256             BUS_SPACE_MAXADDR,          /* highaddr */
1257             NULL, NULL,                 /* filter, filterarg */
1258             nsegs * MLX5E_MAX_RX_BYTES, /* maxsize */
1259             nsegs,                      /* nsegments */
1260             nsegs * MLX5E_MAX_RX_BYTES, /* maxsegsize */
1261             0,                          /* flags */
1262             NULL, NULL,                 /* lockfunc, lockfuncarg */
1263             &rq->dma_tag)))
1264                 goto done;
1265
1266         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1267             &rq->wq_ctrl);
1268         if (err)
1269                 goto err_free_dma_tag;
1270
1271         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
1272
1273         err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs);
1274         if (err != 0)
1275                 goto err_rq_wq_destroy;
1276
1277         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
1278
1279         err = -tcp_lro_init_args(&rq->lro, priv->ifp, TCP_LRO_ENTRIES, wq_sz);
1280         if (err)
1281                 goto err_rq_wq_destroy;
1282
1283         rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1284         for (i = 0; i != wq_sz; i++) {
1285                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
1286                 int j;
1287
1288                 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
1289                 if (err != 0) {
1290                         while (i--)
1291                                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
1292                         goto err_rq_mbuf_free;
1293                 }
1294
1295                 /* set value for constant fields */
1296                 for (j = 0; j < rq->nsegs; j++)
1297                         wqe->data[j].lkey = cpu_to_be32(priv->mr.key);
1298         }
1299
1300         INIT_WORK(&rq->dim.work, mlx5e_dim_work);
1301         if (priv->params.rx_cq_moderation_mode < 2) {
1302                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
1303         } else {
1304                 void *cqc = container_of(param,
1305                     struct mlx5e_channel_param, rq)->rx_cq.cqc;
1306
1307                 switch (MLX5_GET(cqc, cqc, cq_period_mode)) {
1308                 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
1309                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
1310                         break;
1311                 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
1312                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
1313                         break;
1314                 default:
1315                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
1316                         break;
1317                 }
1318         }
1319
1320         rq->ifp = priv->ifp;
1321         rq->channel = c;
1322         rq->ix = c->ix;
1323
1324         snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
1325         mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1326             buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
1327             rq->stats.arg);
1328         return (0);
1329
1330 err_rq_mbuf_free:
1331         free(rq->mbuf, M_MLX5EN);
1332         tcp_lro_free(&rq->lro);
1333 err_rq_wq_destroy:
1334         mlx5_wq_destroy(&rq->wq_ctrl);
1335 err_free_dma_tag:
1336         bus_dma_tag_destroy(rq->dma_tag);
1337 done:
1338         return (err);
1339 }
1340
1341 static void
1342 mlx5e_destroy_rq(struct mlx5e_rq *rq)
1343 {
1344         int wq_sz;
1345         int i;
1346
1347         /* destroy all sysctl nodes */
1348         sysctl_ctx_free(&rq->stats.ctx);
1349
1350         /* free leftover LRO packets, if any */
1351         tcp_lro_free(&rq->lro);
1352
1353         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
1354         for (i = 0; i != wq_sz; i++) {
1355                 if (rq->mbuf[i].mbuf != NULL) {
1356                         bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map);
1357                         m_freem(rq->mbuf[i].mbuf);
1358                 }
1359                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
1360         }
1361         free(rq->mbuf, M_MLX5EN);
1362         mlx5_wq_destroy(&rq->wq_ctrl);
1363         bus_dma_tag_destroy(rq->dma_tag);
1364 }
1365
1366 static int
1367 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
1368 {
1369         struct mlx5e_channel *c = rq->channel;
1370         struct mlx5e_priv *priv = c->priv;
1371         struct mlx5_core_dev *mdev = priv->mdev;
1372
1373         void *in;
1374         void *rqc;
1375         void *wq;
1376         int inlen;
1377         int err;
1378
1379         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
1380             sizeof(u64) * rq->wq_ctrl.buf.npages;
1381         in = mlx5_vzalloc(inlen);
1382         if (in == NULL)
1383                 return (-ENOMEM);
1384
1385         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1386         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1387
1388         memcpy(rqc, param->rqc, sizeof(param->rqc));
1389
1390         MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
1391         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1392         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1393         if (priv->counter_set_id >= 0)
1394                 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
1395         MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
1396             PAGE_SHIFT);
1397         MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
1398
1399         mlx5_fill_page_array(&rq->wq_ctrl.buf,
1400             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1401
1402         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
1403
1404         kvfree(in);
1405
1406         return (err);
1407 }
1408
1409 static int
1410 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
1411 {
1412         struct mlx5e_channel *c = rq->channel;
1413         struct mlx5e_priv *priv = c->priv;
1414         struct mlx5_core_dev *mdev = priv->mdev;
1415
1416         void *in;
1417         void *rqc;
1418         int inlen;
1419         int err;
1420
1421         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1422         in = mlx5_vzalloc(inlen);
1423         if (in == NULL)
1424                 return (-ENOMEM);
1425
1426         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1427
1428         MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
1429         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
1430         MLX5_SET(rqc, rqc, state, next_state);
1431
1432         err = mlx5_core_modify_rq(mdev, in, inlen);
1433
1434         kvfree(in);
1435
1436         return (err);
1437 }
1438
1439 static void
1440 mlx5e_disable_rq(struct mlx5e_rq *rq)
1441 {
1442         struct mlx5e_channel *c = rq->channel;
1443         struct mlx5e_priv *priv = c->priv;
1444         struct mlx5_core_dev *mdev = priv->mdev;
1445
1446         mlx5_core_destroy_rq(mdev, rq->rqn);
1447 }
1448
1449 static int
1450 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
1451 {
1452         struct mlx5e_channel *c = rq->channel;
1453         struct mlx5e_priv *priv = c->priv;
1454         struct mlx5_wq_ll *wq = &rq->wq;
1455         int i;
1456
1457         for (i = 0; i < 1000; i++) {
1458                 if (wq->cur_sz >= priv->params.min_rx_wqes)
1459                         return (0);
1460
1461                 msleep(4);
1462         }
1463         return (-ETIMEDOUT);
1464 }
1465
1466 static int
1467 mlx5e_open_rq(struct mlx5e_channel *c,
1468     struct mlx5e_rq_param *param,
1469     struct mlx5e_rq *rq)
1470 {
1471         int err;
1472
1473         err = mlx5e_create_rq(c, param, rq);
1474         if (err)
1475                 return (err);
1476
1477         err = mlx5e_enable_rq(rq, param);
1478         if (err)
1479                 goto err_destroy_rq;
1480
1481         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1482         if (err)
1483                 goto err_disable_rq;
1484
1485         c->rq.enabled = 1;
1486
1487         return (0);
1488
1489 err_disable_rq:
1490         mlx5e_disable_rq(rq);
1491 err_destroy_rq:
1492         mlx5e_destroy_rq(rq);
1493
1494         return (err);
1495 }
1496
1497 static void
1498 mlx5e_close_rq(struct mlx5e_rq *rq)
1499 {
1500         mtx_lock(&rq->mtx);
1501         rq->enabled = 0;
1502         callout_stop(&rq->watchdog);
1503         mtx_unlock(&rq->mtx);
1504
1505         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
1506 }
1507
1508 static void
1509 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
1510 {
1511
1512         mlx5e_disable_rq(rq);
1513         mlx5e_close_cq(&rq->cq);
1514         cancel_work_sync(&rq->dim.work);
1515         mlx5e_destroy_rq(rq);
1516 }
1517
1518 void
1519 mlx5e_free_sq_db(struct mlx5e_sq *sq)
1520 {
1521         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1522         int x;
1523
1524         for (x = 0; x != wq_sz; x++) {
1525                 if (unlikely(sq->mbuf[x].p_refcount != NULL)) {
1526                         atomic_add_int(sq->mbuf[x].p_refcount, -1);
1527                         sq->mbuf[x].p_refcount = NULL;
1528                 }
1529                 if (sq->mbuf[x].mbuf != NULL) {
1530                         bus_dmamap_unload(sq->dma_tag, sq->mbuf[x].dma_map);
1531                         m_freem(sq->mbuf[x].mbuf);
1532                 }
1533                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1534         }
1535         free(sq->mbuf, M_MLX5EN);
1536 }
1537
1538 int
1539 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
1540 {
1541         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1542         int err;
1543         int x;
1544
1545         sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1546
1547         /* Create DMA descriptor MAPs */
1548         for (x = 0; x != wq_sz; x++) {
1549                 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
1550                 if (err != 0) {
1551                         while (x--)
1552                                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1553                         free(sq->mbuf, M_MLX5EN);
1554                         return (err);
1555                 }
1556         }
1557         return (0);
1558 }
1559
1560 static const char *mlx5e_sq_stats_desc[] = {
1561         MLX5E_SQ_STATS(MLX5E_STATS_DESC)
1562 };
1563
1564 void
1565 mlx5e_update_sq_inline(struct mlx5e_sq *sq)
1566 {
1567         sq->max_inline = sq->priv->params.tx_max_inline;
1568         sq->min_inline_mode = sq->priv->params.tx_min_inline_mode;
1569
1570         /*
1571          * Check if trust state is DSCP or if inline mode is NONE which
1572          * indicates CX-5 or newer hardware.
1573          */
1574         if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP ||
1575             sq->min_inline_mode == MLX5_INLINE_MODE_NONE) {
1576                 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert))
1577                         sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN;
1578                 else
1579                         sq->min_insert_caps = MLX5E_INSERT_NON_VLAN;
1580         } else {
1581                 sq->min_insert_caps = 0;
1582         }
1583 }
1584
1585 static void
1586 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1587 {
1588         int i;
1589
1590         for (i = 0; i != priv->num_tc; i++) {
1591                 mtx_lock(&c->sq[i].lock);
1592                 mlx5e_update_sq_inline(&c->sq[i]);
1593                 mtx_unlock(&c->sq[i].lock);
1594         }
1595 }
1596
1597 void
1598 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv)
1599 {
1600         int i;
1601
1602         /* check if channels are closed */
1603         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
1604                 return;
1605
1606         for (i = 0; i < priv->params.num_channels; i++)
1607                 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]);
1608 }
1609
1610 static int
1611 mlx5e_create_sq(struct mlx5e_channel *c,
1612     int tc,
1613     struct mlx5e_sq_param *param,
1614     struct mlx5e_sq *sq)
1615 {
1616         struct mlx5e_priv *priv = c->priv;
1617         struct mlx5_core_dev *mdev = priv->mdev;
1618         char buffer[16];
1619         void *sqc = param->sqc;
1620         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1621         int err;
1622
1623         /* Create DMA descriptor TAG */
1624         if ((err = -bus_dma_tag_create(
1625             bus_get_dma_tag(mdev->pdev->dev.bsddev),
1626             1,                          /* any alignment */
1627             0,                          /* no boundary */
1628             BUS_SPACE_MAXADDR,          /* lowaddr */
1629             BUS_SPACE_MAXADDR,          /* highaddr */
1630             NULL, NULL,                 /* filter, filterarg */
1631             MLX5E_MAX_TX_PAYLOAD_SIZE,  /* maxsize */
1632             MLX5E_MAX_TX_MBUF_FRAGS,    /* nsegments */
1633             MLX5E_MAX_TX_MBUF_SIZE,     /* maxsegsize */
1634             0,                          /* flags */
1635             NULL, NULL,                 /* lockfunc, lockfuncarg */
1636             &sq->dma_tag)))
1637                 goto done;
1638
1639         err = mlx5_alloc_map_uar(mdev, &sq->uar);
1640         if (err)
1641                 goto err_free_dma_tag;
1642
1643         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
1644             &sq->wq_ctrl);
1645         if (err)
1646                 goto err_unmap_free_uar;
1647
1648         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1649         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1650
1651         err = mlx5e_alloc_sq_db(sq);
1652         if (err)
1653                 goto err_sq_wq_destroy;
1654
1655         sq->mkey_be = cpu_to_be32(priv->mr.key);
1656         sq->ifp = priv->ifp;
1657         sq->priv = priv;
1658         sq->tc = tc;
1659
1660         mlx5e_update_sq_inline(sq);
1661
1662         snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1663         mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1664             buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1665             sq->stats.arg);
1666
1667         return (0);
1668
1669 err_sq_wq_destroy:
1670         mlx5_wq_destroy(&sq->wq_ctrl);
1671
1672 err_unmap_free_uar:
1673         mlx5_unmap_free_uar(mdev, &sq->uar);
1674
1675 err_free_dma_tag:
1676         bus_dma_tag_destroy(sq->dma_tag);
1677 done:
1678         return (err);
1679 }
1680
1681 static void
1682 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1683 {
1684         /* destroy all sysctl nodes */
1685         sysctl_ctx_free(&sq->stats.ctx);
1686
1687         mlx5e_free_sq_db(sq);
1688         mlx5_wq_destroy(&sq->wq_ctrl);
1689         mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1690         bus_dma_tag_destroy(sq->dma_tag);
1691 }
1692
1693 int
1694 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1695     int tis_num)
1696 {
1697         void *in;
1698         void *sqc;
1699         void *wq;
1700         int inlen;
1701         int err;
1702
1703         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1704             sizeof(u64) * sq->wq_ctrl.buf.npages;
1705         in = mlx5_vzalloc(inlen);
1706         if (in == NULL)
1707                 return (-ENOMEM);
1708
1709         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1710         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1711
1712         memcpy(sqc, param->sqc, sizeof(param->sqc));
1713
1714         MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1715         MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1716         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1717         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1718         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1719
1720         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1721         MLX5_SET(wq, wq, uar_page, sq->uar.index);
1722         MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1723             PAGE_SHIFT);
1724         MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1725
1726         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1727             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1728
1729         err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1730
1731         kvfree(in);
1732
1733         return (err);
1734 }
1735
1736 int
1737 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1738 {
1739         void *in;
1740         void *sqc;
1741         int inlen;
1742         int err;
1743
1744         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1745         in = mlx5_vzalloc(inlen);
1746         if (in == NULL)
1747                 return (-ENOMEM);
1748
1749         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1750
1751         MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1752         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1753         MLX5_SET(sqc, sqc, state, next_state);
1754
1755         err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1756
1757         kvfree(in);
1758
1759         return (err);
1760 }
1761
1762 void
1763 mlx5e_disable_sq(struct mlx5e_sq *sq)
1764 {
1765
1766         mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1767 }
1768
1769 static int
1770 mlx5e_open_sq(struct mlx5e_channel *c,
1771     int tc,
1772     struct mlx5e_sq_param *param,
1773     struct mlx5e_sq *sq)
1774 {
1775         int err;
1776
1777         sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1778
1779         /* ensure the TX completion event factor is not zero */
1780         if (sq->cev_factor == 0)
1781                 sq->cev_factor = 1;
1782
1783         err = mlx5e_create_sq(c, tc, param, sq);
1784         if (err)
1785                 return (err);
1786
1787         err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1788         if (err)
1789                 goto err_destroy_sq;
1790
1791         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1792         if (err)
1793                 goto err_disable_sq;
1794
1795         WRITE_ONCE(sq->running, 1);
1796
1797         return (0);
1798
1799 err_disable_sq:
1800         mlx5e_disable_sq(sq);
1801 err_destroy_sq:
1802         mlx5e_destroy_sq(sq);
1803
1804         return (err);
1805 }
1806
1807 static void
1808 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1809 {
1810         /* fill up remainder with NOPs */
1811         while (sq->cev_counter != 0) {
1812                 while (!mlx5e_sq_has_room_for(sq, 1)) {
1813                         if (can_sleep != 0) {
1814                                 mtx_unlock(&sq->lock);
1815                                 msleep(4);
1816                                 mtx_lock(&sq->lock);
1817                         } else {
1818                                 goto done;
1819                         }
1820                 }
1821                 /* send a single NOP */
1822                 mlx5e_send_nop(sq, 1);
1823                 atomic_thread_fence_rel();
1824         }
1825 done:
1826         /* Check if we need to write the doorbell */
1827         if (likely(sq->doorbell.d64 != 0)) {
1828                 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1829                 sq->doorbell.d64 = 0;
1830         }
1831 }
1832
1833 void
1834 mlx5e_sq_cev_timeout(void *arg)
1835 {
1836         struct mlx5e_sq *sq = arg;
1837
1838         mtx_assert(&sq->lock, MA_OWNED);
1839
1840         /* check next state */
1841         switch (sq->cev_next_state) {
1842         case MLX5E_CEV_STATE_SEND_NOPS:
1843                 /* fill TX ring with NOPs, if any */
1844                 mlx5e_sq_send_nops_locked(sq, 0);
1845
1846                 /* check if completed */
1847                 if (sq->cev_counter == 0) {
1848                         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1849                         return;
1850                 }
1851                 break;
1852         default:
1853                 /* send NOPs on next timeout */
1854                 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1855                 break;
1856         }
1857
1858         /* restart timer */
1859         callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1860 }
1861
1862 void
1863 mlx5e_drain_sq(struct mlx5e_sq *sq)
1864 {
1865         int error;
1866         struct mlx5_core_dev *mdev= sq->priv->mdev;
1867
1868         /*
1869          * Check if already stopped.
1870          *
1871          * NOTE: Serialization of this function is managed by the
1872          * caller ensuring the priv's state lock is locked or in case
1873          * of rate limit support, a single thread manages drain and
1874          * resume of SQs. The "running" variable can therefore safely
1875          * be read without any locks.
1876          */
1877         if (READ_ONCE(sq->running) == 0)
1878                 return;
1879
1880         /* don't put more packets into the SQ */
1881         WRITE_ONCE(sq->running, 0);
1882
1883         /* serialize access to DMA rings */
1884         mtx_lock(&sq->lock);
1885
1886         /* teardown event factor timer, if any */
1887         sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1888         callout_stop(&sq->cev_callout);
1889
1890         /* send dummy NOPs in order to flush the transmit ring */
1891         mlx5e_sq_send_nops_locked(sq, 1);
1892         mtx_unlock(&sq->lock);
1893
1894         /* wait till SQ is empty or link is down */
1895         mtx_lock(&sq->lock);
1896         while (sq->cc != sq->pc &&
1897             (sq->priv->media_status_last & IFM_ACTIVE) != 0 &&
1898             mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1899                 mtx_unlock(&sq->lock);
1900                 msleep(1);
1901                 sq->cq.mcq.comp(&sq->cq.mcq);
1902                 mtx_lock(&sq->lock);
1903         }
1904         mtx_unlock(&sq->lock);
1905
1906         /* error out remaining requests */
1907         error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1908         if (error != 0) {
1909                 mlx5_en_err(sq->ifp,
1910                     "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error);
1911         }
1912
1913         /* wait till SQ is empty */
1914         mtx_lock(&sq->lock);
1915         while (sq->cc != sq->pc &&
1916                mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1917                 mtx_unlock(&sq->lock);
1918                 msleep(1);
1919                 sq->cq.mcq.comp(&sq->cq.mcq);
1920                 mtx_lock(&sq->lock);
1921         }
1922         mtx_unlock(&sq->lock);
1923 }
1924
1925 static void
1926 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1927 {
1928
1929         mlx5e_drain_sq(sq);
1930         mlx5e_disable_sq(sq);
1931         mlx5e_destroy_sq(sq);
1932 }
1933
1934 static int
1935 mlx5e_create_cq(struct mlx5e_priv *priv,
1936     struct mlx5e_cq_param *param,
1937     struct mlx5e_cq *cq,
1938     mlx5e_cq_comp_t *comp,
1939     int eq_ix)
1940 {
1941         struct mlx5_core_dev *mdev = priv->mdev;
1942         struct mlx5_core_cq *mcq = &cq->mcq;
1943         int eqn_not_used;
1944         int irqn;
1945         int err;
1946         u32 i;
1947
1948         param->wq.buf_numa_node = 0;
1949         param->wq.db_numa_node = 0;
1950
1951         err = mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1952         if (err)
1953                 return (err);
1954
1955         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1956             &cq->wq_ctrl);
1957         if (err)
1958                 return (err);
1959
1960         mcq->cqe_sz = 64;
1961         mcq->set_ci_db = cq->wq_ctrl.db.db;
1962         mcq->arm_db = cq->wq_ctrl.db.db + 1;
1963         *mcq->set_ci_db = 0;
1964         *mcq->arm_db = 0;
1965         mcq->vector = eq_ix;
1966         mcq->comp = comp;
1967         mcq->event = mlx5e_cq_error_event;
1968         mcq->irqn = irqn;
1969         mcq->uar = &priv->cq_uar;
1970
1971         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1972                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1973
1974                 cqe->op_own = 0xf1;
1975         }
1976
1977         cq->priv = priv;
1978
1979         return (0);
1980 }
1981
1982 static void
1983 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1984 {
1985         mlx5_wq_destroy(&cq->wq_ctrl);
1986 }
1987
1988 static int
1989 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1990 {
1991         struct mlx5_core_cq *mcq = &cq->mcq;
1992         void *in;
1993         void *cqc;
1994         int inlen;
1995         int irqn_not_used;
1996         int eqn;
1997         int err;
1998
1999         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
2000             sizeof(u64) * cq->wq_ctrl.buf.npages;
2001         in = mlx5_vzalloc(inlen);
2002         if (in == NULL)
2003                 return (-ENOMEM);
2004
2005         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
2006
2007         memcpy(cqc, param->cqc, sizeof(param->cqc));
2008
2009         mlx5_fill_page_array(&cq->wq_ctrl.buf,
2010             (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
2011
2012         mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
2013
2014         MLX5_SET(cqc, cqc, c_eqn, eqn);
2015         MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
2016         MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
2017             PAGE_SHIFT);
2018         MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
2019
2020         err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
2021
2022         kvfree(in);
2023
2024         if (err)
2025                 return (err);
2026
2027         mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock));
2028
2029         return (0);
2030 }
2031
2032 static void
2033 mlx5e_disable_cq(struct mlx5e_cq *cq)
2034 {
2035
2036         mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
2037 }
2038
2039 int
2040 mlx5e_open_cq(struct mlx5e_priv *priv,
2041     struct mlx5e_cq_param *param,
2042     struct mlx5e_cq *cq,
2043     mlx5e_cq_comp_t *comp,
2044     int eq_ix)
2045 {
2046         int err;
2047
2048         err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
2049         if (err)
2050                 return (err);
2051
2052         err = mlx5e_enable_cq(cq, param, eq_ix);
2053         if (err)
2054                 goto err_destroy_cq;
2055
2056         return (0);
2057
2058 err_destroy_cq:
2059         mlx5e_destroy_cq(cq);
2060
2061         return (err);
2062 }
2063
2064 void
2065 mlx5e_close_cq(struct mlx5e_cq *cq)
2066 {
2067         mlx5e_disable_cq(cq);
2068         mlx5e_destroy_cq(cq);
2069 }
2070
2071 static int
2072 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
2073     struct mlx5e_channel_param *cparam)
2074 {
2075         int err;
2076         int tc;
2077
2078         for (tc = 0; tc < c->priv->num_tc; tc++) {
2079                 /* open completion queue */
2080                 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
2081                     &mlx5e_tx_cq_comp, c->ix);
2082                 if (err)
2083                         goto err_close_tx_cqs;
2084         }
2085         return (0);
2086
2087 err_close_tx_cqs:
2088         for (tc--; tc >= 0; tc--)
2089                 mlx5e_close_cq(&c->sq[tc].cq);
2090
2091         return (err);
2092 }
2093
2094 static void
2095 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
2096 {
2097         int tc;
2098
2099         for (tc = 0; tc < c->priv->num_tc; tc++)
2100                 mlx5e_close_cq(&c->sq[tc].cq);
2101 }
2102
2103 static int
2104 mlx5e_open_sqs(struct mlx5e_channel *c,
2105     struct mlx5e_channel_param *cparam)
2106 {
2107         int err;
2108         int tc;
2109
2110         for (tc = 0; tc < c->priv->num_tc; tc++) {
2111                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
2112                 if (err)
2113                         goto err_close_sqs;
2114         }
2115
2116         return (0);
2117
2118 err_close_sqs:
2119         for (tc--; tc >= 0; tc--)
2120                 mlx5e_close_sq_wait(&c->sq[tc]);
2121
2122         return (err);
2123 }
2124
2125 static void
2126 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
2127 {
2128         int tc;
2129
2130         for (tc = 0; tc < c->priv->num_tc; tc++)
2131                 mlx5e_close_sq_wait(&c->sq[tc]);
2132 }
2133
2134 static void
2135 mlx5e_chan_static_init(struct mlx5e_priv *priv, struct mlx5e_channel *c, int ix)
2136 {
2137         int tc;
2138
2139         /* setup priv and channel number */
2140         c->priv = priv;
2141         c->ix = ix;
2142
2143         /* setup send tag */
2144         m_snd_tag_init(&c->tag, c->priv->ifp, IF_SND_TAG_TYPE_UNLIMITED);
2145
2146         init_completion(&c->completion);
2147
2148         mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
2149
2150         callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
2151
2152         for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) {
2153                 struct mlx5e_sq *sq = c->sq + tc;
2154
2155                 mtx_init(&sq->lock, "mlx5tx",
2156                     MTX_NETWORK_LOCK " TX", MTX_DEF);
2157                 mtx_init(&sq->comp_lock, "mlx5comp",
2158                     MTX_NETWORK_LOCK " TX", MTX_DEF);
2159
2160                 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
2161         }
2162 }
2163
2164 static void
2165 mlx5e_chan_wait_for_completion(struct mlx5e_channel *c)
2166 {
2167
2168         m_snd_tag_rele(&c->tag);
2169         wait_for_completion(&c->completion);
2170 }
2171
2172 static void
2173 mlx5e_priv_wait_for_completion(struct mlx5e_priv *priv, const uint32_t channels)
2174 {
2175         uint32_t x;
2176
2177         for (x = 0; x != channels; x++)
2178                 mlx5e_chan_wait_for_completion(&priv->channel[x]);
2179 }
2180
2181 static void
2182 mlx5e_chan_static_destroy(struct mlx5e_channel *c)
2183 {
2184         int tc;
2185
2186         callout_drain(&c->rq.watchdog);
2187
2188         mtx_destroy(&c->rq.mtx);
2189
2190         for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) {
2191                 callout_drain(&c->sq[tc].cev_callout);
2192                 mtx_destroy(&c->sq[tc].lock);
2193                 mtx_destroy(&c->sq[tc].comp_lock);
2194         }
2195 }
2196
2197 static int
2198 mlx5e_open_channel(struct mlx5e_priv *priv,
2199     struct mlx5e_channel_param *cparam,
2200     struct mlx5e_channel *c)
2201 {
2202         struct epoch_tracker et;
2203         int i, err;
2204
2205         /* zero non-persistant data */
2206         MLX5E_ZERO(&c->rq, mlx5e_rq_zero_start);
2207         for (i = 0; i != priv->num_tc; i++)
2208                 MLX5E_ZERO(&c->sq[i], mlx5e_sq_zero_start);
2209
2210         /* open transmit completion queue */
2211         err = mlx5e_open_tx_cqs(c, cparam);
2212         if (err)
2213                 goto err_free;
2214
2215         /* open receive completion queue */
2216         err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
2217             &mlx5e_rx_cq_comp, c->ix);
2218         if (err)
2219                 goto err_close_tx_cqs;
2220
2221         err = mlx5e_open_sqs(c, cparam);
2222         if (err)
2223                 goto err_close_rx_cq;
2224
2225         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
2226         if (err)
2227                 goto err_close_sqs;
2228
2229         /* poll receive queue initially */
2230         NET_EPOCH_ENTER(et);
2231         c->rq.cq.mcq.comp(&c->rq.cq.mcq);
2232         NET_EPOCH_EXIT(et);
2233
2234         return (0);
2235
2236 err_close_sqs:
2237         mlx5e_close_sqs_wait(c);
2238
2239 err_close_rx_cq:
2240         mlx5e_close_cq(&c->rq.cq);
2241
2242 err_close_tx_cqs:
2243         mlx5e_close_tx_cqs(c);
2244
2245 err_free:
2246         return (err);
2247 }
2248
2249 static void
2250 mlx5e_close_channel(struct mlx5e_channel *c)
2251 {
2252         mlx5e_close_rq(&c->rq);
2253 }
2254
2255 static void
2256 mlx5e_close_channel_wait(struct mlx5e_channel *c)
2257 {
2258         mlx5e_close_rq_wait(&c->rq);
2259         mlx5e_close_sqs_wait(c);
2260         mlx5e_close_tx_cqs(c);
2261 }
2262
2263 static int
2264 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs)
2265 {
2266         u32 r, n;
2267
2268         r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz :
2269             MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
2270         if (r > MJUM16BYTES)
2271                 return (-ENOMEM);
2272
2273         if (r > MJUM9BYTES)
2274                 r = MJUM16BYTES;
2275         else if (r > MJUMPAGESIZE)
2276                 r = MJUM9BYTES;
2277         else if (r > MCLBYTES)
2278                 r = MJUMPAGESIZE;
2279         else
2280                 r = MCLBYTES;
2281
2282         /*
2283          * n + 1 must be a power of two, because stride size must be.
2284          * Stride size is 16 * (n + 1), as the first segment is
2285          * control.
2286          */
2287         for (n = howmany(r, MLX5E_MAX_RX_BYTES); !powerof2(n + 1); n++)
2288                 ;
2289
2290         if (n > MLX5E_MAX_BUSDMA_RX_SEGS)
2291                 return (-ENOMEM);
2292
2293         *wqe_sz = r;
2294         *nsegs = n;
2295         return (0);
2296 }
2297
2298 static void
2299 mlx5e_build_rq_param(struct mlx5e_priv *priv,
2300     struct mlx5e_rq_param *param)
2301 {
2302         void *rqc = param->rqc;
2303         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2304         u32 wqe_sz, nsegs;
2305
2306         mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
2307         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
2308         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2309         MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) +
2310             nsegs * sizeof(struct mlx5_wqe_data_seg)));
2311         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
2312         MLX5_SET(wq, wq, pd, priv->pdn);
2313
2314         param->wq.buf_numa_node = 0;
2315         param->wq.db_numa_node = 0;
2316         param->wq.linear = 1;
2317 }
2318
2319 static void
2320 mlx5e_build_sq_param(struct mlx5e_priv *priv,
2321     struct mlx5e_sq_param *param)
2322 {
2323         void *sqc = param->sqc;
2324         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2325
2326         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
2327         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2328         MLX5_SET(wq, wq, pd, priv->pdn);
2329
2330         param->wq.buf_numa_node = 0;
2331         param->wq.db_numa_node = 0;
2332         param->wq.linear = 1;
2333 }
2334
2335 static void
2336 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2337     struct mlx5e_cq_param *param)
2338 {
2339         void *cqc = param->cqc;
2340
2341         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
2342 }
2343
2344 static void
2345 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr)
2346 {
2347
2348         *ptr = net_dim_get_profile(mode, MLX5E_DIM_DEFAULT_PROFILE);
2349
2350         /* apply LRO restrictions */
2351         if (priv->params.hw_lro_en &&
2352             ptr->pkts > MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO) {
2353                 ptr->pkts = MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO;
2354         }
2355 }
2356
2357 static void
2358 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2359     struct mlx5e_cq_param *param)
2360 {
2361         struct net_dim_cq_moder curr;
2362         void *cqc = param->cqc;
2363
2364         /*
2365          * We use MLX5_CQE_FORMAT_HASH because the RX hash mini CQE
2366          * format is more beneficial for FreeBSD use case.
2367          *
2368          * Adding support for MLX5_CQE_FORMAT_CSUM will require changes
2369          * in mlx5e_decompress_cqe.
2370          */
2371         if (priv->params.cqe_zipping_en) {
2372                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_HASH);
2373                 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
2374         }
2375
2376         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
2377
2378         switch (priv->params.rx_cq_moderation_mode) {
2379         case 0:
2380                 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
2381                 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
2382                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2383                 break;
2384         case 1:
2385                 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
2386                 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
2387                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2388                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2389                 else
2390                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2391                 break;
2392         case 2:
2393                 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr);
2394                 MLX5_SET(cqc, cqc, cq_period, curr.usec);
2395                 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
2396                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2397                 break;
2398         case 3:
2399                 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr);
2400                 MLX5_SET(cqc, cqc, cq_period, curr.usec);
2401                 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
2402                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2403                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2404                 else
2405                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2406                 break;
2407         default:
2408                 break;
2409         }
2410
2411         mlx5e_dim_build_cq_param(priv, param);
2412
2413         mlx5e_build_common_cq_param(priv, param);
2414 }
2415
2416 static void
2417 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2418     struct mlx5e_cq_param *param)
2419 {
2420         void *cqc = param->cqc;
2421
2422         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
2423         MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
2424         MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
2425
2426         switch (priv->params.tx_cq_moderation_mode) {
2427         case 0:
2428                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2429                 break;
2430         default:
2431                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2432                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2433                 else
2434                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2435                 break;
2436         }
2437
2438         mlx5e_build_common_cq_param(priv, param);
2439 }
2440
2441 static void
2442 mlx5e_build_channel_param(struct mlx5e_priv *priv,
2443     struct mlx5e_channel_param *cparam)
2444 {
2445         memset(cparam, 0, sizeof(*cparam));
2446
2447         mlx5e_build_rq_param(priv, &cparam->rq);
2448         mlx5e_build_sq_param(priv, &cparam->sq);
2449         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
2450         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
2451 }
2452
2453 static int
2454 mlx5e_open_channels(struct mlx5e_priv *priv)
2455 {
2456         struct mlx5e_channel_param *cparam;
2457         int err;
2458         int i;
2459         int j;
2460
2461         cparam = malloc(sizeof(*cparam), M_MLX5EN, M_WAITOK);
2462
2463         mlx5e_build_channel_param(priv, cparam);
2464         for (i = 0; i < priv->params.num_channels; i++) {
2465                 err = mlx5e_open_channel(priv, cparam, &priv->channel[i]);
2466                 if (err)
2467                         goto err_close_channels;
2468         }
2469
2470         for (j = 0; j < priv->params.num_channels; j++) {
2471                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j].rq);
2472                 if (err)
2473                         goto err_close_channels;
2474         }
2475         free(cparam, M_MLX5EN);
2476         return (0);
2477
2478 err_close_channels:
2479         while (i--) {
2480                 mlx5e_close_channel(&priv->channel[i]);
2481                 mlx5e_close_channel_wait(&priv->channel[i]);
2482         }
2483         free(cparam, M_MLX5EN);
2484         return (err);
2485 }
2486
2487 static void
2488 mlx5e_close_channels(struct mlx5e_priv *priv)
2489 {
2490         int i;
2491
2492         for (i = 0; i < priv->params.num_channels; i++)
2493                 mlx5e_close_channel(&priv->channel[i]);
2494         for (i = 0; i < priv->params.num_channels; i++)
2495                 mlx5e_close_channel_wait(&priv->channel[i]);
2496 }
2497
2498 static int
2499 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
2500 {
2501
2502         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2503                 uint8_t cq_mode;
2504
2505                 switch (priv->params.tx_cq_moderation_mode) {
2506                 case 0:
2507                 case 2:
2508                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2509                         break;
2510                 default:
2511                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2512                         break;
2513                 }
2514
2515                 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq,
2516                     priv->params.tx_cq_moderation_usec,
2517                     priv->params.tx_cq_moderation_pkts,
2518                     cq_mode));
2519         }
2520
2521         return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
2522             priv->params.tx_cq_moderation_usec,
2523             priv->params.tx_cq_moderation_pkts));
2524 }
2525
2526 static int
2527 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
2528 {
2529
2530         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2531                 uint8_t cq_mode;
2532                 uint8_t dim_mode;
2533                 int retval;
2534
2535                 switch (priv->params.rx_cq_moderation_mode) {
2536                 case 0:
2537                 case 2:
2538                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2539                         dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2540                         break;
2541                 default:
2542                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2543                         dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
2544                         break;
2545                 }
2546
2547                 /* tear down dynamic interrupt moderation */
2548                 mtx_lock(&rq->mtx);
2549                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
2550                 mtx_unlock(&rq->mtx);
2551
2552                 /* wait for dynamic interrupt moderation work task, if any */
2553                 cancel_work_sync(&rq->dim.work);
2554
2555                 if (priv->params.rx_cq_moderation_mode >= 2) {
2556                         struct net_dim_cq_moder curr;
2557
2558                         mlx5e_get_default_profile(priv, dim_mode, &curr);
2559
2560                         retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2561                             curr.usec, curr.pkts, cq_mode);
2562
2563                         /* set dynamic interrupt moderation mode and zero defaults */
2564                         mtx_lock(&rq->mtx);
2565                         rq->dim.mode = dim_mode;
2566                         rq->dim.state = 0;
2567                         rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE;
2568                         mtx_unlock(&rq->mtx);
2569                 } else {
2570                         retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2571                             priv->params.rx_cq_moderation_usec,
2572                             priv->params.rx_cq_moderation_pkts,
2573                             cq_mode);
2574                 }
2575                 return (retval);
2576         }
2577
2578         return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
2579             priv->params.rx_cq_moderation_usec,
2580             priv->params.rx_cq_moderation_pkts));
2581 }
2582
2583 static int
2584 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
2585 {
2586         int err;
2587         int i;
2588
2589         err = mlx5e_refresh_rq_params(priv, &c->rq);
2590         if (err)
2591                 goto done;
2592
2593         for (i = 0; i != priv->num_tc; i++) {
2594                 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
2595                 if (err)
2596                         goto done;
2597         }
2598 done:
2599         return (err);
2600 }
2601
2602 int
2603 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
2604 {
2605         int i;
2606
2607         /* check if channels are closed */
2608         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2609                 return (EINVAL);
2610
2611         for (i = 0; i < priv->params.num_channels; i++) {
2612                 int err;
2613
2614                 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]);
2615                 if (err)
2616                         return (err);
2617         }
2618         return (0);
2619 }
2620
2621 static int
2622 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
2623 {
2624         struct mlx5_core_dev *mdev = priv->mdev;
2625         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
2626         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2627
2628         memset(in, 0, sizeof(in));
2629
2630         MLX5_SET(tisc, tisc, prio, tc);
2631         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
2632
2633         return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
2634 }
2635
2636 static void
2637 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
2638 {
2639         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2640 }
2641
2642 static int
2643 mlx5e_open_tises(struct mlx5e_priv *priv)
2644 {
2645         int num_tc = priv->num_tc;
2646         int err;
2647         int tc;
2648
2649         for (tc = 0; tc < num_tc; tc++) {
2650                 err = mlx5e_open_tis(priv, tc);
2651                 if (err)
2652                         goto err_close_tises;
2653         }
2654
2655         return (0);
2656
2657 err_close_tises:
2658         for (tc--; tc >= 0; tc--)
2659                 mlx5e_close_tis(priv, tc);
2660
2661         return (err);
2662 }
2663
2664 static void
2665 mlx5e_close_tises(struct mlx5e_priv *priv)
2666 {
2667         int num_tc = priv->num_tc;
2668         int tc;
2669
2670         for (tc = 0; tc < num_tc; tc++)
2671                 mlx5e_close_tis(priv, tc);
2672 }
2673
2674 static int
2675 mlx5e_open_rqt(struct mlx5e_priv *priv)
2676 {
2677         struct mlx5_core_dev *mdev = priv->mdev;
2678         u32 *in;
2679         u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
2680         void *rqtc;
2681         int inlen;
2682         int err;
2683         int sz;
2684         int i;
2685
2686         sz = 1 << priv->params.rx_hash_log_tbl_sz;
2687
2688         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2689         in = mlx5_vzalloc(inlen);
2690         if (in == NULL)
2691                 return (-ENOMEM);
2692         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2693
2694         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2695         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2696
2697         for (i = 0; i < sz; i++) {
2698                 int ix = i;
2699 #ifdef RSS
2700                 ix = rss_get_indirection_to_bucket(ix);
2701 #endif
2702                 /* ensure we don't overflow */
2703                 ix %= priv->params.num_channels;
2704
2705                 /* apply receive side scaling stride, if any */
2706                 ix -= ix % (int)priv->params.channels_rsss;
2707
2708                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn);
2709         }
2710
2711         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
2712
2713         err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
2714         if (!err)
2715                 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
2716
2717         kvfree(in);
2718
2719         return (err);
2720 }
2721
2722 static void
2723 mlx5e_close_rqt(struct mlx5e_priv *priv)
2724 {
2725         u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0};
2726         u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0};
2727
2728         MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
2729         MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
2730
2731         mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out));
2732 }
2733
2734 static void
2735 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
2736 {
2737         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2738         __be32 *hkey;
2739
2740         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2741
2742 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2743
2744 #define MLX5_HASH_IP     (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2745                           MLX5_HASH_FIELD_SEL_DST_IP)
2746
2747 #define MLX5_HASH_ALL    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2748                           MLX5_HASH_FIELD_SEL_DST_IP   |\
2749                           MLX5_HASH_FIELD_SEL_L4_SPORT |\
2750                           MLX5_HASH_FIELD_SEL_L4_DPORT)
2751
2752 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2753                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2754                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2755
2756         if (priv->params.hw_lro_en) {
2757                 MLX5_SET(tirc, tirc, lro_enable_mask,
2758                     MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2759                     MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2760                 MLX5_SET(tirc, tirc, lro_max_msg_sz,
2761                     (priv->params.lro_wqe_sz -
2762                     ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2763                 /* TODO: add the option to choose timer value dynamically */
2764                 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
2765                     MLX5_CAP_ETH(priv->mdev,
2766                     lro_timer_supported_periods[2]));
2767         }
2768
2769         /* setup parameters for hashing TIR type, if any */
2770         switch (tt) {
2771         case MLX5E_TT_ANY:
2772                 MLX5_SET(tirc, tirc, disp_type,
2773                     MLX5_TIRC_DISP_TYPE_DIRECT);
2774                 MLX5_SET(tirc, tirc, inline_rqn,
2775                     priv->channel[0].rq.rqn);
2776                 break;
2777         default:
2778                 MLX5_SET(tirc, tirc, disp_type,
2779                     MLX5_TIRC_DISP_TYPE_INDIRECT);
2780                 MLX5_SET(tirc, tirc, indirect_table,
2781                     priv->rqtn);
2782                 MLX5_SET(tirc, tirc, rx_hash_fn,
2783                     MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
2784                 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
2785 #ifdef RSS
2786                 /*
2787                  * The FreeBSD RSS implementation does currently not
2788                  * support symmetric Toeplitz hashes:
2789                  */
2790                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
2791                 rss_getkey((uint8_t *)hkey);
2792 #else
2793                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2794                 hkey[0] = cpu_to_be32(0xD181C62C);
2795                 hkey[1] = cpu_to_be32(0xF7F4DB5B);
2796                 hkey[2] = cpu_to_be32(0x1983A2FC);
2797                 hkey[3] = cpu_to_be32(0x943E1ADB);
2798                 hkey[4] = cpu_to_be32(0xD9389E6B);
2799                 hkey[5] = cpu_to_be32(0xD1039C2C);
2800                 hkey[6] = cpu_to_be32(0xA74499AD);
2801                 hkey[7] = cpu_to_be32(0x593D56D9);
2802                 hkey[8] = cpu_to_be32(0xF3253C06);
2803                 hkey[9] = cpu_to_be32(0x2ADC1FFC);
2804 #endif
2805                 break;
2806         }
2807
2808         switch (tt) {
2809         case MLX5E_TT_IPV4_TCP:
2810                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2811                     MLX5_L3_PROT_TYPE_IPV4);
2812                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2813                     MLX5_L4_PROT_TYPE_TCP);
2814 #ifdef RSS
2815                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2816                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2817                             MLX5_HASH_IP);
2818                 } else
2819 #endif
2820                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2821                     MLX5_HASH_ALL);
2822                 break;
2823
2824         case MLX5E_TT_IPV6_TCP:
2825                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2826                     MLX5_L3_PROT_TYPE_IPV6);
2827                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2828                     MLX5_L4_PROT_TYPE_TCP);
2829 #ifdef RSS
2830                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2831                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2832                             MLX5_HASH_IP);
2833                 } else
2834 #endif
2835                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2836                     MLX5_HASH_ALL);
2837                 break;
2838
2839         case MLX5E_TT_IPV4_UDP:
2840                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2841                     MLX5_L3_PROT_TYPE_IPV4);
2842                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2843                     MLX5_L4_PROT_TYPE_UDP);
2844 #ifdef RSS
2845                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2846                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2847                             MLX5_HASH_IP);
2848                 } else
2849 #endif
2850                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2851                     MLX5_HASH_ALL);
2852                 break;
2853
2854         case MLX5E_TT_IPV6_UDP:
2855                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2856                     MLX5_L3_PROT_TYPE_IPV6);
2857                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2858                     MLX5_L4_PROT_TYPE_UDP);
2859 #ifdef RSS
2860                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2861                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2862                             MLX5_HASH_IP);
2863                 } else
2864 #endif
2865                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2866                     MLX5_HASH_ALL);
2867                 break;
2868
2869         case MLX5E_TT_IPV4_IPSEC_AH:
2870                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2871                     MLX5_L3_PROT_TYPE_IPV4);
2872                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2873                     MLX5_HASH_IP_IPSEC_SPI);
2874                 break;
2875
2876         case MLX5E_TT_IPV6_IPSEC_AH:
2877                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2878                     MLX5_L3_PROT_TYPE_IPV6);
2879                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2880                     MLX5_HASH_IP_IPSEC_SPI);
2881                 break;
2882
2883         case MLX5E_TT_IPV4_IPSEC_ESP:
2884                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2885                     MLX5_L3_PROT_TYPE_IPV4);
2886                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2887                     MLX5_HASH_IP_IPSEC_SPI);
2888                 break;
2889
2890         case MLX5E_TT_IPV6_IPSEC_ESP:
2891                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2892                     MLX5_L3_PROT_TYPE_IPV6);
2893                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2894                     MLX5_HASH_IP_IPSEC_SPI);
2895                 break;
2896
2897         case MLX5E_TT_IPV4:
2898                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2899                     MLX5_L3_PROT_TYPE_IPV4);
2900                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2901                     MLX5_HASH_IP);
2902                 break;
2903
2904         case MLX5E_TT_IPV6:
2905                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2906                     MLX5_L3_PROT_TYPE_IPV6);
2907                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2908                     MLX5_HASH_IP);
2909                 break;
2910
2911         default:
2912                 break;
2913         }
2914 }
2915
2916 static int
2917 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2918 {
2919         struct mlx5_core_dev *mdev = priv->mdev;
2920         u32 *in;
2921         void *tirc;
2922         int inlen;
2923         int err;
2924
2925         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2926         in = mlx5_vzalloc(inlen);
2927         if (in == NULL)
2928                 return (-ENOMEM);
2929         tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2930
2931         mlx5e_build_tir_ctx(priv, tirc, tt);
2932
2933         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2934
2935         kvfree(in);
2936
2937         return (err);
2938 }
2939
2940 static void
2941 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2942 {
2943         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2944 }
2945
2946 static int
2947 mlx5e_open_tirs(struct mlx5e_priv *priv)
2948 {
2949         int err;
2950         int i;
2951
2952         for (i = 0; i < MLX5E_NUM_TT; i++) {
2953                 err = mlx5e_open_tir(priv, i);
2954                 if (err)
2955                         goto err_close_tirs;
2956         }
2957
2958         return (0);
2959
2960 err_close_tirs:
2961         for (i--; i >= 0; i--)
2962                 mlx5e_close_tir(priv, i);
2963
2964         return (err);
2965 }
2966
2967 static void
2968 mlx5e_close_tirs(struct mlx5e_priv *priv)
2969 {
2970         int i;
2971
2972         for (i = 0; i < MLX5E_NUM_TT; i++)
2973                 mlx5e_close_tir(priv, i);
2974 }
2975
2976 /*
2977  * SW MTU does not include headers,
2978  * HW MTU includes all headers and checksums.
2979  */
2980 static int
2981 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2982 {
2983         struct mlx5e_priv *priv = ifp->if_softc;
2984         struct mlx5_core_dev *mdev = priv->mdev;
2985         int hw_mtu;
2986         int err;
2987
2988         hw_mtu = MLX5E_SW2HW_MTU(sw_mtu);
2989
2990         err = mlx5_set_port_mtu(mdev, hw_mtu);
2991         if (err) {
2992                 mlx5_en_err(ifp, "mlx5_set_port_mtu failed setting %d, err=%d\n",
2993                     sw_mtu, err);
2994                 return (err);
2995         }
2996
2997         /* Update vport context MTU */
2998         err = mlx5_set_vport_mtu(mdev, hw_mtu);
2999         if (err) {
3000                 mlx5_en_err(ifp,
3001                     "Failed updating vport context with MTU size, err=%d\n",
3002                     err);
3003         }
3004
3005         ifp->if_mtu = sw_mtu;
3006
3007         err = mlx5_query_vport_mtu(mdev, &hw_mtu);
3008         if (err || !hw_mtu) {
3009                 /* fallback to port oper mtu */
3010                 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
3011         }
3012         if (err) {
3013                 mlx5_en_err(ifp,
3014                     "Query port MTU, after setting new MTU value, failed\n");
3015                 return (err);
3016         } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
3017                 err = -E2BIG,
3018                 mlx5_en_err(ifp,
3019                     "Port MTU %d is smaller than ifp mtu %d\n",
3020                     hw_mtu, sw_mtu);
3021         } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
3022                 err = -EINVAL;
3023                 mlx5_en_err(ifp,
3024                     "Port MTU %d is bigger than ifp mtu %d\n",
3025                     hw_mtu, sw_mtu);
3026         }
3027         priv->params_ethtool.hw_mtu = hw_mtu;
3028
3029         /* compute MSB */
3030         while (hw_mtu & (hw_mtu - 1))
3031                 hw_mtu &= (hw_mtu - 1);
3032         priv->params_ethtool.hw_mtu_msb = hw_mtu;
3033
3034         return (err);
3035 }
3036
3037 int
3038 mlx5e_open_locked(struct ifnet *ifp)
3039 {
3040         struct mlx5e_priv *priv = ifp->if_softc;
3041         int err;
3042         u16 set_id;
3043
3044         /* check if already opened */
3045         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
3046                 return (0);
3047
3048 #ifdef RSS
3049         if (rss_getnumbuckets() > priv->params.num_channels) {
3050                 mlx5_en_info(ifp,
3051                     "NOTE: There are more RSS buckets(%u) than channels(%u) available\n",
3052                     rss_getnumbuckets(), priv->params.num_channels);
3053         }
3054 #endif
3055         err = mlx5e_open_tises(priv);
3056         if (err) {
3057                 mlx5_en_err(ifp, "mlx5e_open_tises failed, %d\n", err);
3058                 return (err);
3059         }
3060         err = mlx5_vport_alloc_q_counter(priv->mdev,
3061             MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
3062         if (err) {
3063                 mlx5_en_err(priv->ifp,
3064                     "mlx5_vport_alloc_q_counter failed: %d\n", err);
3065                 goto err_close_tises;
3066         }
3067         /* store counter set ID */
3068         priv->counter_set_id = set_id;
3069
3070         err = mlx5e_open_channels(priv);
3071         if (err) {
3072                 mlx5_en_err(ifp,
3073                     "mlx5e_open_channels failed, %d\n", err);
3074                 goto err_dalloc_q_counter;
3075         }
3076         err = mlx5e_open_rqt(priv);
3077         if (err) {
3078                 mlx5_en_err(ifp, "mlx5e_open_rqt failed, %d\n", err);
3079                 goto err_close_channels;
3080         }
3081         err = mlx5e_open_tirs(priv);
3082         if (err) {
3083                 mlx5_en_err(ifp, "mlx5e_open_tir failed, %d\n", err);
3084                 goto err_close_rqls;
3085         }
3086         err = mlx5e_open_flow_table(priv);
3087         if (err) {
3088                 mlx5_en_err(ifp,
3089                     "mlx5e_open_flow_table failed, %d\n", err);
3090                 goto err_close_tirs;
3091         }
3092         err = mlx5e_add_all_vlan_rules(priv);
3093         if (err) {
3094                 mlx5_en_err(ifp,
3095                     "mlx5e_add_all_vlan_rules failed, %d\n", err);
3096                 goto err_close_flow_table;
3097         }
3098         set_bit(MLX5E_STATE_OPENED, &priv->state);
3099
3100         mlx5e_update_carrier(priv);
3101         mlx5e_set_rx_mode_core(priv);
3102
3103         return (0);
3104
3105 err_close_flow_table:
3106         mlx5e_close_flow_table(priv);
3107
3108 err_close_tirs:
3109         mlx5e_close_tirs(priv);
3110
3111 err_close_rqls:
3112         mlx5e_close_rqt(priv);
3113
3114 err_close_channels:
3115         mlx5e_close_channels(priv);
3116
3117 err_dalloc_q_counter:
3118         mlx5_vport_dealloc_q_counter(priv->mdev,
3119             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
3120
3121 err_close_tises:
3122         mlx5e_close_tises(priv);
3123
3124         return (err);
3125 }
3126
3127 static void
3128 mlx5e_open(void *arg)
3129 {
3130         struct mlx5e_priv *priv = arg;
3131
3132         PRIV_LOCK(priv);
3133         if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
3134                 mlx5_en_err(priv->ifp,
3135                     "Setting port status to up failed\n");
3136
3137         mlx5e_open_locked(priv->ifp);
3138         priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
3139         PRIV_UNLOCK(priv);
3140 }
3141
3142 int
3143 mlx5e_close_locked(struct ifnet *ifp)
3144 {
3145         struct mlx5e_priv *priv = ifp->if_softc;
3146
3147         /* check if already closed */
3148         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3149                 return (0);
3150
3151         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3152
3153         mlx5e_set_rx_mode_core(priv);
3154         mlx5e_del_all_vlan_rules(priv);
3155         if_link_state_change(priv->ifp, LINK_STATE_DOWN);
3156         mlx5e_close_flow_table(priv);
3157         mlx5e_close_tirs(priv);
3158         mlx5e_close_rqt(priv);
3159         mlx5e_close_channels(priv);
3160         mlx5_vport_dealloc_q_counter(priv->mdev,
3161             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
3162         mlx5e_close_tises(priv);
3163
3164         return (0);
3165 }
3166
3167 #if (__FreeBSD_version >= 1100000)
3168 static uint64_t
3169 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
3170 {
3171         struct mlx5e_priv *priv = ifp->if_softc;
3172         u64 retval;
3173
3174         /* PRIV_LOCK(priv); XXX not allowed */
3175         switch (cnt) {
3176         case IFCOUNTER_IPACKETS:
3177                 retval = priv->stats.vport.rx_packets;
3178                 break;
3179         case IFCOUNTER_IERRORS:
3180                 retval = priv->stats.pport.in_range_len_errors +
3181                     priv->stats.pport.out_of_range_len +
3182                     priv->stats.pport.too_long_errors +
3183                     priv->stats.pport.check_seq_err +
3184                     priv->stats.pport.alignment_err;
3185                 break;
3186         case IFCOUNTER_IQDROPS:
3187                 retval = priv->stats.vport.rx_out_of_buffer;
3188                 break;
3189         case IFCOUNTER_OPACKETS:
3190                 retval = priv->stats.vport.tx_packets;
3191                 break;
3192         case IFCOUNTER_OERRORS:
3193                 retval = priv->stats.port_stats_debug.out_discards;
3194                 break;
3195         case IFCOUNTER_IBYTES:
3196                 retval = priv->stats.vport.rx_bytes;
3197                 break;
3198         case IFCOUNTER_OBYTES:
3199                 retval = priv->stats.vport.tx_bytes;
3200                 break;
3201         case IFCOUNTER_IMCASTS:
3202                 retval = priv->stats.vport.rx_multicast_packets;
3203                 break;
3204         case IFCOUNTER_OMCASTS:
3205                 retval = priv->stats.vport.tx_multicast_packets;
3206                 break;
3207         case IFCOUNTER_OQDROPS:
3208                 retval = priv->stats.vport.tx_queue_dropped;
3209                 break;
3210         case IFCOUNTER_COLLISIONS:
3211                 retval = priv->stats.pport.collisions;
3212                 break;
3213         default:
3214                 retval = if_get_counter_default(ifp, cnt);
3215                 break;
3216         }
3217         /* PRIV_UNLOCK(priv); XXX not allowed */
3218         return (retval);
3219 }
3220 #endif
3221
3222 static void
3223 mlx5e_set_rx_mode(struct ifnet *ifp)
3224 {
3225         struct mlx5e_priv *priv = ifp->if_softc;
3226
3227         queue_work(priv->wq, &priv->set_rx_mode_work);
3228 }
3229
3230 static int
3231 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3232 {
3233         struct mlx5e_priv *priv;
3234         struct ifreq *ifr;
3235         struct ifdownreason *ifdr;
3236         struct ifi2creq i2c;
3237         int error = 0;
3238         int mask = 0;
3239         int size_read = 0;
3240         int module_status;
3241         int module_num;
3242         int max_mtu;
3243         uint8_t read_addr;
3244
3245         priv = ifp->if_softc;
3246
3247         /* check if detaching */
3248         if (priv == NULL || priv->gone != 0)
3249                 return (ENXIO);
3250
3251         switch (command) {
3252         case SIOCSIFMTU:
3253                 ifr = (struct ifreq *)data;
3254
3255                 PRIV_LOCK(priv);
3256                 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
3257
3258                 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
3259                     ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
3260                         int was_opened;
3261
3262                         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3263                         if (was_opened)
3264                                 mlx5e_close_locked(ifp);
3265
3266                         /* set new MTU */
3267                         mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
3268
3269                         if (was_opened)
3270                                 mlx5e_open_locked(ifp);
3271                 } else {
3272                         error = EINVAL;
3273                         mlx5_en_err(ifp,
3274                             "Invalid MTU value. Min val: %d, Max val: %d\n",
3275                             MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
3276                 }
3277                 PRIV_UNLOCK(priv);
3278                 break;
3279         case SIOCSIFFLAGS:
3280                 if ((ifp->if_flags & IFF_UP) &&
3281                     (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3282                         mlx5e_set_rx_mode(ifp);
3283                         break;
3284                 }
3285                 PRIV_LOCK(priv);
3286                 if (ifp->if_flags & IFF_UP) {
3287                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
3288                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3289                                         mlx5e_open_locked(ifp);
3290                                 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3291                                 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
3292                         }
3293                 } else {
3294                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3295                                 mlx5_set_port_status(priv->mdev,
3296                                     MLX5_PORT_DOWN);
3297                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
3298                                         mlx5e_close_locked(ifp);
3299                                 mlx5e_update_carrier(priv);
3300                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3301                         }
3302                 }
3303                 PRIV_UNLOCK(priv);
3304                 break;
3305         case SIOCADDMULTI:
3306         case SIOCDELMULTI:
3307                 mlx5e_set_rx_mode(ifp);
3308                 break;
3309         case SIOCSIFMEDIA:
3310         case SIOCGIFMEDIA:
3311         case SIOCGIFXMEDIA:
3312                 ifr = (struct ifreq *)data;
3313                 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
3314                 break;
3315         case SIOCSIFCAP:
3316                 ifr = (struct ifreq *)data;
3317                 PRIV_LOCK(priv);
3318                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3319
3320                 if (mask & IFCAP_TXCSUM) {
3321                         ifp->if_capenable ^= IFCAP_TXCSUM;
3322                         ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
3323
3324                         if (IFCAP_TSO4 & ifp->if_capenable &&
3325                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
3326                                 mask &= ~IFCAP_TSO4;
3327                                 ifp->if_capenable &= ~IFCAP_TSO4;
3328                                 ifp->if_hwassist &= ~CSUM_IP_TSO;
3329                                 mlx5_en_err(ifp,
3330                                     "tso4 disabled due to -txcsum.\n");
3331                         }
3332                 }
3333                 if (mask & IFCAP_TXCSUM_IPV6) {
3334                         ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
3335                         ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3336
3337                         if (IFCAP_TSO6 & ifp->if_capenable &&
3338                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
3339                                 mask &= ~IFCAP_TSO6;
3340                                 ifp->if_capenable &= ~IFCAP_TSO6;
3341                                 ifp->if_hwassist &= ~CSUM_IP6_TSO;
3342                                 mlx5_en_err(ifp,
3343                                     "tso6 disabled due to -txcsum6.\n");
3344                         }
3345                 }
3346                 if (mask & IFCAP_NOMAP)
3347                         ifp->if_capenable ^= IFCAP_NOMAP;
3348                 if (mask & IFCAP_TXTLS4)
3349                         ifp->if_capenable ^= IFCAP_TXTLS4;
3350                 if (mask & IFCAP_TXTLS6)
3351                         ifp->if_capenable ^= IFCAP_TXTLS6;
3352                 if (mask & IFCAP_RXCSUM)
3353                         ifp->if_capenable ^= IFCAP_RXCSUM;
3354                 if (mask & IFCAP_RXCSUM_IPV6)
3355                         ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
3356                 if (mask & IFCAP_TSO4) {
3357                         if (!(IFCAP_TSO4 & ifp->if_capenable) &&
3358                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
3359                                 mlx5_en_err(ifp, "enable txcsum first.\n");
3360                                 error = EAGAIN;
3361                                 goto out;
3362                         }
3363                         ifp->if_capenable ^= IFCAP_TSO4;
3364                         ifp->if_hwassist ^= CSUM_IP_TSO;
3365                 }
3366                 if (mask & IFCAP_TSO6) {
3367                         if (!(IFCAP_TSO6 & ifp->if_capenable) &&
3368                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
3369                                 mlx5_en_err(ifp, "enable txcsum6 first.\n");
3370                                 error = EAGAIN;
3371                                 goto out;
3372                         }
3373                         ifp->if_capenable ^= IFCAP_TSO6;
3374                         ifp->if_hwassist ^= CSUM_IP6_TSO;
3375                 }
3376                 if (mask & IFCAP_VLAN_HWFILTER) {
3377                         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
3378                                 mlx5e_disable_vlan_filter(priv);
3379                         else
3380                                 mlx5e_enable_vlan_filter(priv);
3381
3382                         ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
3383                 }
3384                 if (mask & IFCAP_VLAN_HWTAGGING)
3385                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
3386                 if (mask & IFCAP_WOL_MAGIC)
3387                         ifp->if_capenable ^= IFCAP_WOL_MAGIC;
3388
3389                 VLAN_CAPABILITIES(ifp);
3390                 /* turn off LRO means also turn of HW LRO - if it's on */
3391                 if (mask & IFCAP_LRO) {
3392                         int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3393                         bool need_restart = false;
3394
3395                         ifp->if_capenable ^= IFCAP_LRO;
3396
3397                         /* figure out if updating HW LRO is needed */
3398                         if (!(ifp->if_capenable & IFCAP_LRO)) {
3399                                 if (priv->params.hw_lro_en) {
3400                                         priv->params.hw_lro_en = false;
3401                                         need_restart = true;
3402                                 }
3403                         } else {
3404                                 if (priv->params.hw_lro_en == false &&
3405                                     priv->params_ethtool.hw_lro != 0) {
3406                                         priv->params.hw_lro_en = true;
3407                                         need_restart = true;
3408                                 }
3409                         }
3410                         if (was_opened && need_restart) {
3411                                 mlx5e_close_locked(ifp);
3412                                 mlx5e_open_locked(ifp);
3413                         }
3414                 }
3415                 if (mask & IFCAP_HWRXTSTMP) {
3416                         ifp->if_capenable ^= IFCAP_HWRXTSTMP;
3417                         if (ifp->if_capenable & IFCAP_HWRXTSTMP) {
3418                                 if (priv->clbr_done == 0)
3419                                         mlx5e_reset_calibration_callout(priv);
3420                         } else {
3421                                 callout_drain(&priv->tstmp_clbr);
3422                                 priv->clbr_done = 0;
3423                         }
3424                 }
3425 out:
3426                 PRIV_UNLOCK(priv);
3427                 break;
3428
3429         case SIOCGI2C:
3430                 ifr = (struct ifreq *)data;
3431
3432                 /*
3433                  * Copy from the user-space address ifr_data to the
3434                  * kernel-space address i2c
3435                  */
3436                 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
3437                 if (error)
3438                         break;
3439
3440                 if (i2c.len > sizeof(i2c.data)) {
3441                         error = EINVAL;
3442                         break;
3443                 }
3444
3445                 PRIV_LOCK(priv);
3446                 /* Get module_num which is required for the query_eeprom */
3447                 error = mlx5_query_module_num(priv->mdev, &module_num);
3448                 if (error) {
3449                         mlx5_en_err(ifp,
3450                             "Query module num failed, eeprom reading is not supported\n");
3451                         error = EINVAL;
3452                         goto err_i2c;
3453                 }
3454                 /* Check if module is present before doing an access */
3455                 module_status = mlx5_query_module_status(priv->mdev, module_num);
3456                 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED) {
3457                         error = EINVAL;
3458                         goto err_i2c;
3459                 }
3460                 /*
3461                  * Currently 0XA0 and 0xA2 are the only addresses permitted.
3462                  * The internal conversion is as follows:
3463                  */
3464                 if (i2c.dev_addr == 0xA0)
3465                         read_addr = MLX5_I2C_ADDR_LOW;
3466                 else if (i2c.dev_addr == 0xA2)
3467                         read_addr = MLX5_I2C_ADDR_HIGH;
3468                 else {
3469                         mlx5_en_err(ifp,
3470                             "Query eeprom failed, Invalid Address: %X\n",
3471                             i2c.dev_addr);
3472                         error = EINVAL;
3473                         goto err_i2c;
3474                 }
3475                 error = mlx5_query_eeprom(priv->mdev,
3476                     read_addr, MLX5_EEPROM_LOW_PAGE,
3477                     (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
3478                     (uint32_t *)i2c.data, &size_read);
3479                 if (error) {
3480                         mlx5_en_err(ifp,
3481                             "Query eeprom failed, eeprom reading is not supported\n");
3482                         error = EINVAL;
3483                         goto err_i2c;
3484                 }
3485
3486                 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
3487                         error = mlx5_query_eeprom(priv->mdev,
3488                             read_addr, MLX5_EEPROM_LOW_PAGE,
3489                             (uint32_t)(i2c.offset + size_read),
3490                             (uint32_t)(i2c.len - size_read), module_num,
3491                             (uint32_t *)(i2c.data + size_read), &size_read);
3492                 }
3493                 if (error) {
3494                         mlx5_en_err(ifp,
3495                             "Query eeprom failed, eeprom reading is not supported\n");
3496                         error = EINVAL;
3497                         goto err_i2c;
3498                 }
3499
3500                 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
3501 err_i2c:
3502                 PRIV_UNLOCK(priv);
3503                 break;
3504         case SIOCGIFDOWNREASON:
3505                 ifdr = (struct ifdownreason *)data;
3506                 bzero(ifdr->ifdr_msg, sizeof(ifdr->ifdr_msg));
3507                 PRIV_LOCK(priv);
3508                 error = -mlx5_query_pddr_troubleshooting_info(priv->mdev, NULL,
3509                     ifdr->ifdr_msg, sizeof(ifdr->ifdr_msg));
3510                 PRIV_UNLOCK(priv);
3511                 if (error == 0)
3512                         ifdr->ifdr_reason = IFDR_REASON_MSG;
3513                 break;
3514
3515         default:
3516                 error = ether_ioctl(ifp, command, data);
3517                 break;
3518         }
3519         return (error);
3520 }
3521
3522 static int
3523 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3524 {
3525         /*
3526          * TODO: uncoment once FW really sets all these bits if
3527          * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
3528          * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
3529          * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
3530          * -ENOTSUPP;
3531          */
3532
3533         /* TODO: add more must-to-have features */
3534
3535         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3536                 return (-ENODEV);
3537
3538         return (0);
3539 }
3540
3541 static u16
3542 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3543 {
3544         const int min_size = ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN;
3545         const int max_size = MLX5E_MAX_TX_INLINE;
3546         const int bf_buf_size =
3547             ((1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U) -
3548             (sizeof(struct mlx5e_tx_wqe) - 2);
3549
3550         /* verify against driver limits */
3551         if (bf_buf_size > max_size)
3552                 return (max_size);
3553         else if (bf_buf_size < min_size)
3554                 return (min_size);
3555         else
3556                 return (bf_buf_size);
3557 }
3558
3559 static int
3560 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
3561     struct mlx5e_priv *priv,
3562     int num_comp_vectors)
3563 {
3564         int err;
3565
3566         /*
3567          * TODO: Consider link speed for setting "log_sq_size",
3568          * "log_rq_size" and "cq_moderation_xxx":
3569          */
3570         priv->params.log_sq_size =
3571             MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3572         priv->params.log_rq_size =
3573             MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3574         priv->params.rx_cq_moderation_usec =
3575             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3576             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
3577             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3578         priv->params.rx_cq_moderation_mode =
3579             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
3580         priv->params.rx_cq_moderation_pkts =
3581             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3582         priv->params.tx_cq_moderation_usec =
3583             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3584         priv->params.tx_cq_moderation_pkts =
3585             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3586         priv->params.min_rx_wqes =
3587             MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
3588         priv->params.rx_hash_log_tbl_sz =
3589             (order_base_2(num_comp_vectors) >
3590             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
3591             order_base_2(num_comp_vectors) :
3592             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
3593         priv->params.num_tc = 1;
3594         priv->params.default_vlan_prio = 0;
3595         priv->counter_set_id = -1;
3596         priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3597
3598         err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3599         if (err)
3600                 return (err);
3601
3602         /*
3603          * hw lro is currently defaulted to off. when it won't anymore we
3604          * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
3605          */
3606         priv->params.hw_lro_en = false;
3607         priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3608
3609         /*
3610          * CQE zipping is currently defaulted to off. when it won't
3611          * anymore we will consider the HW capability:
3612          * "!!MLX5_CAP_GEN(mdev, cqe_compression)"
3613          */
3614         priv->params.cqe_zipping_en = false;
3615
3616         priv->mdev = mdev;
3617         priv->params.num_channels = num_comp_vectors;
3618         priv->params.channels_rsss = 1;
3619         priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
3620         priv->queue_mapping_channel_mask =
3621             roundup_pow_of_two(num_comp_vectors) - 1;
3622         priv->num_tc = priv->params.num_tc;
3623         priv->default_vlan_prio = priv->params.default_vlan_prio;
3624
3625         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3626         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3627         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3628
3629         return (0);
3630 }
3631
3632 static int
3633 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
3634                   struct mlx5_core_mr *mkey)
3635 {
3636         struct ifnet *ifp = priv->ifp;
3637         struct mlx5_core_dev *mdev = priv->mdev;
3638         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3639         void *mkc;
3640         u32 *in;
3641         int err;
3642
3643         in = mlx5_vzalloc(inlen);
3644         if (in == NULL) {
3645                 mlx5_en_err(ifp, "failed to allocate inbox\n");
3646                 return (-ENOMEM);
3647         }
3648
3649         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3650         MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA);
3651         MLX5_SET(mkc, mkc, umr_en, 1);  /* used by HW TLS */
3652         MLX5_SET(mkc, mkc, lw, 1);
3653         MLX5_SET(mkc, mkc, lr, 1);
3654
3655         MLX5_SET(mkc, mkc, pd, pdn);
3656         MLX5_SET(mkc, mkc, length64, 1);
3657         MLX5_SET(mkc, mkc, qpn, 0xffffff);
3658
3659         err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
3660         if (err)
3661                 mlx5_en_err(ifp, "mlx5_core_create_mkey failed, %d\n",
3662                     err);
3663
3664         kvfree(in);
3665         return (err);
3666 }
3667
3668 static const char *mlx5e_vport_stats_desc[] = {
3669         MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
3670 };
3671
3672 static const char *mlx5e_pport_stats_desc[] = {
3673         MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
3674 };
3675
3676 static void
3677 mlx5e_priv_static_init(struct mlx5e_priv *priv, const uint32_t channels)
3678 {
3679         uint32_t x;
3680
3681         mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
3682         sx_init(&priv->state_lock, "mlx5state");
3683         callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
3684         MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
3685         for (x = 0; x != channels; x++)
3686                 mlx5e_chan_static_init(priv, &priv->channel[x], x);
3687 }
3688
3689 static void
3690 mlx5e_priv_static_destroy(struct mlx5e_priv *priv, const uint32_t channels)
3691 {
3692         uint32_t x;
3693
3694         for (x = 0; x != channels; x++)
3695                 mlx5e_chan_static_destroy(&priv->channel[x]);
3696         callout_drain(&priv->watchdog);
3697         mtx_destroy(&priv->async_events_mtx);
3698         sx_destroy(&priv->state_lock);
3699 }
3700
3701 static int
3702 sysctl_firmware(SYSCTL_HANDLER_ARGS)
3703 {
3704         /*
3705          * %d.%d%.d the string format.
3706          * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
3707          * We need at most 5 chars to store that.
3708          * It also has: two "." and NULL at the end, which means we need 18
3709          * (5*3 + 3) chars at most.
3710          */
3711         char fw[18];
3712         struct mlx5e_priv *priv = arg1;
3713         int error;
3714
3715         snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
3716             fw_rev_sub(priv->mdev));
3717         error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
3718         return (error);
3719 }
3720
3721 static void
3722 mlx5e_disable_tx_dma(struct mlx5e_channel *ch)
3723 {
3724         int i;
3725
3726         for (i = 0; i < ch->priv->num_tc; i++)
3727                 mlx5e_drain_sq(&ch->sq[i]);
3728 }
3729
3730 static void
3731 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq)
3732 {
3733
3734         sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP);
3735         sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8);
3736         mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
3737         sq->doorbell.d64 = 0;
3738 }
3739
3740 void
3741 mlx5e_resume_sq(struct mlx5e_sq *sq)
3742 {
3743         int err;
3744
3745         /* check if already enabled */
3746         if (READ_ONCE(sq->running) != 0)
3747                 return;
3748
3749         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR,
3750             MLX5_SQC_STATE_RST);
3751         if (err != 0) {
3752                 mlx5_en_err(sq->ifp,
3753                     "mlx5e_modify_sq() from ERR to RST failed: %d\n", err);
3754         }
3755
3756         sq->cc = 0;
3757         sq->pc = 0;
3758
3759         /* reset doorbell prior to moving from RST to RDY */
3760         mlx5e_reset_sq_doorbell_record(sq);
3761
3762         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST,
3763             MLX5_SQC_STATE_RDY);
3764         if (err != 0) {
3765                 mlx5_en_err(sq->ifp,
3766                     "mlx5e_modify_sq() from RST to RDY failed: %d\n", err);
3767         }
3768
3769         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
3770         WRITE_ONCE(sq->running, 1);
3771 }
3772
3773 static void
3774 mlx5e_enable_tx_dma(struct mlx5e_channel *ch)
3775 {
3776         int i;
3777
3778         for (i = 0; i < ch->priv->num_tc; i++)
3779                 mlx5e_resume_sq(&ch->sq[i]);
3780 }
3781
3782 static void
3783 mlx5e_disable_rx_dma(struct mlx5e_channel *ch)
3784 {
3785         struct mlx5e_rq *rq = &ch->rq;
3786         struct epoch_tracker et;
3787         int err;
3788
3789         mtx_lock(&rq->mtx);
3790         rq->enabled = 0;
3791         callout_stop(&rq->watchdog);
3792         mtx_unlock(&rq->mtx);
3793
3794         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
3795         if (err != 0) {
3796                 mlx5_en_err(rq->ifp,
3797                     "mlx5e_modify_rq() from RDY to RST failed: %d\n", err);
3798         }
3799
3800         while (!mlx5_wq_ll_is_empty(&rq->wq)) {
3801                 msleep(1);
3802                 NET_EPOCH_ENTER(et);
3803                 rq->cq.mcq.comp(&rq->cq.mcq);
3804                 NET_EPOCH_EXIT(et);
3805         }
3806
3807         /*
3808          * Transitioning into RST state will allow the FW to track less ERR state queues,
3809          * thus reducing the recv queue flushing time
3810          */
3811         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST);
3812         if (err != 0) {
3813                 mlx5_en_err(rq->ifp,
3814                     "mlx5e_modify_rq() from ERR to RST failed: %d\n", err);
3815         }
3816 }
3817
3818 static void
3819 mlx5e_enable_rx_dma(struct mlx5e_channel *ch)
3820 {
3821         struct mlx5e_rq *rq = &ch->rq;
3822         struct epoch_tracker et;
3823         int err;
3824
3825         rq->wq.wqe_ctr = 0;
3826         mlx5_wq_ll_update_db_record(&rq->wq);
3827         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3828         if (err != 0) {
3829                 mlx5_en_err(rq->ifp,
3830                     "mlx5e_modify_rq() from RST to RDY failed: %d\n", err);
3831         }
3832
3833         rq->enabled = 1;
3834
3835         NET_EPOCH_ENTER(et);
3836         rq->cq.mcq.comp(&rq->cq.mcq);
3837         NET_EPOCH_EXIT(et);
3838 }
3839
3840 void
3841 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value)
3842 {
3843         int i;
3844
3845         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3846                 return;
3847
3848         for (i = 0; i < priv->params.num_channels; i++) {
3849                 if (value)
3850                         mlx5e_disable_tx_dma(&priv->channel[i]);
3851                 else
3852                         mlx5e_enable_tx_dma(&priv->channel[i]);
3853         }
3854 }
3855
3856 void
3857 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value)
3858 {
3859         int i;
3860
3861         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3862                 return;
3863
3864         for (i = 0; i < priv->params.num_channels; i++) {
3865                 if (value)
3866                         mlx5e_disable_rx_dma(&priv->channel[i]);
3867                 else
3868                         mlx5e_enable_rx_dma(&priv->channel[i]);
3869         }
3870 }
3871
3872 static void
3873 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
3874 {
3875         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3876             OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD | CTLFLAG_MPSAFE,
3877             priv, 0, sysctl_firmware, "A", "HCA firmware version");
3878
3879         SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3880             OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
3881             "Board ID");
3882 }
3883
3884 static int
3885 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3886 {
3887         struct mlx5e_priv *priv = arg1;
3888         uint8_t temp[MLX5E_MAX_PRIORITY];
3889         uint32_t tx_pfc;
3890         int err;
3891         int i;
3892
3893         PRIV_LOCK(priv);
3894
3895         tx_pfc = priv->params.tx_priority_flow_control;
3896
3897         for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3898                 temp[i] = (tx_pfc >> i) & 1;
3899
3900         err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3901         if (err || !req->newptr)
3902                 goto done;
3903         err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3904         if (err)
3905                 goto done;
3906
3907         priv->params.tx_priority_flow_control = 0;
3908
3909         /* range check input value */
3910         for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3911                 if (temp[i] > 1) {
3912                         err = ERANGE;
3913                         goto done;
3914                 }
3915                 priv->params.tx_priority_flow_control |= (temp[i] << i);
3916         }
3917
3918         /* check if update is required */
3919         if (tx_pfc != priv->params.tx_priority_flow_control)
3920                 err = -mlx5e_set_port_pfc(priv);
3921 done:
3922         if (err != 0)
3923                 priv->params.tx_priority_flow_control= tx_pfc;
3924         PRIV_UNLOCK(priv);
3925
3926         return (err);
3927 }
3928
3929 static int
3930 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3931 {
3932         struct mlx5e_priv *priv = arg1;
3933         uint8_t temp[MLX5E_MAX_PRIORITY];
3934         uint32_t rx_pfc;
3935         int err;
3936         int i;
3937
3938         PRIV_LOCK(priv);
3939
3940         rx_pfc = priv->params.rx_priority_flow_control;
3941
3942         for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3943                 temp[i] = (rx_pfc >> i) & 1;
3944
3945         err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3946         if (err || !req->newptr)
3947                 goto done;
3948         err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3949         if (err)
3950                 goto done;
3951
3952         priv->params.rx_priority_flow_control = 0;
3953
3954         /* range check input value */
3955         for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3956                 if (temp[i] > 1) {
3957                         err = ERANGE;
3958                         goto done;
3959                 }
3960                 priv->params.rx_priority_flow_control |= (temp[i] << i);
3961         }
3962
3963         /* check if update is required */
3964         if (rx_pfc != priv->params.rx_priority_flow_control) {
3965                 err = -mlx5e_set_port_pfc(priv);
3966                 if (err == 0 && priv->sw_is_port_buf_owner)
3967                         err = mlx5e_update_buf_lossy(priv);
3968         }
3969 done:
3970         if (err != 0)
3971                 priv->params.rx_priority_flow_control= rx_pfc;
3972         PRIV_UNLOCK(priv);
3973
3974         return (err);
3975 }
3976
3977 static void
3978 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
3979 {
3980 #if (__FreeBSD_version < 1100000)
3981         char path[96];
3982 #endif
3983         int error;
3984
3985         /* enable pauseframes by default */
3986         priv->params.tx_pauseframe_control = 1;
3987         priv->params.rx_pauseframe_control = 1;
3988
3989         /* disable ports flow control, PFC, by default */
3990         priv->params.tx_priority_flow_control = 0;
3991         priv->params.rx_priority_flow_control = 0;
3992
3993 #if (__FreeBSD_version < 1100000)
3994         /* compute path for sysctl */
3995         snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
3996             device_get_unit(priv->mdev->pdev->dev.bsddev));
3997
3998         /* try to fetch tunable, if any */
3999         TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
4000
4001         /* compute path for sysctl */
4002         snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
4003             device_get_unit(priv->mdev->pdev->dev.bsddev));
4004
4005         /* try to fetch tunable, if any */
4006         TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
4007 #endif
4008
4009         /* register pauseframe SYSCTLs */
4010         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4011             OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
4012             &priv->params.tx_pauseframe_control, 0,
4013             "Set to enable TX pause frames. Clear to disable.");
4014
4015         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4016             OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
4017             &priv->params.rx_pauseframe_control, 0,
4018             "Set to enable RX pause frames. Clear to disable.");
4019
4020         /* register priority flow control, PFC, SYSCTLs */
4021         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4022             OID_AUTO, "tx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
4023             CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_tx_priority_flow_control, "CU",
4024             "Set to enable TX ports flow control frames for priorities 0..7. Clear to disable.");
4025
4026         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4027             OID_AUTO, "rx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
4028             CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_rx_priority_flow_control, "CU",
4029             "Set to enable RX ports flow control frames for priorities 0..7. Clear to disable.");
4030
4031         PRIV_LOCK(priv);
4032
4033         /* range check */
4034         priv->params.tx_pauseframe_control =
4035             priv->params.tx_pauseframe_control ? 1 : 0;
4036         priv->params.rx_pauseframe_control =
4037             priv->params.rx_pauseframe_control ? 1 : 0;
4038
4039         /* update firmware */
4040         error = mlx5e_set_port_pause_and_pfc(priv);
4041         if (error == -EINVAL) {
4042                 mlx5_en_err(priv->ifp,
4043                     "Global pauseframes must be disabled before enabling PFC.\n");
4044                 priv->params.rx_priority_flow_control = 0;
4045                 priv->params.tx_priority_flow_control = 0;
4046
4047                 /* update firmware */
4048                 (void) mlx5e_set_port_pause_and_pfc(priv);
4049         }
4050         PRIV_UNLOCK(priv);
4051 }
4052
4053 int
4054 mlx5e_ul_snd_tag_alloc(struct ifnet *ifp,
4055     union if_snd_tag_alloc_params *params,
4056     struct m_snd_tag **ppmt)
4057 {
4058         struct mlx5e_priv *priv;
4059         struct mlx5e_channel *pch;
4060
4061         priv = ifp->if_softc;
4062
4063         if (unlikely(priv->gone || params->hdr.flowtype == M_HASHTYPE_NONE)) {
4064                 return (EOPNOTSUPP);
4065         } else {
4066                 /* keep this code synced with mlx5e_select_queue() */
4067                 u32 ch = priv->params.num_channels;
4068 #ifdef RSS
4069                 u32 temp;
4070
4071                 if (rss_hash2bucket(params->hdr.flowid,
4072                     params->hdr.flowtype, &temp) == 0)
4073                         ch = temp % ch;
4074                 else
4075 #endif
4076                         ch = (params->hdr.flowid % 128) % ch;
4077
4078                 /*
4079                  * NOTE: The channels array is only freed at detach
4080                  * and it safe to return a pointer to the send tag
4081                  * inside the channels structure as long as we
4082                  * reference the priv.
4083                  */
4084                 pch = priv->channel + ch;
4085
4086                 /* check if send queue is not running */
4087                 if (unlikely(pch->sq[0].running == 0))
4088                         return (ENXIO);
4089                 m_snd_tag_ref(&pch->tag);
4090                 *ppmt = &pch->tag;
4091                 return (0);
4092         }
4093 }
4094
4095 int
4096 mlx5e_ul_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
4097 {
4098         struct mlx5e_channel *pch =
4099             container_of(pmt, struct mlx5e_channel, tag);
4100
4101         params->unlimited.max_rate = -1ULL;
4102         params->unlimited.queue_level = mlx5e_sq_queue_level(&pch->sq[0]);
4103         return (0);
4104 }
4105
4106 void
4107 mlx5e_ul_snd_tag_free(struct m_snd_tag *pmt)
4108 {
4109         struct mlx5e_channel *pch =
4110             container_of(pmt, struct mlx5e_channel, tag);
4111
4112         complete(&pch->completion);
4113 }
4114
4115 static int
4116 mlx5e_snd_tag_alloc(struct ifnet *ifp,
4117     union if_snd_tag_alloc_params *params,
4118     struct m_snd_tag **ppmt)
4119 {
4120
4121         switch (params->hdr.type) {
4122 #ifdef RATELIMIT
4123         case IF_SND_TAG_TYPE_RATE_LIMIT:
4124                 return (mlx5e_rl_snd_tag_alloc(ifp, params, ppmt));
4125 #if defined(KERN_TLS) && defined(IF_SND_TAG_TYPE_TLS_RATE_LIMIT)
4126         case IF_SND_TAG_TYPE_TLS_RATE_LIMIT:
4127                 return (mlx5e_tls_snd_tag_alloc(ifp, params, ppmt));
4128 #endif
4129 #endif
4130         case IF_SND_TAG_TYPE_UNLIMITED:
4131                 return (mlx5e_ul_snd_tag_alloc(ifp, params, ppmt));
4132 #ifdef KERN_TLS
4133         case IF_SND_TAG_TYPE_TLS:
4134                 return (mlx5e_tls_snd_tag_alloc(ifp, params, ppmt));
4135 #endif
4136         default:
4137                 return (EOPNOTSUPP);
4138         }
4139 }
4140
4141 static int
4142 mlx5e_snd_tag_modify(struct m_snd_tag *pmt, union if_snd_tag_modify_params *params)
4143 {
4144
4145         switch (pmt->type) {
4146 #ifdef RATELIMIT
4147         case IF_SND_TAG_TYPE_RATE_LIMIT:
4148                 return (mlx5e_rl_snd_tag_modify(pmt, params));
4149 #if defined(KERN_TLS) && defined(IF_SND_TAG_TYPE_TLS_RATE_LIMIT)
4150         case IF_SND_TAG_TYPE_TLS_RATE_LIMIT:
4151                 return (mlx5e_tls_snd_tag_modify(pmt, params));
4152 #endif
4153 #endif
4154         case IF_SND_TAG_TYPE_UNLIMITED:
4155 #ifdef KERN_TLS
4156         case IF_SND_TAG_TYPE_TLS:
4157 #endif
4158         default:
4159                 return (EOPNOTSUPP);
4160         }
4161 }
4162
4163 static int
4164 mlx5e_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
4165 {
4166
4167         switch (pmt->type) {
4168 #ifdef RATELIMIT
4169         case IF_SND_TAG_TYPE_RATE_LIMIT:
4170                 return (mlx5e_rl_snd_tag_query(pmt, params));
4171 #if defined(KERN_TLS) && defined(IF_SND_TAG_TYPE_TLS_RATE_LIMIT)
4172         case IF_SND_TAG_TYPE_TLS_RATE_LIMIT:
4173                 return (mlx5e_tls_snd_tag_query(pmt, params));
4174 #endif
4175 #endif
4176         case IF_SND_TAG_TYPE_UNLIMITED:
4177                 return (mlx5e_ul_snd_tag_query(pmt, params));
4178 #ifdef KERN_TLS
4179         case IF_SND_TAG_TYPE_TLS:
4180                 return (mlx5e_tls_snd_tag_query(pmt, params));
4181 #endif
4182         default:
4183                 return (EOPNOTSUPP);
4184         }
4185 }
4186
4187 #ifdef RATELIMIT
4188 #define NUM_HDWR_RATES_MLX 13
4189 static const uint64_t adapter_rates_mlx[NUM_HDWR_RATES_MLX] = {
4190         135375,                 /* 1,083,000 */
4191         180500,                 /* 1,444,000 */
4192         270750,                 /* 2,166,000 */
4193         361000,                 /* 2,888,000 */
4194         541500,                 /* 4,332,000 */
4195         721875,                 /* 5,775,000 */
4196         1082875,                /* 8,663,000 */
4197         1443875,                /* 11,551,000 */
4198         2165750,                /* 17,326,000 */
4199         2887750,                /* 23,102,000 */
4200         4331625,                /* 34,653,000 */
4201         5775500,                /* 46,204,000 */
4202         8663125                 /* 69,305,000 */
4203 };
4204
4205 static void
4206 mlx5e_ratelimit_query(struct ifnet *ifp __unused, struct if_ratelimit_query_results *q)
4207 {
4208         /*
4209          * This function needs updating by the driver maintainer!
4210          * For the MLX card there are currently (ConectX-4?) 13
4211          * pre-set rates and others i.e. ConnectX-5, 6, 7??
4212          *
4213          * This will change based on later adapters
4214          * and this code should be updated to look at ifp
4215          * and figure out the specific adapter type
4216          * settings i.e. how many rates as well
4217          * as if they are fixed (as is shown here) or
4218          * if they are dynamic (example chelsio t4). Also if there
4219          * is a maximum number of flows that the adapter
4220          * can handle that too needs to be updated in
4221          * the max_flows field.
4222          */
4223         q->rate_table = adapter_rates_mlx;
4224         q->flags = RT_IS_FIXED_TABLE;
4225         q->max_flows = 0;       /* mlx has no limit */
4226         q->number_of_rates = NUM_HDWR_RATES_MLX;
4227         q->min_segment_burst = 1;
4228 }
4229 #endif
4230
4231 static void
4232 mlx5e_snd_tag_free(struct m_snd_tag *pmt)
4233 {
4234
4235         switch (pmt->type) {
4236 #ifdef RATELIMIT
4237         case IF_SND_TAG_TYPE_RATE_LIMIT:
4238                 mlx5e_rl_snd_tag_free(pmt);
4239                 break;
4240 #if defined(KERN_TLS) && defined(IF_SND_TAG_TYPE_TLS_RATE_LIMIT)
4241         case IF_SND_TAG_TYPE_TLS_RATE_LIMIT:
4242                 mlx5e_tls_snd_tag_free(pmt);
4243                 break;
4244 #endif
4245 #endif
4246         case IF_SND_TAG_TYPE_UNLIMITED:
4247                 mlx5e_ul_snd_tag_free(pmt);
4248                 break;
4249 #ifdef KERN_TLS
4250         case IF_SND_TAG_TYPE_TLS:
4251                 mlx5e_tls_snd_tag_free(pmt);
4252                 break;
4253 #endif
4254         default:
4255                 break;
4256         }
4257 }
4258
4259 static void *
4260 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
4261 {
4262         struct ifnet *ifp;
4263         struct mlx5e_priv *priv;
4264         u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
4265         u8 connector_type;
4266         struct sysctl_oid_list *child;
4267         int ncv = mdev->priv.eq_table.num_comp_vectors;
4268         char unit[16];
4269         struct pfil_head_args pa;
4270         int err;
4271         int i,j;
4272         u32 eth_proto_cap;
4273         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
4274         bool ext = 0;
4275         u32 speeds_num;
4276         struct media media_entry = {};
4277
4278         if (mlx5e_check_required_hca_cap(mdev)) {
4279                 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
4280                 return (NULL);
4281         }
4282         /*
4283          * Try to allocate the priv and make room for worst-case
4284          * number of channel structures:
4285          */
4286         priv = malloc(sizeof(*priv) +
4287             (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors),
4288             M_MLX5EN, M_WAITOK | M_ZERO);
4289
4290         ifp = priv->ifp = if_alloc_dev(IFT_ETHER, mdev->pdev->dev.bsddev);
4291         if (ifp == NULL) {
4292                 mlx5_core_err(mdev, "if_alloc() failed\n");
4293                 goto err_free_priv;
4294         }
4295         /* setup all static fields */
4296         mlx5e_priv_static_init(priv, mdev->priv.eq_table.num_comp_vectors);
4297
4298         ifp->if_softc = priv;
4299         if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev));
4300         ifp->if_mtu = ETHERMTU;
4301         ifp->if_init = mlx5e_open;
4302         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST |
4303             IFF_KNOWSEPOCH;
4304         ifp->if_ioctl = mlx5e_ioctl;
4305         ifp->if_transmit = mlx5e_xmit;
4306         ifp->if_qflush = if_qflush;
4307 #if (__FreeBSD_version >= 1100000)
4308         ifp->if_get_counter = mlx5e_get_counter;
4309 #endif
4310         ifp->if_snd.ifq_maxlen = ifqmaxlen;
4311         /*
4312          * Set driver features
4313          */
4314         ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
4315         ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
4316         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
4317         ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
4318         ifp->if_capabilities |= IFCAP_LRO;
4319         ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
4320         ifp->if_capabilities |= IFCAP_HWSTATS | IFCAP_HWRXTSTMP;
4321         ifp->if_capabilities |= IFCAP_NOMAP;
4322         ifp->if_capabilities |= IFCAP_TXTLS4 | IFCAP_TXTLS6;
4323         ifp->if_capabilities |= IFCAP_TXRTLMT;
4324         ifp->if_snd_tag_alloc = mlx5e_snd_tag_alloc;
4325         ifp->if_snd_tag_free = mlx5e_snd_tag_free;
4326         ifp->if_snd_tag_modify = mlx5e_snd_tag_modify;
4327         ifp->if_snd_tag_query = mlx5e_snd_tag_query;
4328 #ifdef RATELIMIT
4329         ifp->if_ratelimit_query = mlx5e_ratelimit_query;
4330 #endif
4331         /* set TSO limits so that we don't have to drop TX packets */
4332         ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
4333         ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
4334         ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
4335
4336         ifp->if_capenable = ifp->if_capabilities;
4337         ifp->if_hwassist = 0;
4338         if (ifp->if_capenable & IFCAP_TSO)
4339                 ifp->if_hwassist |= CSUM_TSO;
4340         if (ifp->if_capenable & IFCAP_TXCSUM)
4341                 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
4342         if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
4343                 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
4344
4345         /* ifnet sysctl tree */
4346         sysctl_ctx_init(&priv->sysctl_ctx);
4347         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
4348             OID_AUTO, ifp->if_dname, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
4349             "MLX5 ethernet - interface name");
4350         if (priv->sysctl_ifnet == NULL) {
4351                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4352                 goto err_free_sysctl;
4353         }
4354         snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
4355         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4356             OID_AUTO, unit, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
4357             "MLX5 ethernet - interface unit");
4358         if (priv->sysctl_ifnet == NULL) {
4359                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4360                 goto err_free_sysctl;
4361         }
4362
4363         /* HW sysctl tree */
4364         child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
4365         priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
4366             OID_AUTO, "hw", CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
4367             "MLX5 ethernet dev hw");
4368         if (priv->sysctl_hw == NULL) {
4369                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4370                 goto err_free_sysctl;
4371         }
4372
4373         err = mlx5e_build_ifp_priv(mdev, priv, ncv);
4374         if (err) {
4375                 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err);
4376                 goto err_free_sysctl;
4377         }
4378
4379         /* reuse mlx5core's watchdog workqueue */
4380         priv->wq = mdev->priv.health.wq_watchdog;
4381
4382         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
4383         if (err) {
4384                 mlx5_en_err(ifp, "mlx5_alloc_map_uar failed, %d\n", err);
4385                 goto err_free_wq;
4386         }
4387         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
4388         if (err) {
4389                 mlx5_en_err(ifp, "mlx5_core_alloc_pd failed, %d\n", err);
4390                 goto err_unmap_free_uar;
4391         }
4392         err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
4393         if (err) {
4394                 mlx5_en_err(ifp,
4395                     "mlx5_alloc_transport_domain failed, %d\n", err);
4396                 goto err_dealloc_pd;
4397         }
4398         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
4399         if (err) {
4400                 mlx5_en_err(ifp, "mlx5e_create_mkey failed, %d\n", err);
4401                 goto err_dealloc_transport_domain;
4402         }
4403         mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
4404
4405         /* check if we should generate a random MAC address */
4406         if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
4407             is_zero_ether_addr(dev_addr)) {
4408                 random_ether_addr(dev_addr);
4409                 mlx5_en_err(ifp, "Assigned random MAC address\n");
4410         }
4411
4412         err = mlx5e_rl_init(priv);
4413         if (err) {
4414                 mlx5_en_err(ifp, "mlx5e_rl_init failed, %d\n", err);
4415                 goto err_create_mkey;
4416         }
4417
4418         err = mlx5e_tls_init(priv);
4419         if (err) {
4420                 if_printf(ifp, "%s: mlx5e_tls_init failed\n", __func__);
4421                 goto err_rl_init;
4422         }
4423
4424         /* set default MTU */
4425         mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
4426
4427         /* Set default media status */
4428         priv->media_status_last = IFM_AVALID;
4429         priv->media_active_last = IFM_ETHER | IFM_AUTO |
4430             IFM_ETH_RXPAUSE | IFM_FDX;
4431
4432         /* setup default pauseframes configuration */
4433         mlx5e_setup_pauseframes(priv);
4434
4435         /* Setup supported medias */
4436         //TODO: If we failed to query ptys is it ok to proceed??
4437         if (!mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1)) {
4438                 ext = MLX5_CAP_PCAM_FEATURE(mdev,
4439                     ptys_extended_ethernet);
4440                 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
4441                     eth_proto_capability);
4442                 if (MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type))
4443                         connector_type = MLX5_GET(ptys_reg, out,
4444                             connector_type);
4445         } else {
4446                 eth_proto_cap = 0;
4447                 mlx5_en_err(ifp, "Query port media capability failed, %d\n", err);
4448         }
4449
4450         ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
4451             mlx5e_media_change, mlx5e_media_status);
4452
4453         speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER : MLX5E_LINK_SPEEDS_NUMBER;
4454         for (i = 0; i != speeds_num; i++) {
4455                 for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) {
4456                         media_entry = ext ? mlx5e_ext_mode_table[i][j] :
4457                             mlx5e_mode_table[i][j];
4458                         if (media_entry.baudrate == 0)
4459                                 continue;
4460                         if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
4461                                 ifmedia_add(&priv->media,
4462                                     media_entry.subtype |
4463                                     IFM_ETHER, 0, NULL);
4464                                 ifmedia_add(&priv->media,
4465                                     media_entry.subtype |
4466                                     IFM_ETHER | IFM_FDX |
4467                                     IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
4468                         }
4469                 }
4470         }
4471
4472         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
4473         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
4474             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
4475
4476         /* Set autoselect by default */
4477         ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
4478             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
4479
4480         DEBUGNET_SET(ifp, mlx5_en);
4481
4482         ether_ifattach(ifp, dev_addr);
4483
4484         /* Register for VLAN events */
4485         priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
4486             mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
4487         priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
4488             mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
4489
4490         /* Link is down by default */
4491         if_link_state_change(ifp, LINK_STATE_DOWN);
4492
4493         mlx5e_enable_async_events(priv);
4494
4495         mlx5e_add_hw_stats(priv);
4496
4497         mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4498             "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
4499             priv->stats.vport.arg);
4500
4501         mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4502             "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
4503             priv->stats.pport.arg);
4504
4505         mlx5e_create_ethtool(priv);
4506
4507         mtx_lock(&priv->async_events_mtx);
4508         mlx5e_update_stats(priv);
4509         mtx_unlock(&priv->async_events_mtx);
4510
4511         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4512             OID_AUTO, "rx_clbr_done", CTLFLAG_RD,
4513             &priv->clbr_done, 0,
4514             "RX timestamps calibration state");
4515         callout_init(&priv->tstmp_clbr, CALLOUT_DIRECT);
4516         mlx5e_reset_calibration_callout(priv);
4517
4518         pa.pa_version = PFIL_VERSION;
4519         pa.pa_flags = PFIL_IN;
4520         pa.pa_type = PFIL_TYPE_ETHERNET;
4521         pa.pa_headname = ifp->if_xname;
4522         priv->pfil = pfil_head_register(&pa);
4523
4524         return (priv);
4525
4526 err_rl_init:
4527         mlx5e_rl_cleanup(priv);
4528
4529 err_create_mkey:
4530         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
4531
4532 err_dealloc_transport_domain:
4533         mlx5_dealloc_transport_domain(mdev, priv->tdn);
4534
4535 err_dealloc_pd:
4536         mlx5_core_dealloc_pd(mdev, priv->pdn);
4537
4538 err_unmap_free_uar:
4539         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
4540
4541 err_free_wq:
4542         flush_workqueue(priv->wq);
4543
4544 err_free_sysctl:
4545         sysctl_ctx_free(&priv->sysctl_ctx);
4546         if (priv->sysctl_debug)
4547                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4548         mlx5e_priv_static_destroy(priv, mdev->priv.eq_table.num_comp_vectors);
4549         if_free(ifp);
4550
4551 err_free_priv:
4552         free(priv, M_MLX5EN);
4553         return (NULL);
4554 }
4555
4556 static void
4557 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
4558 {
4559         struct mlx5e_priv *priv = vpriv;
4560         struct ifnet *ifp = priv->ifp;
4561
4562         /* don't allow more IOCTLs */
4563         priv->gone = 1;
4564
4565         /* XXX wait a bit to allow IOCTL handlers to complete */
4566         pause("W", hz);
4567
4568 #ifdef RATELIMIT
4569         /*
4570          * The kernel can have reference(s) via the m_snd_tag's into
4571          * the ratelimit channels, and these must go away before
4572          * detaching:
4573          */
4574         while (READ_ONCE(priv->rl.stats.tx_active_connections) != 0) {
4575                 mlx5_en_err(priv->ifp,
4576                     "Waiting for all ratelimit connections to terminate\n");
4577                 pause("W", hz);
4578         }
4579 #endif
4580         /* wait for all unlimited send tags to complete */
4581         mlx5e_priv_wait_for_completion(priv, mdev->priv.eq_table.num_comp_vectors);
4582
4583         /* stop watchdog timer */
4584         callout_drain(&priv->watchdog);
4585
4586         callout_drain(&priv->tstmp_clbr);
4587
4588         if (priv->vlan_attach != NULL)
4589                 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
4590         if (priv->vlan_detach != NULL)
4591                 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
4592
4593         /* make sure device gets closed */
4594         PRIV_LOCK(priv);
4595         mlx5e_close_locked(ifp);
4596         PRIV_UNLOCK(priv);
4597
4598         /* deregister pfil */
4599         if (priv->pfil != NULL) {
4600                 pfil_head_unregister(priv->pfil);
4601                 priv->pfil = NULL;
4602         }
4603
4604         /* unregister device */
4605         ifmedia_removeall(&priv->media);
4606         ether_ifdetach(ifp);
4607
4608         mlx5e_tls_cleanup(priv);
4609         mlx5e_rl_cleanup(priv);
4610
4611         /* destroy all remaining sysctl nodes */
4612         sysctl_ctx_free(&priv->stats.vport.ctx);
4613         sysctl_ctx_free(&priv->stats.pport.ctx);
4614         if (priv->sysctl_debug)
4615                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4616         sysctl_ctx_free(&priv->sysctl_ctx);
4617
4618         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
4619         mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
4620         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
4621         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
4622         mlx5e_disable_async_events(priv);
4623         flush_workqueue(priv->wq);
4624         mlx5e_priv_static_destroy(priv, mdev->priv.eq_table.num_comp_vectors);
4625         if_free(ifp);
4626         free(priv, M_MLX5EN);
4627 }
4628
4629 #ifdef DEBUGNET
4630 static void
4631 mlx5_en_debugnet_init(struct ifnet *dev, int *nrxr, int *ncl, int *clsize)
4632 {
4633         struct mlx5e_priv *priv = if_getsoftc(dev);
4634
4635         PRIV_LOCK(priv);
4636         *nrxr = priv->params.num_channels;
4637         *ncl = DEBUGNET_MAX_IN_FLIGHT;
4638         *clsize = MLX5E_MAX_RX_BYTES;
4639         PRIV_UNLOCK(priv);
4640 }
4641
4642 static void
4643 mlx5_en_debugnet_event(struct ifnet *dev, enum debugnet_ev event)
4644 {
4645 }
4646
4647 static int
4648 mlx5_en_debugnet_transmit(struct ifnet *dev, struct mbuf *m)
4649 {
4650         struct mlx5e_priv *priv = if_getsoftc(dev);
4651         struct mlx5e_sq *sq;
4652         int err;
4653
4654         if ((if_getdrvflags(dev) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
4655             IFF_DRV_RUNNING || (priv->media_status_last & IFM_ACTIVE) == 0)
4656                 return (ENOENT);
4657
4658         sq = &priv->channel[0].sq[0];
4659
4660         if (sq->running == 0) {
4661                 m_freem(m);
4662                 return (ENOENT);
4663         }
4664
4665         if (mlx5e_sq_xmit(sq, &m) != 0) {
4666                 m_freem(m);
4667                 err = ENOBUFS;
4668         } else {
4669                 err = 0;
4670         }
4671
4672         if (likely(sq->doorbell.d64 != 0)) {
4673                 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
4674                 sq->doorbell.d64 = 0;
4675         }
4676         return (err);
4677 }
4678
4679 static int
4680 mlx5_en_debugnet_poll(struct ifnet *dev, int count)
4681 {
4682         struct mlx5e_priv *priv = if_getsoftc(dev);
4683
4684         if ((if_getdrvflags(dev) & IFF_DRV_RUNNING) == 0 ||
4685             (priv->media_status_last & IFM_ACTIVE) == 0)
4686                 return (ENOENT);
4687
4688         mlx5_poll_interrupts(priv->mdev);
4689
4690         return (0);
4691 }
4692 #endif /* DEBUGNET */
4693
4694 static void *
4695 mlx5e_get_ifp(void *vpriv)
4696 {
4697         struct mlx5e_priv *priv = vpriv;
4698
4699         return (priv->ifp);
4700 }
4701
4702 static struct mlx5_interface mlx5e_interface = {
4703         .add = mlx5e_create_ifp,
4704         .remove = mlx5e_destroy_ifp,
4705         .event = mlx5e_async_event,
4706         .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4707         .get_dev = mlx5e_get_ifp,
4708 };
4709
4710 void
4711 mlx5e_init(void)
4712 {
4713         mlx5_register_interface(&mlx5e_interface);
4714 }
4715
4716 void
4717 mlx5e_cleanup(void)
4718 {
4719         mlx5_unregister_interface(&mlx5e_interface);
4720 }
4721
4722 static void
4723 mlx5e_show_version(void __unused *arg)
4724 {
4725
4726         printf("%s", mlx5e_version);
4727 }
4728 SYSINIT(mlx5e_show_version, SI_SUB_DRIVERS, SI_ORDER_ANY, mlx5e_show_version, NULL);
4729
4730 module_init_order(mlx5e_init, SI_ORDER_SIXTH);
4731 module_exit_order(mlx5e_cleanup, SI_ORDER_SIXTH);
4732
4733 #if (__FreeBSD_version >= 1100000)
4734 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
4735 #endif
4736 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
4737 MODULE_VERSION(mlx5en, 1);