sys/dev/mlx5/mlx5_en/mlx5_en_main.c

   1 /*-
   2  * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include "en.h"
  29
  30 #include <sys/sockio.h>
  31 #include <machine/atomic.h>
  32
  33 #define ETH_DRIVER_VERSION      "3.1.0-dev"
  34 char mlx5e_version[] = "Mellanox Ethernet driver"
  35     " (" ETH_DRIVER_VERSION ")";
  36
  37 struct mlx5e_channel_param {
  38         struct mlx5e_rq_param rq;
  39         struct mlx5e_sq_param sq;
  40         struct mlx5e_cq_param rx_cq;
  41         struct mlx5e_cq_param tx_cq;
  42 };
  43
  44 static const struct {
  45         u32     subtype;
  46         u64     baudrate;
  47 }       mlx5e_mode_table[MLX5E_LINK_MODES_NUMBER] = {
  48
  49         [MLX5E_1000BASE_CX_SGMII] = {
  50                 .subtype = IFM_1000_CX_SGMII,
  51                 .baudrate = IF_Mbps(1000ULL),
  52         },
  53         [MLX5E_1000BASE_KX] = {
  54                 .subtype = IFM_1000_KX,
  55                 .baudrate = IF_Mbps(1000ULL),
  56         },
  57         [MLX5E_10GBASE_CX4] = {
  58                 .subtype = IFM_10G_CX4,
  59                 .baudrate = IF_Gbps(10ULL),
  60         },
  61         [MLX5E_10GBASE_KX4] = {
  62                 .subtype = IFM_10G_KX4,
  63                 .baudrate = IF_Gbps(10ULL),
  64         },
  65         [MLX5E_10GBASE_KR] = {
  66                 .subtype = IFM_10G_KR,
  67                 .baudrate = IF_Gbps(10ULL),
  68         },
  69         [MLX5E_20GBASE_KR2] = {
  70                 .subtype = IFM_20G_KR2,
  71                 .baudrate = IF_Gbps(20ULL),
  72         },
  73         [MLX5E_40GBASE_CR4] = {
  74                 .subtype = IFM_40G_CR4,
  75                 .baudrate = IF_Gbps(40ULL),
  76         },
  77         [MLX5E_40GBASE_KR4] = {
  78                 .subtype = IFM_40G_KR4,
  79                 .baudrate = IF_Gbps(40ULL),
  80         },
  81         [MLX5E_56GBASE_R4] = {
  82                 .subtype = IFM_56G_R4,
  83                 .baudrate = IF_Gbps(56ULL),
  84         },
  85         [MLX5E_10GBASE_CR] = {
  86                 .subtype = IFM_10G_CR1,
  87                 .baudrate = IF_Gbps(10ULL),
  88         },
  89         [MLX5E_10GBASE_SR] = {
  90                 .subtype = IFM_10G_SR,
  91                 .baudrate = IF_Gbps(10ULL),
  92         },
  93         [MLX5E_10GBASE_ER] = {
  94                 .subtype = IFM_10G_ER,
  95                 .baudrate = IF_Gbps(10ULL),
  96         },
  97         [MLX5E_40GBASE_SR4] = {
  98                 .subtype = IFM_40G_SR4,
  99                 .baudrate = IF_Gbps(40ULL),
 100         },
 101         [MLX5E_40GBASE_LR4] = {
 102                 .subtype = IFM_40G_LR4,
 103                 .baudrate = IF_Gbps(40ULL),
 104         },
 105         [MLX5E_100GBASE_CR4] = {
 106                 .subtype = IFM_100G_CR4,
 107                 .baudrate = IF_Gbps(100ULL),
 108         },
 109         [MLX5E_100GBASE_SR4] = {
 110                 .subtype = IFM_100G_SR4,
 111                 .baudrate = IF_Gbps(100ULL),
 112         },
 113         [MLX5E_100GBASE_KR4] = {
 114                 .subtype = IFM_100G_KR4,
 115                 .baudrate = IF_Gbps(100ULL),
 116         },
 117         [MLX5E_100GBASE_LR4] = {
 118                 .subtype = IFM_100G_LR4,
 119                 .baudrate = IF_Gbps(100ULL),
 120         },
 121         [MLX5E_100BASE_TX] = {
 122                 .subtype = IFM_100_TX,
 123                 .baudrate = IF_Mbps(100ULL),
 124         },
 125         [MLX5E_1000BASE_T] = {
 126                 .subtype = IFM_1000_T,
 127                 .baudrate = IF_Mbps(1000ULL),
 128         },
 129         [MLX5E_10GBASE_T] = {
 130                 .subtype = IFM_10G_T,
 131                 .baudrate = IF_Gbps(10ULL),
 132         },
 133         [MLX5E_25GBASE_CR] = {
 134                 .subtype = IFM_25G_CR,
 135                 .baudrate = IF_Gbps(25ULL),
 136         },
 137         [MLX5E_25GBASE_KR] = {
 138                 .subtype = IFM_25G_KR,
 139                 .baudrate = IF_Gbps(25ULL),
 140         },
 141         [MLX5E_25GBASE_SR] = {
 142                 .subtype = IFM_25G_SR,
 143                 .baudrate = IF_Gbps(25ULL),
 144         },
 145         [MLX5E_50GBASE_CR2] = {
 146                 .subtype = IFM_50G_CR2,
 147                 .baudrate = IF_Gbps(50ULL),
 148         },
 149         [MLX5E_50GBASE_KR2] = {
 150                 .subtype = IFM_50G_KR2,
 151                 .baudrate = IF_Gbps(50ULL),
 152         },
 153 };
 154
 155 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
 156
 157 static SYSCTL_NODE(_hw, OID_AUTO, mlx5, CTLFLAG_RW, 0, "MLX5 driver parameters");
 158
 159 static void
 160 mlx5e_update_carrier(struct mlx5e_priv *priv)
 161 {
 162         struct mlx5_core_dev *mdev = priv->mdev;
 163         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 164         u32 eth_proto_oper;
 165         int error;
 166         u8 port_state;
 167         u8 i;
 168
 169         port_state = mlx5_query_vport_state(mdev,
 170             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 171
 172         if (port_state == VPORT_STATE_UP) {
 173                 priv->media_status_last |= IFM_ACTIVE;
 174         } else {
 175                 priv->media_status_last &= ~IFM_ACTIVE;
 176                 priv->media_active_last = IFM_ETHER;
 177                 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
 178                 return;
 179         }
 180
 181         error = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
 182         if (error) {
 183                 priv->media_active_last = IFM_ETHER;
 184                 priv->ifp->if_baudrate = 1;
 185                 if_printf(priv->ifp, "%s: query port ptys failed: 0x%x\n",
 186                     __func__, error);
 187                 return;
 188         }
 189         eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
 190
 191         for (i = 0; i != MLX5E_LINK_MODES_NUMBER; i++) {
 192                 if (mlx5e_mode_table[i].baudrate == 0)
 193                         continue;
 194                 if (MLX5E_PROT_MASK(i) & eth_proto_oper) {
 195                         priv->ifp->if_baudrate =
 196                             mlx5e_mode_table[i].baudrate;
 197                         priv->media_active_last =
 198                             mlx5e_mode_table[i].subtype | IFM_ETHER | IFM_FDX;
 199                 }
 200         }
 201         if_link_state_change(priv->ifp, LINK_STATE_UP);
 202 }
 203
 204 static void
 205 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
 206 {
 207         struct mlx5e_priv *priv = dev->if_softc;
 208
 209         ifmr->ifm_status = priv->media_status_last;
 210         ifmr->ifm_active = priv->media_active_last |
 211             (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
 212             (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
 213
 214 }
 215
 216 static u32
 217 mlx5e_find_link_mode(u32 subtype)
 218 {
 219         u32 i;
 220         u32 link_mode = 0;
 221
 222         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
 223                 if (mlx5e_mode_table[i].baudrate == 0)
 224                         continue;
 225                 if (mlx5e_mode_table[i].subtype == subtype)
 226                         link_mode |= MLX5E_PROT_MASK(i);
 227         }
 228
 229         return (link_mode);
 230 }
 231
 232 static int
 233 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv)
 234 {
 235         return (mlx5_set_port_pause_and_pfc(priv->mdev, 1,
 236             priv->params.rx_pauseframe_control,
 237             priv->params.tx_pauseframe_control,
 238             priv->params.rx_priority_flow_control,
 239             priv->params.tx_priority_flow_control));
 240 }
 241
 242 static int
 243 mlx5e_set_port_pfc(struct mlx5e_priv *priv)
 244 {
 245         int error;
 246
 247         if (priv->params.rx_pauseframe_control ||
 248             priv->params.tx_pauseframe_control) {
 249                 if_printf(priv->ifp,
 250                     "Global pauseframes must be disabled before enabling PFC.\n");
 251                 error = -EINVAL;
 252         } else {
 253                 error = mlx5e_set_port_pause_and_pfc(priv);
 254         }
 255         return (error);
 256 }
 257
 258 static int
 259 mlx5e_media_change(struct ifnet *dev)
 260 {
 261         struct mlx5e_priv *priv = dev->if_softc;
 262         struct mlx5_core_dev *mdev = priv->mdev;
 263         u32 eth_proto_cap;
 264         u32 link_mode;
 265         int was_opened;
 266         int locked;
 267         int error;
 268
 269         locked = PRIV_LOCKED(priv);
 270         if (!locked)
 271                 PRIV_LOCK(priv);
 272
 273         if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
 274                 error = EINVAL;
 275                 goto done;
 276         }
 277         link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media));
 278
 279         /* query supported capabilities */
 280         error = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
 281         if (error != 0) {
 282                 if_printf(dev, "Query port media capability failed\n");
 283                 goto done;
 284         }
 285         /* check for autoselect */
 286         if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
 287                 link_mode = eth_proto_cap;
 288                 if (link_mode == 0) {
 289                         if_printf(dev, "Port media capability is zero\n");
 290                         error = EINVAL;
 291                         goto done;
 292                 }
 293         } else {
 294                 link_mode = link_mode & eth_proto_cap;
 295                 if (link_mode == 0) {
 296                         if_printf(dev, "Not supported link mode requested\n");
 297                         error = EINVAL;
 298                         goto done;
 299                 }
 300         }
 301         if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
 302                 /* check if PFC is enabled */
 303                 if (priv->params.rx_priority_flow_control ||
 304                     priv->params.tx_priority_flow_control) {
 305                         if_printf(dev, "PFC must be disabled before enabling global pauseframes.\n");
 306                         error = EINVAL;
 307                         goto done;
 308                 }
 309         }
 310         /* update pauseframe control bits */
 311         priv->params.rx_pauseframe_control =
 312             (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
 313         priv->params.tx_pauseframe_control =
 314             (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
 315
 316         /* check if device is opened */
 317         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
 318
 319         /* reconfigure the hardware */
 320         mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
 321         mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN);
 322         error = -mlx5e_set_port_pause_and_pfc(priv);
 323         if (was_opened)
 324                 mlx5_set_port_status(mdev, MLX5_PORT_UP);
 325
 326 done:
 327         if (!locked)
 328                 PRIV_UNLOCK(priv);
 329         return (error);
 330 }
 331
 332 static void
 333 mlx5e_update_carrier_work(struct work_struct *work)
 334 {
 335         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 336             update_carrier_work);
 337
 338         PRIV_LOCK(priv);
 339         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 340                 mlx5e_update_carrier(priv);
 341         PRIV_UNLOCK(priv);
 342 }
 343
 344 /*
 345  * This function reads the physical port counters from the firmware
 346  * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
 347  * macros. The output is converted from big-endian 64-bit values into
 348  * host endian ones and stored in the "priv->stats.pport" structure.
 349  */
 350 static void
 351 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 352 {
 353         struct mlx5_core_dev *mdev = priv->mdev;
 354         struct mlx5e_pport_stats *s = &priv->stats.pport;
 355         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 356         u32 *in;
 357         u32 *out;
 358         const u64 *ptr;
 359         unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 360         unsigned x;
 361         unsigned y;
 362         unsigned z;
 363
 364         /* allocate firmware request structures */
 365         in = mlx5_vzalloc(sz);
 366         out = mlx5_vzalloc(sz);
 367         if (in == NULL || out == NULL)
 368                 goto free_out;
 369
 370         /*
 371          * Get pointer to the 64-bit counter set which is located at a
 372          * fixed offset in the output firmware request structure:
 373          */
 374         ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
 375
 376         MLX5_SET(ppcnt_reg, in, local_port, 1);
 377
 378         /* read IEEE802_3 counter group using predefined counter layout */
 379         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 380         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 381         for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM;
 382              x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
 383                 s->arg[y] = be64toh(ptr[x]);
 384
 385         /* read RFC2819 counter group using predefined counter layout */
 386         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 387         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 388         for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
 389                 s->arg[y] = be64toh(ptr[x]);
 390         for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
 391             MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
 392                 s_debug->arg[y] = be64toh(ptr[x]);
 393
 394         /* read RFC2863 counter group using predefined counter layout */
 395         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 396         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 397         for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
 398                 s_debug->arg[y] = be64toh(ptr[x]);
 399
 400         /* read physical layer stats counter group using predefined counter layout */
 401         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 402         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 403         for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
 404                 s_debug->arg[y] = be64toh(ptr[x]);
 405
 406         /* read per-priority counters */
 407         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 408
 409         /* iterate all the priorities */
 410         for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) {
 411                 MLX5_SET(ppcnt_reg, in, prio_tc, z);
 412                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 413
 414                 /* read per priority stats counter group using predefined counter layout */
 415                 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM /
 416                     MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++)
 417                         s->arg[y] = be64toh(ptr[x]);
 418         }
 419 free_out:
 420         /* free firmware request structures */
 421         kvfree(in);
 422         kvfree(out);
 423 }
 424
 425 /*
 426  * This function is called regularly to collect all statistics
 427  * counters from the firmware. The values can be viewed through the
 428  * sysctl interface. Execution is serialized using the priv's global
 429  * configuration lock.
 430  */
 431 static void
 432 mlx5e_update_stats_work(struct work_struct *work)
 433 {
 434         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 435             update_stats_work);
 436         struct mlx5_core_dev *mdev = priv->mdev;
 437         struct mlx5e_vport_stats *s = &priv->stats.vport;
 438         struct mlx5e_rq_stats *rq_stats;
 439         struct mlx5e_sq_stats *sq_stats;
 440         struct buf_ring *sq_br;
 441 #if (__FreeBSD_version < 1100000)
 442         struct ifnet *ifp = priv->ifp;
 443 #endif
 444
 445         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 446         u32 *out;
 447         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 448         u64 tso_packets = 0;
 449         u64 tso_bytes = 0;
 450         u64 tx_queue_dropped = 0;
 451         u64 tx_defragged = 0;
 452         u64 tx_offload_none = 0;
 453         u64 lro_packets = 0;
 454         u64 lro_bytes = 0;
 455         u64 sw_lro_queued = 0;
 456         u64 sw_lro_flushed = 0;
 457         u64 rx_csum_none = 0;
 458         u64 rx_wqe_err = 0;
 459         u32 rx_out_of_buffer = 0;
 460         int i;
 461         int j;
 462
 463         PRIV_LOCK(priv);
 464         out = mlx5_vzalloc(outlen);
 465         if (out == NULL)
 466                 goto free_out;
 467         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
 468                 goto free_out;
 469
 470         /* Collect firts the SW counters and then HW for consistency */
 471         for (i = 0; i < priv->params.num_channels; i++) {
 472                 struct mlx5e_rq *rq = &priv->channel[i]->rq;
 473
 474                 rq_stats = &priv->channel[i]->rq.stats;
 475
 476                 /* collect stats from LRO */
 477                 rq_stats->sw_lro_queued = rq->lro.lro_queued;
 478                 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
 479                 sw_lro_queued += rq_stats->sw_lro_queued;
 480                 sw_lro_flushed += rq_stats->sw_lro_flushed;
 481                 lro_packets += rq_stats->lro_packets;
 482                 lro_bytes += rq_stats->lro_bytes;
 483                 rx_csum_none += rq_stats->csum_none;
 484                 rx_wqe_err += rq_stats->wqe_err;
 485
 486                 for (j = 0; j < priv->num_tc; j++) {
 487                         sq_stats = &priv->channel[i]->sq[j].stats;
 488                         sq_br = priv->channel[i]->sq[j].br;
 489
 490                         tso_packets += sq_stats->tso_packets;
 491                         tso_bytes += sq_stats->tso_bytes;
 492                         tx_queue_dropped += sq_stats->dropped;
 493                         if (sq_br != NULL)
 494                                 tx_queue_dropped += sq_br->br_drops;
 495                         tx_defragged += sq_stats->defragged;
 496                         tx_offload_none += sq_stats->csum_offload_none;
 497                 }
 498         }
 499
 500         /* update counters */
 501         s->tso_packets = tso_packets;
 502         s->tso_bytes = tso_bytes;
 503         s->tx_queue_dropped = tx_queue_dropped;
 504         s->tx_defragged = tx_defragged;
 505         s->lro_packets = lro_packets;
 506         s->lro_bytes = lro_bytes;
 507         s->sw_lro_queued = sw_lro_queued;
 508         s->sw_lro_flushed = sw_lro_flushed;
 509         s->rx_csum_none = rx_csum_none;
 510         s->rx_wqe_err = rx_wqe_err;
 511
 512         /* HW counters */
 513         memset(in, 0, sizeof(in));
 514
 515         MLX5_SET(query_vport_counter_in, in, opcode,
 516             MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 517         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 518         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 519
 520         memset(out, 0, outlen);
 521
 522         /* get number of out-of-buffer drops first */
 523         if (mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
 524             &rx_out_of_buffer))
 525                 goto free_out;
 526
 527         /* accumulate difference into a 64-bit counter */
 528         s->rx_out_of_buffer += (u64)(u32)(rx_out_of_buffer - s->rx_out_of_buffer_prev);
 529         s->rx_out_of_buffer_prev = rx_out_of_buffer;
 530
 531         /* get port statistics */
 532         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
 533                 goto free_out;
 534
 535 #define MLX5_GET_CTR(out, x) \
 536         MLX5_GET64(query_vport_counter_out, out, x)
 537
 538         s->rx_error_packets =
 539             MLX5_GET_CTR(out, received_errors.packets);
 540         s->rx_error_bytes =
 541             MLX5_GET_CTR(out, received_errors.octets);
 542         s->tx_error_packets =
 543             MLX5_GET_CTR(out, transmit_errors.packets);
 544         s->tx_error_bytes =
 545             MLX5_GET_CTR(out, transmit_errors.octets);
 546
 547         s->rx_unicast_packets =
 548             MLX5_GET_CTR(out, received_eth_unicast.packets);
 549         s->rx_unicast_bytes =
 550             MLX5_GET_CTR(out, received_eth_unicast.octets);
 551         s->tx_unicast_packets =
 552             MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 553         s->tx_unicast_bytes =
 554             MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 555
 556         s->rx_multicast_packets =
 557             MLX5_GET_CTR(out, received_eth_multicast.packets);
 558         s->rx_multicast_bytes =
 559             MLX5_GET_CTR(out, received_eth_multicast.octets);
 560         s->tx_multicast_packets =
 561             MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 562         s->tx_multicast_bytes =
 563             MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 564
 565         s->rx_broadcast_packets =
 566             MLX5_GET_CTR(out, received_eth_broadcast.packets);
 567         s->rx_broadcast_bytes =
 568             MLX5_GET_CTR(out, received_eth_broadcast.octets);
 569         s->tx_broadcast_packets =
 570             MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 571         s->tx_broadcast_bytes =
 572             MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 573
 574         s->rx_packets =
 575             s->rx_unicast_packets +
 576             s->rx_multicast_packets +
 577             s->rx_broadcast_packets -
 578             s->rx_out_of_buffer;
 579         s->rx_bytes =
 580             s->rx_unicast_bytes +
 581             s->rx_multicast_bytes +
 582             s->rx_broadcast_bytes;
 583         s->tx_packets =
 584             s->tx_unicast_packets +
 585             s->tx_multicast_packets +
 586             s->tx_broadcast_packets;
 587         s->tx_bytes =
 588             s->tx_unicast_bytes +
 589             s->tx_multicast_bytes +
 590             s->tx_broadcast_bytes;
 591
 592         /* Update calculated offload counters */
 593         s->tx_csum_offload = s->tx_packets - tx_offload_none;
 594         s->rx_csum_good = s->rx_packets - s->rx_csum_none;
 595
 596         /* Get physical port counters */
 597         mlx5e_update_pport_counters(priv);
 598
 599 #if (__FreeBSD_version < 1100000)
 600         /* no get_counters interface in fbsd 10 */
 601         ifp->if_ipackets = s->rx_packets;
 602         ifp->if_ierrors = s->rx_error_packets +
 603             priv->stats.pport.alignment_err +
 604             priv->stats.pport.check_seq_err +
 605             priv->stats.pport.crc_align_errors +
 606             priv->stats.pport.in_range_len_errors +
 607             priv->stats.pport.jabbers +
 608             priv->stats.pport.out_of_range_len +
 609             priv->stats.pport.oversize_pkts +
 610             priv->stats.pport.symbol_err +
 611             priv->stats.pport.too_long_errors +
 612             priv->stats.pport.undersize_pkts +
 613             priv->stats.pport.unsupported_op_rx;
 614         ifp->if_iqdrops = s->rx_out_of_buffer +
 615             priv->stats.pport.drop_events;
 616         ifp->if_opackets = s->tx_packets;
 617         ifp->if_oerrors = s->tx_error_packets;
 618         ifp->if_snd.ifq_drops = s->tx_queue_dropped;
 619         ifp->if_ibytes = s->rx_bytes;
 620         ifp->if_obytes = s->tx_bytes;
 621         ifp->if_collisions =
 622             priv->stats.pport.collisions;
 623 #endif
 624
 625 free_out:
 626         kvfree(out);
 627
 628         /* Update diagnostics, if any */
 629         if (priv->params_ethtool.diag_pci_enable ||
 630             priv->params_ethtool.diag_general_enable) {
 631                 int error = mlx5_core_get_diagnostics_full(mdev,
 632                     priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL,
 633                     priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL);
 634                 if (error != 0)
 635                         if_printf(priv->ifp, "Failed reading diagnostics: %d\n", error);
 636         }
 637         PRIV_UNLOCK(priv);
 638 }
 639
 640 static void
 641 mlx5e_update_stats(void *arg)
 642 {
 643         struct mlx5e_priv *priv = arg;
 644
 645         queue_work(priv->wq, &priv->update_stats_work);
 646
 647         callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
 648 }
 649
 650 static void
 651 mlx5e_async_event_sub(struct mlx5e_priv *priv,
 652     enum mlx5_dev_event event)
 653 {
 654         switch (event) {
 655         case MLX5_DEV_EVENT_PORT_UP:
 656         case MLX5_DEV_EVENT_PORT_DOWN:
 657                 queue_work(priv->wq, &priv->update_carrier_work);
 658                 break;
 659
 660         default:
 661                 break;
 662         }
 663 }
 664
 665 static void
 666 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 667     enum mlx5_dev_event event, unsigned long param)
 668 {
 669         struct mlx5e_priv *priv = vpriv;
 670
 671         mtx_lock(&priv->async_events_mtx);
 672         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 673                 mlx5e_async_event_sub(priv, event);
 674         mtx_unlock(&priv->async_events_mtx);
 675 }
 676
 677 static void
 678 mlx5e_enable_async_events(struct mlx5e_priv *priv)
 679 {
 680         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 681 }
 682
 683 static void
 684 mlx5e_disable_async_events(struct mlx5e_priv *priv)
 685 {
 686         mtx_lock(&priv->async_events_mtx);
 687         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 688         mtx_unlock(&priv->async_events_mtx);
 689 }
 690
 691 static void mlx5e_calibration_callout(void *arg);
 692 static int mlx5e_calibration_duration = 20;
 693 static int mlx5e_fast_calibration = 1;
 694 static int mlx5e_normal_calibration = 30;
 695
 696 static SYSCTL_NODE(_hw_mlx5, OID_AUTO, calibr, CTLFLAG_RW, 0,
 697     "MLX5 timestamp calibration parameteres");
 698
 699 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, duration, CTLFLAG_RWTUN,
 700     &mlx5e_calibration_duration, 0,
 701     "Duration of initial calibration");
 702 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, fast, CTLFLAG_RWTUN,
 703     &mlx5e_fast_calibration, 0,
 704     "Recalibration interval during initial calibration");
 705 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, normal, CTLFLAG_RWTUN,
 706     &mlx5e_normal_calibration, 0,
 707     "Recalibration interval during normal operations");
 708
 709 /*
 710  * Ignites the calibration process.
 711  */
 712 static void
 713 mlx5e_reset_calibration_callout(struct mlx5e_priv *priv)
 714 {
 715
 716         if (priv->clbr_done == 0)
 717                 mlx5e_calibration_callout(priv);
 718         else
 719                 callout_reset_curcpu(&priv->tstmp_clbr, (priv->clbr_done <
 720                     mlx5e_calibration_duration ? mlx5e_fast_calibration :
 721                     mlx5e_normal_calibration) * hz, mlx5e_calibration_callout,
 722                     priv);
 723 }
 724
 725 static uint64_t
 726 mlx5e_timespec2usec(const struct timespec *ts)
 727 {
 728
 729         return ((uint64_t)ts->tv_sec * 1000000000 + ts->tv_nsec);
 730 }
 731
 732 static uint64_t
 733 mlx5e_hw_clock(struct mlx5e_priv *priv)
 734 {
 735         struct mlx5_init_seg *iseg;
 736         uint32_t hw_h, hw_h1, hw_l;
 737
 738         iseg = priv->mdev->iseg;
 739         do {
 740                 hw_h = ioread32be(&iseg->internal_timer_h);
 741                 hw_l = ioread32be(&iseg->internal_timer_l);
 742                 hw_h1 = ioread32be(&iseg->internal_timer_h);
 743         } while (hw_h1 != hw_h);
 744         return (((uint64_t)hw_h << 32) | hw_l);
 745 }
 746
 747 /*
 748  * The calibration callout, it runs either in the context of the
 749  * thread which enables calibration, or in callout.  It takes the
 750  * snapshot of system and adapter clocks, then advances the pointers to
 751  * the calibration point to allow rx path to read the consistent data
 752  * lockless.
 753  */
 754 static void
 755 mlx5e_calibration_callout(void *arg)
 756 {
 757         struct mlx5e_priv *priv;
 758         struct mlx5e_clbr_point *next, *curr;
 759         struct timespec ts;
 760         int clbr_curr_next;
 761
 762         priv = arg;
 763         curr = &priv->clbr_points[priv->clbr_curr];
 764         clbr_curr_next = priv->clbr_curr + 1;
 765         if (clbr_curr_next >= nitems(priv->clbr_points))
 766                 clbr_curr_next = 0;
 767         next = &priv->clbr_points[clbr_curr_next];
 768
 769         next->base_prev = curr->base_curr;
 770         next->clbr_hw_prev = curr->clbr_hw_curr;
 771
 772         next->clbr_hw_curr = mlx5e_hw_clock(priv);
 773         if (((next->clbr_hw_curr - curr->clbr_hw_prev) >> MLX5E_TSTMP_PREC) ==
 774             0) {
 775                 if_printf(priv->ifp, "HW failed tstmp frozen %#jx %#jx,"
 776                     "disabling\n", next->clbr_hw_curr, curr->clbr_hw_prev);
 777                 priv->clbr_done = 0;
 778                 return;
 779         }
 780
 781         nanouptime(&ts);
 782         next->base_curr = mlx5e_timespec2usec(&ts);
 783
 784         curr->clbr_gen = 0;
 785         atomic_thread_fence_rel();
 786         priv->clbr_curr = clbr_curr_next;
 787         atomic_store_rel_int(&next->clbr_gen, ++(priv->clbr_gen));
 788
 789         if (priv->clbr_done < mlx5e_calibration_duration)
 790                 priv->clbr_done++;
 791         mlx5e_reset_calibration_callout(priv);
 792 }
 793
 794 static const char *mlx5e_rq_stats_desc[] = {
 795         MLX5E_RQ_STATS(MLX5E_STATS_DESC)
 796 };
 797
 798 static int
 799 mlx5e_create_rq(struct mlx5e_channel *c,
 800     struct mlx5e_rq_param *param,
 801     struct mlx5e_rq *rq)
 802 {
 803         struct mlx5e_priv *priv = c->priv;
 804         struct mlx5_core_dev *mdev = priv->mdev;
 805         char buffer[16];
 806         void *rqc = param->rqc;
 807         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 808         int wq_sz;
 809         int err;
 810         int i;
 811
 812         /* Create DMA descriptor TAG */
 813         if ((err = -bus_dma_tag_create(
 814             bus_get_dma_tag(mdev->pdev->dev.bsddev),
 815             1,                          /* any alignment */
 816             0,                          /* no boundary */
 817             BUS_SPACE_MAXADDR,          /* lowaddr */
 818             BUS_SPACE_MAXADDR,          /* highaddr */
 819             NULL, NULL,                 /* filter, filterarg */
 820             MJUM16BYTES,                /* maxsize */
 821             1,                          /* nsegments */
 822             MJUM16BYTES,                /* maxsegsize */
 823             0,                          /* flags */
 824             NULL, NULL,                 /* lockfunc, lockfuncarg */
 825             &rq->dma_tag)))
 826                 goto done;
 827
 828         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 829             &rq->wq_ctrl);
 830         if (err)
 831                 goto err_free_dma_tag;
 832
 833         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 834
 835         if (priv->params.hw_lro_en) {
 836                 rq->wqe_sz = priv->params.lro_wqe_sz;
 837         } else {
 838                 rq->wqe_sz = MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
 839         }
 840         if (rq->wqe_sz > MJUM16BYTES) {
 841                 err = -ENOMEM;
 842                 goto err_rq_wq_destroy;
 843         } else if (rq->wqe_sz > MJUM9BYTES) {
 844                 rq->wqe_sz = MJUM16BYTES;
 845         } else if (rq->wqe_sz > MJUMPAGESIZE) {
 846                 rq->wqe_sz = MJUM9BYTES;
 847         } else if (rq->wqe_sz > MCLBYTES) {
 848                 rq->wqe_sz = MJUMPAGESIZE;
 849         } else {
 850                 rq->wqe_sz = MCLBYTES;
 851         }
 852
 853         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 854
 855         err = -tcp_lro_init_args(&rq->lro, c->ifp, TCP_LRO_ENTRIES, wq_sz);
 856         if (err)
 857                 goto err_rq_wq_destroy;
 858
 859         rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
 860         for (i = 0; i != wq_sz; i++) {
 861                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 862                 uint32_t byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 863
 864                 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
 865                 if (err != 0) {
 866                         while (i--)
 867                                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 868                         goto err_rq_mbuf_free;
 869                 }
 870                 wqe->data.lkey = c->mkey_be;
 871                 wqe->data.byte_count = cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
 872         }
 873
 874         rq->ifp = c->ifp;
 875         rq->channel = c;
 876         rq->ix = c->ix;
 877
 878         snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
 879         mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
 880             buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
 881             rq->stats.arg);
 882         return (0);
 883
 884 err_rq_mbuf_free:
 885         free(rq->mbuf, M_MLX5EN);
 886         tcp_lro_free(&rq->lro);
 887 err_rq_wq_destroy:
 888         mlx5_wq_destroy(&rq->wq_ctrl);
 889 err_free_dma_tag:
 890         bus_dma_tag_destroy(rq->dma_tag);
 891 done:
 892         return (err);
 893 }
 894
 895 static void
 896 mlx5e_destroy_rq(struct mlx5e_rq *rq)
 897 {
 898         int wq_sz;
 899         int i;
 900
 901         /* destroy all sysctl nodes */
 902         sysctl_ctx_free(&rq->stats.ctx);
 903
 904         /* free leftover LRO packets, if any */
 905         tcp_lro_free(&rq->lro);
 906
 907         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 908         for (i = 0; i != wq_sz; i++) {
 909                 if (rq->mbuf[i].mbuf != NULL) {
 910                         bus_dmamap_unload(rq->dma_tag,
 911                             rq->mbuf[i].dma_map);
 912                         m_freem(rq->mbuf[i].mbuf);
 913                 }
 914                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 915         }
 916         free(rq->mbuf, M_MLX5EN);
 917         mlx5_wq_destroy(&rq->wq_ctrl);
 918 }
 919
 920 static int
 921 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 922 {
 923         struct mlx5e_channel *c = rq->channel;
 924         struct mlx5e_priv *priv = c->priv;
 925         struct mlx5_core_dev *mdev = priv->mdev;
 926
 927         void *in;
 928         void *rqc;
 929         void *wq;
 930         int inlen;
 931         int err;
 932
 933         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 934             sizeof(u64) * rq->wq_ctrl.buf.npages;
 935         in = mlx5_vzalloc(inlen);
 936         if (in == NULL)
 937                 return (-ENOMEM);
 938
 939         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 940         wq = MLX5_ADDR_OF(rqc, rqc, wq);
 941
 942         memcpy(rqc, param->rqc, sizeof(param->rqc));
 943
 944         MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
 945         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
 946         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
 947         if (priv->counter_set_id >= 0)
 948                 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
 949         MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
 950             PAGE_SHIFT);
 951         MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
 952
 953         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 954             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
 955
 956         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 957
 958         kvfree(in);
 959
 960         return (err);
 961 }
 962
 963 static int
 964 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
 965 {
 966         struct mlx5e_channel *c = rq->channel;
 967         struct mlx5e_priv *priv = c->priv;
 968         struct mlx5_core_dev *mdev = priv->mdev;
 969
 970         void *in;
 971         void *rqc;
 972         int inlen;
 973         int err;
 974
 975         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 976         in = mlx5_vzalloc(inlen);
 977         if (in == NULL)
 978                 return (-ENOMEM);
 979
 980         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 981
 982         MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
 983         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 984         MLX5_SET(rqc, rqc, state, next_state);
 985
 986         err = mlx5_core_modify_rq(mdev, in, inlen);
 987
 988         kvfree(in);
 989
 990         return (err);
 991 }
 992
 993 static void
 994 mlx5e_disable_rq(struct mlx5e_rq *rq)
 995 {
 996         struct mlx5e_channel *c = rq->channel;
 997         struct mlx5e_priv *priv = c->priv;
 998         struct mlx5_core_dev *mdev = priv->mdev;
 999
1000         mlx5_core_destroy_rq(mdev, rq->rqn);
1001 }
1002
1003 static int
1004 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
1005 {
1006         struct mlx5e_channel *c = rq->channel;
1007         struct mlx5e_priv *priv = c->priv;
1008         struct mlx5_wq_ll *wq = &rq->wq;
1009         int i;
1010
1011         for (i = 0; i < 1000; i++) {
1012                 if (wq->cur_sz >= priv->params.min_rx_wqes)
1013                         return (0);
1014
1015                 msleep(4);
1016         }
1017         return (-ETIMEDOUT);
1018 }
1019
1020 static int
1021 mlx5e_open_rq(struct mlx5e_channel *c,
1022     struct mlx5e_rq_param *param,
1023     struct mlx5e_rq *rq)
1024 {
1025         int err;
1026
1027         err = mlx5e_create_rq(c, param, rq);
1028         if (err)
1029                 return (err);
1030
1031         err = mlx5e_enable_rq(rq, param);
1032         if (err)
1033                 goto err_destroy_rq;
1034
1035         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1036         if (err)
1037                 goto err_disable_rq;
1038
1039         c->rq.enabled = 1;
1040
1041         return (0);
1042
1043 err_disable_rq:
1044         mlx5e_disable_rq(rq);
1045 err_destroy_rq:
1046         mlx5e_destroy_rq(rq);
1047
1048         return (err);
1049 }
1050
1051 static void
1052 mlx5e_close_rq(struct mlx5e_rq *rq)
1053 {
1054         mtx_lock(&rq->mtx);
1055         rq->enabled = 0;
1056         callout_stop(&rq->watchdog);
1057         mtx_unlock(&rq->mtx);
1058
1059         callout_drain(&rq->watchdog);
1060
1061         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
1062 }
1063
1064 static void
1065 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
1066 {
1067         /* wait till RQ is empty */
1068         while (!mlx5_wq_ll_is_empty(&rq->wq)) {
1069                 msleep(4);
1070                 rq->cq.mcq.comp(&rq->cq.mcq);
1071         }
1072
1073         mlx5e_disable_rq(rq);
1074         mlx5e_destroy_rq(rq);
1075 }
1076
1077 void
1078 mlx5e_free_sq_db(struct mlx5e_sq *sq)
1079 {
1080         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1081         int x;
1082
1083         for (x = 0; x != wq_sz; x++)
1084                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1085         free(sq->mbuf, M_MLX5EN);
1086 }
1087
1088 int
1089 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
1090 {
1091         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1092         int err;
1093         int x;
1094
1095         sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1096
1097         /* Create DMA descriptor MAPs */
1098         for (x = 0; x != wq_sz; x++) {
1099                 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
1100                 if (err != 0) {
1101                         while (x--)
1102                                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1103                         free(sq->mbuf, M_MLX5EN);
1104                         return (err);
1105                 }
1106         }
1107         return (0);
1108 }
1109
1110 static const char *mlx5e_sq_stats_desc[] = {
1111         MLX5E_SQ_STATS(MLX5E_STATS_DESC)
1112 };
1113
1114 static int
1115 mlx5e_create_sq(struct mlx5e_channel *c,
1116     int tc,
1117     struct mlx5e_sq_param *param,
1118     struct mlx5e_sq *sq)
1119 {
1120         struct mlx5e_priv *priv = c->priv;
1121         struct mlx5_core_dev *mdev = priv->mdev;
1122         char buffer[16];
1123
1124         void *sqc = param->sqc;
1125         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1126 #ifdef RSS
1127         cpuset_t cpu_mask;
1128         int cpu_id;
1129 #endif
1130         int err;
1131
1132         /* Create DMA descriptor TAG */
1133         if ((err = -bus_dma_tag_create(
1134             bus_get_dma_tag(mdev->pdev->dev.bsddev),
1135             1,                          /* any alignment */
1136             0,                          /* no boundary */
1137             BUS_SPACE_MAXADDR,          /* lowaddr */
1138             BUS_SPACE_MAXADDR,          /* highaddr */
1139             NULL, NULL,                 /* filter, filterarg */
1140             MLX5E_MAX_TX_PAYLOAD_SIZE,  /* maxsize */
1141             MLX5E_MAX_TX_MBUF_FRAGS,    /* nsegments */
1142             MLX5E_MAX_TX_MBUF_SIZE,     /* maxsegsize */
1143             0,                          /* flags */
1144             NULL, NULL,                 /* lockfunc, lockfuncarg */
1145             &sq->dma_tag)))
1146                 goto done;
1147
1148         err = mlx5_alloc_map_uar(mdev, &sq->uar);
1149         if (err)
1150                 goto err_free_dma_tag;
1151
1152         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
1153             &sq->wq_ctrl);
1154         if (err)
1155                 goto err_unmap_free_uar;
1156
1157         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1158         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1159
1160         err = mlx5e_alloc_sq_db(sq);
1161         if (err)
1162                 goto err_sq_wq_destroy;
1163
1164         sq->mkey_be = c->mkey_be;
1165         sq->ifp = priv->ifp;
1166         sq->priv = priv;
1167         sq->tc = tc;
1168
1169         /* check if we should allocate a second packet buffer */
1170         if (priv->params_ethtool.tx_bufring_disable == 0) {
1171                 sq->br = buf_ring_alloc(MLX5E_SQ_TX_QUEUE_SIZE, M_MLX5EN,
1172                     M_WAITOK, &sq->lock);
1173                 if (sq->br == NULL) {
1174                         if_printf(c->ifp, "%s: Failed allocating sq drbr buffer\n",
1175                             __func__);
1176                         err = -ENOMEM;
1177                         goto err_free_sq_db;
1178                 }
1179
1180                 sq->sq_tq = taskqueue_create_fast("mlx5e_que", M_WAITOK,
1181                     taskqueue_thread_enqueue, &sq->sq_tq);
1182                 if (sq->sq_tq == NULL) {
1183                         if_printf(c->ifp, "%s: Failed allocating taskqueue\n",
1184                             __func__);
1185                         err = -ENOMEM;
1186                         goto err_free_drbr;
1187                 }
1188
1189                 TASK_INIT(&sq->sq_task, 0, mlx5e_tx_que, sq);
1190 #ifdef RSS
1191                 cpu_id = rss_getcpu(c->ix % rss_getnumbuckets());
1192                 CPU_SETOF(cpu_id, &cpu_mask);
1193                 taskqueue_start_threads_cpuset(&sq->sq_tq, 1, PI_NET, &cpu_mask,
1194                     "%s TX SQ%d.%d CPU%d", c->ifp->if_xname, c->ix, tc, cpu_id);
1195 #else
1196                 taskqueue_start_threads(&sq->sq_tq, 1, PI_NET,
1197                     "%s TX SQ%d.%d", c->ifp->if_xname, c->ix, tc);
1198 #endif
1199         }
1200         snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1201         mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1202             buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1203             sq->stats.arg);
1204
1205         return (0);
1206
1207 err_free_drbr:
1208         buf_ring_free(sq->br, M_MLX5EN);
1209 err_free_sq_db:
1210         mlx5e_free_sq_db(sq);
1211 err_sq_wq_destroy:
1212         mlx5_wq_destroy(&sq->wq_ctrl);
1213
1214 err_unmap_free_uar:
1215         mlx5_unmap_free_uar(mdev, &sq->uar);
1216
1217 err_free_dma_tag:
1218         bus_dma_tag_destroy(sq->dma_tag);
1219 done:
1220         return (err);
1221 }
1222
1223 static void
1224 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1225 {
1226         /* destroy all sysctl nodes */
1227         sysctl_ctx_free(&sq->stats.ctx);
1228
1229         mlx5e_free_sq_db(sq);
1230         mlx5_wq_destroy(&sq->wq_ctrl);
1231         mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1232         if (sq->sq_tq != NULL) {
1233                 taskqueue_drain(sq->sq_tq, &sq->sq_task);
1234                 taskqueue_free(sq->sq_tq);
1235         }
1236         if (sq->br != NULL)
1237                 buf_ring_free(sq->br, M_MLX5EN);
1238 }
1239
1240 int
1241 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1242     int tis_num)
1243 {
1244         void *in;
1245         void *sqc;
1246         void *wq;
1247         int inlen;
1248         int err;
1249
1250         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1251             sizeof(u64) * sq->wq_ctrl.buf.npages;
1252         in = mlx5_vzalloc(inlen);
1253         if (in == NULL)
1254                 return (-ENOMEM);
1255
1256         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1257         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1258
1259         memcpy(sqc, param->sqc, sizeof(param->sqc));
1260
1261         MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1262         MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1263         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1264         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1265         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1266
1267         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1268         MLX5_SET(wq, wq, uar_page, sq->uar.index);
1269         MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1270             PAGE_SHIFT);
1271         MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1272
1273         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1274             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1275
1276         err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1277
1278         kvfree(in);
1279
1280         return (err);
1281 }
1282
1283 int
1284 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1285 {
1286         void *in;
1287         void *sqc;
1288         int inlen;
1289         int err;
1290
1291         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1292         in = mlx5_vzalloc(inlen);
1293         if (in == NULL)
1294                 return (-ENOMEM);
1295
1296         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1297
1298         MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1299         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1300         MLX5_SET(sqc, sqc, state, next_state);
1301
1302         err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1303
1304         kvfree(in);
1305
1306         return (err);
1307 }
1308
1309 void
1310 mlx5e_disable_sq(struct mlx5e_sq *sq)
1311 {
1312
1313         mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1314 }
1315
1316 static int
1317 mlx5e_open_sq(struct mlx5e_channel *c,
1318     int tc,
1319     struct mlx5e_sq_param *param,
1320     struct mlx5e_sq *sq)
1321 {
1322         int err;
1323
1324         err = mlx5e_create_sq(c, tc, param, sq);
1325         if (err)
1326                 return (err);
1327
1328         err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1329         if (err)
1330                 goto err_destroy_sq;
1331
1332         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1333         if (err)
1334                 goto err_disable_sq;
1335
1336         atomic_store_rel_int(&sq->queue_state, MLX5E_SQ_READY);
1337
1338         return (0);
1339
1340 err_disable_sq:
1341         mlx5e_disable_sq(sq);
1342 err_destroy_sq:
1343         mlx5e_destroy_sq(sq);
1344
1345         return (err);
1346 }
1347
1348 static void
1349 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1350 {
1351         /* fill up remainder with NOPs */
1352         while (sq->cev_counter != 0) {
1353                 while (!mlx5e_sq_has_room_for(sq, 1)) {
1354                         if (can_sleep != 0) {
1355                                 mtx_unlock(&sq->lock);
1356                                 msleep(4);
1357                                 mtx_lock(&sq->lock);
1358                         } else {
1359                                 goto done;
1360                         }
1361                 }
1362                 /* send a single NOP */
1363                 mlx5e_send_nop(sq, 1);
1364                 atomic_thread_fence_rel();
1365         }
1366 done:
1367         /* Check if we need to write the doorbell */
1368         if (likely(sq->doorbell.d64 != 0)) {
1369                 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1370                 sq->doorbell.d64 = 0;
1371         }
1372 }
1373
1374 void
1375 mlx5e_sq_cev_timeout(void *arg)
1376 {
1377         struct mlx5e_sq *sq = arg;
1378
1379         mtx_assert(&sq->lock, MA_OWNED);
1380
1381         /* check next state */
1382         switch (sq->cev_next_state) {
1383         case MLX5E_CEV_STATE_SEND_NOPS:
1384                 /* fill TX ring with NOPs, if any */
1385                 mlx5e_sq_send_nops_locked(sq, 0);
1386
1387                 /* check if completed */
1388                 if (sq->cev_counter == 0) {
1389                         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1390                         return;
1391                 }
1392                 break;
1393         default:
1394                 /* send NOPs on next timeout */
1395                 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1396                 break;
1397         }
1398
1399         /* restart timer */
1400         callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1401 }
1402
1403 void
1404 mlx5e_drain_sq(struct mlx5e_sq *sq)
1405 {
1406         int error;
1407
1408         /*
1409          * Check if already stopped.
1410          *
1411          * NOTE: The "stopped" variable is only written when both the
1412          * priv's configuration lock and the SQ's lock is locked. It
1413          * can therefore safely be read when only one of the two locks
1414          * is locked. This function is always called when the priv's
1415          * configuration lock is locked.
1416          */
1417         if (sq->stopped != 0)
1418                 return;
1419
1420         mtx_lock(&sq->lock);
1421
1422         /* don't put more packets into the SQ */
1423         sq->stopped = 1;
1424
1425         /* teardown event factor timer, if any */
1426         sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1427         callout_stop(&sq->cev_callout);
1428
1429         /* send dummy NOPs in order to flush the transmit ring */
1430         mlx5e_sq_send_nops_locked(sq, 1);
1431         mtx_unlock(&sq->lock);
1432
1433         /* make sure it is safe to free the callout */
1434         callout_drain(&sq->cev_callout);
1435
1436         /* wait till SQ is empty or link is down */
1437         mtx_lock(&sq->lock);
1438         while (sq->cc != sq->pc &&
1439             (sq->priv->media_status_last & IFM_ACTIVE) != 0) {
1440                 mtx_unlock(&sq->lock);
1441                 msleep(1);
1442                 sq->cq.mcq.comp(&sq->cq.mcq);
1443                 mtx_lock(&sq->lock);
1444         }
1445         mtx_unlock(&sq->lock);
1446
1447         /* error out remaining requests */
1448         error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1449         if (error != 0) {
1450                 if_printf(sq->ifp,
1451                     "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error);
1452         }
1453
1454         /* wait till SQ is empty */
1455         mtx_lock(&sq->lock);
1456         while (sq->cc != sq->pc) {
1457                 mtx_unlock(&sq->lock);
1458                 msleep(1);
1459                 sq->cq.mcq.comp(&sq->cq.mcq);
1460                 mtx_lock(&sq->lock);
1461         }
1462         mtx_unlock(&sq->lock);
1463 }
1464
1465 static void
1466 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1467 {
1468
1469         mlx5e_drain_sq(sq);
1470         mlx5e_disable_sq(sq);
1471         mlx5e_destroy_sq(sq);
1472 }
1473
1474 static int
1475 mlx5e_create_cq(struct mlx5e_priv *priv,
1476     struct mlx5e_cq_param *param,
1477     struct mlx5e_cq *cq,
1478     mlx5e_cq_comp_t *comp,
1479     int eq_ix)
1480 {
1481         struct mlx5_core_dev *mdev = priv->mdev;
1482         struct mlx5_core_cq *mcq = &cq->mcq;
1483         int eqn_not_used;
1484         int irqn;
1485         int err;
1486         u32 i;
1487
1488         param->wq.buf_numa_node = 0;
1489         param->wq.db_numa_node = 0;
1490
1491         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1492             &cq->wq_ctrl);
1493         if (err)
1494                 return (err);
1495
1496         mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1497
1498         mcq->cqe_sz = 64;
1499         mcq->set_ci_db = cq->wq_ctrl.db.db;
1500         mcq->arm_db = cq->wq_ctrl.db.db + 1;
1501         *mcq->set_ci_db = 0;
1502         *mcq->arm_db = 0;
1503         mcq->vector = eq_ix;
1504         mcq->comp = comp;
1505         mcq->event = mlx5e_cq_error_event;
1506         mcq->irqn = irqn;
1507         mcq->uar = &priv->cq_uar;
1508
1509         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1510                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1511
1512                 cqe->op_own = 0xf1;
1513         }
1514
1515         cq->priv = priv;
1516
1517         return (0);
1518 }
1519
1520 static void
1521 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1522 {
1523         mlx5_wq_destroy(&cq->wq_ctrl);
1524 }
1525
1526 static int
1527 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1528 {
1529         struct mlx5_core_cq *mcq = &cq->mcq;
1530         void *in;
1531         void *cqc;
1532         int inlen;
1533         int irqn_not_used;
1534         int eqn;
1535         int err;
1536
1537         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1538             sizeof(u64) * cq->wq_ctrl.buf.npages;
1539         in = mlx5_vzalloc(inlen);
1540         if (in == NULL)
1541                 return (-ENOMEM);
1542
1543         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1544
1545         memcpy(cqc, param->cqc, sizeof(param->cqc));
1546
1547         mlx5_fill_page_array(&cq->wq_ctrl.buf,
1548             (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1549
1550         mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
1551
1552         MLX5_SET(cqc, cqc, c_eqn, eqn);
1553         MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1554         MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1555             PAGE_SHIFT);
1556         MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1557
1558         err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
1559
1560         kvfree(in);
1561
1562         if (err)
1563                 return (err);
1564
1565         mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock));
1566
1567         return (0);
1568 }
1569
1570 static void
1571 mlx5e_disable_cq(struct mlx5e_cq *cq)
1572 {
1573
1574         mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
1575 }
1576
1577 int
1578 mlx5e_open_cq(struct mlx5e_priv *priv,
1579     struct mlx5e_cq_param *param,
1580     struct mlx5e_cq *cq,
1581     mlx5e_cq_comp_t *comp,
1582     int eq_ix)
1583 {
1584         int err;
1585
1586         err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
1587         if (err)
1588                 return (err);
1589
1590         err = mlx5e_enable_cq(cq, param, eq_ix);
1591         if (err)
1592                 goto err_destroy_cq;
1593
1594         return (0);
1595
1596 err_destroy_cq:
1597         mlx5e_destroy_cq(cq);
1598
1599         return (err);
1600 }
1601
1602 void
1603 mlx5e_close_cq(struct mlx5e_cq *cq)
1604 {
1605         mlx5e_disable_cq(cq);
1606         mlx5e_destroy_cq(cq);
1607 }
1608
1609 static int
1610 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1611     struct mlx5e_channel_param *cparam)
1612 {
1613         int err;
1614         int tc;
1615
1616         for (tc = 0; tc < c->num_tc; tc++) {
1617                 /* open completion queue */
1618                 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
1619                     &mlx5e_tx_cq_comp, c->ix);
1620                 if (err)
1621                         goto err_close_tx_cqs;
1622         }
1623         return (0);
1624
1625 err_close_tx_cqs:
1626         for (tc--; tc >= 0; tc--)
1627                 mlx5e_close_cq(&c->sq[tc].cq);
1628
1629         return (err);
1630 }
1631
1632 static void
1633 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1634 {
1635         int tc;
1636
1637         for (tc = 0; tc < c->num_tc; tc++)
1638                 mlx5e_close_cq(&c->sq[tc].cq);
1639 }
1640
1641 static int
1642 mlx5e_open_sqs(struct mlx5e_channel *c,
1643     struct mlx5e_channel_param *cparam)
1644 {
1645         int err;
1646         int tc;
1647
1648         for (tc = 0; tc < c->num_tc; tc++) {
1649                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1650                 if (err)
1651                         goto err_close_sqs;
1652         }
1653
1654         return (0);
1655
1656 err_close_sqs:
1657         for (tc--; tc >= 0; tc--)
1658                 mlx5e_close_sq_wait(&c->sq[tc]);
1659
1660         return (err);
1661 }
1662
1663 static void
1664 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
1665 {
1666         int tc;
1667
1668         for (tc = 0; tc < c->num_tc; tc++)
1669                 mlx5e_close_sq_wait(&c->sq[tc]);
1670 }
1671
1672 static void
1673 mlx5e_chan_mtx_init(struct mlx5e_channel *c)
1674 {
1675         int tc;
1676
1677         mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
1678
1679         callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
1680
1681         for (tc = 0; tc < c->num_tc; tc++) {
1682                 struct mlx5e_sq *sq = c->sq + tc;
1683
1684                 mtx_init(&sq->lock, "mlx5tx",
1685                     MTX_NETWORK_LOCK " TX", MTX_DEF);
1686                 mtx_init(&sq->comp_lock, "mlx5comp",
1687                     MTX_NETWORK_LOCK " TX", MTX_DEF);
1688
1689                 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
1690
1691                 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1692
1693                 /* ensure the TX completion event factor is not zero */
1694                 if (sq->cev_factor == 0)
1695                         sq->cev_factor = 1;
1696         }
1697 }
1698
1699 static void
1700 mlx5e_chan_mtx_destroy(struct mlx5e_channel *c)
1701 {
1702         int tc;
1703
1704         mtx_destroy(&c->rq.mtx);
1705
1706         for (tc = 0; tc < c->num_tc; tc++) {
1707                 mtx_destroy(&c->sq[tc].lock);
1708                 mtx_destroy(&c->sq[tc].comp_lock);
1709         }
1710 }
1711
1712 static int
1713 mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1714     struct mlx5e_channel_param *cparam,
1715     struct mlx5e_channel *volatile *cp)
1716 {
1717         struct mlx5e_channel *c;
1718         int err;
1719
1720         c = malloc(sizeof(*c), M_MLX5EN, M_WAITOK | M_ZERO);
1721         c->priv = priv;
1722         c->ix = ix;
1723         c->cpu = 0;
1724         c->ifp = priv->ifp;
1725         c->mkey_be = cpu_to_be32(priv->mr.key);
1726         c->num_tc = priv->num_tc;
1727
1728         /* init mutexes */
1729         mlx5e_chan_mtx_init(c);
1730
1731         /* open transmit completion queue */
1732         err = mlx5e_open_tx_cqs(c, cparam);
1733         if (err)
1734                 goto err_free;
1735
1736         /* open receive completion queue */
1737         err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
1738             &mlx5e_rx_cq_comp, c->ix);
1739         if (err)
1740                 goto err_close_tx_cqs;
1741
1742         err = mlx5e_open_sqs(c, cparam);
1743         if (err)
1744                 goto err_close_rx_cq;
1745
1746         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1747         if (err)
1748                 goto err_close_sqs;
1749
1750         /* store channel pointer */
1751         *cp = c;
1752
1753         /* poll receive queue initially */
1754         c->rq.cq.mcq.comp(&c->rq.cq.mcq);
1755
1756         return (0);
1757
1758 err_close_sqs:
1759         mlx5e_close_sqs_wait(c);
1760
1761 err_close_rx_cq:
1762         mlx5e_close_cq(&c->rq.cq);
1763
1764 err_close_tx_cqs:
1765         mlx5e_close_tx_cqs(c);
1766
1767 err_free:
1768         /* destroy mutexes */
1769         mlx5e_chan_mtx_destroy(c);
1770         free(c, M_MLX5EN);
1771         return (err);
1772 }
1773
1774 static void
1775 mlx5e_close_channel(struct mlx5e_channel *volatile *pp)
1776 {
1777         struct mlx5e_channel *c = *pp;
1778
1779         /* check if channel is already closed */
1780         if (c == NULL)
1781                 return;
1782         mlx5e_close_rq(&c->rq);
1783 }
1784
1785 static void
1786 mlx5e_close_channel_wait(struct mlx5e_channel *volatile *pp)
1787 {
1788         struct mlx5e_channel *c = *pp;
1789
1790         /* check if channel is already closed */
1791         if (c == NULL)
1792                 return;
1793         /* ensure channel pointer is no longer used */
1794         *pp = NULL;
1795
1796         mlx5e_close_rq_wait(&c->rq);
1797         mlx5e_close_sqs_wait(c);
1798         mlx5e_close_cq(&c->rq.cq);
1799         mlx5e_close_tx_cqs(c);
1800         /* destroy mutexes */
1801         mlx5e_chan_mtx_destroy(c);
1802         free(c, M_MLX5EN);
1803 }
1804
1805 static void
1806 mlx5e_build_rq_param(struct mlx5e_priv *priv,
1807     struct mlx5e_rq_param *param)
1808 {
1809         void *rqc = param->rqc;
1810         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1811
1812         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1813         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1814         MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1815         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1816         MLX5_SET(wq, wq, pd, priv->pdn);
1817
1818         param->wq.buf_numa_node = 0;
1819         param->wq.db_numa_node = 0;
1820         param->wq.linear = 1;
1821 }
1822
1823 static void
1824 mlx5e_build_sq_param(struct mlx5e_priv *priv,
1825     struct mlx5e_sq_param *param)
1826 {
1827         void *sqc = param->sqc;
1828         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1829
1830         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1831         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1832         MLX5_SET(wq, wq, pd, priv->pdn);
1833
1834         param->wq.buf_numa_node = 0;
1835         param->wq.db_numa_node = 0;
1836         param->wq.linear = 1;
1837 }
1838
1839 static void
1840 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1841     struct mlx5e_cq_param *param)
1842 {
1843         void *cqc = param->cqc;
1844
1845         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1846 }
1847
1848 static void
1849 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1850     struct mlx5e_cq_param *param)
1851 {
1852         void *cqc = param->cqc;
1853
1854
1855         /*
1856          * TODO The sysctl to control on/off is a bool value for now, which means
1857          * we only support CSUM, once HASH is implemnted we'll need to address that.
1858          */
1859         if (priv->params.cqe_zipping_en) {
1860                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1861                 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
1862         }
1863
1864         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1865         MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1866         MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1867
1868         switch (priv->params.rx_cq_moderation_mode) {
1869         case 0:
1870                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1871                 break;
1872         default:
1873                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1874                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1875                 else
1876                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1877                 break;
1878         }
1879
1880         mlx5e_build_common_cq_param(priv, param);
1881 }
1882
1883 static void
1884 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1885     struct mlx5e_cq_param *param)
1886 {
1887         void *cqc = param->cqc;
1888
1889         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1890         MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
1891         MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
1892
1893         switch (priv->params.tx_cq_moderation_mode) {
1894         case 0:
1895                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1896                 break;
1897         default:
1898                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1899                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1900                 else
1901                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1902                 break;
1903         }
1904
1905         mlx5e_build_common_cq_param(priv, param);
1906 }
1907
1908 static void
1909 mlx5e_build_channel_param(struct mlx5e_priv *priv,
1910     struct mlx5e_channel_param *cparam)
1911 {
1912         memset(cparam, 0, sizeof(*cparam));
1913
1914         mlx5e_build_rq_param(priv, &cparam->rq);
1915         mlx5e_build_sq_param(priv, &cparam->sq);
1916         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1917         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1918 }
1919
1920 static int
1921 mlx5e_open_channels(struct mlx5e_priv *priv)
1922 {
1923         struct mlx5e_channel_param cparam;
1924         void *ptr;
1925         int err;
1926         int i;
1927         int j;
1928
1929         priv->channel = malloc(priv->params.num_channels *
1930             sizeof(struct mlx5e_channel *), M_MLX5EN, M_WAITOK | M_ZERO);
1931
1932         mlx5e_build_channel_param(priv, &cparam);
1933         for (i = 0; i < priv->params.num_channels; i++) {
1934                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1935                 if (err)
1936                         goto err_close_channels;
1937         }
1938
1939         for (j = 0; j < priv->params.num_channels; j++) {
1940                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1941                 if (err)
1942                         goto err_close_channels;
1943         }
1944
1945         return (0);
1946
1947 err_close_channels:
1948         for (i--; i >= 0; i--) {
1949                 mlx5e_close_channel(&priv->channel[i]);
1950                 mlx5e_close_channel_wait(&priv->channel[i]);
1951         }
1952
1953         /* remove "volatile" attribute from "channel" pointer */
1954         ptr = __DECONST(void *, priv->channel);
1955         priv->channel = NULL;
1956
1957         free(ptr, M_MLX5EN);
1958
1959         return (err);
1960 }
1961
1962 static void
1963 mlx5e_close_channels(struct mlx5e_priv *priv)
1964 {
1965         void *ptr;
1966         int i;
1967
1968         if (priv->channel == NULL)
1969                 return;
1970
1971         for (i = 0; i < priv->params.num_channels; i++)
1972                 mlx5e_close_channel(&priv->channel[i]);
1973         for (i = 0; i < priv->params.num_channels; i++)
1974                 mlx5e_close_channel_wait(&priv->channel[i]);
1975
1976         /* remove "volatile" attribute from "channel" pointer */
1977         ptr = __DECONST(void *, priv->channel);
1978         priv->channel = NULL;
1979
1980         free(ptr, M_MLX5EN);
1981 }
1982
1983 static int
1984 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
1985 {
1986
1987         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
1988                 uint8_t cq_mode;
1989
1990                 switch (priv->params.tx_cq_moderation_mode) {
1991                 case 0:
1992                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1993                         break;
1994                 default:
1995                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
1996                         break;
1997                 }
1998
1999                 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq,
2000                     priv->params.tx_cq_moderation_usec,
2001                     priv->params.tx_cq_moderation_pkts,
2002                     cq_mode));
2003         }
2004
2005         return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
2006             priv->params.tx_cq_moderation_usec,
2007             priv->params.tx_cq_moderation_pkts));
2008 }
2009
2010 static int
2011 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
2012 {
2013
2014         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2015                 uint8_t cq_mode;
2016                 int retval;
2017
2018                 switch (priv->params.rx_cq_moderation_mode) {
2019                 case 0:
2020                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2021                         break;
2022                 default:
2023                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2024                         break;
2025                 }
2026
2027                 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2028                     priv->params.rx_cq_moderation_usec,
2029                     priv->params.rx_cq_moderation_pkts,
2030                     cq_mode);
2031
2032                 return (retval);
2033         }
2034
2035         return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
2036             priv->params.rx_cq_moderation_usec,
2037             priv->params.rx_cq_moderation_pkts));
2038 }
2039
2040 static int
2041 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
2042 {
2043         int err;
2044         int i;
2045
2046         if (c == NULL)
2047                 return (EINVAL);
2048
2049         err = mlx5e_refresh_rq_params(priv, &c->rq);
2050         if (err)
2051                 goto done;
2052
2053         for (i = 0; i != c->num_tc; i++) {
2054                 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
2055                 if (err)
2056                         goto done;
2057         }
2058 done:
2059         return (err);
2060 }
2061
2062 int
2063 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
2064 {
2065         int i;
2066
2067         if (priv->channel == NULL)
2068                 return (EINVAL);
2069
2070         for (i = 0; i < priv->params.num_channels; i++) {
2071                 int err;
2072
2073                 err = mlx5e_refresh_channel_params_sub(priv, priv->channel[i]);
2074                 if (err)
2075                         return (err);
2076         }
2077         return (0);
2078 }
2079
2080 static int
2081 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
2082 {
2083         struct mlx5_core_dev *mdev = priv->mdev;
2084         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
2085         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2086
2087         memset(in, 0, sizeof(in));
2088
2089         MLX5_SET(tisc, tisc, prio, tc);
2090         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
2091
2092         return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
2093 }
2094
2095 static void
2096 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
2097 {
2098         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2099 }
2100
2101 static int
2102 mlx5e_open_tises(struct mlx5e_priv *priv)
2103 {
2104         int num_tc = priv->num_tc;
2105         int err;
2106         int tc;
2107
2108         for (tc = 0; tc < num_tc; tc++) {
2109                 err = mlx5e_open_tis(priv, tc);
2110                 if (err)
2111                         goto err_close_tises;
2112         }
2113
2114         return (0);
2115
2116 err_close_tises:
2117         for (tc--; tc >= 0; tc--)
2118                 mlx5e_close_tis(priv, tc);
2119
2120         return (err);
2121 }
2122
2123 static void
2124 mlx5e_close_tises(struct mlx5e_priv *priv)
2125 {
2126         int num_tc = priv->num_tc;
2127         int tc;
2128
2129         for (tc = 0; tc < num_tc; tc++)
2130                 mlx5e_close_tis(priv, tc);
2131 }
2132
2133 static int
2134 mlx5e_open_rqt(struct mlx5e_priv *priv)
2135 {
2136         struct mlx5_core_dev *mdev = priv->mdev;
2137         u32 *in;
2138         u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
2139         void *rqtc;
2140         int inlen;
2141         int err;
2142         int sz;
2143         int i;
2144
2145         sz = 1 << priv->params.rx_hash_log_tbl_sz;
2146
2147         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2148         in = mlx5_vzalloc(inlen);
2149         if (in == NULL)
2150                 return (-ENOMEM);
2151         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2152
2153         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2154         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2155
2156         for (i = 0; i < sz; i++) {
2157                 int ix;
2158 #ifdef RSS
2159                 ix = rss_get_indirection_to_bucket(i);
2160 #else
2161                 ix = i;
2162 #endif
2163                 /* ensure we don't overflow */
2164                 ix %= priv->params.num_channels;
2165                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix]->rq.rqn);
2166         }
2167
2168         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
2169
2170         err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
2171         if (!err)
2172                 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
2173
2174         kvfree(in);
2175
2176         return (err);
2177 }
2178
2179 static void
2180 mlx5e_close_rqt(struct mlx5e_priv *priv)
2181 {
2182         u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0};
2183         u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0};
2184
2185         MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
2186         MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
2187
2188         mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out));
2189 }
2190
2191 static void
2192 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
2193 {
2194         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2195         __be32 *hkey;
2196
2197         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2198
2199 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2200
2201 #define MLX5_HASH_IP     (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2202                           MLX5_HASH_FIELD_SEL_DST_IP)
2203
2204 #define MLX5_HASH_ALL    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2205                           MLX5_HASH_FIELD_SEL_DST_IP   |\
2206                           MLX5_HASH_FIELD_SEL_L4_SPORT |\
2207                           MLX5_HASH_FIELD_SEL_L4_DPORT)
2208
2209 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2210                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2211                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2212
2213         if (priv->params.hw_lro_en) {
2214                 MLX5_SET(tirc, tirc, lro_enable_mask,
2215                     MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2216                     MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2217                 MLX5_SET(tirc, tirc, lro_max_msg_sz,
2218                     (priv->params.lro_wqe_sz -
2219                     ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2220                 /* TODO: add the option to choose timer value dynamically */
2221                 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
2222                     MLX5_CAP_ETH(priv->mdev,
2223                     lro_timer_supported_periods[2]));
2224         }
2225
2226         /* setup parameters for hashing TIR type, if any */
2227         switch (tt) {
2228         case MLX5E_TT_ANY:
2229                 MLX5_SET(tirc, tirc, disp_type,
2230                     MLX5_TIRC_DISP_TYPE_DIRECT);
2231                 MLX5_SET(tirc, tirc, inline_rqn,
2232                     priv->channel[0]->rq.rqn);
2233                 break;
2234         default:
2235                 MLX5_SET(tirc, tirc, disp_type,
2236                     MLX5_TIRC_DISP_TYPE_INDIRECT);
2237                 MLX5_SET(tirc, tirc, indirect_table,
2238                     priv->rqtn);
2239                 MLX5_SET(tirc, tirc, rx_hash_fn,
2240                     MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
2241                 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
2242 #ifdef RSS
2243                 /*
2244                  * The FreeBSD RSS implementation does currently not
2245                  * support symmetric Toeplitz hashes:
2246                  */
2247                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
2248                 rss_getkey((uint8_t *)hkey);
2249 #else
2250                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2251                 hkey[0] = cpu_to_be32(0xD181C62C);
2252                 hkey[1] = cpu_to_be32(0xF7F4DB5B);
2253                 hkey[2] = cpu_to_be32(0x1983A2FC);
2254                 hkey[3] = cpu_to_be32(0x943E1ADB);
2255                 hkey[4] = cpu_to_be32(0xD9389E6B);
2256                 hkey[5] = cpu_to_be32(0xD1039C2C);
2257                 hkey[6] = cpu_to_be32(0xA74499AD);
2258                 hkey[7] = cpu_to_be32(0x593D56D9);
2259                 hkey[8] = cpu_to_be32(0xF3253C06);
2260                 hkey[9] = cpu_to_be32(0x2ADC1FFC);
2261 #endif
2262                 break;
2263         }
2264
2265         switch (tt) {
2266         case MLX5E_TT_IPV4_TCP:
2267                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2268                     MLX5_L3_PROT_TYPE_IPV4);
2269                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2270                     MLX5_L4_PROT_TYPE_TCP);
2271 #ifdef RSS
2272                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2273                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2274                             MLX5_HASH_IP);
2275                 } else
2276 #endif
2277                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2278                     MLX5_HASH_ALL);
2279                 break;
2280
2281         case MLX5E_TT_IPV6_TCP:
2282                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2283                     MLX5_L3_PROT_TYPE_IPV6);
2284                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2285                     MLX5_L4_PROT_TYPE_TCP);
2286 #ifdef RSS
2287                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2288                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2289                             MLX5_HASH_IP);
2290                 } else
2291 #endif
2292                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2293                     MLX5_HASH_ALL);
2294                 break;
2295
2296         case MLX5E_TT_IPV4_UDP:
2297                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2298                     MLX5_L3_PROT_TYPE_IPV4);
2299                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2300                     MLX5_L4_PROT_TYPE_UDP);
2301 #ifdef RSS
2302                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2303                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2304                             MLX5_HASH_IP);
2305                 } else
2306 #endif
2307                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2308                     MLX5_HASH_ALL);
2309                 break;
2310
2311         case MLX5E_TT_IPV6_UDP:
2312                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2313                     MLX5_L3_PROT_TYPE_IPV6);
2314                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2315                     MLX5_L4_PROT_TYPE_UDP);
2316 #ifdef RSS
2317                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2318                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2319                             MLX5_HASH_IP);
2320                 } else
2321 #endif
2322                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2323                     MLX5_HASH_ALL);
2324                 break;
2325
2326         case MLX5E_TT_IPV4_IPSEC_AH:
2327                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2328                     MLX5_L3_PROT_TYPE_IPV4);
2329                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2330                     MLX5_HASH_IP_IPSEC_SPI);
2331                 break;
2332
2333         case MLX5E_TT_IPV6_IPSEC_AH:
2334                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2335                     MLX5_L3_PROT_TYPE_IPV6);
2336                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2337                     MLX5_HASH_IP_IPSEC_SPI);
2338                 break;
2339
2340         case MLX5E_TT_IPV4_IPSEC_ESP:
2341                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2342                     MLX5_L3_PROT_TYPE_IPV4);
2343                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2344                     MLX5_HASH_IP_IPSEC_SPI);
2345                 break;
2346
2347         case MLX5E_TT_IPV6_IPSEC_ESP:
2348                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2349                     MLX5_L3_PROT_TYPE_IPV6);
2350                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2351                     MLX5_HASH_IP_IPSEC_SPI);
2352                 break;
2353
2354         case MLX5E_TT_IPV4:
2355                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2356                     MLX5_L3_PROT_TYPE_IPV4);
2357                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2358                     MLX5_HASH_IP);
2359                 break;
2360
2361         case MLX5E_TT_IPV6:
2362                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2363                     MLX5_L3_PROT_TYPE_IPV6);
2364                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2365                     MLX5_HASH_IP);
2366                 break;
2367
2368         default:
2369                 break;
2370         }
2371 }
2372
2373 static int
2374 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2375 {
2376         struct mlx5_core_dev *mdev = priv->mdev;
2377         u32 *in;
2378         void *tirc;
2379         int inlen;
2380         int err;
2381
2382         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2383         in = mlx5_vzalloc(inlen);
2384         if (in == NULL)
2385                 return (-ENOMEM);
2386         tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2387
2388         mlx5e_build_tir_ctx(priv, tirc, tt);
2389
2390         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2391
2392         kvfree(in);
2393
2394         return (err);
2395 }
2396
2397 static void
2398 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2399 {
2400         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2401 }
2402
2403 static int
2404 mlx5e_open_tirs(struct mlx5e_priv *priv)
2405 {
2406         int err;
2407         int i;
2408
2409         for (i = 0; i < MLX5E_NUM_TT; i++) {
2410                 err = mlx5e_open_tir(priv, i);
2411                 if (err)
2412                         goto err_close_tirs;
2413         }
2414
2415         return (0);
2416
2417 err_close_tirs:
2418         for (i--; i >= 0; i--)
2419                 mlx5e_close_tir(priv, i);
2420
2421         return (err);
2422 }
2423
2424 static void
2425 mlx5e_close_tirs(struct mlx5e_priv *priv)
2426 {
2427         int i;
2428
2429         for (i = 0; i < MLX5E_NUM_TT; i++)
2430                 mlx5e_close_tir(priv, i);
2431 }
2432
2433 /*
2434  * SW MTU does not include headers,
2435  * HW MTU includes all headers and checksums.
2436  */
2437 static int
2438 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2439 {
2440         struct mlx5e_priv *priv = ifp->if_softc;
2441         struct mlx5_core_dev *mdev = priv->mdev;
2442         int hw_mtu;
2443         int err;
2444
2445         hw_mtu = MLX5E_SW2HW_MTU(sw_mtu);
2446
2447         err = mlx5_set_port_mtu(mdev, hw_mtu);
2448         if (err) {
2449                 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n",
2450                     __func__, sw_mtu, err);
2451                 return (err);
2452         }
2453
2454         /* Update vport context MTU */
2455         err = mlx5_set_vport_mtu(mdev, hw_mtu);
2456         if (err) {
2457                 if_printf(ifp, "%s: Failed updating vport context with MTU size, err=%d\n",
2458                     __func__, err);
2459         }
2460
2461         ifp->if_mtu = sw_mtu;
2462
2463         err = mlx5_query_vport_mtu(mdev, &hw_mtu);
2464         if (err || !hw_mtu) {
2465                 /* fallback to port oper mtu */
2466                 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2467         }
2468         if (err) {
2469                 if_printf(ifp, "Query port MTU, after setting new "
2470                     "MTU value, failed\n");
2471                 return (err);
2472         } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
2473                 err = -E2BIG,
2474                 if_printf(ifp, "Port MTU %d is smaller than "
2475                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2476         } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
2477                 err = -EINVAL;
2478                 if_printf(ifp, "Port MTU %d is bigger than "
2479                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2480         }
2481         priv->params_ethtool.hw_mtu = hw_mtu;
2482
2483         return (err);
2484 }
2485
2486 int
2487 mlx5e_open_locked(struct ifnet *ifp)
2488 {
2489         struct mlx5e_priv *priv = ifp->if_softc;
2490         int err;
2491         u16 set_id;
2492
2493         /* check if already opened */
2494         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2495                 return (0);
2496
2497 #ifdef RSS
2498         if (rss_getnumbuckets() > priv->params.num_channels) {
2499                 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than "
2500                     "channels(%u) available\n", rss_getnumbuckets(),
2501                     priv->params.num_channels);
2502         }
2503 #endif
2504         err = mlx5e_open_tises(priv);
2505         if (err) {
2506                 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n",
2507                     __func__, err);
2508                 return (err);
2509         }
2510         err = mlx5_vport_alloc_q_counter(priv->mdev,
2511             MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
2512         if (err) {
2513                 if_printf(priv->ifp,
2514                     "%s: mlx5_vport_alloc_q_counter failed: %d\n",
2515                     __func__, err);
2516                 goto err_close_tises;
2517         }
2518         /* store counter set ID */
2519         priv->counter_set_id = set_id;
2520
2521         err = mlx5e_open_channels(priv);
2522         if (err) {
2523                 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n",
2524                     __func__, err);
2525                 goto err_dalloc_q_counter;
2526         }
2527         err = mlx5e_open_rqt(priv);
2528         if (err) {
2529                 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n",
2530                     __func__, err);
2531                 goto err_close_channels;
2532         }
2533         err = mlx5e_open_tirs(priv);
2534         if (err) {
2535                 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n",
2536                     __func__, err);
2537                 goto err_close_rqls;
2538         }
2539         err = mlx5e_open_flow_table(priv);
2540         if (err) {
2541                 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n",
2542                     __func__, err);
2543                 goto err_close_tirs;
2544         }
2545         err = mlx5e_add_all_vlan_rules(priv);
2546         if (err) {
2547                 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
2548                     __func__, err);
2549                 goto err_close_flow_table;
2550         }
2551         set_bit(MLX5E_STATE_OPENED, &priv->state);
2552
2553         mlx5e_update_carrier(priv);
2554         mlx5e_set_rx_mode_core(priv);
2555
2556         return (0);
2557
2558 err_close_flow_table:
2559         mlx5e_close_flow_table(priv);
2560
2561 err_close_tirs:
2562         mlx5e_close_tirs(priv);
2563
2564 err_close_rqls:
2565         mlx5e_close_rqt(priv);
2566
2567 err_close_channels:
2568         mlx5e_close_channels(priv);
2569
2570 err_dalloc_q_counter:
2571         mlx5_vport_dealloc_q_counter(priv->mdev,
2572             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2573
2574 err_close_tises:
2575         mlx5e_close_tises(priv);
2576
2577         return (err);
2578 }
2579
2580 static void
2581 mlx5e_open(void *arg)
2582 {
2583         struct mlx5e_priv *priv = arg;
2584
2585         PRIV_LOCK(priv);
2586         if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
2587                 if_printf(priv->ifp,
2588                     "%s: Setting port status to up failed\n",
2589                     __func__);
2590
2591         mlx5e_open_locked(priv->ifp);
2592         priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
2593         PRIV_UNLOCK(priv);
2594 }
2595
2596 int
2597 mlx5e_close_locked(struct ifnet *ifp)
2598 {
2599         struct mlx5e_priv *priv = ifp->if_softc;
2600
2601         /* check if already closed */
2602         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2603                 return (0);
2604
2605         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2606
2607         mlx5e_set_rx_mode_core(priv);
2608         mlx5e_del_all_vlan_rules(priv);
2609         if_link_state_change(priv->ifp, LINK_STATE_DOWN);
2610         mlx5e_close_flow_table(priv);
2611         mlx5e_close_tirs(priv);
2612         mlx5e_close_rqt(priv);
2613         mlx5e_close_channels(priv);
2614         mlx5_vport_dealloc_q_counter(priv->mdev,
2615             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2616         mlx5e_close_tises(priv);
2617
2618         return (0);
2619 }
2620
2621 #if (__FreeBSD_version >= 1100000)
2622 static uint64_t
2623 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
2624 {
2625         struct mlx5e_priv *priv = ifp->if_softc;
2626         u64 retval;
2627
2628         /* PRIV_LOCK(priv); XXX not allowed */
2629         switch (cnt) {
2630         case IFCOUNTER_IPACKETS:
2631                 retval = priv->stats.vport.rx_packets;
2632                 break;
2633         case IFCOUNTER_IERRORS:
2634                 retval = priv->stats.vport.rx_error_packets +
2635                     priv->stats.pport.alignment_err +
2636                     priv->stats.pport.check_seq_err +
2637                     priv->stats.pport.crc_align_errors +
2638                     priv->stats.pport.in_range_len_errors +
2639                     priv->stats.pport.jabbers +
2640                     priv->stats.pport.out_of_range_len +
2641                     priv->stats.pport.oversize_pkts +
2642                     priv->stats.pport.symbol_err +
2643                     priv->stats.pport.too_long_errors +
2644                     priv->stats.pport.undersize_pkts +
2645                     priv->stats.pport.unsupported_op_rx;
2646                 break;
2647         case IFCOUNTER_IQDROPS:
2648                 retval = priv->stats.vport.rx_out_of_buffer +
2649                     priv->stats.pport.drop_events;
2650                 break;
2651         case IFCOUNTER_OPACKETS:
2652                 retval = priv->stats.vport.tx_packets;
2653                 break;
2654         case IFCOUNTER_OERRORS:
2655                 retval = priv->stats.vport.tx_error_packets;
2656                 break;
2657         case IFCOUNTER_IBYTES:
2658                 retval = priv->stats.vport.rx_bytes;
2659                 break;
2660         case IFCOUNTER_OBYTES:
2661                 retval = priv->stats.vport.tx_bytes;
2662                 break;
2663         case IFCOUNTER_IMCASTS:
2664                 retval = priv->stats.vport.rx_multicast_packets;
2665                 break;
2666         case IFCOUNTER_OMCASTS:
2667                 retval = priv->stats.vport.tx_multicast_packets;
2668                 break;
2669         case IFCOUNTER_OQDROPS:
2670                 retval = priv->stats.vport.tx_queue_dropped;
2671                 break;
2672         case IFCOUNTER_COLLISIONS:
2673                 retval = priv->stats.pport.collisions;
2674                 break;
2675         default:
2676                 retval = if_get_counter_default(ifp, cnt);
2677                 break;
2678         }
2679         /* PRIV_UNLOCK(priv); XXX not allowed */
2680         return (retval);
2681 }
2682 #endif
2683
2684 static void
2685 mlx5e_set_rx_mode(struct ifnet *ifp)
2686 {
2687         struct mlx5e_priv *priv = ifp->if_softc;
2688
2689         queue_work(priv->wq, &priv->set_rx_mode_work);
2690 }
2691
2692 static int
2693 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2694 {
2695         struct mlx5e_priv *priv;
2696         struct ifreq *ifr;
2697         struct ifi2creq i2c;
2698         int error = 0;
2699         int mask = 0;
2700         int size_read = 0;
2701         int module_status;
2702         int module_num;
2703         int max_mtu;
2704         uint8_t read_addr;
2705
2706         priv = ifp->if_softc;
2707
2708         /* check if detaching */
2709         if (priv == NULL || priv->gone != 0)
2710                 return (ENXIO);
2711
2712         switch (command) {
2713         case SIOCSIFMTU:
2714                 ifr = (struct ifreq *)data;
2715
2716                 PRIV_LOCK(priv);
2717                 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
2718
2719                 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
2720                     ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
2721                         int was_opened;
2722
2723                         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2724                         if (was_opened)
2725                                 mlx5e_close_locked(ifp);
2726
2727                         /* set new MTU */
2728                         mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
2729
2730                         if (was_opened)
2731                                 mlx5e_open_locked(ifp);
2732                 } else {
2733                         error = EINVAL;
2734                         if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n",
2735                             MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
2736                 }
2737                 PRIV_UNLOCK(priv);
2738                 break;
2739         case SIOCSIFFLAGS:
2740                 if ((ifp->if_flags & IFF_UP) &&
2741                     (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2742                         mlx5e_set_rx_mode(ifp);
2743                         break;
2744                 }
2745                 PRIV_LOCK(priv);
2746                 if (ifp->if_flags & IFF_UP) {
2747                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2748                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2749                                         mlx5e_open_locked(ifp);
2750                                 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2751                                 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
2752                         }
2753                 } else {
2754                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2755                                 mlx5_set_port_status(priv->mdev,
2756                                     MLX5_PORT_DOWN);
2757                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2758                                         mlx5e_close_locked(ifp);
2759                                 mlx5e_update_carrier(priv);
2760                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2761                         }
2762                 }
2763                 PRIV_UNLOCK(priv);
2764                 break;
2765         case SIOCADDMULTI:
2766         case SIOCDELMULTI:
2767                 mlx5e_set_rx_mode(ifp);
2768                 break;
2769         case SIOCSIFMEDIA:
2770         case SIOCGIFMEDIA:
2771         case SIOCGIFXMEDIA:
2772                 ifr = (struct ifreq *)data;
2773                 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
2774                 break;
2775         case SIOCSIFCAP:
2776                 ifr = (struct ifreq *)data;
2777                 PRIV_LOCK(priv);
2778                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2779
2780                 if (mask & IFCAP_TXCSUM) {
2781                         ifp->if_capenable ^= IFCAP_TXCSUM;
2782                         ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2783
2784                         if (IFCAP_TSO4 & ifp->if_capenable &&
2785                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2786                                 ifp->if_capenable &= ~IFCAP_TSO4;
2787                                 ifp->if_hwassist &= ~CSUM_IP_TSO;
2788                                 if_printf(ifp,
2789                                     "tso4 disabled due to -txcsum.\n");
2790                         }
2791                 }
2792                 if (mask & IFCAP_TXCSUM_IPV6) {
2793                         ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
2794                         ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2795
2796                         if (IFCAP_TSO6 & ifp->if_capenable &&
2797                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2798                                 ifp->if_capenable &= ~IFCAP_TSO6;
2799                                 ifp->if_hwassist &= ~CSUM_IP6_TSO;
2800                                 if_printf(ifp,
2801                                     "tso6 disabled due to -txcsum6.\n");
2802                         }
2803                 }
2804                 if (mask & IFCAP_RXCSUM)
2805                         ifp->if_capenable ^= IFCAP_RXCSUM;
2806                 if (mask & IFCAP_RXCSUM_IPV6)
2807                         ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
2808                 if (mask & IFCAP_TSO4) {
2809                         if (!(IFCAP_TSO4 & ifp->if_capenable) &&
2810                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2811                                 if_printf(ifp, "enable txcsum first.\n");
2812                                 error = EAGAIN;
2813                                 goto out;
2814                         }
2815                         ifp->if_capenable ^= IFCAP_TSO4;
2816                         ifp->if_hwassist ^= CSUM_IP_TSO;
2817                 }
2818                 if (mask & IFCAP_TSO6) {
2819                         if (!(IFCAP_TSO6 & ifp->if_capenable) &&
2820                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2821                                 if_printf(ifp, "enable txcsum6 first.\n");
2822                                 error = EAGAIN;
2823                                 goto out;
2824                         }
2825                         ifp->if_capenable ^= IFCAP_TSO6;
2826                         ifp->if_hwassist ^= CSUM_IP6_TSO;
2827                 }
2828                 if (mask & IFCAP_VLAN_HWFILTER) {
2829                         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
2830                                 mlx5e_disable_vlan_filter(priv);
2831                         else
2832                                 mlx5e_enable_vlan_filter(priv);
2833
2834                         ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
2835                 }
2836                 if (mask & IFCAP_VLAN_HWTAGGING)
2837                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2838                 if (mask & IFCAP_WOL_MAGIC)
2839                         ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2840
2841                 VLAN_CAPABILITIES(ifp);
2842                 /* turn off LRO means also turn of HW LRO - if it's on */
2843                 if (mask & IFCAP_LRO) {
2844                         int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2845                         bool need_restart = false;
2846
2847                         ifp->if_capenable ^= IFCAP_LRO;
2848                         if (!(ifp->if_capenable & IFCAP_LRO)) {
2849                                 if (priv->params.hw_lro_en) {
2850                                         priv->params.hw_lro_en = false;
2851                                         need_restart = true;
2852                                         /* Not sure this is the correct way */
2853                                         priv->params_ethtool.hw_lro = priv->params.hw_lro_en;
2854                                 }
2855                         }
2856                         if (was_opened && need_restart) {
2857                                 mlx5e_close_locked(ifp);
2858                                 mlx5e_open_locked(ifp);
2859                         }
2860                 }
2861                 if (mask & IFCAP_HWRXTSTMP) {
2862                         ifp->if_capenable ^= IFCAP_HWRXTSTMP;
2863                         if (ifp->if_capenable & IFCAP_HWRXTSTMP) {
2864                                 if (priv->clbr_done == 0)
2865                                         mlx5e_reset_calibration_callout(priv);
2866                         } else {
2867                                 callout_drain(&priv->tstmp_clbr);
2868                                 priv->clbr_done = 0;
2869                         }
2870                 }
2871 out:
2872                 PRIV_UNLOCK(priv);
2873                 break;
2874
2875         case SIOCGI2C:
2876                 ifr = (struct ifreq *)data;
2877
2878                 /*
2879                  * Copy from the user-space address ifr_data to the
2880                  * kernel-space address i2c
2881                  */
2882                 error = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
2883                 if (error)
2884                         break;
2885
2886                 if (i2c.len > sizeof(i2c.data)) {
2887                         error = EINVAL;
2888                         break;
2889                 }
2890
2891                 PRIV_LOCK(priv);
2892                 /* Get module_num which is required for the query_eeprom */
2893                 error = mlx5_query_module_num(priv->mdev, &module_num);
2894                 if (error) {
2895                         if_printf(ifp, "Query module num failed, eeprom "
2896                             "reading is not supported\n");
2897                         error = EINVAL;
2898                         goto err_i2c;
2899                 }
2900                 /* Check if module is present before doing an access */
2901                 module_status = mlx5_query_module_status(priv->mdev, module_num);
2902                 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED &&
2903                     module_status != MLX5_MODULE_STATUS_PLUGGED_DISABLED) {
2904                         error = EINVAL;
2905                         goto err_i2c;
2906                 }
2907                 /*
2908                  * Currently 0XA0 and 0xA2 are the only addresses permitted.
2909                  * The internal conversion is as follows:
2910                  */
2911                 if (i2c.dev_addr == 0xA0)
2912                         read_addr = MLX5E_I2C_ADDR_LOW;
2913                 else if (i2c.dev_addr == 0xA2)
2914                         read_addr = MLX5E_I2C_ADDR_HIGH;
2915                 else {
2916                         if_printf(ifp, "Query eeprom failed, "
2917                             "Invalid Address: %X\n", i2c.dev_addr);
2918                         error = EINVAL;
2919                         goto err_i2c;
2920                 }
2921                 error = mlx5_query_eeprom(priv->mdev,
2922                     read_addr, MLX5E_EEPROM_LOW_PAGE,
2923                     (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
2924                     (uint32_t *)i2c.data, &size_read);
2925                 if (error) {
2926                         if_printf(ifp, "Query eeprom failed, eeprom "
2927                             "reading is not supported\n");
2928                         error = EINVAL;
2929                         goto err_i2c;
2930                 }
2931
2932                 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
2933                         error = mlx5_query_eeprom(priv->mdev,
2934                             read_addr, MLX5E_EEPROM_LOW_PAGE,
2935                             (uint32_t)(i2c.offset + size_read),
2936                             (uint32_t)(i2c.len - size_read), module_num,
2937                             (uint32_t *)(i2c.data + size_read), &size_read);
2938                 }
2939                 if (error) {
2940                         if_printf(ifp, "Query eeprom failed, eeprom "
2941                             "reading is not supported\n");
2942                         error = EINVAL;
2943                         goto err_i2c;
2944                 }
2945
2946                 error = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
2947 err_i2c:
2948                 PRIV_UNLOCK(priv);
2949                 break;
2950
2951         default:
2952                 error = ether_ioctl(ifp, command, data);
2953                 break;
2954         }
2955         return (error);
2956 }
2957
2958 static int
2959 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2960 {
2961         /*
2962          * TODO: uncoment once FW really sets all these bits if
2963          * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
2964          * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
2965          * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
2966          * -ENOTSUPP;
2967          */
2968
2969         /* TODO: add more must-to-have features */
2970
2971         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2972                 return (-ENODEV);
2973
2974         return (0);
2975 }
2976
2977 static void
2978 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
2979     struct mlx5e_priv *priv,
2980     int num_comp_vectors)
2981 {
2982         /*
2983          * TODO: Consider link speed for setting "log_sq_size",
2984          * "log_rq_size" and "cq_moderation_xxx":
2985          */
2986         priv->params.log_sq_size =
2987             MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2988         priv->params.log_rq_size =
2989             MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2990         priv->params.rx_cq_moderation_usec =
2991             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
2992             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
2993             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2994         priv->params.rx_cq_moderation_mode =
2995             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
2996         priv->params.rx_cq_moderation_pkts =
2997             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2998         priv->params.tx_cq_moderation_usec =
2999             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3000         priv->params.tx_cq_moderation_pkts =
3001             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3002         priv->params.min_rx_wqes =
3003             MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
3004         priv->params.rx_hash_log_tbl_sz =
3005             (order_base_2(num_comp_vectors) >
3006             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
3007             order_base_2(num_comp_vectors) :
3008             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
3009         priv->params.num_tc = 1;
3010         priv->params.default_vlan_prio = 0;
3011         priv->counter_set_id = -1;
3012
3013         /*
3014          * hw lro is currently defaulted to off. when it won't anymore we
3015          * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
3016          */
3017         priv->params.hw_lro_en = false;
3018         priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3019
3020         priv->params.cqe_zipping_en = !!MLX5_CAP_GEN(mdev, cqe_compression);
3021
3022         priv->mdev = mdev;
3023         priv->params.num_channels = num_comp_vectors;
3024         priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
3025         priv->queue_mapping_channel_mask =
3026             roundup_pow_of_two(num_comp_vectors) - 1;
3027         priv->num_tc = priv->params.num_tc;
3028         priv->default_vlan_prio = priv->params.default_vlan_prio;
3029
3030         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3031         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3032         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3033 }
3034
3035 static int
3036 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
3037                   struct mlx5_core_mr *mkey)
3038 {
3039         struct ifnet *ifp = priv->ifp;
3040         struct mlx5_core_dev *mdev = priv->mdev;
3041         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3042         void *mkc;
3043         u32 *in;
3044         int err;
3045
3046         in = mlx5_vzalloc(inlen);
3047         if (in == NULL) {
3048                 if_printf(ifp, "%s: failed to allocate inbox\n", __func__);
3049                 return (-ENOMEM);
3050         }
3051
3052         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3053         MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA);
3054         MLX5_SET(mkc, mkc, lw, 1);
3055         MLX5_SET(mkc, mkc, lr, 1);
3056
3057         MLX5_SET(mkc, mkc, pd, pdn);
3058         MLX5_SET(mkc, mkc, length64, 1);
3059         MLX5_SET(mkc, mkc, qpn, 0xffffff);
3060
3061         err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
3062         if (err)
3063                 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n",
3064                     __func__, err);
3065
3066         kvfree(in);
3067         return (err);
3068 }
3069
3070 static const char *mlx5e_vport_stats_desc[] = {
3071         MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
3072 };
3073
3074 static const char *mlx5e_pport_stats_desc[] = {
3075         MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
3076 };
3077
3078 static void
3079 mlx5e_priv_mtx_init(struct mlx5e_priv *priv)
3080 {
3081         mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
3082         sx_init(&priv->state_lock, "mlx5state");
3083         callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
3084         MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
3085 }
3086
3087 static void
3088 mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv)
3089 {
3090         mtx_destroy(&priv->async_events_mtx);
3091         sx_destroy(&priv->state_lock);
3092 }
3093
3094 static int
3095 sysctl_firmware(SYSCTL_HANDLER_ARGS)
3096 {
3097         /*
3098          * %d.%d%.d the string format.
3099          * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
3100          * We need at most 5 chars to store that.
3101          * It also has: two "." and NULL at the end, which means we need 18
3102          * (5*3 + 3) chars at most.
3103          */
3104         char fw[18];
3105         struct mlx5e_priv *priv = arg1;
3106         int error;
3107
3108         snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
3109             fw_rev_sub(priv->mdev));
3110         error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
3111         return (error);
3112 }
3113
3114 static void
3115 mlx5e_disable_tx_dma(struct mlx5e_channel *ch)
3116 {
3117         int i;
3118
3119         for (i = 0; i < ch->num_tc; i++)
3120                 mlx5e_drain_sq(&ch->sq[i]);
3121 }
3122
3123 static void
3124 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq)
3125 {
3126
3127         sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP);
3128         sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8);
3129         mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
3130         sq->doorbell.d64 = 0;
3131 }
3132
3133 void
3134 mlx5e_resume_sq(struct mlx5e_sq *sq)
3135 {
3136         int err;
3137
3138         /* check if already enabled */
3139         if (sq->stopped == 0)
3140                 return;
3141
3142         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR,
3143             MLX5_SQC_STATE_RST);
3144         if (err != 0) {
3145                 if_printf(sq->ifp,
3146                     "mlx5e_modify_sq() from ERR to RST failed: %d\n", err);
3147         }
3148
3149         sq->cc = 0;
3150         sq->pc = 0;
3151
3152         /* reset doorbell prior to moving from RST to RDY */
3153         mlx5e_reset_sq_doorbell_record(sq);
3154
3155         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST,
3156             MLX5_SQC_STATE_RDY);
3157         if (err != 0) {
3158                 if_printf(sq->ifp,
3159                     "mlx5e_modify_sq() from RST to RDY failed: %d\n", err);
3160         }
3161
3162         mtx_lock(&sq->lock);
3163         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
3164         sq->stopped = 0;
3165         mtx_unlock(&sq->lock);
3166
3167 }
3168
3169 static void
3170 mlx5e_enable_tx_dma(struct mlx5e_channel *ch)
3171 {
3172         int i;
3173
3174         for (i = 0; i < ch->num_tc; i++)
3175                 mlx5e_resume_sq(&ch->sq[i]);
3176 }
3177
3178 static void
3179 mlx5e_disable_rx_dma(struct mlx5e_channel *ch)
3180 {
3181         struct mlx5e_rq *rq = &ch->rq;
3182         int err;
3183
3184         mtx_lock(&rq->mtx);
3185         rq->enabled = 0;
3186         callout_stop(&rq->watchdog);
3187         mtx_unlock(&rq->mtx);
3188
3189         callout_drain(&rq->watchdog);
3190
3191         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
3192         if (err != 0) {
3193                 if_printf(rq->ifp,
3194                     "mlx5e_modify_rq() from RDY to RST failed: %d\n", err);
3195         }
3196
3197         while (!mlx5_wq_ll_is_empty(&rq->wq)) {
3198                 msleep(1);
3199                 rq->cq.mcq.comp(&rq->cq.mcq);
3200         }
3201
3202         /*
3203          * Transitioning into RST state will allow the FW to track less ERR state queues,
3204          * thus reducing the recv queue flushing time
3205          */
3206         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST);
3207         if (err != 0) {
3208                 if_printf(rq->ifp,
3209                     "mlx5e_modify_rq() from ERR to RST failed: %d\n", err);
3210         }
3211 }
3212
3213 static void
3214 mlx5e_enable_rx_dma(struct mlx5e_channel *ch)
3215 {
3216         struct mlx5e_rq *rq = &ch->rq;
3217         int err;
3218
3219         rq->wq.wqe_ctr = 0;
3220         mlx5_wq_ll_update_db_record(&rq->wq);
3221         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3222         if (err != 0) {
3223                 if_printf(rq->ifp,
3224                     "mlx5e_modify_rq() from RST to RDY failed: %d\n", err);
3225         }
3226
3227         rq->enabled = 1;
3228
3229         rq->cq.mcq.comp(&rq->cq.mcq);
3230 }
3231
3232 void
3233 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value)
3234 {
3235         int i;
3236
3237         if (priv->channel == NULL)
3238                 return;
3239
3240         for (i = 0; i < priv->params.num_channels; i++) {
3241
3242                 if (!priv->channel[i])
3243                         continue;
3244
3245                 if (value)
3246                         mlx5e_disable_tx_dma(priv->channel[i]);
3247                 else
3248                         mlx5e_enable_tx_dma(priv->channel[i]);
3249         }
3250 }
3251
3252 void
3253 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value)
3254 {
3255         int i;
3256
3257         if (priv->channel == NULL)
3258                 return;
3259
3260         for (i = 0; i < priv->params.num_channels; i++) {
3261
3262                 if (!priv->channel[i])
3263                         continue;
3264
3265                 if (value)
3266                         mlx5e_disable_rx_dma(priv->channel[i]);
3267                 else
3268                         mlx5e_enable_rx_dma(priv->channel[i]);
3269         }
3270 }
3271
3272 static void
3273 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
3274 {
3275         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3276             OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
3277             sysctl_firmware, "A", "HCA firmware version");
3278
3279         SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3280             OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
3281             "Board ID");
3282 }
3283
3284 static int
3285 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3286 {
3287         struct mlx5e_priv *priv = arg1;
3288         uint32_t tx_pfc;
3289         uint32_t value;
3290         int error;
3291
3292         PRIV_LOCK(priv);
3293
3294         tx_pfc = priv->params.tx_priority_flow_control;
3295
3296         /* get current value */
3297         value = (tx_pfc >> arg2) & 1;
3298
3299         error = sysctl_handle_32(oidp, &value, 0, req);
3300
3301         /* range check value */
3302         if (value != 0)
3303                 priv->params.tx_priority_flow_control |= (1 << arg2);
3304         else
3305                 priv->params.tx_priority_flow_control &= ~(1 << arg2);
3306
3307         /* check if update is required */
3308         if (error == 0 && priv->gone == 0 &&
3309             tx_pfc != priv->params.tx_priority_flow_control) {
3310                 error = -mlx5e_set_port_pfc(priv);
3311                 /* restore previous value */
3312                 if (error != 0)
3313                         priv->params.tx_priority_flow_control= tx_pfc;
3314         }
3315         PRIV_UNLOCK(priv);
3316
3317         return (error);
3318 }
3319
3320 static int
3321 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3322 {
3323         struct mlx5e_priv *priv = arg1;
3324         uint32_t rx_pfc;
3325         uint32_t value;
3326         int error;
3327
3328         PRIV_LOCK(priv);
3329
3330         rx_pfc = priv->params.rx_priority_flow_control;
3331
3332         /* get current value */
3333         value = (rx_pfc >> arg2) & 1;
3334
3335         error = sysctl_handle_32(oidp, &value, 0, req);
3336
3337         /* range check value */
3338         if (value != 0)
3339                 priv->params.rx_priority_flow_control |= (1 << arg2);
3340         else
3341                 priv->params.rx_priority_flow_control &= ~(1 << arg2);
3342
3343         /* check if update is required */
3344         if (error == 0 && priv->gone == 0 &&
3345             rx_pfc != priv->params.rx_priority_flow_control) {
3346                 error = -mlx5e_set_port_pfc(priv);
3347                 /* restore previous value */
3348                 if (error != 0)
3349                         priv->params.rx_priority_flow_control= rx_pfc;
3350         }
3351         PRIV_UNLOCK(priv);
3352
3353         return (error);
3354 }
3355
3356 static void
3357 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
3358 {
3359         unsigned int x;
3360         char path[96];
3361         int error;
3362
3363         /* Only receiving pauseframes is enabled by default */
3364         priv->params.tx_pauseframe_control = 0;
3365         priv->params.rx_pauseframe_control = 1;
3366
3367         /* disable ports flow control, PFC, by default */
3368         priv->params.tx_priority_flow_control = 0;
3369         priv->params.rx_priority_flow_control = 0;
3370
3371 #if (__FreeBSD_version < 1100000)
3372         /* compute path for sysctl */
3373         snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
3374             device_get_unit(priv->mdev->pdev->dev.bsddev));
3375
3376         /* try to fetch tunable, if any */
3377         TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
3378
3379         /* compute path for sysctl */
3380         snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
3381             device_get_unit(priv->mdev->pdev->dev.bsddev));
3382
3383         /* try to fetch tunable, if any */
3384         TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
3385
3386         for (x = 0; x != 8; x++) {
3387
3388                 /* compute path for sysctl */
3389                 snprintf(path, sizeof(path), "dev.mce.%d.tx_priority_flow_control_%u",
3390                     device_get_unit(priv->mdev->pdev->dev.bsddev), x);
3391
3392                 /* try to fetch tunable, if any */
3393                 if (TUNABLE_INT_FETCH(path, &value) == 0 && value != 0)
3394                         priv->params.tx_priority_flow_control |= 1 << x;
3395
3396                 /* compute path for sysctl */
3397                 snprintf(path, sizeof(path), "dev.mce.%d.rx_priority_flow_control_%u",
3398                     device_get_unit(priv->mdev->pdev->dev.bsddev), x);
3399
3400                 /* try to fetch tunable, if any */
3401                 if (TUNABLE_INT_FETCH(path, &value) == 0 && value != 0)
3402                         priv->params.rx_priority_flow_control |= 1 << x;
3403         }
3404 #endif
3405
3406         /* register pauseframe SYSCTLs */
3407         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3408             OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
3409             &priv->params.tx_pauseframe_control, 0,
3410             "Set to enable TX pause frames. Clear to disable.");
3411
3412         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3413             OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
3414             &priv->params.rx_pauseframe_control, 0,
3415             "Set to enable RX pause frames. Clear to disable.");
3416
3417         /* register priority_flow control, PFC, SYSCTLs */
3418         for (x = 0; x != 8; x++) {
3419                 snprintf(path, sizeof(path), "tx_priority_flow_control_%u", x);
3420
3421                 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3422                     OID_AUTO, path, CTLTYPE_UINT | CTLFLAG_RWTUN |
3423                     CTLFLAG_MPSAFE, priv, x, &mlx5e_sysctl_tx_priority_flow_control, "IU",
3424                     "Set to enable TX ports flow control frames for given priority. Clear to disable.");
3425
3426                 snprintf(path, sizeof(path), "rx_priority_flow_control_%u", x);
3427
3428                 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3429                     OID_AUTO, path, CTLTYPE_UINT | CTLFLAG_RWTUN |
3430                     CTLFLAG_MPSAFE, priv, x, &mlx5e_sysctl_rx_priority_flow_control, "IU",
3431                     "Set to enable RX ports flow control frames for given priority. Clear to disable.");
3432         }
3433
3434         PRIV_LOCK(priv);
3435
3436         /* range check */
3437         priv->params.tx_pauseframe_control =
3438             priv->params.tx_pauseframe_control ? 1 : 0;
3439         priv->params.rx_pauseframe_control =
3440             priv->params.rx_pauseframe_control ? 1 : 0;
3441
3442         /* update firmware */
3443         error = mlx5e_set_port_pause_and_pfc(priv);
3444         if (error == -EINVAL) {
3445                 if_printf(priv->ifp,
3446                     "Global pauseframes must be disabled before enabling PFC.\n");
3447                 priv->params.rx_priority_flow_control = 0;
3448                 priv->params.tx_priority_flow_control = 0;
3449
3450                 /* update firmware */
3451                 (void) mlx5e_set_port_pause_and_pfc(priv);
3452         }
3453         PRIV_UNLOCK(priv);
3454 }
3455
3456 static void *
3457 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
3458 {
3459         struct ifnet *ifp;
3460         struct mlx5e_priv *priv;
3461         u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
3462         struct sysctl_oid_list *child;
3463         int ncv = mdev->priv.eq_table.num_comp_vectors;
3464         char unit[16];
3465         int err;
3466         int i;
3467         u32 eth_proto_cap;
3468
3469         if (mlx5e_check_required_hca_cap(mdev)) {
3470                 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
3471                 return (NULL);
3472         }
3473         priv = malloc(sizeof(*priv), M_MLX5EN, M_WAITOK | M_ZERO);
3474         mlx5e_priv_mtx_init(priv);
3475
3476         ifp = priv->ifp = if_alloc(IFT_ETHER);
3477         if (ifp == NULL) {
3478                 mlx5_core_err(mdev, "if_alloc() failed\n");
3479                 goto err_free_priv;
3480         }
3481         ifp->if_softc = priv;
3482         if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev));
3483         ifp->if_mtu = ETHERMTU;
3484         ifp->if_init = mlx5e_open;
3485         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
3486         ifp->if_ioctl = mlx5e_ioctl;
3487         ifp->if_transmit = mlx5e_xmit;
3488         ifp->if_qflush = if_qflush;
3489 #if (__FreeBSD_version >= 1100000)
3490         ifp->if_get_counter = mlx5e_get_counter;
3491 #endif
3492         ifp->if_snd.ifq_maxlen = ifqmaxlen;
3493         /*
3494          * Set driver features
3495          */
3496         ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
3497         ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
3498         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
3499         ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
3500         ifp->if_capabilities |= IFCAP_LRO;
3501         ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
3502         ifp->if_capabilities |= IFCAP_HWSTATS | IFCAP_HWRXTSTMP;
3503
3504         /* set TSO limits so that we don't have to drop TX packets */
3505         ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
3506         ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
3507         ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
3508
3509         ifp->if_capenable = ifp->if_capabilities;
3510         ifp->if_hwassist = 0;
3511         if (ifp->if_capenable & IFCAP_TSO)
3512                 ifp->if_hwassist |= CSUM_TSO;
3513         if (ifp->if_capenable & IFCAP_TXCSUM)
3514                 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
3515         if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
3516                 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3517
3518         /* ifnet sysctl tree */
3519         sysctl_ctx_init(&priv->sysctl_ctx);
3520         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
3521             OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
3522         if (priv->sysctl_ifnet == NULL) {
3523                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3524                 goto err_free_sysctl;
3525         }
3526         snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
3527         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3528             OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
3529         if (priv->sysctl_ifnet == NULL) {
3530                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3531                 goto err_free_sysctl;
3532         }
3533
3534         /* HW sysctl tree */
3535         child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
3536         priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
3537             OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
3538         if (priv->sysctl_hw == NULL) {
3539                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3540                 goto err_free_sysctl;
3541         }
3542         mlx5e_build_ifp_priv(mdev, priv, ncv);
3543
3544         snprintf(unit, sizeof(unit), "mce%u_wq",
3545             device_get_unit(mdev->pdev->dev.bsddev));
3546         priv->wq = alloc_workqueue(unit, 0, 1);
3547         if (priv->wq == NULL) {
3548                 if_printf(ifp, "%s: alloc_workqueue failed\n", __func__);
3549                 goto err_free_sysctl;
3550         }
3551
3552         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
3553         if (err) {
3554                 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n",
3555                     __func__, err);
3556                 goto err_free_wq;
3557         }
3558         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
3559         if (err) {
3560                 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n",
3561                     __func__, err);
3562                 goto err_unmap_free_uar;
3563         }
3564         err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
3565         if (err) {
3566                 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n",
3567                     __func__, err);
3568                 goto err_dealloc_pd;
3569         }
3570         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
3571         if (err) {
3572                 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n",
3573                     __func__, err);
3574                 goto err_dealloc_transport_domain;
3575         }
3576         mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
3577
3578         /* check if we should generate a random MAC address */
3579         if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
3580             is_zero_ether_addr(dev_addr)) {
3581                 random_ether_addr(dev_addr);
3582                 if_printf(ifp, "Assigned random MAC address\n");
3583         }
3584
3585         /* set default MTU */
3586         mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
3587
3588         /* Set desc */
3589         device_set_desc(mdev->pdev->dev.bsddev, mlx5e_version);
3590
3591         /* Set default media status */
3592         priv->media_status_last = IFM_AVALID;
3593         priv->media_active_last = IFM_ETHER | IFM_AUTO |
3594             IFM_ETH_RXPAUSE | IFM_FDX;
3595
3596         /* setup default pauseframes configuration */
3597         mlx5e_setup_pauseframes(priv);
3598
3599         err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
3600         if (err) {
3601                 eth_proto_cap = 0;
3602                 if_printf(ifp, "%s: Query port media capability failed, %d\n",
3603                     __func__, err);
3604         }
3605
3606         /* Setup supported medias */
3607         ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
3608             mlx5e_media_change, mlx5e_media_status);
3609
3610         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
3611                 if (mlx5e_mode_table[i].baudrate == 0)
3612                         continue;
3613                 if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
3614                         ifmedia_add(&priv->media,
3615                             mlx5e_mode_table[i].subtype |
3616                             IFM_ETHER, 0, NULL);
3617                         ifmedia_add(&priv->media,
3618                             mlx5e_mode_table[i].subtype |
3619                             IFM_ETHER | IFM_FDX |
3620                             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3621                 }
3622         }
3623
3624         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
3625         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3626             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3627
3628         /* Set autoselect by default */
3629         ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3630             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
3631         ether_ifattach(ifp, dev_addr);
3632
3633         /* Register for VLAN events */
3634         priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
3635             mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
3636         priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
3637             mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
3638
3639         /* Link is down by default */
3640         if_link_state_change(ifp, LINK_STATE_DOWN);
3641
3642         mlx5e_enable_async_events(priv);
3643
3644         mlx5e_add_hw_stats(priv);
3645
3646         mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3647             "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
3648             priv->stats.vport.arg);
3649
3650         mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3651             "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
3652             priv->stats.pport.arg);
3653
3654         mlx5e_create_ethtool(priv);
3655
3656         mtx_lock(&priv->async_events_mtx);
3657         mlx5e_update_stats(priv);
3658         mtx_unlock(&priv->async_events_mtx);
3659
3660         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3661             OID_AUTO, "rx_clbr_done", CTLFLAG_RD,
3662             &priv->clbr_done, 0,
3663             "RX timestamps calibration state");
3664         callout_init(&priv->tstmp_clbr, CALLOUT_DIRECT);
3665         mlx5e_reset_calibration_callout(priv);
3666
3667         return (priv);
3668
3669 err_dealloc_transport_domain:
3670         mlx5_dealloc_transport_domain(mdev, priv->tdn);
3671
3672 err_dealloc_pd:
3673         mlx5_core_dealloc_pd(mdev, priv->pdn);
3674
3675 err_unmap_free_uar:
3676         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3677
3678 err_free_wq:
3679         destroy_workqueue(priv->wq);
3680
3681 err_free_sysctl:
3682         sysctl_ctx_free(&priv->sysctl_ctx);
3683
3684         if_free(ifp);
3685
3686 err_free_priv:
3687         mlx5e_priv_mtx_destroy(priv);
3688         free(priv, M_MLX5EN);
3689         return (NULL);
3690 }
3691
3692 static void
3693 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
3694 {
3695         struct mlx5e_priv *priv = vpriv;
3696         struct ifnet *ifp = priv->ifp;
3697
3698         /* don't allow more IOCTLs */
3699         priv->gone = 1;
3700
3701         /*
3702          * Clear the device description to avoid use after free,
3703          * because the bsddev is not destroyed when this module is
3704          * unloaded:
3705          */
3706         device_set_desc(mdev->pdev->dev.bsddev, NULL);
3707
3708         /* XXX wait a bit to allow IOCTL handlers to complete */
3709         pause("W", hz);
3710
3711         /* stop watchdog timer */
3712         callout_drain(&priv->watchdog);
3713
3714         callout_drain(&priv->tstmp_clbr);
3715
3716         if (priv->vlan_attach != NULL)
3717                 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
3718         if (priv->vlan_detach != NULL)
3719                 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
3720
3721         /* make sure device gets closed */
3722         PRIV_LOCK(priv);
3723         mlx5e_close_locked(ifp);
3724         PRIV_UNLOCK(priv);
3725
3726         /* unregister device */
3727         ifmedia_removeall(&priv->media);
3728         ether_ifdetach(ifp);
3729         if_free(ifp);
3730
3731         /* destroy all remaining sysctl nodes */
3732         if (priv->sysctl_debug)
3733                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
3734         sysctl_ctx_free(&priv->stats.vport.ctx);
3735         sysctl_ctx_free(&priv->stats.pport.ctx);
3736         sysctl_ctx_free(&priv->sysctl_ctx);
3737
3738         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
3739         mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
3740         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3741         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
3742         mlx5e_disable_async_events(priv);
3743         destroy_workqueue(priv->wq);
3744         mlx5e_priv_mtx_destroy(priv);
3745         free(priv, M_MLX5EN);
3746 }
3747
3748 static void *
3749 mlx5e_get_ifp(void *vpriv)
3750 {
3751         struct mlx5e_priv *priv = vpriv;
3752
3753         return (priv->ifp);
3754 }
3755
3756 static struct mlx5_interface mlx5e_interface = {
3757         .add = mlx5e_create_ifp,
3758         .remove = mlx5e_destroy_ifp,
3759         .event = mlx5e_async_event,
3760         .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3761         .get_dev = mlx5e_get_ifp,
3762 };
3763
3764 void
3765 mlx5e_init(void)
3766 {
3767         mlx5_register_interface(&mlx5e_interface);
3768 }
3769
3770 void
3771 mlx5e_cleanup(void)
3772 {
3773         mlx5_unregister_interface(&mlx5e_interface);
3774 }
3775
3776 module_init_order(mlx5e_init, SI_ORDER_THIRD);
3777 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
3778
3779 #if (__FreeBSD_version >= 1100000)
3780 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
3781 #endif
3782 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
3783 MODULE_VERSION(mlx5en, 1);