2 * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/eventhandler.h>
31 #include <sys/sockio.h>
32 #include <machine/atomic.h>
34 #ifndef ETH_DRIVER_VERSION
35 #define ETH_DRIVER_VERSION "3.5.2"
37 #define DRIVER_RELDATE "September 2019"
39 static const char mlx5e_version[] = "mlx5en: Mellanox Ethernet driver "
40 ETH_DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
42 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs);
44 struct mlx5e_channel_param {
45 struct mlx5e_rq_param rq;
46 struct mlx5e_sq_param sq;
47 struct mlx5e_cq_param rx_cq;
48 struct mlx5e_cq_param tx_cq;
56 static const struct media mlx5e_mode_table[MLX5E_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = {
58 [MLX5E_1000BASE_CX_SGMII][MLX5E_SGMII] = {
59 .subtype = IFM_1000_CX_SGMII,
60 .baudrate = IF_Mbps(1000ULL),
62 [MLX5E_1000BASE_KX][MLX5E_KX] = {
63 .subtype = IFM_1000_KX,
64 .baudrate = IF_Mbps(1000ULL),
66 [MLX5E_10GBASE_CX4][MLX5E_CX4] = {
67 .subtype = IFM_10G_CX4,
68 .baudrate = IF_Gbps(10ULL),
70 [MLX5E_10GBASE_KX4][MLX5E_KX4] = {
71 .subtype = IFM_10G_KX4,
72 .baudrate = IF_Gbps(10ULL),
74 [MLX5E_10GBASE_KR][MLX5E_KR] = {
75 .subtype = IFM_10G_KR,
76 .baudrate = IF_Gbps(10ULL),
78 [MLX5E_20GBASE_KR2][MLX5E_KR2] = {
79 .subtype = IFM_20G_KR2,
80 .baudrate = IF_Gbps(20ULL),
82 [MLX5E_40GBASE_CR4][MLX5E_CR4] = {
83 .subtype = IFM_40G_CR4,
84 .baudrate = IF_Gbps(40ULL),
86 [MLX5E_40GBASE_KR4][MLX5E_KR4] = {
87 .subtype = IFM_40G_KR4,
88 .baudrate = IF_Gbps(40ULL),
90 [MLX5E_56GBASE_R4][MLX5E_R] = {
91 .subtype = IFM_56G_R4,
92 .baudrate = IF_Gbps(56ULL),
94 [MLX5E_10GBASE_CR][MLX5E_CR1] = {
95 .subtype = IFM_10G_CR1,
96 .baudrate = IF_Gbps(10ULL),
98 [MLX5E_10GBASE_SR][MLX5E_SR] = {
99 .subtype = IFM_10G_SR,
100 .baudrate = IF_Gbps(10ULL),
102 [MLX5E_10GBASE_ER_LR][MLX5E_ER] = {
103 .subtype = IFM_10G_ER,
104 .baudrate = IF_Gbps(10ULL),
106 [MLX5E_10GBASE_ER_LR][MLX5E_LR] = {
107 .subtype = IFM_10G_LR,
108 .baudrate = IF_Gbps(10ULL),
110 [MLX5E_40GBASE_SR4][MLX5E_SR4] = {
111 .subtype = IFM_40G_SR4,
112 .baudrate = IF_Gbps(40ULL),
114 [MLX5E_40GBASE_LR4_ER4][MLX5E_LR4] = {
115 .subtype = IFM_40G_LR4,
116 .baudrate = IF_Gbps(40ULL),
118 [MLX5E_40GBASE_LR4_ER4][MLX5E_ER4] = {
119 .subtype = IFM_40G_ER4,
120 .baudrate = IF_Gbps(40ULL),
122 [MLX5E_100GBASE_CR4][MLX5E_CR4] = {
123 .subtype = IFM_100G_CR4,
124 .baudrate = IF_Gbps(100ULL),
126 [MLX5E_100GBASE_SR4][MLX5E_SR4] = {
127 .subtype = IFM_100G_SR4,
128 .baudrate = IF_Gbps(100ULL),
130 [MLX5E_100GBASE_KR4][MLX5E_KR4] = {
131 .subtype = IFM_100G_KR4,
132 .baudrate = IF_Gbps(100ULL),
134 [MLX5E_100GBASE_LR4][MLX5E_LR4] = {
135 .subtype = IFM_100G_LR4,
136 .baudrate = IF_Gbps(100ULL),
138 [MLX5E_100BASE_TX][MLX5E_TX] = {
139 .subtype = IFM_100_TX,
140 .baudrate = IF_Mbps(100ULL),
142 [MLX5E_1000BASE_T][MLX5E_T] = {
143 .subtype = IFM_1000_T,
144 .baudrate = IF_Mbps(1000ULL),
146 [MLX5E_10GBASE_T][MLX5E_T] = {
147 .subtype = IFM_10G_T,
148 .baudrate = IF_Gbps(10ULL),
150 [MLX5E_25GBASE_CR][MLX5E_CR] = {
151 .subtype = IFM_25G_CR,
152 .baudrate = IF_Gbps(25ULL),
154 [MLX5E_25GBASE_KR][MLX5E_KR] = {
155 .subtype = IFM_25G_KR,
156 .baudrate = IF_Gbps(25ULL),
158 [MLX5E_25GBASE_SR][MLX5E_SR] = {
159 .subtype = IFM_25G_SR,
160 .baudrate = IF_Gbps(25ULL),
162 [MLX5E_50GBASE_CR2][MLX5E_CR2] = {
163 .subtype = IFM_50G_CR2,
164 .baudrate = IF_Gbps(50ULL),
166 [MLX5E_50GBASE_KR2][MLX5E_KR2] = {
167 .subtype = IFM_50G_KR2,
168 .baudrate = IF_Gbps(50ULL),
172 static const struct media mlx5e_ext_mode_table[MLX5E_EXT_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = {
173 [MLX5E_SGMII_100M][MLX5E_SGMII] = {
174 .subtype = IFM_100_SGMII,
175 .baudrate = IF_Mbps(100),
177 [MLX5E_1000BASE_X_SGMII][MLX5E_KX] = {
178 .subtype = IFM_1000_KX,
179 .baudrate = IF_Mbps(1000),
181 [MLX5E_1000BASE_X_SGMII][MLX5E_CX_SGMII] = {
182 .subtype = IFM_1000_CX_SGMII,
183 .baudrate = IF_Mbps(1000),
185 [MLX5E_1000BASE_X_SGMII][MLX5E_CX] = {
186 .subtype = IFM_1000_CX,
187 .baudrate = IF_Mbps(1000),
189 [MLX5E_1000BASE_X_SGMII][MLX5E_LX] = {
190 .subtype = IFM_1000_LX,
191 .baudrate = IF_Mbps(1000),
193 [MLX5E_1000BASE_X_SGMII][MLX5E_SX] = {
194 .subtype = IFM_1000_SX,
195 .baudrate = IF_Mbps(1000),
197 [MLX5E_1000BASE_X_SGMII][MLX5E_T] = {
198 .subtype = IFM_1000_T,
199 .baudrate = IF_Mbps(1000),
201 [MLX5E_5GBASE_R][MLX5E_T] = {
202 .subtype = IFM_5000_T,
203 .baudrate = IF_Mbps(5000),
205 [MLX5E_5GBASE_R][MLX5E_KR] = {
206 .subtype = IFM_5000_KR,
207 .baudrate = IF_Mbps(5000),
209 [MLX5E_5GBASE_R][MLX5E_KR1] = {
210 .subtype = IFM_5000_KR1,
211 .baudrate = IF_Mbps(5000),
213 [MLX5E_5GBASE_R][MLX5E_KR_S] = {
214 .subtype = IFM_5000_KR_S,
215 .baudrate = IF_Mbps(5000),
217 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_ER] = {
218 .subtype = IFM_10G_ER,
219 .baudrate = IF_Gbps(10ULL),
221 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_KR] = {
222 .subtype = IFM_10G_KR,
223 .baudrate = IF_Gbps(10ULL),
225 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_LR] = {
226 .subtype = IFM_10G_LR,
227 .baudrate = IF_Gbps(10ULL),
229 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_SR] = {
230 .subtype = IFM_10G_SR,
231 .baudrate = IF_Gbps(10ULL),
233 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_T] = {
234 .subtype = IFM_10G_T,
235 .baudrate = IF_Gbps(10ULL),
237 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_AOC] = {
238 .subtype = IFM_10G_AOC,
239 .baudrate = IF_Gbps(10ULL),
241 [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CR1] = {
242 .subtype = IFM_10G_CR1,
243 .baudrate = IF_Gbps(10ULL),
245 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CR4] = {
246 .subtype = IFM_40G_CR4,
247 .baudrate = IF_Gbps(40ULL),
249 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_KR4] = {
250 .subtype = IFM_40G_KR4,
251 .baudrate = IF_Gbps(40ULL),
253 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_LR4] = {
254 .subtype = IFM_40G_LR4,
255 .baudrate = IF_Gbps(40ULL),
257 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_SR4] = {
258 .subtype = IFM_40G_SR4,
259 .baudrate = IF_Gbps(40ULL),
261 [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_ER4] = {
262 .subtype = IFM_40G_ER4,
263 .baudrate = IF_Gbps(40ULL),
266 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR] = {
267 .subtype = IFM_25G_CR,
268 .baudrate = IF_Gbps(25ULL),
270 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR] = {
271 .subtype = IFM_25G_KR,
272 .baudrate = IF_Gbps(25ULL),
274 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_SR] = {
275 .subtype = IFM_25G_SR,
276 .baudrate = IF_Gbps(25ULL),
278 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_ACC] = {
279 .subtype = IFM_25G_ACC,
280 .baudrate = IF_Gbps(25ULL),
282 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_AOC] = {
283 .subtype = IFM_25G_AOC,
284 .baudrate = IF_Gbps(25ULL),
286 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR1] = {
287 .subtype = IFM_25G_CR1,
288 .baudrate = IF_Gbps(25ULL),
290 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR_S] = {
291 .subtype = IFM_25G_CR_S,
292 .baudrate = IF_Gbps(25ULL),
294 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR1] = {
295 .subtype = IFM_5000_KR1,
296 .baudrate = IF_Gbps(25ULL),
298 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR_S] = {
299 .subtype = IFM_25G_KR_S,
300 .baudrate = IF_Gbps(25ULL),
302 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_LR] = {
303 .subtype = IFM_25G_LR,
304 .baudrate = IF_Gbps(25ULL),
306 [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_T] = {
307 .subtype = IFM_25G_T,
308 .baudrate = IF_Gbps(25ULL),
310 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CR2] = {
311 .subtype = IFM_50G_CR2,
312 .baudrate = IF_Gbps(50ULL),
314 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_KR2] = {
315 .subtype = IFM_50G_KR2,
316 .baudrate = IF_Gbps(50ULL),
318 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_SR2] = {
319 .subtype = IFM_50G_SR2,
320 .baudrate = IF_Gbps(50ULL),
322 [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_LR2] = {
323 .subtype = IFM_50G_LR2,
324 .baudrate = IF_Gbps(50ULL),
326 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_LR] = {
327 .subtype = IFM_50G_LR,
328 .baudrate = IF_Gbps(50ULL),
330 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_SR] = {
331 .subtype = IFM_50G_SR,
332 .baudrate = IF_Gbps(50ULL),
334 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CP] = {
335 .subtype = IFM_50G_CP,
336 .baudrate = IF_Gbps(50ULL),
338 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_FR] = {
339 .subtype = IFM_50G_FR,
340 .baudrate = IF_Gbps(50ULL),
342 [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_KR_PAM4] = {
343 .subtype = IFM_50G_KR_PAM4,
344 .baudrate = IF_Gbps(50ULL),
346 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CR4] = {
347 .subtype = IFM_100G_CR4,
348 .baudrate = IF_Gbps(100ULL),
350 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_KR4] = {
351 .subtype = IFM_100G_KR4,
352 .baudrate = IF_Gbps(100ULL),
354 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_LR4] = {
355 .subtype = IFM_100G_LR4,
356 .baudrate = IF_Gbps(100ULL),
358 [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_SR4] = {
359 .subtype = IFM_100G_SR4,
360 .baudrate = IF_Gbps(100ULL),
362 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_SR2] = {
363 .subtype = IFM_100G_SR2,
364 .baudrate = IF_Gbps(100ULL),
366 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CP2] = {
367 .subtype = IFM_100G_CP2,
368 .baudrate = IF_Gbps(100ULL),
370 [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_KR2_PAM4] = {
371 .subtype = IFM_100G_KR2_PAM4,
372 .baudrate = IF_Gbps(100ULL),
374 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_DR4] = {
375 .subtype = IFM_200G_DR4,
376 .baudrate = IF_Gbps(200ULL),
378 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_LR4] = {
379 .subtype = IFM_200G_LR4,
380 .baudrate = IF_Gbps(200ULL),
382 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_SR4] = {
383 .subtype = IFM_200G_SR4,
384 .baudrate = IF_Gbps(200ULL),
386 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_FR4] = {
387 .subtype = IFM_200G_FR4,
388 .baudrate = IF_Gbps(200ULL),
390 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CR4_PAM4] = {
391 .subtype = IFM_200G_CR4_PAM4,
392 .baudrate = IF_Gbps(200ULL),
394 [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_KR4_PAM4] = {
395 .subtype = IFM_200G_KR4_PAM4,
396 .baudrate = IF_Gbps(200ULL),
400 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
403 mlx5e_update_carrier(struct mlx5e_priv *priv)
405 struct mlx5_core_dev *mdev = priv->mdev;
406 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
413 struct media media_entry = {};
415 port_state = mlx5_query_vport_state(mdev,
416 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
418 if (port_state == VPORT_STATE_UP) {
419 priv->media_status_last |= IFM_ACTIVE;
421 priv->media_status_last &= ~IFM_ACTIVE;
422 priv->media_active_last = IFM_ETHER;
423 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
427 error = mlx5_query_port_ptys(mdev, out, sizeof(out),
430 priv->media_active_last = IFM_ETHER;
431 priv->ifp->if_baudrate = 1;
432 mlx5_en_err(priv->ifp, "query port ptys failed: 0x%x\n",
437 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
438 eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
441 i = ilog2(eth_proto_oper);
443 for (j = 0; j != MLX5E_LINK_MODES_NUMBER; j++) {
444 media_entry = ext ? mlx5e_ext_mode_table[i][j] :
445 mlx5e_mode_table[i][j];
446 if (media_entry.baudrate != 0)
450 if (media_entry.subtype == 0) {
451 mlx5_en_err(priv->ifp,
452 "Could not find operational media subtype\n");
456 switch (media_entry.subtype) {
458 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
460 mlx5_en_err(priv->ifp,
461 "query port pddr failed: %d\n", error);
463 if (error != 0 || is_er_type == 0)
464 media_entry.subtype = IFM_10G_LR;
467 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
469 mlx5_en_err(priv->ifp,
470 "query port pddr failed: %d\n", error);
472 if (error == 0 && is_er_type != 0)
473 media_entry.subtype = IFM_40G_ER4;
476 priv->media_active_last = media_entry.subtype | IFM_ETHER | IFM_FDX;
477 priv->ifp->if_baudrate = media_entry.baudrate;
479 if_link_state_change(priv->ifp, LINK_STATE_UP);
483 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
485 struct mlx5e_priv *priv = dev->if_softc;
487 ifmr->ifm_status = priv->media_status_last;
488 ifmr->ifm_active = priv->media_active_last |
489 (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
490 (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
495 mlx5e_find_link_mode(u32 subtype, bool ext)
501 struct media media_entry = {};
505 subtype = IFM_10G_ER;
508 subtype = IFM_40G_LR4;
512 speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER :
513 MLX5E_LINK_SPEEDS_NUMBER;
515 for (i = 0; i != speeds_num; i++) {
516 for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) {
517 media_entry = ext ? mlx5e_ext_mode_table[i][j] :
518 mlx5e_mode_table[i][j];
519 if (media_entry.baudrate == 0)
521 if (media_entry.subtype == subtype) {
522 link_mode |= MLX5E_PROT_MASK(i);
531 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv)
533 return (mlx5_set_port_pause_and_pfc(priv->mdev, 1,
534 priv->params.rx_pauseframe_control,
535 priv->params.tx_pauseframe_control,
536 priv->params.rx_priority_flow_control,
537 priv->params.tx_priority_flow_control));
541 mlx5e_set_port_pfc(struct mlx5e_priv *priv)
545 if (priv->gone != 0) {
547 } else if (priv->params.rx_pauseframe_control ||
548 priv->params.tx_pauseframe_control) {
549 mlx5_en_err(priv->ifp,
550 "Global pauseframes must be disabled before enabling PFC.\n");
553 error = mlx5e_set_port_pause_and_pfc(priv);
559 mlx5e_media_change(struct ifnet *dev)
561 struct mlx5e_priv *priv = dev->if_softc;
562 struct mlx5_core_dev *mdev = priv->mdev;
565 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
571 locked = PRIV_LOCKED(priv);
575 if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
580 error = mlx5_query_port_ptys(mdev, out, sizeof(out),
583 mlx5_en_err(dev, "Query port media capability failed\n");
587 ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
588 link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media), ext);
590 /* query supported capabilities */
591 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
592 eth_proto_capability);
594 /* check for autoselect */
595 if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
596 link_mode = eth_proto_cap;
597 if (link_mode == 0) {
598 mlx5_en_err(dev, "Port media capability is zero\n");
603 link_mode = link_mode & eth_proto_cap;
604 if (link_mode == 0) {
605 mlx5_en_err(dev, "Not supported link mode requested\n");
610 if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
611 /* check if PFC is enabled */
612 if (priv->params.rx_priority_flow_control ||
613 priv->params.tx_priority_flow_control) {
614 mlx5_en_err(dev, "PFC must be disabled before enabling global pauseframes.\n");
619 /* update pauseframe control bits */
620 priv->params.rx_pauseframe_control =
621 (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
622 priv->params.tx_pauseframe_control =
623 (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
625 /* check if device is opened */
626 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
628 /* reconfigure the hardware */
629 mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
630 mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN, ext);
631 error = -mlx5e_set_port_pause_and_pfc(priv);
633 mlx5_set_port_status(mdev, MLX5_PORT_UP);
642 mlx5e_update_carrier_work(struct work_struct *work)
644 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
645 update_carrier_work);
648 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
649 mlx5e_update_carrier(priv);
653 #define MLX5E_PCIE_PERF_GET_64(a,b,c,d,e,f) \
654 s_debug->c = MLX5_GET64(mpcnt_reg, out, counter_set.f.c);
656 #define MLX5E_PCIE_PERF_GET_32(a,b,c,d,e,f) \
657 s_debug->c = MLX5_GET(mpcnt_reg, out, counter_set.f.c);
660 mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
662 struct mlx5_core_dev *mdev = priv->mdev;
663 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
664 const unsigned sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
669 /* allocate firmware request structures */
670 in = mlx5_vzalloc(sz);
671 out = mlx5_vzalloc(sz);
672 if (in == NULL || out == NULL)
675 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
676 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
680 MLX5E_PCIE_PERFORMANCE_COUNTERS_64(MLX5E_PCIE_PERF_GET_64)
681 MLX5E_PCIE_PERFORMANCE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
683 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP);
684 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
688 MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
690 MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_LANE_COUNTERS_GROUP);
691 err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
695 MLX5E_PCIE_LANE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
698 /* free firmware request structures */
704 * This function reads the physical port counters from the firmware
705 * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
706 * macros. The output is converted from big-endian 64-bit values into
707 * host endian ones and stored in the "priv->stats.pport" structure.
710 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
712 struct mlx5_core_dev *mdev = priv->mdev;
713 struct mlx5e_pport_stats *s = &priv->stats.pport;
714 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
718 unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
723 /* allocate firmware request structures */
724 in = mlx5_vzalloc(sz);
725 out = mlx5_vzalloc(sz);
726 if (in == NULL || out == NULL)
730 * Get pointer to the 64-bit counter set which is located at a
731 * fixed offset in the output firmware request structure:
733 ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
735 MLX5_SET(ppcnt_reg, in, local_port, 1);
737 /* read IEEE802_3 counter group using predefined counter layout */
738 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
739 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
740 for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM;
741 x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
742 s->arg[y] = be64toh(ptr[x]);
744 /* read RFC2819 counter group using predefined counter layout */
745 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
746 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
747 for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
748 s->arg[y] = be64toh(ptr[x]);
750 for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
751 MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
752 s_debug->arg[y] = be64toh(ptr[x]);
754 /* read RFC2863 counter group using predefined counter layout */
755 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
756 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
757 for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
758 s_debug->arg[y] = be64toh(ptr[x]);
760 /* read physical layer stats counter group using predefined counter layout */
761 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
762 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
763 for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
764 s_debug->arg[y] = be64toh(ptr[x]);
766 /* read Extended Ethernet counter group using predefined counter layout */
767 MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
768 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
769 for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++)
770 s_debug->arg[y] = be64toh(ptr[x]);
772 /* read Extended Statistical Group */
773 if (MLX5_CAP_GEN(mdev, pcam_reg) &&
774 MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) &&
775 MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) {
776 /* read Extended Statistical counter group using predefined counter layout */
777 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
778 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
780 for (x = 0; x != MLX5E_PPORT_STATISTICAL_DEBUG_NUM; x++, y++)
781 s_debug->arg[y] = be64toh(ptr[x]);
784 /* read PCIE counters */
785 mlx5e_update_pcie_counters(priv);
787 /* read per-priority counters */
788 MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
790 /* iterate all the priorities */
791 for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) {
792 MLX5_SET(ppcnt_reg, in, prio_tc, z);
793 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
795 /* read per priority stats counter group using predefined counter layout */
796 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM /
797 MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++)
798 s->arg[y] = be64toh(ptr[x]);
802 /* free firmware request structures */
808 mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv)
810 u32 out[MLX5_ST_SZ_DW(query_vnic_env_out)] = {};
811 u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {};
813 if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
816 MLX5_SET(query_vnic_env_in, in, opcode,
817 MLX5_CMD_OP_QUERY_VNIC_ENV);
818 MLX5_SET(query_vnic_env_in, in, op_mod, 0);
819 MLX5_SET(query_vnic_env_in, in, other_vport, 0);
821 if (mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out)) != 0)
824 priv->stats.vport.rx_steer_missed_packets =
825 MLX5_GET64(query_vnic_env_out, out,
826 vport_env.nic_receive_steering_discard);
830 * This function is called regularly to collect all statistics
831 * counters from the firmware. The values can be viewed through the
832 * sysctl interface. Execution is serialized using the priv's global
833 * configuration lock.
836 mlx5e_update_stats_locked(struct mlx5e_priv *priv)
838 struct mlx5_core_dev *mdev = priv->mdev;
839 struct mlx5e_vport_stats *s = &priv->stats.vport;
840 struct mlx5e_sq_stats *sq_stats;
841 struct buf_ring *sq_br;
842 #if (__FreeBSD_version < 1100000)
843 struct ifnet *ifp = priv->ifp;
846 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
848 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
851 u64 tx_queue_dropped = 0;
852 u64 tx_defragged = 0;
853 u64 tx_offload_none = 0;
856 u64 sw_lro_queued = 0;
857 u64 sw_lro_flushed = 0;
858 u64 rx_csum_none = 0;
862 u32 rx_out_of_buffer = 0;
867 out = mlx5_vzalloc(outlen);
871 /* Collect firts the SW counters and then HW for consistency */
872 for (i = 0; i < priv->params.num_channels; i++) {
873 struct mlx5e_channel *pch = priv->channel + i;
874 struct mlx5e_rq *rq = &pch->rq;
875 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats;
877 /* collect stats from LRO */
878 rq_stats->sw_lro_queued = rq->lro.lro_queued;
879 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
880 sw_lro_queued += rq_stats->sw_lro_queued;
881 sw_lro_flushed += rq_stats->sw_lro_flushed;
882 lro_packets += rq_stats->lro_packets;
883 lro_bytes += rq_stats->lro_bytes;
884 rx_csum_none += rq_stats->csum_none;
885 rx_wqe_err += rq_stats->wqe_err;
886 rx_packets += rq_stats->packets;
887 rx_bytes += rq_stats->bytes;
889 for (j = 0; j < priv->num_tc; j++) {
890 sq_stats = &pch->sq[j].stats;
891 sq_br = pch->sq[j].br;
893 tso_packets += sq_stats->tso_packets;
894 tso_bytes += sq_stats->tso_bytes;
895 tx_queue_dropped += sq_stats->dropped;
897 tx_queue_dropped += sq_br->br_drops;
898 tx_defragged += sq_stats->defragged;
899 tx_offload_none += sq_stats->csum_offload_none;
903 /* update counters */
904 s->tso_packets = tso_packets;
905 s->tso_bytes = tso_bytes;
906 s->tx_queue_dropped = tx_queue_dropped;
907 s->tx_defragged = tx_defragged;
908 s->lro_packets = lro_packets;
909 s->lro_bytes = lro_bytes;
910 s->sw_lro_queued = sw_lro_queued;
911 s->sw_lro_flushed = sw_lro_flushed;
912 s->rx_csum_none = rx_csum_none;
913 s->rx_wqe_err = rx_wqe_err;
914 s->rx_packets = rx_packets;
915 s->rx_bytes = rx_bytes;
917 mlx5e_grp_vnic_env_update_stats(priv);
920 memset(in, 0, sizeof(in));
922 MLX5_SET(query_vport_counter_in, in, opcode,
923 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
924 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
925 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
927 memset(out, 0, outlen);
929 /* get number of out-of-buffer drops first */
930 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 &&
931 mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
932 &rx_out_of_buffer) == 0) {
933 s->rx_out_of_buffer = rx_out_of_buffer;
936 /* get port statistics */
937 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen) == 0) {
938 #define MLX5_GET_CTR(out, x) \
939 MLX5_GET64(query_vport_counter_out, out, x)
941 s->rx_error_packets =
942 MLX5_GET_CTR(out, received_errors.packets);
944 MLX5_GET_CTR(out, received_errors.octets);
945 s->tx_error_packets =
946 MLX5_GET_CTR(out, transmit_errors.packets);
948 MLX5_GET_CTR(out, transmit_errors.octets);
950 s->rx_unicast_packets =
951 MLX5_GET_CTR(out, received_eth_unicast.packets);
952 s->rx_unicast_bytes =
953 MLX5_GET_CTR(out, received_eth_unicast.octets);
954 s->tx_unicast_packets =
955 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
956 s->tx_unicast_bytes =
957 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
959 s->rx_multicast_packets =
960 MLX5_GET_CTR(out, received_eth_multicast.packets);
961 s->rx_multicast_bytes =
962 MLX5_GET_CTR(out, received_eth_multicast.octets);
963 s->tx_multicast_packets =
964 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
965 s->tx_multicast_bytes =
966 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
968 s->rx_broadcast_packets =
969 MLX5_GET_CTR(out, received_eth_broadcast.packets);
970 s->rx_broadcast_bytes =
971 MLX5_GET_CTR(out, received_eth_broadcast.octets);
972 s->tx_broadcast_packets =
973 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
974 s->tx_broadcast_bytes =
975 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
977 s->tx_packets = s->tx_unicast_packets +
978 s->tx_multicast_packets + s->tx_broadcast_packets;
979 s->tx_bytes = s->tx_unicast_bytes + s->tx_multicast_bytes +
980 s->tx_broadcast_bytes;
982 /* Update calculated offload counters */
983 s->tx_csum_offload = s->tx_packets - tx_offload_none;
984 s->rx_csum_good = s->rx_packets - s->rx_csum_none;
987 /* Get physical port counters */
988 mlx5e_update_pport_counters(priv);
990 s->tx_jumbo_packets =
991 priv->stats.port_stats_debug.tx_stat_p1519to2047octets +
992 priv->stats.port_stats_debug.tx_stat_p2048to4095octets +
993 priv->stats.port_stats_debug.tx_stat_p4096to8191octets +
994 priv->stats.port_stats_debug.tx_stat_p8192to10239octets;
996 #if (__FreeBSD_version < 1100000)
997 /* no get_counters interface in fbsd 10 */
998 ifp->if_ipackets = s->rx_packets;
999 ifp->if_ierrors = priv->stats.pport.in_range_len_errors +
1000 priv->stats.pport.out_of_range_len +
1001 priv->stats.pport.too_long_errors +
1002 priv->stats.pport.check_seq_err +
1003 priv->stats.pport.alignment_err;
1004 ifp->if_iqdrops = s->rx_out_of_buffer;
1005 ifp->if_opackets = s->tx_packets;
1006 ifp->if_oerrors = priv->stats.port_stats_debug.out_discards;
1007 ifp->if_snd.ifq_drops = s->tx_queue_dropped;
1008 ifp->if_ibytes = s->rx_bytes;
1009 ifp->if_obytes = s->tx_bytes;
1010 ifp->if_collisions =
1011 priv->stats.pport.collisions;
1017 /* Update diagnostics, if any */
1018 if (priv->params_ethtool.diag_pci_enable ||
1019 priv->params_ethtool.diag_general_enable) {
1020 error = mlx5_core_get_diagnostics_full(mdev,
1021 priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL,
1022 priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL);
1024 mlx5_en_err(priv->ifp,
1025 "Failed reading diagnostics: %d\n", error);
1028 /* Update FEC, if any */
1029 error = mlx5e_fec_update(priv);
1030 if (error != 0 && error != EOPNOTSUPP) {
1031 mlx5_en_err(priv->ifp,
1032 "Updating FEC failed: %d\n", error);
1037 mlx5e_update_stats_work(struct work_struct *work)
1039 struct mlx5e_priv *priv;
1041 priv = container_of(work, struct mlx5e_priv, update_stats_work);
1043 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
1044 mlx5e_update_stats_locked(priv);
1049 mlx5e_update_stats(void *arg)
1051 struct mlx5e_priv *priv = arg;
1053 queue_work(priv->wq, &priv->update_stats_work);
1055 callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
1059 mlx5e_async_event_sub(struct mlx5e_priv *priv,
1060 enum mlx5_dev_event event)
1063 case MLX5_DEV_EVENT_PORT_UP:
1064 case MLX5_DEV_EVENT_PORT_DOWN:
1065 queue_work(priv->wq, &priv->update_carrier_work);
1074 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
1075 enum mlx5_dev_event event, unsigned long param)
1077 struct mlx5e_priv *priv = vpriv;
1079 mtx_lock(&priv->async_events_mtx);
1080 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
1081 mlx5e_async_event_sub(priv, event);
1082 mtx_unlock(&priv->async_events_mtx);
1086 mlx5e_enable_async_events(struct mlx5e_priv *priv)
1088 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
1092 mlx5e_disable_async_events(struct mlx5e_priv *priv)
1094 mtx_lock(&priv->async_events_mtx);
1095 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
1096 mtx_unlock(&priv->async_events_mtx);
1099 static void mlx5e_calibration_callout(void *arg);
1100 static int mlx5e_calibration_duration = 20;
1101 static int mlx5e_fast_calibration = 1;
1102 static int mlx5e_normal_calibration = 30;
1104 static SYSCTL_NODE(_hw_mlx5, OID_AUTO, calibr, CTLFLAG_RW, 0,
1105 "MLX5 timestamp calibration parameteres");
1107 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, duration, CTLFLAG_RWTUN,
1108 &mlx5e_calibration_duration, 0,
1109 "Duration of initial calibration");
1110 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, fast, CTLFLAG_RWTUN,
1111 &mlx5e_fast_calibration, 0,
1112 "Recalibration interval during initial calibration");
1113 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, normal, CTLFLAG_RWTUN,
1114 &mlx5e_normal_calibration, 0,
1115 "Recalibration interval during normal operations");
1118 * Ignites the calibration process.
1121 mlx5e_reset_calibration_callout(struct mlx5e_priv *priv)
1124 if (priv->clbr_done == 0)
1125 mlx5e_calibration_callout(priv);
1127 callout_reset_curcpu(&priv->tstmp_clbr, (priv->clbr_done <
1128 mlx5e_calibration_duration ? mlx5e_fast_calibration :
1129 mlx5e_normal_calibration) * hz, mlx5e_calibration_callout,
1134 mlx5e_timespec2usec(const struct timespec *ts)
1137 return ((uint64_t)ts->tv_sec * 1000000000 + ts->tv_nsec);
1141 mlx5e_hw_clock(struct mlx5e_priv *priv)
1143 struct mlx5_init_seg *iseg;
1144 uint32_t hw_h, hw_h1, hw_l;
1146 iseg = priv->mdev->iseg;
1148 hw_h = ioread32be(&iseg->internal_timer_h);
1149 hw_l = ioread32be(&iseg->internal_timer_l);
1150 hw_h1 = ioread32be(&iseg->internal_timer_h);
1151 } while (hw_h1 != hw_h);
1152 return (((uint64_t)hw_h << 32) | hw_l);
1156 * The calibration callout, it runs either in the context of the
1157 * thread which enables calibration, or in callout. It takes the
1158 * snapshot of system and adapter clocks, then advances the pointers to
1159 * the calibration point to allow rx path to read the consistent data
1163 mlx5e_calibration_callout(void *arg)
1165 struct mlx5e_priv *priv;
1166 struct mlx5e_clbr_point *next, *curr;
1171 curr = &priv->clbr_points[priv->clbr_curr];
1172 clbr_curr_next = priv->clbr_curr + 1;
1173 if (clbr_curr_next >= nitems(priv->clbr_points))
1175 next = &priv->clbr_points[clbr_curr_next];
1177 next->base_prev = curr->base_curr;
1178 next->clbr_hw_prev = curr->clbr_hw_curr;
1180 next->clbr_hw_curr = mlx5e_hw_clock(priv);
1181 if (((next->clbr_hw_curr - curr->clbr_hw_curr) >> MLX5E_TSTMP_PREC) ==
1183 if (priv->clbr_done != 0) {
1184 mlx5_en_err(priv->ifp,
1185 "HW failed tstmp frozen %#jx %#jx, disabling\n",
1186 next->clbr_hw_curr, curr->clbr_hw_prev);
1187 priv->clbr_done = 0;
1189 atomic_store_rel_int(&curr->clbr_gen, 0);
1194 next->base_curr = mlx5e_timespec2usec(&ts);
1197 atomic_thread_fence_rel();
1198 priv->clbr_curr = clbr_curr_next;
1199 atomic_store_rel_int(&next->clbr_gen, ++(priv->clbr_gen));
1201 if (priv->clbr_done < mlx5e_calibration_duration)
1203 mlx5e_reset_calibration_callout(priv);
1206 static const char *mlx5e_rq_stats_desc[] = {
1207 MLX5E_RQ_STATS(MLX5E_STATS_DESC)
1211 mlx5e_create_rq(struct mlx5e_channel *c,
1212 struct mlx5e_rq_param *param,
1213 struct mlx5e_rq *rq)
1215 struct mlx5e_priv *priv = c->priv;
1216 struct mlx5_core_dev *mdev = priv->mdev;
1218 void *rqc = param->rqc;
1219 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1225 err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
1229 /* Create DMA descriptor TAG */
1230 if ((err = -bus_dma_tag_create(
1231 bus_get_dma_tag(mdev->pdev->dev.bsddev),
1232 1, /* any alignment */
1233 0, /* no boundary */
1234 BUS_SPACE_MAXADDR, /* lowaddr */
1235 BUS_SPACE_MAXADDR, /* highaddr */
1236 NULL, NULL, /* filter, filterarg */
1237 nsegs * MLX5E_MAX_RX_BYTES, /* maxsize */
1238 nsegs, /* nsegments */
1239 nsegs * MLX5E_MAX_RX_BYTES, /* maxsegsize */
1241 NULL, NULL, /* lockfunc, lockfuncarg */
1245 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
1248 goto err_free_dma_tag;
1250 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
1252 err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs);
1254 goto err_rq_wq_destroy;
1256 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
1258 err = -tcp_lro_init_args(&rq->lro, priv->ifp, TCP_LRO_ENTRIES, wq_sz);
1260 goto err_rq_wq_destroy;
1262 rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1263 for (i = 0; i != wq_sz; i++) {
1264 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
1267 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
1270 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
1271 goto err_rq_mbuf_free;
1274 /* set value for constant fields */
1275 for (j = 0; j < rq->nsegs; j++)
1276 wqe->data[j].lkey = cpu_to_be32(priv->mr.key);
1279 INIT_WORK(&rq->dim.work, mlx5e_dim_work);
1280 if (priv->params.rx_cq_moderation_mode < 2) {
1281 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
1283 void *cqc = container_of(param,
1284 struct mlx5e_channel_param, rq)->rx_cq.cqc;
1286 switch (MLX5_GET(cqc, cqc, cq_period_mode)) {
1287 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
1288 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
1290 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
1291 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
1294 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
1299 rq->ifp = priv->ifp;
1303 snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
1304 mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1305 buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
1310 free(rq->mbuf, M_MLX5EN);
1311 tcp_lro_free(&rq->lro);
1313 mlx5_wq_destroy(&rq->wq_ctrl);
1315 bus_dma_tag_destroy(rq->dma_tag);
1321 mlx5e_destroy_rq(struct mlx5e_rq *rq)
1326 /* destroy all sysctl nodes */
1327 sysctl_ctx_free(&rq->stats.ctx);
1329 /* free leftover LRO packets, if any */
1330 tcp_lro_free(&rq->lro);
1332 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
1333 for (i = 0; i != wq_sz; i++) {
1334 if (rq->mbuf[i].mbuf != NULL) {
1335 bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map);
1336 m_freem(rq->mbuf[i].mbuf);
1338 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
1340 free(rq->mbuf, M_MLX5EN);
1341 mlx5_wq_destroy(&rq->wq_ctrl);
1342 bus_dma_tag_destroy(rq->dma_tag);
1346 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
1348 struct mlx5e_channel *c = rq->channel;
1349 struct mlx5e_priv *priv = c->priv;
1350 struct mlx5_core_dev *mdev = priv->mdev;
1358 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
1359 sizeof(u64) * rq->wq_ctrl.buf.npages;
1360 in = mlx5_vzalloc(inlen);
1364 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1365 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1367 memcpy(rqc, param->rqc, sizeof(param->rqc));
1369 MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
1370 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1371 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1372 if (priv->counter_set_id >= 0)
1373 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
1374 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
1376 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
1378 mlx5_fill_page_array(&rq->wq_ctrl.buf,
1379 (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1381 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
1389 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
1391 struct mlx5e_channel *c = rq->channel;
1392 struct mlx5e_priv *priv = c->priv;
1393 struct mlx5_core_dev *mdev = priv->mdev;
1400 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1401 in = mlx5_vzalloc(inlen);
1405 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1407 MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
1408 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
1409 MLX5_SET(rqc, rqc, state, next_state);
1411 err = mlx5_core_modify_rq(mdev, in, inlen);
1419 mlx5e_disable_rq(struct mlx5e_rq *rq)
1421 struct mlx5e_channel *c = rq->channel;
1422 struct mlx5e_priv *priv = c->priv;
1423 struct mlx5_core_dev *mdev = priv->mdev;
1425 mlx5_core_destroy_rq(mdev, rq->rqn);
1429 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
1431 struct mlx5e_channel *c = rq->channel;
1432 struct mlx5e_priv *priv = c->priv;
1433 struct mlx5_wq_ll *wq = &rq->wq;
1436 for (i = 0; i < 1000; i++) {
1437 if (wq->cur_sz >= priv->params.min_rx_wqes)
1442 return (-ETIMEDOUT);
1446 mlx5e_open_rq(struct mlx5e_channel *c,
1447 struct mlx5e_rq_param *param,
1448 struct mlx5e_rq *rq)
1452 err = mlx5e_create_rq(c, param, rq);
1456 err = mlx5e_enable_rq(rq, param);
1458 goto err_destroy_rq;
1460 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1462 goto err_disable_rq;
1469 mlx5e_disable_rq(rq);
1471 mlx5e_destroy_rq(rq);
1477 mlx5e_close_rq(struct mlx5e_rq *rq)
1481 callout_stop(&rq->watchdog);
1482 mtx_unlock(&rq->mtx);
1484 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
1488 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
1491 mlx5e_disable_rq(rq);
1492 mlx5e_close_cq(&rq->cq);
1493 cancel_work_sync(&rq->dim.work);
1494 mlx5e_destroy_rq(rq);
1498 mlx5e_free_sq_db(struct mlx5e_sq *sq)
1500 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1503 for (x = 0; x != wq_sz; x++) {
1504 if (sq->mbuf[x].mbuf != NULL) {
1505 bus_dmamap_unload(sq->dma_tag, sq->mbuf[x].dma_map);
1506 m_freem(sq->mbuf[x].mbuf);
1508 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1510 free(sq->mbuf, M_MLX5EN);
1514 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
1516 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1520 sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1522 /* Create DMA descriptor MAPs */
1523 for (x = 0; x != wq_sz; x++) {
1524 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
1527 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1528 free(sq->mbuf, M_MLX5EN);
1535 static const char *mlx5e_sq_stats_desc[] = {
1536 MLX5E_SQ_STATS(MLX5E_STATS_DESC)
1540 mlx5e_update_sq_inline(struct mlx5e_sq *sq)
1542 sq->max_inline = sq->priv->params.tx_max_inline;
1543 sq->min_inline_mode = sq->priv->params.tx_min_inline_mode;
1546 * Check if trust state is DSCP or if inline mode is NONE which
1547 * indicates CX-5 or newer hardware.
1549 if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP ||
1550 sq->min_inline_mode == MLX5_INLINE_MODE_NONE) {
1551 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert))
1552 sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN;
1554 sq->min_insert_caps = MLX5E_INSERT_NON_VLAN;
1556 sq->min_insert_caps = 0;
1561 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1565 for (i = 0; i != priv->num_tc; i++) {
1566 mtx_lock(&c->sq[i].lock);
1567 mlx5e_update_sq_inline(&c->sq[i]);
1568 mtx_unlock(&c->sq[i].lock);
1573 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv)
1577 /* check if channels are closed */
1578 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
1581 for (i = 0; i < priv->params.num_channels; i++)
1582 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]);
1586 mlx5e_create_sq(struct mlx5e_channel *c,
1588 struct mlx5e_sq_param *param,
1589 struct mlx5e_sq *sq)
1591 struct mlx5e_priv *priv = c->priv;
1592 struct mlx5_core_dev *mdev = priv->mdev;
1594 void *sqc = param->sqc;
1595 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1598 /* Create DMA descriptor TAG */
1599 if ((err = -bus_dma_tag_create(
1600 bus_get_dma_tag(mdev->pdev->dev.bsddev),
1601 1, /* any alignment */
1602 0, /* no boundary */
1603 BUS_SPACE_MAXADDR, /* lowaddr */
1604 BUS_SPACE_MAXADDR, /* highaddr */
1605 NULL, NULL, /* filter, filterarg */
1606 MLX5E_MAX_TX_PAYLOAD_SIZE, /* maxsize */
1607 MLX5E_MAX_TX_MBUF_FRAGS, /* nsegments */
1608 MLX5E_MAX_TX_MBUF_SIZE, /* maxsegsize */
1610 NULL, NULL, /* lockfunc, lockfuncarg */
1614 err = mlx5_alloc_map_uar(mdev, &sq->uar);
1616 goto err_free_dma_tag;
1618 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq,
1621 goto err_unmap_free_uar;
1623 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1624 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1626 err = mlx5e_alloc_sq_db(sq);
1628 goto err_sq_wq_destroy;
1630 sq->mkey_be = cpu_to_be32(priv->mr.key);
1631 sq->ifp = priv->ifp;
1635 mlx5e_update_sq_inline(sq);
1637 snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1638 mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1639 buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1645 mlx5_wq_destroy(&sq->wq_ctrl);
1648 mlx5_unmap_free_uar(mdev, &sq->uar);
1651 bus_dma_tag_destroy(sq->dma_tag);
1657 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1659 /* destroy all sysctl nodes */
1660 sysctl_ctx_free(&sq->stats.ctx);
1662 mlx5e_free_sq_db(sq);
1663 mlx5_wq_destroy(&sq->wq_ctrl);
1664 mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1665 bus_dma_tag_destroy(sq->dma_tag);
1669 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1678 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1679 sizeof(u64) * sq->wq_ctrl.buf.npages;
1680 in = mlx5_vzalloc(inlen);
1684 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1685 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1687 memcpy(sqc, param->sqc, sizeof(param->sqc));
1689 MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1690 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1691 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1692 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1693 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1695 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1696 MLX5_SET(wq, wq, uar_page, sq->uar.index);
1697 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1699 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1701 mlx5_fill_page_array(&sq->wq_ctrl.buf,
1702 (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1704 err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1712 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1719 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1720 in = mlx5_vzalloc(inlen);
1724 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1726 MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1727 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1728 MLX5_SET(sqc, sqc, state, next_state);
1730 err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1738 mlx5e_disable_sq(struct mlx5e_sq *sq)
1741 mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1745 mlx5e_open_sq(struct mlx5e_channel *c,
1747 struct mlx5e_sq_param *param,
1748 struct mlx5e_sq *sq)
1752 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1754 /* ensure the TX completion event factor is not zero */
1755 if (sq->cev_factor == 0)
1758 err = mlx5e_create_sq(c, tc, param, sq);
1762 err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1764 goto err_destroy_sq;
1766 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1768 goto err_disable_sq;
1770 WRITE_ONCE(sq->running, 1);
1775 mlx5e_disable_sq(sq);
1777 mlx5e_destroy_sq(sq);
1783 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1785 /* fill up remainder with NOPs */
1786 while (sq->cev_counter != 0) {
1787 while (!mlx5e_sq_has_room_for(sq, 1)) {
1788 if (can_sleep != 0) {
1789 mtx_unlock(&sq->lock);
1791 mtx_lock(&sq->lock);
1796 /* send a single NOP */
1797 mlx5e_send_nop(sq, 1);
1798 atomic_thread_fence_rel();
1801 /* Check if we need to write the doorbell */
1802 if (likely(sq->doorbell.d64 != 0)) {
1803 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1804 sq->doorbell.d64 = 0;
1809 mlx5e_sq_cev_timeout(void *arg)
1811 struct mlx5e_sq *sq = arg;
1813 mtx_assert(&sq->lock, MA_OWNED);
1815 /* check next state */
1816 switch (sq->cev_next_state) {
1817 case MLX5E_CEV_STATE_SEND_NOPS:
1818 /* fill TX ring with NOPs, if any */
1819 mlx5e_sq_send_nops_locked(sq, 0);
1821 /* check if completed */
1822 if (sq->cev_counter == 0) {
1823 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1828 /* send NOPs on next timeout */
1829 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1834 callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1838 mlx5e_drain_sq(struct mlx5e_sq *sq)
1841 struct mlx5_core_dev *mdev= sq->priv->mdev;
1844 * Check if already stopped.
1846 * NOTE: Serialization of this function is managed by the
1847 * caller ensuring the priv's state lock is locked or in case
1848 * of rate limit support, a single thread manages drain and
1849 * resume of SQs. The "running" variable can therefore safely
1850 * be read without any locks.
1852 if (READ_ONCE(sq->running) == 0)
1855 /* don't put more packets into the SQ */
1856 WRITE_ONCE(sq->running, 0);
1858 /* serialize access to DMA rings */
1859 mtx_lock(&sq->lock);
1861 /* teardown event factor timer, if any */
1862 sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1863 callout_stop(&sq->cev_callout);
1865 /* send dummy NOPs in order to flush the transmit ring */
1866 mlx5e_sq_send_nops_locked(sq, 1);
1867 mtx_unlock(&sq->lock);
1869 /* wait till SQ is empty or link is down */
1870 mtx_lock(&sq->lock);
1871 while (sq->cc != sq->pc &&
1872 (sq->priv->media_status_last & IFM_ACTIVE) != 0 &&
1873 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1874 mtx_unlock(&sq->lock);
1876 sq->cq.mcq.comp(&sq->cq.mcq);
1877 mtx_lock(&sq->lock);
1879 mtx_unlock(&sq->lock);
1881 /* error out remaining requests */
1882 error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1884 mlx5_en_err(sq->ifp,
1885 "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error);
1888 /* wait till SQ is empty */
1889 mtx_lock(&sq->lock);
1890 while (sq->cc != sq->pc &&
1891 mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1892 mtx_unlock(&sq->lock);
1894 sq->cq.mcq.comp(&sq->cq.mcq);
1895 mtx_lock(&sq->lock);
1897 mtx_unlock(&sq->lock);
1901 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1905 mlx5e_disable_sq(sq);
1906 mlx5e_destroy_sq(sq);
1910 mlx5e_create_cq(struct mlx5e_priv *priv,
1911 struct mlx5e_cq_param *param,
1912 struct mlx5e_cq *cq,
1913 mlx5e_cq_comp_t *comp,
1916 struct mlx5_core_dev *mdev = priv->mdev;
1917 struct mlx5_core_cq *mcq = &cq->mcq;
1923 param->wq.buf_numa_node = 0;
1924 param->wq.db_numa_node = 0;
1926 err = mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1930 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1936 mcq->set_ci_db = cq->wq_ctrl.db.db;
1937 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1938 *mcq->set_ci_db = 0;
1940 mcq->vector = eq_ix;
1942 mcq->event = mlx5e_cq_error_event;
1944 mcq->uar = &priv->cq_uar;
1946 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1947 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1958 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1960 mlx5_wq_destroy(&cq->wq_ctrl);
1964 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1966 struct mlx5_core_cq *mcq = &cq->mcq;
1974 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1975 sizeof(u64) * cq->wq_ctrl.buf.npages;
1976 in = mlx5_vzalloc(inlen);
1980 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1982 memcpy(cqc, param->cqc, sizeof(param->cqc));
1984 mlx5_fill_page_array(&cq->wq_ctrl.buf,
1985 (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1987 mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
1989 MLX5_SET(cqc, cqc, c_eqn, eqn);
1990 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1991 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1993 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1995 err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
2002 mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock));
2008 mlx5e_disable_cq(struct mlx5e_cq *cq)
2011 mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
2015 mlx5e_open_cq(struct mlx5e_priv *priv,
2016 struct mlx5e_cq_param *param,
2017 struct mlx5e_cq *cq,
2018 mlx5e_cq_comp_t *comp,
2023 err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
2027 err = mlx5e_enable_cq(cq, param, eq_ix);
2029 goto err_destroy_cq;
2034 mlx5e_destroy_cq(cq);
2040 mlx5e_close_cq(struct mlx5e_cq *cq)
2042 mlx5e_disable_cq(cq);
2043 mlx5e_destroy_cq(cq);
2047 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
2048 struct mlx5e_channel_param *cparam)
2053 for (tc = 0; tc < c->priv->num_tc; tc++) {
2054 /* open completion queue */
2055 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
2056 &mlx5e_tx_cq_comp, c->ix);
2058 goto err_close_tx_cqs;
2063 for (tc--; tc >= 0; tc--)
2064 mlx5e_close_cq(&c->sq[tc].cq);
2070 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
2074 for (tc = 0; tc < c->priv->num_tc; tc++)
2075 mlx5e_close_cq(&c->sq[tc].cq);
2079 mlx5e_open_sqs(struct mlx5e_channel *c,
2080 struct mlx5e_channel_param *cparam)
2085 for (tc = 0; tc < c->priv->num_tc; tc++) {
2086 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
2094 for (tc--; tc >= 0; tc--)
2095 mlx5e_close_sq_wait(&c->sq[tc]);
2101 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
2105 for (tc = 0; tc < c->priv->num_tc; tc++)
2106 mlx5e_close_sq_wait(&c->sq[tc]);
2110 mlx5e_chan_static_init(struct mlx5e_priv *priv, struct mlx5e_channel *c, int ix)
2114 /* setup priv and channel number */
2118 /* setup send tag */
2119 c->tag.type = IF_SND_TAG_TYPE_UNLIMITED;
2120 m_snd_tag_init(&c->tag.m_snd_tag, c->priv->ifp);
2122 init_completion(&c->completion);
2124 mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
2126 callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
2128 for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) {
2129 struct mlx5e_sq *sq = c->sq + tc;
2131 mtx_init(&sq->lock, "mlx5tx",
2132 MTX_NETWORK_LOCK " TX", MTX_DEF);
2133 mtx_init(&sq->comp_lock, "mlx5comp",
2134 MTX_NETWORK_LOCK " TX", MTX_DEF);
2136 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
2141 mlx5e_chan_wait_for_completion(struct mlx5e_channel *c)
2144 m_snd_tag_rele(&c->tag.m_snd_tag);
2145 wait_for_completion(&c->completion);
2149 mlx5e_priv_wait_for_completion(struct mlx5e_priv *priv, const uint32_t channels)
2153 for (x = 0; x != channels; x++)
2154 mlx5e_chan_wait_for_completion(&priv->channel[x]);
2158 mlx5e_chan_static_destroy(struct mlx5e_channel *c)
2162 callout_drain(&c->rq.watchdog);
2164 mtx_destroy(&c->rq.mtx);
2166 for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) {
2167 callout_drain(&c->sq[tc].cev_callout);
2168 mtx_destroy(&c->sq[tc].lock);
2169 mtx_destroy(&c->sq[tc].comp_lock);
2174 mlx5e_open_channel(struct mlx5e_priv *priv,
2175 struct mlx5e_channel_param *cparam,
2176 struct mlx5e_channel *c)
2180 /* zero non-persistant data */
2181 MLX5E_ZERO(&c->rq, mlx5e_rq_zero_start);
2182 for (i = 0; i != priv->num_tc; i++)
2183 MLX5E_ZERO(&c->sq[i], mlx5e_sq_zero_start);
2185 /* open transmit completion queue */
2186 err = mlx5e_open_tx_cqs(c, cparam);
2190 /* open receive completion queue */
2191 err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
2192 &mlx5e_rx_cq_comp, c->ix);
2194 goto err_close_tx_cqs;
2196 err = mlx5e_open_sqs(c, cparam);
2198 goto err_close_rx_cq;
2200 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
2204 /* poll receive queue initially */
2205 c->rq.cq.mcq.comp(&c->rq.cq.mcq);
2210 mlx5e_close_sqs_wait(c);
2213 mlx5e_close_cq(&c->rq.cq);
2216 mlx5e_close_tx_cqs(c);
2223 mlx5e_close_channel(struct mlx5e_channel *c)
2225 mlx5e_close_rq(&c->rq);
2229 mlx5e_close_channel_wait(struct mlx5e_channel *c)
2231 mlx5e_close_rq_wait(&c->rq);
2232 mlx5e_close_sqs_wait(c);
2233 mlx5e_close_tx_cqs(c);
2237 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs)
2241 r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz :
2242 MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
2243 if (r > MJUM16BYTES)
2248 else if (r > MJUMPAGESIZE)
2250 else if (r > MCLBYTES)
2256 * n + 1 must be a power of two, because stride size must be.
2257 * Stride size is 16 * (n + 1), as the first segment is
2260 for (n = howmany(r, MLX5E_MAX_RX_BYTES); !powerof2(n + 1); n++)
2263 if (n > MLX5E_MAX_BUSDMA_RX_SEGS)
2272 mlx5e_build_rq_param(struct mlx5e_priv *priv,
2273 struct mlx5e_rq_param *param)
2275 void *rqc = param->rqc;
2276 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2279 mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
2280 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
2281 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2282 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) +
2283 nsegs * sizeof(struct mlx5_wqe_data_seg)));
2284 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
2285 MLX5_SET(wq, wq, pd, priv->pdn);
2287 param->wq.buf_numa_node = 0;
2288 param->wq.db_numa_node = 0;
2289 param->wq.linear = 1;
2293 mlx5e_build_sq_param(struct mlx5e_priv *priv,
2294 struct mlx5e_sq_param *param)
2296 void *sqc = param->sqc;
2297 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2299 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
2300 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2301 MLX5_SET(wq, wq, pd, priv->pdn);
2303 param->wq.buf_numa_node = 0;
2304 param->wq.db_numa_node = 0;
2305 param->wq.linear = 1;
2309 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2310 struct mlx5e_cq_param *param)
2312 void *cqc = param->cqc;
2314 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
2318 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr)
2321 *ptr = net_dim_get_profile(mode, MLX5E_DIM_DEFAULT_PROFILE);
2323 /* apply LRO restrictions */
2324 if (priv->params.hw_lro_en &&
2325 ptr->pkts > MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO) {
2326 ptr->pkts = MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO;
2331 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2332 struct mlx5e_cq_param *param)
2334 struct net_dim_cq_moder curr;
2335 void *cqc = param->cqc;
2338 * We use MLX5_CQE_FORMAT_HASH because the RX hash mini CQE
2339 * format is more beneficial for FreeBSD use case.
2341 * Adding support for MLX5_CQE_FORMAT_CSUM will require changes
2342 * in mlx5e_decompress_cqe.
2344 if (priv->params.cqe_zipping_en) {
2345 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_HASH);
2346 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
2349 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
2351 switch (priv->params.rx_cq_moderation_mode) {
2353 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
2354 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
2355 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2358 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
2359 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
2360 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2361 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2363 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2366 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr);
2367 MLX5_SET(cqc, cqc, cq_period, curr.usec);
2368 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
2369 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2372 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr);
2373 MLX5_SET(cqc, cqc, cq_period, curr.usec);
2374 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
2375 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2376 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2378 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2384 mlx5e_dim_build_cq_param(priv, param);
2386 mlx5e_build_common_cq_param(priv, param);
2390 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2391 struct mlx5e_cq_param *param)
2393 void *cqc = param->cqc;
2395 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
2396 MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
2397 MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
2399 switch (priv->params.tx_cq_moderation_mode) {
2401 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2404 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2405 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2407 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2411 mlx5e_build_common_cq_param(priv, param);
2415 mlx5e_build_channel_param(struct mlx5e_priv *priv,
2416 struct mlx5e_channel_param *cparam)
2418 memset(cparam, 0, sizeof(*cparam));
2420 mlx5e_build_rq_param(priv, &cparam->rq);
2421 mlx5e_build_sq_param(priv, &cparam->sq);
2422 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
2423 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
2427 mlx5e_open_channels(struct mlx5e_priv *priv)
2429 struct mlx5e_channel_param *cparam;
2434 cparam = malloc(sizeof(*cparam), M_MLX5EN, M_WAITOK);
2436 mlx5e_build_channel_param(priv, cparam);
2437 for (i = 0; i < priv->params.num_channels; i++) {
2438 err = mlx5e_open_channel(priv, cparam, &priv->channel[i]);
2440 goto err_close_channels;
2443 for (j = 0; j < priv->params.num_channels; j++) {
2444 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j].rq);
2446 goto err_close_channels;
2448 free(cparam, M_MLX5EN);
2453 mlx5e_close_channel(&priv->channel[i]);
2454 mlx5e_close_channel_wait(&priv->channel[i]);
2456 free(cparam, M_MLX5EN);
2461 mlx5e_close_channels(struct mlx5e_priv *priv)
2465 for (i = 0; i < priv->params.num_channels; i++)
2466 mlx5e_close_channel(&priv->channel[i]);
2467 for (i = 0; i < priv->params.num_channels; i++)
2468 mlx5e_close_channel_wait(&priv->channel[i]);
2472 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
2475 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2478 switch (priv->params.tx_cq_moderation_mode) {
2481 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2484 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2488 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq,
2489 priv->params.tx_cq_moderation_usec,
2490 priv->params.tx_cq_moderation_pkts,
2494 return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
2495 priv->params.tx_cq_moderation_usec,
2496 priv->params.tx_cq_moderation_pkts));
2500 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
2503 if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2508 switch (priv->params.rx_cq_moderation_mode) {
2511 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2512 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2515 cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2516 dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
2520 /* tear down dynamic interrupt moderation */
2522 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
2523 mtx_unlock(&rq->mtx);
2525 /* wait for dynamic interrupt moderation work task, if any */
2526 cancel_work_sync(&rq->dim.work);
2528 if (priv->params.rx_cq_moderation_mode >= 2) {
2529 struct net_dim_cq_moder curr;
2531 mlx5e_get_default_profile(priv, dim_mode, &curr);
2533 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2534 curr.usec, curr.pkts, cq_mode);
2536 /* set dynamic interrupt moderation mode and zero defaults */
2538 rq->dim.mode = dim_mode;
2540 rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE;
2541 mtx_unlock(&rq->mtx);
2543 retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2544 priv->params.rx_cq_moderation_usec,
2545 priv->params.rx_cq_moderation_pkts,
2551 return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
2552 priv->params.rx_cq_moderation_usec,
2553 priv->params.rx_cq_moderation_pkts));
2557 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
2562 err = mlx5e_refresh_rq_params(priv, &c->rq);
2566 for (i = 0; i != priv->num_tc; i++) {
2567 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
2576 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
2580 /* check if channels are closed */
2581 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2584 for (i = 0; i < priv->params.num_channels; i++) {
2587 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]);
2595 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
2597 struct mlx5_core_dev *mdev = priv->mdev;
2598 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
2599 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2601 memset(in, 0, sizeof(in));
2603 MLX5_SET(tisc, tisc, prio, tc);
2604 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
2606 return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
2610 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
2612 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2616 mlx5e_open_tises(struct mlx5e_priv *priv)
2618 int num_tc = priv->num_tc;
2622 for (tc = 0; tc < num_tc; tc++) {
2623 err = mlx5e_open_tis(priv, tc);
2625 goto err_close_tises;
2631 for (tc--; tc >= 0; tc--)
2632 mlx5e_close_tis(priv, tc);
2638 mlx5e_close_tises(struct mlx5e_priv *priv)
2640 int num_tc = priv->num_tc;
2643 for (tc = 0; tc < num_tc; tc++)
2644 mlx5e_close_tis(priv, tc);
2648 mlx5e_open_rqt(struct mlx5e_priv *priv)
2650 struct mlx5_core_dev *mdev = priv->mdev;
2652 u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
2659 sz = 1 << priv->params.rx_hash_log_tbl_sz;
2661 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2662 in = mlx5_vzalloc(inlen);
2665 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2667 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2668 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2670 for (i = 0; i < sz; i++) {
2673 ix = rss_get_indirection_to_bucket(ix);
2675 /* ensure we don't overflow */
2676 ix %= priv->params.num_channels;
2678 /* apply receive side scaling stride, if any */
2679 ix -= ix % (int)priv->params.channels_rsss;
2681 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn);
2684 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
2686 err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
2688 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
2696 mlx5e_close_rqt(struct mlx5e_priv *priv)
2698 u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0};
2699 u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0};
2701 MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
2702 MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
2704 mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out));
2708 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
2710 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2713 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2715 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2717 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2718 MLX5_HASH_FIELD_SEL_DST_IP)
2720 #define MLX5_HASH_ALL (MLX5_HASH_FIELD_SEL_SRC_IP |\
2721 MLX5_HASH_FIELD_SEL_DST_IP |\
2722 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2723 MLX5_HASH_FIELD_SEL_L4_DPORT)
2725 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2726 MLX5_HASH_FIELD_SEL_DST_IP |\
2727 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2729 if (priv->params.hw_lro_en) {
2730 MLX5_SET(tirc, tirc, lro_enable_mask,
2731 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2732 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2733 MLX5_SET(tirc, tirc, lro_max_msg_sz,
2734 (priv->params.lro_wqe_sz -
2735 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2736 /* TODO: add the option to choose timer value dynamically */
2737 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
2738 MLX5_CAP_ETH(priv->mdev,
2739 lro_timer_supported_periods[2]));
2742 /* setup parameters for hashing TIR type, if any */
2745 MLX5_SET(tirc, tirc, disp_type,
2746 MLX5_TIRC_DISP_TYPE_DIRECT);
2747 MLX5_SET(tirc, tirc, inline_rqn,
2748 priv->channel[0].rq.rqn);
2751 MLX5_SET(tirc, tirc, disp_type,
2752 MLX5_TIRC_DISP_TYPE_INDIRECT);
2753 MLX5_SET(tirc, tirc, indirect_table,
2755 MLX5_SET(tirc, tirc, rx_hash_fn,
2756 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
2757 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
2760 * The FreeBSD RSS implementation does currently not
2761 * support symmetric Toeplitz hashes:
2763 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
2764 rss_getkey((uint8_t *)hkey);
2766 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2767 hkey[0] = cpu_to_be32(0xD181C62C);
2768 hkey[1] = cpu_to_be32(0xF7F4DB5B);
2769 hkey[2] = cpu_to_be32(0x1983A2FC);
2770 hkey[3] = cpu_to_be32(0x943E1ADB);
2771 hkey[4] = cpu_to_be32(0xD9389E6B);
2772 hkey[5] = cpu_to_be32(0xD1039C2C);
2773 hkey[6] = cpu_to_be32(0xA74499AD);
2774 hkey[7] = cpu_to_be32(0x593D56D9);
2775 hkey[8] = cpu_to_be32(0xF3253C06);
2776 hkey[9] = cpu_to_be32(0x2ADC1FFC);
2782 case MLX5E_TT_IPV4_TCP:
2783 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2784 MLX5_L3_PROT_TYPE_IPV4);
2785 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2786 MLX5_L4_PROT_TYPE_TCP);
2788 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2789 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2793 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2797 case MLX5E_TT_IPV6_TCP:
2798 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2799 MLX5_L3_PROT_TYPE_IPV6);
2800 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2801 MLX5_L4_PROT_TYPE_TCP);
2803 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2804 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2808 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2812 case MLX5E_TT_IPV4_UDP:
2813 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2814 MLX5_L3_PROT_TYPE_IPV4);
2815 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2816 MLX5_L4_PROT_TYPE_UDP);
2818 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2819 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2823 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2827 case MLX5E_TT_IPV6_UDP:
2828 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2829 MLX5_L3_PROT_TYPE_IPV6);
2830 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2831 MLX5_L4_PROT_TYPE_UDP);
2833 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2834 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2838 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2842 case MLX5E_TT_IPV4_IPSEC_AH:
2843 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2844 MLX5_L3_PROT_TYPE_IPV4);
2845 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2846 MLX5_HASH_IP_IPSEC_SPI);
2849 case MLX5E_TT_IPV6_IPSEC_AH:
2850 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2851 MLX5_L3_PROT_TYPE_IPV6);
2852 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2853 MLX5_HASH_IP_IPSEC_SPI);
2856 case MLX5E_TT_IPV4_IPSEC_ESP:
2857 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2858 MLX5_L3_PROT_TYPE_IPV4);
2859 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2860 MLX5_HASH_IP_IPSEC_SPI);
2863 case MLX5E_TT_IPV6_IPSEC_ESP:
2864 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2865 MLX5_L3_PROT_TYPE_IPV6);
2866 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2867 MLX5_HASH_IP_IPSEC_SPI);
2871 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2872 MLX5_L3_PROT_TYPE_IPV4);
2873 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2878 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2879 MLX5_L3_PROT_TYPE_IPV6);
2880 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2890 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2892 struct mlx5_core_dev *mdev = priv->mdev;
2898 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2899 in = mlx5_vzalloc(inlen);
2902 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2904 mlx5e_build_tir_ctx(priv, tirc, tt);
2906 err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2914 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2916 mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2920 mlx5e_open_tirs(struct mlx5e_priv *priv)
2925 for (i = 0; i < MLX5E_NUM_TT; i++) {
2926 err = mlx5e_open_tir(priv, i);
2928 goto err_close_tirs;
2934 for (i--; i >= 0; i--)
2935 mlx5e_close_tir(priv, i);
2941 mlx5e_close_tirs(struct mlx5e_priv *priv)
2945 for (i = 0; i < MLX5E_NUM_TT; i++)
2946 mlx5e_close_tir(priv, i);
2950 * SW MTU does not include headers,
2951 * HW MTU includes all headers and checksums.
2954 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2956 struct mlx5e_priv *priv = ifp->if_softc;
2957 struct mlx5_core_dev *mdev = priv->mdev;
2961 hw_mtu = MLX5E_SW2HW_MTU(sw_mtu);
2963 err = mlx5_set_port_mtu(mdev, hw_mtu);
2965 mlx5_en_err(ifp, "mlx5_set_port_mtu failed setting %d, err=%d\n",
2970 /* Update vport context MTU */
2971 err = mlx5_set_vport_mtu(mdev, hw_mtu);
2974 "Failed updating vport context with MTU size, err=%d\n",
2978 ifp->if_mtu = sw_mtu;
2980 err = mlx5_query_vport_mtu(mdev, &hw_mtu);
2981 if (err || !hw_mtu) {
2982 /* fallback to port oper mtu */
2983 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2987 "Query port MTU, after setting new MTU value, failed\n");
2989 } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
2992 "Port MTU %d is smaller than ifp mtu %d\n",
2994 } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
2997 "Port MTU %d is bigger than ifp mtu %d\n",
3000 priv->params_ethtool.hw_mtu = hw_mtu;
3006 mlx5e_open_locked(struct ifnet *ifp)
3008 struct mlx5e_priv *priv = ifp->if_softc;
3012 /* check if already opened */
3013 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
3017 if (rss_getnumbuckets() > priv->params.num_channels) {
3019 "NOTE: There are more RSS buckets(%u) than channels(%u) available\n",
3020 rss_getnumbuckets(), priv->params.num_channels);
3023 err = mlx5e_open_tises(priv);
3025 mlx5_en_err(ifp, "mlx5e_open_tises failed, %d\n", err);
3028 err = mlx5_vport_alloc_q_counter(priv->mdev,
3029 MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
3031 mlx5_en_err(priv->ifp,
3032 "mlx5_vport_alloc_q_counter failed: %d\n", err);
3033 goto err_close_tises;
3035 /* store counter set ID */
3036 priv->counter_set_id = set_id;
3038 err = mlx5e_open_channels(priv);
3041 "mlx5e_open_channels failed, %d\n", err);
3042 goto err_dalloc_q_counter;
3044 err = mlx5e_open_rqt(priv);
3046 mlx5_en_err(ifp, "mlx5e_open_rqt failed, %d\n", err);
3047 goto err_close_channels;
3049 err = mlx5e_open_tirs(priv);
3051 mlx5_en_err(ifp, "mlx5e_open_tir failed, %d\n", err);
3052 goto err_close_rqls;
3054 err = mlx5e_open_flow_table(priv);
3057 "mlx5e_open_flow_table failed, %d\n", err);
3058 goto err_close_tirs;
3060 err = mlx5e_add_all_vlan_rules(priv);
3063 "mlx5e_add_all_vlan_rules failed, %d\n", err);
3064 goto err_close_flow_table;
3066 set_bit(MLX5E_STATE_OPENED, &priv->state);
3068 mlx5e_update_carrier(priv);
3069 mlx5e_set_rx_mode_core(priv);
3073 err_close_flow_table:
3074 mlx5e_close_flow_table(priv);
3077 mlx5e_close_tirs(priv);
3080 mlx5e_close_rqt(priv);
3083 mlx5e_close_channels(priv);
3085 err_dalloc_q_counter:
3086 mlx5_vport_dealloc_q_counter(priv->mdev,
3087 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
3090 mlx5e_close_tises(priv);
3096 mlx5e_open(void *arg)
3098 struct mlx5e_priv *priv = arg;
3101 if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
3102 mlx5_en_err(priv->ifp,
3103 "Setting port status to up failed\n");
3105 mlx5e_open_locked(priv->ifp);
3106 priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
3111 mlx5e_close_locked(struct ifnet *ifp)
3113 struct mlx5e_priv *priv = ifp->if_softc;
3115 /* check if already closed */
3116 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3119 clear_bit(MLX5E_STATE_OPENED, &priv->state);
3121 mlx5e_set_rx_mode_core(priv);
3122 mlx5e_del_all_vlan_rules(priv);
3123 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
3124 mlx5e_close_flow_table(priv);
3125 mlx5e_close_tirs(priv);
3126 mlx5e_close_rqt(priv);
3127 mlx5e_close_channels(priv);
3128 mlx5_vport_dealloc_q_counter(priv->mdev,
3129 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
3130 mlx5e_close_tises(priv);
3135 #if (__FreeBSD_version >= 1100000)
3137 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
3139 struct mlx5e_priv *priv = ifp->if_softc;
3142 /* PRIV_LOCK(priv); XXX not allowed */
3144 case IFCOUNTER_IPACKETS:
3145 retval = priv->stats.vport.rx_packets;
3147 case IFCOUNTER_IERRORS:
3148 retval = priv->stats.pport.in_range_len_errors +
3149 priv->stats.pport.out_of_range_len +
3150 priv->stats.pport.too_long_errors +
3151 priv->stats.pport.check_seq_err +
3152 priv->stats.pport.alignment_err;
3154 case IFCOUNTER_IQDROPS:
3155 retval = priv->stats.vport.rx_out_of_buffer;
3157 case IFCOUNTER_OPACKETS:
3158 retval = priv->stats.vport.tx_packets;
3160 case IFCOUNTER_OERRORS:
3161 retval = priv->stats.port_stats_debug.out_discards;
3163 case IFCOUNTER_IBYTES:
3164 retval = priv->stats.vport.rx_bytes;
3166 case IFCOUNTER_OBYTES:
3167 retval = priv->stats.vport.tx_bytes;
3169 case IFCOUNTER_IMCASTS:
3170 retval = priv->stats.vport.rx_multicast_packets;
3172 case IFCOUNTER_OMCASTS:
3173 retval = priv->stats.vport.tx_multicast_packets;
3175 case IFCOUNTER_OQDROPS:
3176 retval = priv->stats.vport.tx_queue_dropped;
3178 case IFCOUNTER_COLLISIONS:
3179 retval = priv->stats.pport.collisions;
3182 retval = if_get_counter_default(ifp, cnt);
3185 /* PRIV_UNLOCK(priv); XXX not allowed */
3191 mlx5e_set_rx_mode(struct ifnet *ifp)
3193 struct mlx5e_priv *priv = ifp->if_softc;
3195 queue_work(priv->wq, &priv->set_rx_mode_work);
3199 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3201 struct mlx5e_priv *priv;
3203 struct ifi2creq i2c;
3212 priv = ifp->if_softc;
3214 /* check if detaching */
3215 if (priv == NULL || priv->gone != 0)
3220 ifr = (struct ifreq *)data;
3223 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
3225 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
3226 ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
3229 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3231 mlx5e_close_locked(ifp);
3234 mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
3237 mlx5e_open_locked(ifp);
3241 "Invalid MTU value. Min val: %d, Max val: %d\n",
3242 MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
3247 if ((ifp->if_flags & IFF_UP) &&
3248 (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3249 mlx5e_set_rx_mode(ifp);
3253 if (ifp->if_flags & IFF_UP) {
3254 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
3255 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3256 mlx5e_open_locked(ifp);
3257 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3258 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
3261 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3262 mlx5_set_port_status(priv->mdev,
3264 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
3265 mlx5e_close_locked(ifp);
3266 mlx5e_update_carrier(priv);
3267 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3274 mlx5e_set_rx_mode(ifp);
3279 ifr = (struct ifreq *)data;
3280 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
3283 ifr = (struct ifreq *)data;
3285 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3287 if (mask & IFCAP_TXCSUM) {
3288 ifp->if_capenable ^= IFCAP_TXCSUM;
3289 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
3291 if (IFCAP_TSO4 & ifp->if_capenable &&
3292 !(IFCAP_TXCSUM & ifp->if_capenable)) {
3293 ifp->if_capenable &= ~IFCAP_TSO4;
3294 ifp->if_hwassist &= ~CSUM_IP_TSO;
3296 "tso4 disabled due to -txcsum.\n");
3299 if (mask & IFCAP_TXCSUM_IPV6) {
3300 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
3301 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3303 if (IFCAP_TSO6 & ifp->if_capenable &&
3304 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
3305 ifp->if_capenable &= ~IFCAP_TSO6;
3306 ifp->if_hwassist &= ~CSUM_IP6_TSO;
3308 "tso6 disabled due to -txcsum6.\n");
3311 if (mask & IFCAP_NOMAP)
3312 ifp->if_capenable ^= IFCAP_NOMAP;
3313 if (mask & IFCAP_RXCSUM)
3314 ifp->if_capenable ^= IFCAP_RXCSUM;
3315 if (mask & IFCAP_RXCSUM_IPV6)
3316 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
3317 if (mask & IFCAP_TSO4) {
3318 if (!(IFCAP_TSO4 & ifp->if_capenable) &&
3319 !(IFCAP_TXCSUM & ifp->if_capenable)) {
3320 mlx5_en_err(ifp, "enable txcsum first.\n");
3324 ifp->if_capenable ^= IFCAP_TSO4;
3325 ifp->if_hwassist ^= CSUM_IP_TSO;
3327 if (mask & IFCAP_TSO6) {
3328 if (!(IFCAP_TSO6 & ifp->if_capenable) &&
3329 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
3330 mlx5_en_err(ifp, "enable txcsum6 first.\n");
3334 ifp->if_capenable ^= IFCAP_TSO6;
3335 ifp->if_hwassist ^= CSUM_IP6_TSO;
3337 if (mask & IFCAP_VLAN_HWFILTER) {
3338 if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
3339 mlx5e_disable_vlan_filter(priv);
3341 mlx5e_enable_vlan_filter(priv);
3343 ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
3345 if (mask & IFCAP_VLAN_HWTAGGING)
3346 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
3347 if (mask & IFCAP_WOL_MAGIC)
3348 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
3350 VLAN_CAPABILITIES(ifp);
3351 /* turn off LRO means also turn of HW LRO - if it's on */
3352 if (mask & IFCAP_LRO) {
3353 int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3354 bool need_restart = false;
3356 ifp->if_capenable ^= IFCAP_LRO;
3358 /* figure out if updating HW LRO is needed */
3359 if (!(ifp->if_capenable & IFCAP_LRO)) {
3360 if (priv->params.hw_lro_en) {
3361 priv->params.hw_lro_en = false;
3362 need_restart = true;
3365 if (priv->params.hw_lro_en == false &&
3366 priv->params_ethtool.hw_lro != 0) {
3367 priv->params.hw_lro_en = true;
3368 need_restart = true;
3371 if (was_opened && need_restart) {
3372 mlx5e_close_locked(ifp);
3373 mlx5e_open_locked(ifp);
3376 if (mask & IFCAP_HWRXTSTMP) {
3377 ifp->if_capenable ^= IFCAP_HWRXTSTMP;
3378 if (ifp->if_capenable & IFCAP_HWRXTSTMP) {
3379 if (priv->clbr_done == 0)
3380 mlx5e_reset_calibration_callout(priv);
3382 callout_drain(&priv->tstmp_clbr);
3383 priv->clbr_done = 0;
3391 ifr = (struct ifreq *)data;
3394 * Copy from the user-space address ifr_data to the
3395 * kernel-space address i2c
3397 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
3401 if (i2c.len > sizeof(i2c.data)) {
3407 /* Get module_num which is required for the query_eeprom */
3408 error = mlx5_query_module_num(priv->mdev, &module_num);
3411 "Query module num failed, eeprom reading is not supported\n");
3415 /* Check if module is present before doing an access */
3416 module_status = mlx5_query_module_status(priv->mdev, module_num);
3417 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED) {
3422 * Currently 0XA0 and 0xA2 are the only addresses permitted.
3423 * The internal conversion is as follows:
3425 if (i2c.dev_addr == 0xA0)
3426 read_addr = MLX5_I2C_ADDR_LOW;
3427 else if (i2c.dev_addr == 0xA2)
3428 read_addr = MLX5_I2C_ADDR_HIGH;
3431 "Query eeprom failed, Invalid Address: %X\n",
3436 error = mlx5_query_eeprom(priv->mdev,
3437 read_addr, MLX5_EEPROM_LOW_PAGE,
3438 (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
3439 (uint32_t *)i2c.data, &size_read);
3442 "Query eeprom failed, eeprom reading is not supported\n");
3447 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
3448 error = mlx5_query_eeprom(priv->mdev,
3449 read_addr, MLX5_EEPROM_LOW_PAGE,
3450 (uint32_t)(i2c.offset + size_read),
3451 (uint32_t)(i2c.len - size_read), module_num,
3452 (uint32_t *)(i2c.data + size_read), &size_read);
3456 "Query eeprom failed, eeprom reading is not supported\n");
3461 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
3467 error = ether_ioctl(ifp, command, data);
3474 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3477 * TODO: uncoment once FW really sets all these bits if
3478 * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
3479 * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
3480 * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
3484 /* TODO: add more must-to-have features */
3486 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3493 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3495 uint32_t bf_buf_size = (1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U;
3497 bf_buf_size -= sizeof(struct mlx5e_tx_wqe) - 2;
3499 /* verify against driver hardware limit */
3500 if (bf_buf_size > MLX5E_MAX_TX_INLINE)
3501 bf_buf_size = MLX5E_MAX_TX_INLINE;
3503 return (bf_buf_size);
3507 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
3508 struct mlx5e_priv *priv,
3509 int num_comp_vectors)
3514 * TODO: Consider link speed for setting "log_sq_size",
3515 * "log_rq_size" and "cq_moderation_xxx":
3517 priv->params.log_sq_size =
3518 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3519 priv->params.log_rq_size =
3520 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3521 priv->params.rx_cq_moderation_usec =
3522 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3523 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
3524 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3525 priv->params.rx_cq_moderation_mode =
3526 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
3527 priv->params.rx_cq_moderation_pkts =
3528 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3529 priv->params.tx_cq_moderation_usec =
3530 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3531 priv->params.tx_cq_moderation_pkts =
3532 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3533 priv->params.min_rx_wqes =
3534 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
3535 priv->params.rx_hash_log_tbl_sz =
3536 (order_base_2(num_comp_vectors) >
3537 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
3538 order_base_2(num_comp_vectors) :
3539 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
3540 priv->params.num_tc = 1;
3541 priv->params.default_vlan_prio = 0;
3542 priv->counter_set_id = -1;
3543 priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3545 err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3550 * hw lro is currently defaulted to off. when it won't anymore we
3551 * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
3553 priv->params.hw_lro_en = false;
3554 priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3557 * CQE zipping is currently defaulted to off. when it won't
3558 * anymore we will consider the HW capability:
3559 * "!!MLX5_CAP_GEN(mdev, cqe_compression)"
3561 priv->params.cqe_zipping_en = false;
3564 priv->params.num_channels = num_comp_vectors;
3565 priv->params.channels_rsss = 1;
3566 priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
3567 priv->queue_mapping_channel_mask =
3568 roundup_pow_of_two(num_comp_vectors) - 1;
3569 priv->num_tc = priv->params.num_tc;
3570 priv->default_vlan_prio = priv->params.default_vlan_prio;
3572 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3573 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3574 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3580 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
3581 struct mlx5_core_mr *mkey)
3583 struct ifnet *ifp = priv->ifp;
3584 struct mlx5_core_dev *mdev = priv->mdev;
3585 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3590 in = mlx5_vzalloc(inlen);
3592 mlx5_en_err(ifp, "failed to allocate inbox\n");
3596 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3597 MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA);
3598 MLX5_SET(mkc, mkc, lw, 1);
3599 MLX5_SET(mkc, mkc, lr, 1);
3601 MLX5_SET(mkc, mkc, pd, pdn);
3602 MLX5_SET(mkc, mkc, length64, 1);
3603 MLX5_SET(mkc, mkc, qpn, 0xffffff);
3605 err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
3607 mlx5_en_err(ifp, "mlx5_core_create_mkey failed, %d\n",
3614 static const char *mlx5e_vport_stats_desc[] = {
3615 MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
3618 static const char *mlx5e_pport_stats_desc[] = {
3619 MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
3623 mlx5e_priv_static_init(struct mlx5e_priv *priv, const uint32_t channels)
3627 mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
3628 sx_init(&priv->state_lock, "mlx5state");
3629 callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
3630 MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
3631 for (x = 0; x != channels; x++)
3632 mlx5e_chan_static_init(priv, &priv->channel[x], x);
3636 mlx5e_priv_static_destroy(struct mlx5e_priv *priv, const uint32_t channels)
3640 for (x = 0; x != channels; x++)
3641 mlx5e_chan_static_destroy(&priv->channel[x]);
3642 callout_drain(&priv->watchdog);
3643 mtx_destroy(&priv->async_events_mtx);
3644 sx_destroy(&priv->state_lock);
3648 sysctl_firmware(SYSCTL_HANDLER_ARGS)
3651 * %d.%d%.d the string format.
3652 * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
3653 * We need at most 5 chars to store that.
3654 * It also has: two "." and NULL at the end, which means we need 18
3655 * (5*3 + 3) chars at most.
3658 struct mlx5e_priv *priv = arg1;
3661 snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
3662 fw_rev_sub(priv->mdev));
3663 error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
3668 mlx5e_disable_tx_dma(struct mlx5e_channel *ch)
3672 for (i = 0; i < ch->priv->num_tc; i++)
3673 mlx5e_drain_sq(&ch->sq[i]);
3677 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq)
3680 sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP);
3681 sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8);
3682 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
3683 sq->doorbell.d64 = 0;
3687 mlx5e_resume_sq(struct mlx5e_sq *sq)
3691 /* check if already enabled */
3692 if (READ_ONCE(sq->running) != 0)
3695 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR,
3696 MLX5_SQC_STATE_RST);
3698 mlx5_en_err(sq->ifp,
3699 "mlx5e_modify_sq() from ERR to RST failed: %d\n", err);
3705 /* reset doorbell prior to moving from RST to RDY */
3706 mlx5e_reset_sq_doorbell_record(sq);
3708 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST,
3709 MLX5_SQC_STATE_RDY);
3711 mlx5_en_err(sq->ifp,
3712 "mlx5e_modify_sq() from RST to RDY failed: %d\n", err);
3715 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
3716 WRITE_ONCE(sq->running, 1);
3720 mlx5e_enable_tx_dma(struct mlx5e_channel *ch)
3724 for (i = 0; i < ch->priv->num_tc; i++)
3725 mlx5e_resume_sq(&ch->sq[i]);
3729 mlx5e_disable_rx_dma(struct mlx5e_channel *ch)
3731 struct mlx5e_rq *rq = &ch->rq;
3736 callout_stop(&rq->watchdog);
3737 mtx_unlock(&rq->mtx);
3739 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
3741 mlx5_en_err(rq->ifp,
3742 "mlx5e_modify_rq() from RDY to RST failed: %d\n", err);
3745 while (!mlx5_wq_ll_is_empty(&rq->wq)) {
3747 rq->cq.mcq.comp(&rq->cq.mcq);
3751 * Transitioning into RST state will allow the FW to track less ERR state queues,
3752 * thus reducing the recv queue flushing time
3754 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST);
3756 mlx5_en_err(rq->ifp,
3757 "mlx5e_modify_rq() from ERR to RST failed: %d\n", err);
3762 mlx5e_enable_rx_dma(struct mlx5e_channel *ch)
3764 struct mlx5e_rq *rq = &ch->rq;
3768 mlx5_wq_ll_update_db_record(&rq->wq);
3769 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3771 mlx5_en_err(rq->ifp,
3772 "mlx5e_modify_rq() from RST to RDY failed: %d\n", err);
3777 rq->cq.mcq.comp(&rq->cq.mcq);
3781 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value)
3785 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3788 for (i = 0; i < priv->params.num_channels; i++) {
3790 mlx5e_disable_tx_dma(&priv->channel[i]);
3792 mlx5e_enable_tx_dma(&priv->channel[i]);
3797 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value)
3801 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3804 for (i = 0; i < priv->params.num_channels; i++) {
3806 mlx5e_disable_rx_dma(&priv->channel[i]);
3808 mlx5e_enable_rx_dma(&priv->channel[i]);
3813 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
3815 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3816 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
3817 sysctl_firmware, "A", "HCA firmware version");
3819 SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3820 OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
3825 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3827 struct mlx5e_priv *priv = arg1;
3828 uint8_t temp[MLX5E_MAX_PRIORITY];
3835 tx_pfc = priv->params.tx_priority_flow_control;
3837 for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3838 temp[i] = (tx_pfc >> i) & 1;
3840 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3841 if (err || !req->newptr)
3843 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3847 priv->params.tx_priority_flow_control = 0;
3849 /* range check input value */
3850 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3855 priv->params.tx_priority_flow_control |= (temp[i] << i);
3858 /* check if update is required */
3859 if (tx_pfc != priv->params.tx_priority_flow_control)
3860 err = -mlx5e_set_port_pfc(priv);
3863 priv->params.tx_priority_flow_control= tx_pfc;
3870 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3872 struct mlx5e_priv *priv = arg1;
3873 uint8_t temp[MLX5E_MAX_PRIORITY];
3880 rx_pfc = priv->params.rx_priority_flow_control;
3882 for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3883 temp[i] = (rx_pfc >> i) & 1;
3885 err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3886 if (err || !req->newptr)
3888 err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3892 priv->params.rx_priority_flow_control = 0;
3894 /* range check input value */
3895 for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3900 priv->params.rx_priority_flow_control |= (temp[i] << i);
3903 /* check if update is required */
3904 if (rx_pfc != priv->params.rx_priority_flow_control) {
3905 err = -mlx5e_set_port_pfc(priv);
3906 if (err == 0 && priv->sw_is_port_buf_owner)
3907 err = mlx5e_update_buf_lossy(priv);
3911 priv->params.rx_priority_flow_control= rx_pfc;
3918 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
3920 #if (__FreeBSD_version < 1100000)
3925 /* enable pauseframes by default */
3926 priv->params.tx_pauseframe_control = 1;
3927 priv->params.rx_pauseframe_control = 1;
3929 /* disable ports flow control, PFC, by default */
3930 priv->params.tx_priority_flow_control = 0;
3931 priv->params.rx_priority_flow_control = 0;
3933 #if (__FreeBSD_version < 1100000)
3934 /* compute path for sysctl */
3935 snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
3936 device_get_unit(priv->mdev->pdev->dev.bsddev));
3938 /* try to fetch tunable, if any */
3939 TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
3941 /* compute path for sysctl */
3942 snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
3943 device_get_unit(priv->mdev->pdev->dev.bsddev));
3945 /* try to fetch tunable, if any */
3946 TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
3949 /* register pauseframe SYSCTLs */
3950 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3951 OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
3952 &priv->params.tx_pauseframe_control, 0,
3953 "Set to enable TX pause frames. Clear to disable.");
3955 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3956 OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
3957 &priv->params.rx_pauseframe_control, 0,
3958 "Set to enable RX pause frames. Clear to disable.");
3960 /* register priority flow control, PFC, SYSCTLs */
3961 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3962 OID_AUTO, "tx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
3963 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_tx_priority_flow_control, "CU",
3964 "Set to enable TX ports flow control frames for priorities 0..7. Clear to disable.");
3966 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3967 OID_AUTO, "rx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
3968 CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_rx_priority_flow_control, "CU",
3969 "Set to enable RX ports flow control frames for priorities 0..7. Clear to disable.");
3974 priv->params.tx_pauseframe_control =
3975 priv->params.tx_pauseframe_control ? 1 : 0;
3976 priv->params.rx_pauseframe_control =
3977 priv->params.rx_pauseframe_control ? 1 : 0;
3979 /* update firmware */
3980 error = mlx5e_set_port_pause_and_pfc(priv);
3981 if (error == -EINVAL) {
3982 mlx5_en_err(priv->ifp,
3983 "Global pauseframes must be disabled before enabling PFC.\n");
3984 priv->params.rx_priority_flow_control = 0;
3985 priv->params.tx_priority_flow_control = 0;
3987 /* update firmware */
3988 (void) mlx5e_set_port_pause_and_pfc(priv);
3994 mlx5e_ul_snd_tag_alloc(struct ifnet *ifp,
3995 union if_snd_tag_alloc_params *params,
3996 struct m_snd_tag **ppmt)
3998 struct mlx5e_priv *priv;
3999 struct mlx5e_channel *pch;
4001 priv = ifp->if_softc;
4003 if (unlikely(priv->gone || params->hdr.flowtype == M_HASHTYPE_NONE)) {
4004 return (EOPNOTSUPP);
4006 /* keep this code synced with mlx5e_select_queue() */
4007 u32 ch = priv->params.num_channels;
4011 if (rss_hash2bucket(params->hdr.flowid,
4012 params->hdr.flowtype, &temp) == 0)
4016 ch = (params->hdr.flowid % 128) % ch;
4019 * NOTE: The channels array is only freed at detach
4020 * and it safe to return a pointer to the send tag
4021 * inside the channels structure as long as we
4022 * reference the priv.
4024 pch = priv->channel + ch;
4026 /* check if send queue is not running */
4027 if (unlikely(pch->sq[0].running == 0))
4029 m_snd_tag_ref(&pch->tag.m_snd_tag);
4030 *ppmt = &pch->tag.m_snd_tag;
4036 mlx5e_ul_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
4038 struct mlx5e_channel *pch =
4039 container_of(pmt, struct mlx5e_channel, tag.m_snd_tag);
4041 params->unlimited.max_rate = -1ULL;
4042 params->unlimited.queue_level = mlx5e_sq_queue_level(&pch->sq[0]);
4047 mlx5e_ul_snd_tag_free(struct m_snd_tag *pmt)
4049 struct mlx5e_channel *pch =
4050 container_of(pmt, struct mlx5e_channel, tag.m_snd_tag);
4052 complete(&pch->completion);
4056 mlx5e_snd_tag_alloc(struct ifnet *ifp,
4057 union if_snd_tag_alloc_params *params,
4058 struct m_snd_tag **ppmt)
4061 switch (params->hdr.type) {
4063 case IF_SND_TAG_TYPE_RATE_LIMIT:
4064 return (mlx5e_rl_snd_tag_alloc(ifp, params, ppmt));
4066 case IF_SND_TAG_TYPE_UNLIMITED:
4067 return (mlx5e_ul_snd_tag_alloc(ifp, params, ppmt));
4069 return (EOPNOTSUPP);
4074 mlx5e_snd_tag_modify(struct m_snd_tag *pmt, union if_snd_tag_modify_params *params)
4076 struct mlx5e_snd_tag *tag =
4077 container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
4079 switch (tag->type) {
4081 case IF_SND_TAG_TYPE_RATE_LIMIT:
4082 return (mlx5e_rl_snd_tag_modify(pmt, params));
4084 case IF_SND_TAG_TYPE_UNLIMITED:
4086 return (EOPNOTSUPP);
4091 mlx5e_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
4093 struct mlx5e_snd_tag *tag =
4094 container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
4096 switch (tag->type) {
4098 case IF_SND_TAG_TYPE_RATE_LIMIT:
4099 return (mlx5e_rl_snd_tag_query(pmt, params));
4101 case IF_SND_TAG_TYPE_UNLIMITED:
4102 return (mlx5e_ul_snd_tag_query(pmt, params));
4104 return (EOPNOTSUPP);
4109 #define NUM_HDWR_RATES_MLX 13
4110 static const uint64_t adapter_rates_mlx[NUM_HDWR_RATES_MLX] = {
4111 135375, /* 1,083,000 */
4112 180500, /* 1,444,000 */
4113 270750, /* 2,166,000 */
4114 361000, /* 2,888,000 */
4115 541500, /* 4,332,000 */
4116 721875, /* 5,775,000 */
4117 1082875, /* 8,663,000 */
4118 1443875, /* 11,551,000 */
4119 2165750, /* 17,326,000 */
4120 2887750, /* 23,102,000 */
4121 4331625, /* 34,653,000 */
4122 5775500, /* 46,204,000 */
4123 8663125 /* 69,305,000 */
4127 mlx5e_ratelimit_query(struct ifnet *ifp __unused, struct if_ratelimit_query_results *q)
4130 * This function needs updating by the driver maintainer!
4131 * For the MLX card there are currently (ConectX-4?) 13
4132 * pre-set rates and others i.e. ConnectX-5, 6, 7??
4134 * This will change based on later adapters
4135 * and this code should be updated to look at ifp
4136 * and figure out the specific adapter type
4137 * settings i.e. how many rates as well
4138 * as if they are fixed (as is shown here) or
4139 * if they are dynamic (example chelsio t4). Also if there
4140 * is a maximum number of flows that the adapter
4141 * can handle that too needs to be updated in
4142 * the max_flows field.
4144 q->rate_table = adapter_rates_mlx;
4145 q->flags = RT_IS_FIXED_TABLE;
4146 q->max_flows = 0; /* mlx has no limit */
4147 q->number_of_rates = NUM_HDWR_RATES_MLX;
4148 q->min_segment_burst = 1;
4153 mlx5e_snd_tag_free(struct m_snd_tag *pmt)
4155 struct mlx5e_snd_tag *tag =
4156 container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
4158 switch (tag->type) {
4160 case IF_SND_TAG_TYPE_RATE_LIMIT:
4161 mlx5e_rl_snd_tag_free(pmt);
4164 case IF_SND_TAG_TYPE_UNLIMITED:
4165 mlx5e_ul_snd_tag_free(pmt);
4173 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
4176 struct mlx5e_priv *priv;
4177 u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
4179 struct sysctl_oid_list *child;
4180 int ncv = mdev->priv.eq_table.num_comp_vectors;
4182 struct pfil_head_args pa;
4186 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
4189 struct media media_entry = {};
4191 if (mlx5e_check_required_hca_cap(mdev)) {
4192 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
4196 * Try to allocate the priv and make room for worst-case
4197 * number of channel structures:
4199 priv = malloc(sizeof(*priv) +
4200 (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors),
4201 M_MLX5EN, M_WAITOK | M_ZERO);
4203 ifp = priv->ifp = if_alloc_dev(IFT_ETHER, mdev->pdev->dev.bsddev);
4205 mlx5_core_err(mdev, "if_alloc() failed\n");
4208 /* setup all static fields */
4209 mlx5e_priv_static_init(priv, mdev->priv.eq_table.num_comp_vectors);
4211 ifp->if_softc = priv;
4212 if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev));
4213 ifp->if_mtu = ETHERMTU;
4214 ifp->if_init = mlx5e_open;
4215 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
4216 ifp->if_ioctl = mlx5e_ioctl;
4217 ifp->if_transmit = mlx5e_xmit;
4218 ifp->if_qflush = if_qflush;
4219 #if (__FreeBSD_version >= 1100000)
4220 ifp->if_get_counter = mlx5e_get_counter;
4222 ifp->if_snd.ifq_maxlen = ifqmaxlen;
4224 * Set driver features
4226 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
4227 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
4228 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
4229 ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
4230 ifp->if_capabilities |= IFCAP_LRO;
4231 ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
4232 ifp->if_capabilities |= IFCAP_HWSTATS | IFCAP_HWRXTSTMP;
4233 ifp->if_capabilities |= IFCAP_NOMAP;
4234 ifp->if_capabilities |= IFCAP_TXRTLMT;
4235 ifp->if_snd_tag_alloc = mlx5e_snd_tag_alloc;
4236 ifp->if_snd_tag_free = mlx5e_snd_tag_free;
4237 ifp->if_snd_tag_modify = mlx5e_snd_tag_modify;
4238 ifp->if_snd_tag_query = mlx5e_snd_tag_query;
4240 ifp->if_ratelimit_query = mlx5e_ratelimit_query;
4242 /* set TSO limits so that we don't have to drop TX packets */
4243 ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
4244 ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
4245 ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
4247 ifp->if_capenable = ifp->if_capabilities;
4248 ifp->if_hwassist = 0;
4249 if (ifp->if_capenable & IFCAP_TSO)
4250 ifp->if_hwassist |= CSUM_TSO;
4251 if (ifp->if_capenable & IFCAP_TXCSUM)
4252 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
4253 if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
4254 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
4256 /* ifnet sysctl tree */
4257 sysctl_ctx_init(&priv->sysctl_ctx);
4258 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
4259 OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
4260 if (priv->sysctl_ifnet == NULL) {
4261 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4262 goto err_free_sysctl;
4264 snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
4265 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4266 OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
4267 if (priv->sysctl_ifnet == NULL) {
4268 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4269 goto err_free_sysctl;
4272 /* HW sysctl tree */
4273 child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
4274 priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
4275 OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
4276 if (priv->sysctl_hw == NULL) {
4277 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4278 goto err_free_sysctl;
4281 err = mlx5e_build_ifp_priv(mdev, priv, ncv);
4283 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err);
4284 goto err_free_sysctl;
4287 /* reuse mlx5core's watchdog workqueue */
4288 priv->wq = mdev->priv.health.wq_watchdog;
4290 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
4292 mlx5_en_err(ifp, "mlx5_alloc_map_uar failed, %d\n", err);
4295 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
4297 mlx5_en_err(ifp, "mlx5_core_alloc_pd failed, %d\n", err);
4298 goto err_unmap_free_uar;
4300 err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
4303 "mlx5_alloc_transport_domain failed, %d\n", err);
4304 goto err_dealloc_pd;
4306 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
4308 mlx5_en_err(ifp, "mlx5e_create_mkey failed, %d\n", err);
4309 goto err_dealloc_transport_domain;
4311 mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
4313 /* check if we should generate a random MAC address */
4314 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
4315 is_zero_ether_addr(dev_addr)) {
4316 random_ether_addr(dev_addr);
4317 mlx5_en_err(ifp, "Assigned random MAC address\n");
4320 err = mlx5e_rl_init(priv);
4322 mlx5_en_err(ifp, "mlx5e_rl_init failed, %d\n", err);
4323 goto err_create_mkey;
4327 /* set default MTU */
4328 mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
4330 /* Set default media status */
4331 priv->media_status_last = IFM_AVALID;
4332 priv->media_active_last = IFM_ETHER | IFM_AUTO |
4333 IFM_ETH_RXPAUSE | IFM_FDX;
4335 /* setup default pauseframes configuration */
4336 mlx5e_setup_pauseframes(priv);
4338 /* Setup supported medias */
4339 //TODO: If we failed to query ptys is it ok to proceed??
4340 if (!mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1)) {
4341 ext = MLX5_CAP_PCAM_FEATURE(mdev,
4342 ptys_extended_ethernet);
4343 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
4344 eth_proto_capability);
4345 if (MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type))
4346 connector_type = MLX5_GET(ptys_reg, out,
4350 mlx5_en_err(ifp, "Query port media capability failed, %d\n", err);
4353 ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
4354 mlx5e_media_change, mlx5e_media_status);
4356 speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER : MLX5E_LINK_SPEEDS_NUMBER;
4357 for (i = 0; i != speeds_num; i++) {
4358 for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) {
4359 media_entry = ext ? mlx5e_ext_mode_table[i][j] :
4360 mlx5e_mode_table[i][j];
4361 if (media_entry.baudrate == 0)
4363 if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
4364 ifmedia_add(&priv->media,
4365 media_entry.subtype |
4366 IFM_ETHER, 0, NULL);
4367 ifmedia_add(&priv->media,
4368 media_entry.subtype |
4369 IFM_ETHER | IFM_FDX |
4370 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
4375 ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
4376 ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
4377 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
4379 /* Set autoselect by default */
4380 ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
4381 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
4382 ether_ifattach(ifp, dev_addr);
4384 /* Register for VLAN events */
4385 priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
4386 mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
4387 priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
4388 mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
4390 /* Link is down by default */
4391 if_link_state_change(ifp, LINK_STATE_DOWN);
4393 mlx5e_enable_async_events(priv);
4395 mlx5e_add_hw_stats(priv);
4397 mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4398 "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
4399 priv->stats.vport.arg);
4401 mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4402 "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
4403 priv->stats.pport.arg);
4405 mlx5e_create_ethtool(priv);
4407 mtx_lock(&priv->async_events_mtx);
4408 mlx5e_update_stats(priv);
4409 mtx_unlock(&priv->async_events_mtx);
4411 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4412 OID_AUTO, "rx_clbr_done", CTLFLAG_RD,
4413 &priv->clbr_done, 0,
4414 "RX timestamps calibration state");
4415 callout_init(&priv->tstmp_clbr, CALLOUT_DIRECT);
4416 mlx5e_reset_calibration_callout(priv);
4418 pa.pa_version = PFIL_VERSION;
4419 pa.pa_flags = PFIL_IN;
4420 pa.pa_type = PFIL_TYPE_ETHERNET;
4421 pa.pa_headname = ifp->if_xname;
4422 priv->pfil = pfil_head_register(&pa);
4428 mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
4430 err_dealloc_transport_domain:
4431 mlx5_dealloc_transport_domain(mdev, priv->tdn);
4434 mlx5_core_dealloc_pd(mdev, priv->pdn);
4437 mlx5_unmap_free_uar(mdev, &priv->cq_uar);
4440 flush_workqueue(priv->wq);
4443 sysctl_ctx_free(&priv->sysctl_ctx);
4444 if (priv->sysctl_debug)
4445 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4446 mlx5e_priv_static_destroy(priv, mdev->priv.eq_table.num_comp_vectors);
4450 free(priv, M_MLX5EN);
4455 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
4457 struct mlx5e_priv *priv = vpriv;
4458 struct ifnet *ifp = priv->ifp;
4460 /* don't allow more IOCTLs */
4463 /* XXX wait a bit to allow IOCTL handlers to complete */
4468 * The kernel can have reference(s) via the m_snd_tag's into
4469 * the ratelimit channels, and these must go away before
4472 while (READ_ONCE(priv->rl.stats.tx_active_connections) != 0) {
4473 mlx5_en_err(priv->ifp,
4474 "Waiting for all ratelimit connections to terminate\n");
4478 /* wait for all unlimited send tags to complete */
4479 mlx5e_priv_wait_for_completion(priv, mdev->priv.eq_table.num_comp_vectors);
4481 /* stop watchdog timer */
4482 callout_drain(&priv->watchdog);
4484 callout_drain(&priv->tstmp_clbr);
4486 if (priv->vlan_attach != NULL)
4487 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
4488 if (priv->vlan_detach != NULL)
4489 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
4491 /* make sure device gets closed */
4493 mlx5e_close_locked(ifp);
4496 /* deregister pfil */
4497 if (priv->pfil != NULL) {
4498 pfil_head_unregister(priv->pfil);
4502 /* unregister device */
4503 ifmedia_removeall(&priv->media);
4504 ether_ifdetach(ifp);
4507 mlx5e_rl_cleanup(priv);
4509 /* destroy all remaining sysctl nodes */
4510 sysctl_ctx_free(&priv->stats.vport.ctx);
4511 sysctl_ctx_free(&priv->stats.pport.ctx);
4512 if (priv->sysctl_debug)
4513 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4514 sysctl_ctx_free(&priv->sysctl_ctx);
4516 mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
4517 mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
4518 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
4519 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
4520 mlx5e_disable_async_events(priv);
4521 flush_workqueue(priv->wq);
4522 mlx5e_priv_static_destroy(priv, mdev->priv.eq_table.num_comp_vectors);
4524 free(priv, M_MLX5EN);
4528 mlx5e_get_ifp(void *vpriv)
4530 struct mlx5e_priv *priv = vpriv;
4535 static struct mlx5_interface mlx5e_interface = {
4536 .add = mlx5e_create_ifp,
4537 .remove = mlx5e_destroy_ifp,
4538 .event = mlx5e_async_event,
4539 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4540 .get_dev = mlx5e_get_ifp,
4546 mlx5_register_interface(&mlx5e_interface);
4552 mlx5_unregister_interface(&mlx5e_interface);
4556 mlx5e_show_version(void __unused *arg)
4559 printf("%s", mlx5e_version);
4561 SYSINIT(mlx5e_show_version, SI_SUB_DRIVERS, SI_ORDER_ANY, mlx5e_show_version, NULL);
4563 module_init_order(mlx5e_init, SI_ORDER_THIRD);
4564 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
4566 #if (__FreeBSD_version >= 1100000)
4567 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
4569 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
4570 MODULE_VERSION(mlx5en, 1);