2 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/sockio.h>
31 #include <machine/atomic.h>
33 #define ETH_DRIVER_VERSION "3.1.0-dev"
34 char mlx5e_version[] = "Mellanox Ethernet driver"
35 " (" ETH_DRIVER_VERSION ")";
37 struct mlx5e_channel_param {
38 struct mlx5e_rq_param rq;
39 struct mlx5e_sq_param sq;
40 struct mlx5e_cq_param rx_cq;
41 struct mlx5e_cq_param tx_cq;
47 } mlx5e_mode_table[MLX5E_LINK_MODES_NUMBER] = {
49 [MLX5E_1000BASE_CX_SGMII] = {
50 .subtype = IFM_1000_CX_SGMII,
51 .baudrate = IF_Mbps(1000ULL),
53 [MLX5E_1000BASE_KX] = {
54 .subtype = IFM_1000_KX,
55 .baudrate = IF_Mbps(1000ULL),
57 [MLX5E_10GBASE_CX4] = {
58 .subtype = IFM_10G_CX4,
59 .baudrate = IF_Gbps(10ULL),
61 [MLX5E_10GBASE_KX4] = {
62 .subtype = IFM_10G_KX4,
63 .baudrate = IF_Gbps(10ULL),
65 [MLX5E_10GBASE_KR] = {
66 .subtype = IFM_10G_KR,
67 .baudrate = IF_Gbps(10ULL),
69 [MLX5E_20GBASE_KR2] = {
70 .subtype = IFM_20G_KR2,
71 .baudrate = IF_Gbps(20ULL),
73 [MLX5E_40GBASE_CR4] = {
74 .subtype = IFM_40G_CR4,
75 .baudrate = IF_Gbps(40ULL),
77 [MLX5E_40GBASE_KR4] = {
78 .subtype = IFM_40G_KR4,
79 .baudrate = IF_Gbps(40ULL),
81 [MLX5E_56GBASE_R4] = {
82 .subtype = IFM_56G_R4,
83 .baudrate = IF_Gbps(56ULL),
85 [MLX5E_10GBASE_CR] = {
86 .subtype = IFM_10G_CR1,
87 .baudrate = IF_Gbps(10ULL),
89 [MLX5E_10GBASE_SR] = {
90 .subtype = IFM_10G_SR,
91 .baudrate = IF_Gbps(10ULL),
93 [MLX5E_10GBASE_LR] = {
94 .subtype = IFM_10G_LR,
95 .baudrate = IF_Gbps(10ULL),
97 [MLX5E_40GBASE_SR4] = {
98 .subtype = IFM_40G_SR4,
99 .baudrate = IF_Gbps(40ULL),
101 [MLX5E_40GBASE_LR4] = {
102 .subtype = IFM_40G_LR4,
103 .baudrate = IF_Gbps(40ULL),
105 [MLX5E_100GBASE_CR4] = {
106 .subtype = IFM_100G_CR4,
107 .baudrate = IF_Gbps(100ULL),
109 [MLX5E_100GBASE_SR4] = {
110 .subtype = IFM_100G_SR4,
111 .baudrate = IF_Gbps(100ULL),
113 [MLX5E_100GBASE_KR4] = {
114 .subtype = IFM_100G_KR4,
115 .baudrate = IF_Gbps(100ULL),
117 [MLX5E_100GBASE_LR4] = {
118 .subtype = IFM_100G_LR4,
119 .baudrate = IF_Gbps(100ULL),
121 [MLX5E_100BASE_TX] = {
122 .subtype = IFM_100_TX,
123 .baudrate = IF_Mbps(100ULL),
125 [MLX5E_100BASE_T] = {
126 .subtype = IFM_100_T,
127 .baudrate = IF_Mbps(100ULL),
129 [MLX5E_10GBASE_T] = {
130 .subtype = IFM_10G_T,
131 .baudrate = IF_Gbps(10ULL),
133 [MLX5E_25GBASE_CR] = {
134 .subtype = IFM_25G_CR,
135 .baudrate = IF_Gbps(25ULL),
137 [MLX5E_25GBASE_KR] = {
138 .subtype = IFM_25G_KR,
139 .baudrate = IF_Gbps(25ULL),
141 [MLX5E_25GBASE_SR] = {
142 .subtype = IFM_25G_SR,
143 .baudrate = IF_Gbps(25ULL),
145 [MLX5E_50GBASE_CR2] = {
146 .subtype = IFM_50G_CR2,
147 .baudrate = IF_Gbps(50ULL),
149 [MLX5E_50GBASE_KR2] = {
150 .subtype = IFM_50G_KR2,
151 .baudrate = IF_Gbps(50ULL),
155 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
158 mlx5e_update_carrier(struct mlx5e_priv *priv)
160 struct mlx5_core_dev *mdev = priv->mdev;
161 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
167 port_state = mlx5_query_vport_state(mdev,
168 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
170 if (port_state == VPORT_STATE_UP) {
171 priv->media_status_last |= IFM_ACTIVE;
173 priv->media_status_last &= ~IFM_ACTIVE;
174 priv->media_active_last = IFM_ETHER;
175 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
179 error = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN);
181 priv->media_active_last = IFM_ETHER;
182 priv->ifp->if_baudrate = 1;
183 if_printf(priv->ifp, "%s: query port ptys failed: 0x%x\n",
187 eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
189 for (i = 0; i != MLX5E_LINK_MODES_NUMBER; i++) {
190 if (mlx5e_mode_table[i].baudrate == 0)
192 if (MLX5E_PROT_MASK(i) & eth_proto_oper) {
193 priv->ifp->if_baudrate =
194 mlx5e_mode_table[i].baudrate;
195 priv->media_active_last =
196 mlx5e_mode_table[i].subtype | IFM_ETHER | IFM_FDX;
199 if_link_state_change(priv->ifp, LINK_STATE_UP);
203 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
205 struct mlx5e_priv *priv = dev->if_softc;
207 ifmr->ifm_status = priv->media_status_last;
208 ifmr->ifm_active = priv->media_active_last |
209 (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
210 (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
215 mlx5e_find_link_mode(u32 subtype)
220 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
221 if (mlx5e_mode_table[i].baudrate == 0)
223 if (mlx5e_mode_table[i].subtype == subtype)
224 link_mode |= MLX5E_PROT_MASK(i);
231 mlx5e_media_change(struct ifnet *dev)
233 struct mlx5e_priv *priv = dev->if_softc;
234 struct mlx5_core_dev *mdev = priv->mdev;
241 locked = PRIV_LOCKED(priv);
245 if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
249 link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media));
251 /* query supported capabilities */
252 error = mlx5_query_port_proto_cap(mdev, ð_proto_cap, MLX5_PTYS_EN);
254 if_printf(dev, "Query port media capability failed\n");
257 /* check for autoselect */
258 if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
259 link_mode = eth_proto_cap;
260 if (link_mode == 0) {
261 if_printf(dev, "Port media capability is zero\n");
266 link_mode = link_mode & eth_proto_cap;
267 if (link_mode == 0) {
268 if_printf(dev, "Not supported link mode requested\n");
273 /* update pauseframe control bits */
274 priv->params.rx_pauseframe_control =
275 (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
276 priv->params.tx_pauseframe_control =
277 (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
279 /* check if device is opened */
280 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
282 /* reconfigure the hardware */
283 mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
284 mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN);
285 mlx5_set_port_pause(mdev, 1,
286 priv->params.rx_pauseframe_control,
287 priv->params.tx_pauseframe_control);
289 mlx5_set_port_status(mdev, MLX5_PORT_UP);
298 mlx5e_update_carrier_work(struct work_struct *work)
300 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
301 update_carrier_work);
304 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
305 mlx5e_update_carrier(priv);
310 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
312 struct mlx5_core_dev *mdev = priv->mdev;
313 struct mlx5e_pport_stats *s = &priv->stats.pport;
314 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
318 unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
322 in = mlx5_vzalloc(sz);
323 out = mlx5_vzalloc(sz);
324 if (in == NULL || out == NULL)
327 ptr = (uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
329 MLX5_SET(ppcnt_reg, in, local_port, 1);
331 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
332 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
333 for (x = y = 0; x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
334 s->arg[y] = be64toh(ptr[x]);
336 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
337 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
338 for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
339 s->arg[y] = be64toh(ptr[x]);
340 for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
341 MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
342 s_debug->arg[y] = be64toh(ptr[x]);
344 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
345 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
346 for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
347 s_debug->arg[y] = be64toh(ptr[x]);
349 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
350 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
351 for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
352 s_debug->arg[y] = be64toh(ptr[x]);
359 mlx5e_update_stats_work(struct work_struct *work)
361 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
363 struct mlx5_core_dev *mdev = priv->mdev;
364 struct mlx5e_vport_stats *s = &priv->stats.vport;
365 struct mlx5e_rq_stats *rq_stats;
366 struct mlx5e_sq_stats *sq_stats;
367 struct buf_ring *sq_br;
368 #if (__FreeBSD_version < 1100000)
369 struct ifnet *ifp = priv->ifp;
372 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
374 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
377 u64 tx_queue_dropped = 0;
378 u64 tx_defragged = 0;
379 u64 tx_offload_none = 0;
382 u64 sw_lro_queued = 0;
383 u64 sw_lro_flushed = 0;
384 u64 rx_csum_none = 0;
386 u32 rx_out_of_buffer = 0;
391 out = mlx5_vzalloc(outlen);
394 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
397 /* Collect firts the SW counters and then HW for consistency */
398 for (i = 0; i < priv->params.num_channels; i++) {
399 struct mlx5e_rq *rq = &priv->channel[i]->rq;
401 rq_stats = &priv->channel[i]->rq.stats;
403 /* collect stats from LRO */
404 rq_stats->sw_lro_queued = rq->lro.lro_queued;
405 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
406 sw_lro_queued += rq_stats->sw_lro_queued;
407 sw_lro_flushed += rq_stats->sw_lro_flushed;
408 lro_packets += rq_stats->lro_packets;
409 lro_bytes += rq_stats->lro_bytes;
410 rx_csum_none += rq_stats->csum_none;
411 rx_wqe_err += rq_stats->wqe_err;
413 for (j = 0; j < priv->num_tc; j++) {
414 sq_stats = &priv->channel[i]->sq[j].stats;
415 sq_br = priv->channel[i]->sq[j].br;
417 tso_packets += sq_stats->tso_packets;
418 tso_bytes += sq_stats->tso_bytes;
419 tx_queue_dropped += sq_stats->dropped;
420 tx_queue_dropped += sq_br->br_drops;
421 tx_defragged += sq_stats->defragged;
422 tx_offload_none += sq_stats->csum_offload_none;
426 /* update counters */
427 s->tso_packets = tso_packets;
428 s->tso_bytes = tso_bytes;
429 s->tx_queue_dropped = tx_queue_dropped;
430 s->tx_defragged = tx_defragged;
431 s->lro_packets = lro_packets;
432 s->lro_bytes = lro_bytes;
433 s->sw_lro_queued = sw_lro_queued;
434 s->sw_lro_flushed = sw_lro_flushed;
435 s->rx_csum_none = rx_csum_none;
436 s->rx_wqe_err = rx_wqe_err;
439 memset(in, 0, sizeof(in));
441 MLX5_SET(query_vport_counter_in, in, opcode,
442 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
443 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
444 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
446 memset(out, 0, outlen);
448 /* get number of out-of-buffer drops first */
449 if (mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
453 /* accumulate difference into a 64-bit counter */
454 s->rx_out_of_buffer += (u64)(u32)(rx_out_of_buffer - s->rx_out_of_buffer_prev);
455 s->rx_out_of_buffer_prev = rx_out_of_buffer;
457 /* get port statistics */
458 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
461 #define MLX5_GET_CTR(out, x) \
462 MLX5_GET64(query_vport_counter_out, out, x)
464 s->rx_error_packets =
465 MLX5_GET_CTR(out, received_errors.packets);
467 MLX5_GET_CTR(out, received_errors.octets);
468 s->tx_error_packets =
469 MLX5_GET_CTR(out, transmit_errors.packets);
471 MLX5_GET_CTR(out, transmit_errors.octets);
473 s->rx_unicast_packets =
474 MLX5_GET_CTR(out, received_eth_unicast.packets);
475 s->rx_unicast_bytes =
476 MLX5_GET_CTR(out, received_eth_unicast.octets);
477 s->tx_unicast_packets =
478 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
479 s->tx_unicast_bytes =
480 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
482 s->rx_multicast_packets =
483 MLX5_GET_CTR(out, received_eth_multicast.packets);
484 s->rx_multicast_bytes =
485 MLX5_GET_CTR(out, received_eth_multicast.octets);
486 s->tx_multicast_packets =
487 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
488 s->tx_multicast_bytes =
489 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
491 s->rx_broadcast_packets =
492 MLX5_GET_CTR(out, received_eth_broadcast.packets);
493 s->rx_broadcast_bytes =
494 MLX5_GET_CTR(out, received_eth_broadcast.octets);
495 s->tx_broadcast_packets =
496 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
497 s->tx_broadcast_bytes =
498 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
501 s->rx_unicast_packets +
502 s->rx_multicast_packets +
503 s->rx_broadcast_packets -
506 s->rx_unicast_bytes +
507 s->rx_multicast_bytes +
508 s->rx_broadcast_bytes;
510 s->tx_unicast_packets +
511 s->tx_multicast_packets +
512 s->tx_broadcast_packets;
514 s->tx_unicast_bytes +
515 s->tx_multicast_bytes +
516 s->tx_broadcast_bytes;
518 /* Update calculated offload counters */
519 s->tx_csum_offload = s->tx_packets - tx_offload_none;
520 s->rx_csum_good = s->rx_packets - s->rx_csum_none;
522 /* Update per port counters */
523 mlx5e_update_pport_counters(priv);
525 #if (__FreeBSD_version < 1100000)
526 /* no get_counters interface in fbsd 10 */
527 ifp->if_ipackets = s->rx_packets;
528 ifp->if_ierrors = s->rx_error_packets;
529 ifp->if_iqdrops = s->rx_out_of_buffer;
530 ifp->if_opackets = s->tx_packets;
531 ifp->if_oerrors = s->tx_error_packets;
532 ifp->if_snd.ifq_drops = s->tx_queue_dropped;
533 ifp->if_ibytes = s->rx_bytes;
534 ifp->if_obytes = s->tx_bytes;
543 mlx5e_update_stats(void *arg)
545 struct mlx5e_priv *priv = arg;
547 schedule_work(&priv->update_stats_work);
549 callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
553 mlx5e_async_event_sub(struct mlx5e_priv *priv,
554 enum mlx5_dev_event event)
557 case MLX5_DEV_EVENT_PORT_UP:
558 case MLX5_DEV_EVENT_PORT_DOWN:
559 schedule_work(&priv->update_carrier_work);
568 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
569 enum mlx5_dev_event event, unsigned long param)
571 struct mlx5e_priv *priv = vpriv;
573 mtx_lock(&priv->async_events_mtx);
574 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
575 mlx5e_async_event_sub(priv, event);
576 mtx_unlock(&priv->async_events_mtx);
580 mlx5e_enable_async_events(struct mlx5e_priv *priv)
582 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
586 mlx5e_disable_async_events(struct mlx5e_priv *priv)
588 mtx_lock(&priv->async_events_mtx);
589 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
590 mtx_unlock(&priv->async_events_mtx);
593 static const char *mlx5e_rq_stats_desc[] = {
594 MLX5E_RQ_STATS(MLX5E_STATS_DESC)
598 mlx5e_create_rq(struct mlx5e_channel *c,
599 struct mlx5e_rq_param *param,
602 struct mlx5e_priv *priv = c->priv;
603 struct mlx5_core_dev *mdev = priv->mdev;
605 void *rqc = param->rqc;
606 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
611 /* Create DMA descriptor TAG */
612 if ((err = -bus_dma_tag_create(
613 bus_get_dma_tag(mdev->pdev->dev.bsddev),
614 1, /* any alignment */
616 BUS_SPACE_MAXADDR, /* lowaddr */
617 BUS_SPACE_MAXADDR, /* highaddr */
618 NULL, NULL, /* filter, filterarg */
619 MJUM16BYTES, /* maxsize */
621 MJUM16BYTES, /* maxsegsize */
623 NULL, NULL, /* lockfunc, lockfuncarg */
627 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
630 goto err_free_dma_tag;
632 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
634 if (priv->params.hw_lro_en) {
635 rq->wqe_sz = priv->params.lro_wqe_sz;
637 rq->wqe_sz = MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
639 if (rq->wqe_sz > MJUM16BYTES) {
641 goto err_rq_wq_destroy;
642 } else if (rq->wqe_sz > MJUM9BYTES) {
643 rq->wqe_sz = MJUM16BYTES;
644 } else if (rq->wqe_sz > MJUMPAGESIZE) {
645 rq->wqe_sz = MJUM9BYTES;
646 } else if (rq->wqe_sz > MCLBYTES) {
647 rq->wqe_sz = MJUMPAGESIZE;
649 rq->wqe_sz = MCLBYTES;
652 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
654 err = -tcp_lro_init_args(&rq->lro, c->ifp, TCP_LRO_ENTRIES, wq_sz);
656 goto err_rq_wq_destroy;
658 rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
659 if (rq->mbuf == NULL) {
663 for (i = 0; i != wq_sz; i++) {
664 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
665 uint32_t byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
667 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
670 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
671 goto err_rq_mbuf_free;
673 wqe->data.lkey = c->mkey_be;
674 wqe->data.byte_count = cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
681 snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
682 mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
683 buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
688 free(rq->mbuf, M_MLX5EN);
690 tcp_lro_free(&rq->lro);
692 mlx5_wq_destroy(&rq->wq_ctrl);
694 bus_dma_tag_destroy(rq->dma_tag);
700 mlx5e_destroy_rq(struct mlx5e_rq *rq)
705 /* destroy all sysctl nodes */
706 sysctl_ctx_free(&rq->stats.ctx);
708 /* free leftover LRO packets, if any */
709 tcp_lro_free(&rq->lro);
711 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
712 for (i = 0; i != wq_sz; i++) {
713 if (rq->mbuf[i].mbuf != NULL) {
714 bus_dmamap_unload(rq->dma_tag,
715 rq->mbuf[i].dma_map);
716 m_freem(rq->mbuf[i].mbuf);
718 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
720 free(rq->mbuf, M_MLX5EN);
721 mlx5_wq_destroy(&rq->wq_ctrl);
725 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
727 struct mlx5e_channel *c = rq->channel;
728 struct mlx5e_priv *priv = c->priv;
729 struct mlx5_core_dev *mdev = priv->mdev;
737 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
738 sizeof(u64) * rq->wq_ctrl.buf.npages;
739 in = mlx5_vzalloc(inlen);
743 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
744 wq = MLX5_ADDR_OF(rqc, rqc, wq);
746 memcpy(rqc, param->rqc, sizeof(param->rqc));
748 MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
749 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
750 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
751 if (priv->counter_set_id >= 0)
752 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
753 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
755 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
757 mlx5_fill_page_array(&rq->wq_ctrl.buf,
758 (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
760 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
768 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
770 struct mlx5e_channel *c = rq->channel;
771 struct mlx5e_priv *priv = c->priv;
772 struct mlx5_core_dev *mdev = priv->mdev;
779 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
780 in = mlx5_vzalloc(inlen);
784 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
786 MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
787 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
788 MLX5_SET(rqc, rqc, state, next_state);
790 err = mlx5_core_modify_rq(mdev, in, inlen);
798 mlx5e_disable_rq(struct mlx5e_rq *rq)
800 struct mlx5e_channel *c = rq->channel;
801 struct mlx5e_priv *priv = c->priv;
802 struct mlx5_core_dev *mdev = priv->mdev;
804 mlx5_core_destroy_rq(mdev, rq->rqn);
808 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
810 struct mlx5e_channel *c = rq->channel;
811 struct mlx5e_priv *priv = c->priv;
812 struct mlx5_wq_ll *wq = &rq->wq;
815 for (i = 0; i < 1000; i++) {
816 if (wq->cur_sz >= priv->params.min_rx_wqes)
825 mlx5e_open_rq(struct mlx5e_channel *c,
826 struct mlx5e_rq_param *param,
831 err = mlx5e_create_rq(c, param, rq);
835 err = mlx5e_enable_rq(rq, param);
839 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
848 mlx5e_disable_rq(rq);
850 mlx5e_destroy_rq(rq);
856 mlx5e_close_rq(struct mlx5e_rq *rq)
859 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
863 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
865 /* wait till RQ is empty */
866 while (!mlx5_wq_ll_is_empty(&rq->wq)) {
868 rq->cq.mcq.comp(&rq->cq.mcq);
871 mlx5e_disable_rq(rq);
872 mlx5e_destroy_rq(rq);
876 mlx5e_free_sq_db(struct mlx5e_sq *sq)
878 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
881 for (x = 0; x != wq_sz; x++)
882 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
883 free(sq->mbuf, M_MLX5EN);
887 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
889 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
893 sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
894 if (sq->mbuf == NULL)
897 /* Create DMA descriptor MAPs */
898 for (x = 0; x != wq_sz; x++) {
899 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
902 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
903 free(sq->mbuf, M_MLX5EN);
910 static const char *mlx5e_sq_stats_desc[] = {
911 MLX5E_SQ_STATS(MLX5E_STATS_DESC)
915 mlx5e_create_sq(struct mlx5e_channel *c,
917 struct mlx5e_sq_param *param,
920 struct mlx5e_priv *priv = c->priv;
921 struct mlx5_core_dev *mdev = priv->mdev;
924 void *sqc = param->sqc;
925 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
932 /* Create DMA descriptor TAG */
933 if ((err = -bus_dma_tag_create(
934 bus_get_dma_tag(mdev->pdev->dev.bsddev),
935 1, /* any alignment */
937 BUS_SPACE_MAXADDR, /* lowaddr */
938 BUS_SPACE_MAXADDR, /* highaddr */
939 NULL, NULL, /* filter, filterarg */
940 MLX5E_MAX_TX_PAYLOAD_SIZE, /* maxsize */
941 MLX5E_MAX_TX_MBUF_FRAGS, /* nsegments */
942 MLX5E_MAX_TX_MBUF_SIZE, /* maxsegsize */
944 NULL, NULL, /* lockfunc, lockfuncarg */
948 err = mlx5_alloc_map_uar(mdev, &sq->uar);
950 goto err_free_dma_tag;
952 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq,
955 goto err_unmap_free_uar;
957 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
958 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
960 err = mlx5e_alloc_sq_db(sq);
962 goto err_sq_wq_destroy;
964 sq->mkey_be = c->mkey_be;
969 sq->br = buf_ring_alloc(MLX5E_SQ_TX_QUEUE_SIZE, M_MLX5EN,
970 M_WAITOK, &sq->lock);
971 if (sq->br == NULL) {
972 if_printf(c->ifp, "%s: Failed allocating sq drbr buffer\n",
978 sq->sq_tq = taskqueue_create_fast("mlx5e_que", M_WAITOK,
979 taskqueue_thread_enqueue, &sq->sq_tq);
980 if (sq->sq_tq == NULL) {
981 if_printf(c->ifp, "%s: Failed allocating taskqueue\n",
987 TASK_INIT(&sq->sq_task, 0, mlx5e_tx_que, sq);
989 cpu_id = rss_getcpu(c->ix % rss_getnumbuckets());
990 CPU_SETOF(cpu_id, &cpu_mask);
991 taskqueue_start_threads_cpuset(&sq->sq_tq, 1, PI_NET, &cpu_mask,
992 "%s TX SQ%d.%d CPU%d", c->ifp->if_xname, c->ix, tc, cpu_id);
994 taskqueue_start_threads(&sq->sq_tq, 1, PI_NET,
995 "%s TX SQ%d.%d", c->ifp->if_xname, c->ix, tc);
997 snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
998 mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
999 buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1005 buf_ring_free(sq->br, M_MLX5EN);
1007 mlx5e_free_sq_db(sq);
1009 mlx5_wq_destroy(&sq->wq_ctrl);
1012 mlx5_unmap_free_uar(mdev, &sq->uar);
1015 bus_dma_tag_destroy(sq->dma_tag);
1021 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1023 /* destroy all sysctl nodes */
1024 sysctl_ctx_free(&sq->stats.ctx);
1026 mlx5e_free_sq_db(sq);
1027 mlx5_wq_destroy(&sq->wq_ctrl);
1028 mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1029 taskqueue_drain(sq->sq_tq, &sq->sq_task);
1030 taskqueue_free(sq->sq_tq);
1031 buf_ring_free(sq->br, M_MLX5EN);
1035 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1044 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1045 sizeof(u64) * sq->wq_ctrl.buf.npages;
1046 in = mlx5_vzalloc(inlen);
1050 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1051 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1053 memcpy(sqc, param->sqc, sizeof(param->sqc));
1055 MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1056 MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1057 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1058 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1059 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1061 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1062 MLX5_SET(wq, wq, uar_page, sq->uar.index);
1063 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1065 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1067 mlx5_fill_page_array(&sq->wq_ctrl.buf,
1068 (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1070 err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1078 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1085 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1086 in = mlx5_vzalloc(inlen);
1090 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1092 MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1093 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1094 MLX5_SET(sqc, sqc, state, next_state);
1096 err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1104 mlx5e_disable_sq(struct mlx5e_sq *sq)
1107 mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1111 mlx5e_open_sq(struct mlx5e_channel *c,
1113 struct mlx5e_sq_param *param,
1114 struct mlx5e_sq *sq)
1118 err = mlx5e_create_sq(c, tc, param, sq);
1122 err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1124 goto err_destroy_sq;
1126 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1128 goto err_disable_sq;
1130 atomic_store_rel_int(&sq->queue_state, MLX5E_SQ_READY);
1135 mlx5e_disable_sq(sq);
1137 mlx5e_destroy_sq(sq);
1143 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1145 /* fill up remainder with NOPs */
1146 while (sq->cev_counter != 0) {
1147 while (!mlx5e_sq_has_room_for(sq, 1)) {
1148 if (can_sleep != 0) {
1149 mtx_unlock(&sq->lock);
1151 mtx_lock(&sq->lock);
1156 /* send a single NOP */
1157 mlx5e_send_nop(sq, 1);
1161 /* Check if we need to write the doorbell */
1162 if (likely(sq->doorbell.d64 != 0)) {
1163 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1164 sq->doorbell.d64 = 0;
1170 mlx5e_sq_cev_timeout(void *arg)
1172 struct mlx5e_sq *sq = arg;
1174 mtx_assert(&sq->lock, MA_OWNED);
1176 /* check next state */
1177 switch (sq->cev_next_state) {
1178 case MLX5E_CEV_STATE_SEND_NOPS:
1179 /* fill TX ring with NOPs, if any */
1180 mlx5e_sq_send_nops_locked(sq, 0);
1182 /* check if completed */
1183 if (sq->cev_counter == 0) {
1184 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1189 /* send NOPs on next timeout */
1190 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1195 callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1199 mlx5e_drain_sq(struct mlx5e_sq *sq)
1202 mtx_lock(&sq->lock);
1203 /* teardown event factor timer, if any */
1204 sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1205 callout_stop(&sq->cev_callout);
1207 /* send dummy NOPs in order to flush the transmit ring */
1208 mlx5e_sq_send_nops_locked(sq, 1);
1209 mtx_unlock(&sq->lock);
1211 /* make sure it is safe to free the callout */
1212 callout_drain(&sq->cev_callout);
1214 /* error out remaining requests */
1215 mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1217 /* wait till SQ is empty */
1218 mtx_lock(&sq->lock);
1219 while (sq->cc != sq->pc) {
1220 mtx_unlock(&sq->lock);
1222 sq->cq.mcq.comp(&sq->cq.mcq);
1223 mtx_lock(&sq->lock);
1225 mtx_unlock(&sq->lock);
1229 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1233 mlx5e_disable_sq(sq);
1234 mlx5e_destroy_sq(sq);
1238 mlx5e_create_cq(struct mlx5e_priv *priv,
1239 struct mlx5e_cq_param *param,
1240 struct mlx5e_cq *cq,
1241 mlx5e_cq_comp_t *comp,
1244 struct mlx5_core_dev *mdev = priv->mdev;
1245 struct mlx5_core_cq *mcq = &cq->mcq;
1251 param->wq.buf_numa_node = 0;
1252 param->wq.db_numa_node = 0;
1254 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1259 mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1262 mcq->set_ci_db = cq->wq_ctrl.db.db;
1263 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1264 *mcq->set_ci_db = 0;
1266 mcq->vector = eq_ix;
1268 mcq->event = mlx5e_cq_error_event;
1270 mcq->uar = &priv->cq_uar;
1272 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1273 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1284 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1286 mlx5_wq_destroy(&cq->wq_ctrl);
1290 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1292 struct mlx5_core_cq *mcq = &cq->mcq;
1300 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1301 sizeof(u64) * cq->wq_ctrl.buf.npages;
1302 in = mlx5_vzalloc(inlen);
1306 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1308 memcpy(cqc, param->cqc, sizeof(param->cqc));
1310 mlx5_fill_page_array(&cq->wq_ctrl.buf,
1311 (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1313 mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
1315 MLX5_SET(cqc, cqc, c_eqn, eqn);
1316 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1317 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1319 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1321 err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
1334 mlx5e_disable_cq(struct mlx5e_cq *cq)
1337 mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
1341 mlx5e_open_cq(struct mlx5e_priv *priv,
1342 struct mlx5e_cq_param *param,
1343 struct mlx5e_cq *cq,
1344 mlx5e_cq_comp_t *comp,
1349 err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
1353 err = mlx5e_enable_cq(cq, param, eq_ix);
1355 goto err_destroy_cq;
1360 mlx5e_destroy_cq(cq);
1366 mlx5e_close_cq(struct mlx5e_cq *cq)
1368 mlx5e_disable_cq(cq);
1369 mlx5e_destroy_cq(cq);
1373 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1374 struct mlx5e_channel_param *cparam)
1379 for (tc = 0; tc < c->num_tc; tc++) {
1380 /* open completion queue */
1381 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
1382 &mlx5e_tx_cq_comp, c->ix);
1384 goto err_close_tx_cqs;
1389 for (tc--; tc >= 0; tc--)
1390 mlx5e_close_cq(&c->sq[tc].cq);
1396 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1400 for (tc = 0; tc < c->num_tc; tc++)
1401 mlx5e_close_cq(&c->sq[tc].cq);
1405 mlx5e_open_sqs(struct mlx5e_channel *c,
1406 struct mlx5e_channel_param *cparam)
1411 for (tc = 0; tc < c->num_tc; tc++) {
1412 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1420 for (tc--; tc >= 0; tc--)
1421 mlx5e_close_sq_wait(&c->sq[tc]);
1427 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
1431 for (tc = 0; tc < c->num_tc; tc++)
1432 mlx5e_close_sq_wait(&c->sq[tc]);
1436 mlx5e_chan_mtx_init(struct mlx5e_channel *c)
1440 mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
1442 for (tc = 0; tc < c->num_tc; tc++) {
1443 struct mlx5e_sq *sq = c->sq + tc;
1445 mtx_init(&sq->lock, "mlx5tx", MTX_NETWORK_LOCK, MTX_DEF);
1446 mtx_init(&sq->comp_lock, "mlx5comp", MTX_NETWORK_LOCK,
1449 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
1451 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1453 /* ensure the TX completion event factor is not zero */
1454 if (sq->cev_factor == 0)
1460 mlx5e_chan_mtx_destroy(struct mlx5e_channel *c)
1464 mtx_destroy(&c->rq.mtx);
1466 for (tc = 0; tc < c->num_tc; tc++) {
1467 mtx_destroy(&c->sq[tc].lock);
1468 mtx_destroy(&c->sq[tc].comp_lock);
1473 mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1474 struct mlx5e_channel_param *cparam,
1475 struct mlx5e_channel *volatile *cp)
1477 struct mlx5e_channel *c;
1480 c = malloc(sizeof(*c), M_MLX5EN, M_WAITOK | M_ZERO);
1488 c->mkey_be = cpu_to_be32(priv->mr.key);
1489 c->num_tc = priv->num_tc;
1492 mlx5e_chan_mtx_init(c);
1494 /* open transmit completion queue */
1495 err = mlx5e_open_tx_cqs(c, cparam);
1499 /* open receive completion queue */
1500 err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
1501 &mlx5e_rx_cq_comp, c->ix);
1503 goto err_close_tx_cqs;
1505 err = mlx5e_open_sqs(c, cparam);
1507 goto err_close_rx_cq;
1509 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1513 /* store channel pointer */
1516 /* poll receive queue initially */
1517 c->rq.cq.mcq.comp(&c->rq.cq.mcq);
1522 mlx5e_close_sqs_wait(c);
1525 mlx5e_close_cq(&c->rq.cq);
1528 mlx5e_close_tx_cqs(c);
1531 /* destroy mutexes */
1532 mlx5e_chan_mtx_destroy(c);
1538 mlx5e_close_channel(struct mlx5e_channel *volatile *pp)
1540 struct mlx5e_channel *c = *pp;
1542 /* check if channel is already closed */
1545 mlx5e_close_rq(&c->rq);
1549 mlx5e_close_channel_wait(struct mlx5e_channel *volatile *pp)
1551 struct mlx5e_channel *c = *pp;
1553 /* check if channel is already closed */
1556 /* ensure channel pointer is no longer used */
1559 mlx5e_close_rq_wait(&c->rq);
1560 mlx5e_close_sqs_wait(c);
1561 mlx5e_close_cq(&c->rq.cq);
1562 mlx5e_close_tx_cqs(c);
1563 /* destroy mutexes */
1564 mlx5e_chan_mtx_destroy(c);
1569 mlx5e_build_rq_param(struct mlx5e_priv *priv,
1570 struct mlx5e_rq_param *param)
1572 void *rqc = param->rqc;
1573 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1575 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1576 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1577 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1578 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1579 MLX5_SET(wq, wq, pd, priv->pdn);
1581 param->wq.buf_numa_node = 0;
1582 param->wq.db_numa_node = 0;
1583 param->wq.linear = 1;
1587 mlx5e_build_sq_param(struct mlx5e_priv *priv,
1588 struct mlx5e_sq_param *param)
1590 void *sqc = param->sqc;
1591 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1593 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1594 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1595 MLX5_SET(wq, wq, pd, priv->pdn);
1597 param->wq.buf_numa_node = 0;
1598 param->wq.db_numa_node = 0;
1599 param->wq.linear = 1;
1603 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1604 struct mlx5e_cq_param *param)
1606 void *cqc = param->cqc;
1608 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1612 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1613 struct mlx5e_cq_param *param)
1615 void *cqc = param->cqc;
1619 * TODO The sysctl to control on/off is a bool value for now, which means
1620 * we only support CSUM, once HASH is implemnted we'll need to address that.
1622 if (priv->params.cqe_zipping_en) {
1623 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1624 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
1627 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1628 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1629 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1631 switch (priv->params.rx_cq_moderation_mode) {
1633 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1636 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1637 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1639 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1643 mlx5e_build_common_cq_param(priv, param);
1647 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1648 struct mlx5e_cq_param *param)
1650 void *cqc = param->cqc;
1652 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1653 MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
1654 MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
1656 switch (priv->params.tx_cq_moderation_mode) {
1658 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1661 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1662 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1664 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1668 mlx5e_build_common_cq_param(priv, param);
1672 mlx5e_build_channel_param(struct mlx5e_priv *priv,
1673 struct mlx5e_channel_param *cparam)
1675 memset(cparam, 0, sizeof(*cparam));
1677 mlx5e_build_rq_param(priv, &cparam->rq);
1678 mlx5e_build_sq_param(priv, &cparam->sq);
1679 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1680 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1684 mlx5e_open_channels(struct mlx5e_priv *priv)
1686 struct mlx5e_channel_param cparam;
1692 priv->channel = malloc(priv->params.num_channels *
1693 sizeof(struct mlx5e_channel *), M_MLX5EN, M_WAITOK | M_ZERO);
1694 if (priv->channel == NULL)
1697 mlx5e_build_channel_param(priv, &cparam);
1698 for (i = 0; i < priv->params.num_channels; i++) {
1699 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1701 goto err_close_channels;
1704 for (j = 0; j < priv->params.num_channels; j++) {
1705 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1707 goto err_close_channels;
1713 for (i--; i >= 0; i--) {
1714 mlx5e_close_channel(&priv->channel[i]);
1715 mlx5e_close_channel_wait(&priv->channel[i]);
1718 /* remove "volatile" attribute from "channel" pointer */
1719 ptr = __DECONST(void *, priv->channel);
1720 priv->channel = NULL;
1722 free(ptr, M_MLX5EN);
1728 mlx5e_close_channels(struct mlx5e_priv *priv)
1733 if (priv->channel == NULL)
1736 for (i = 0; i < priv->params.num_channels; i++)
1737 mlx5e_close_channel(&priv->channel[i]);
1738 for (i = 0; i < priv->params.num_channels; i++)
1739 mlx5e_close_channel_wait(&priv->channel[i]);
1741 /* remove "volatile" attribute from "channel" pointer */
1742 ptr = __DECONST(void *, priv->channel);
1743 priv->channel = NULL;
1745 free(ptr, M_MLX5EN);
1749 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
1751 return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
1752 priv->params.tx_cq_moderation_usec,
1753 priv->params.tx_cq_moderation_pkts));
1757 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
1759 return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
1760 priv->params.rx_cq_moderation_usec,
1761 priv->params.rx_cq_moderation_pkts));
1765 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1773 err = mlx5e_refresh_rq_params(priv, &c->rq);
1777 for (i = 0; i != c->num_tc; i++) {
1778 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
1787 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
1791 if (priv->channel == NULL)
1794 for (i = 0; i < priv->params.num_channels; i++) {
1797 err = mlx5e_refresh_channel_params_sub(priv, priv->channel[i]);
1805 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
1807 struct mlx5_core_dev *mdev = priv->mdev;
1808 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1809 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1811 memset(in, 0, sizeof(in));
1813 MLX5_SET(tisc, tisc, prio, tc);
1814 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1816 return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
1820 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
1822 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1826 mlx5e_open_tises(struct mlx5e_priv *priv)
1828 int num_tc = priv->num_tc;
1832 for (tc = 0; tc < num_tc; tc++) {
1833 err = mlx5e_open_tis(priv, tc);
1835 goto err_close_tises;
1841 for (tc--; tc >= 0; tc--)
1842 mlx5e_close_tis(priv, tc);
1848 mlx5e_close_tises(struct mlx5e_priv *priv)
1850 int num_tc = priv->num_tc;
1853 for (tc = 0; tc < num_tc; tc++)
1854 mlx5e_close_tis(priv, tc);
1858 mlx5e_open_rqt(struct mlx5e_priv *priv)
1860 struct mlx5_core_dev *mdev = priv->mdev;
1862 u32 out[MLX5_ST_SZ_DW(create_rqt_out)];
1869 sz = 1 << priv->params.rx_hash_log_tbl_sz;
1871 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1872 in = mlx5_vzalloc(inlen);
1875 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1877 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1878 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1880 for (i = 0; i < sz; i++) {
1883 ix = rss_get_indirection_to_bucket(i);
1887 /* ensure we don't overflow */
1888 ix %= priv->params.num_channels;
1889 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix]->rq.rqn);
1892 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1894 memset(out, 0, sizeof(out));
1895 err = mlx5_cmd_exec_check_status(mdev, in, inlen, out, sizeof(out));
1897 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
1905 mlx5e_close_rqt(struct mlx5e_priv *priv)
1907 u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)];
1908 u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)];
1910 memset(in, 0, sizeof(in));
1912 MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
1913 MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
1915 mlx5_cmd_exec_check_status(priv->mdev, in, sizeof(in), out,
1920 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
1922 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1925 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1927 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1929 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
1930 MLX5_HASH_FIELD_SEL_DST_IP)
1932 #define MLX5_HASH_ALL (MLX5_HASH_FIELD_SEL_SRC_IP |\
1933 MLX5_HASH_FIELD_SEL_DST_IP |\
1934 MLX5_HASH_FIELD_SEL_L4_SPORT |\
1935 MLX5_HASH_FIELD_SEL_L4_DPORT)
1937 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
1938 MLX5_HASH_FIELD_SEL_DST_IP |\
1939 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1941 if (priv->params.hw_lro_en) {
1942 MLX5_SET(tirc, tirc, lro_enable_mask,
1943 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1944 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1945 MLX5_SET(tirc, tirc, lro_max_msg_sz,
1946 (priv->params.lro_wqe_sz -
1947 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1948 /* TODO: add the option to choose timer value dynamically */
1949 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1950 MLX5_CAP_ETH(priv->mdev,
1951 lro_timer_supported_periods[2]));
1954 /* setup parameters for hashing TIR type, if any */
1957 MLX5_SET(tirc, tirc, disp_type,
1958 MLX5_TIRC_DISP_TYPE_DIRECT);
1959 MLX5_SET(tirc, tirc, inline_rqn,
1960 priv->channel[0]->rq.rqn);
1963 MLX5_SET(tirc, tirc, disp_type,
1964 MLX5_TIRC_DISP_TYPE_INDIRECT);
1965 MLX5_SET(tirc, tirc, indirect_table,
1967 MLX5_SET(tirc, tirc, rx_hash_fn,
1968 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
1969 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1972 * The FreeBSD RSS implementation does currently not
1973 * support symmetric Toeplitz hashes:
1975 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
1976 rss_getkey((uint8_t *)hkey);
1978 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1979 hkey[0] = cpu_to_be32(0xD181C62C);
1980 hkey[1] = cpu_to_be32(0xF7F4DB5B);
1981 hkey[2] = cpu_to_be32(0x1983A2FC);
1982 hkey[3] = cpu_to_be32(0x943E1ADB);
1983 hkey[4] = cpu_to_be32(0xD9389E6B);
1984 hkey[5] = cpu_to_be32(0xD1039C2C);
1985 hkey[6] = cpu_to_be32(0xA74499AD);
1986 hkey[7] = cpu_to_be32(0x593D56D9);
1987 hkey[8] = cpu_to_be32(0xF3253C06);
1988 hkey[9] = cpu_to_be32(0x2ADC1FFC);
1994 case MLX5E_TT_IPV4_TCP:
1995 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1996 MLX5_L3_PROT_TYPE_IPV4);
1997 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1998 MLX5_L4_PROT_TYPE_TCP);
2000 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2001 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2005 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2009 case MLX5E_TT_IPV6_TCP:
2010 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2011 MLX5_L3_PROT_TYPE_IPV6);
2012 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2013 MLX5_L4_PROT_TYPE_TCP);
2015 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2016 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2020 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2024 case MLX5E_TT_IPV4_UDP:
2025 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2026 MLX5_L3_PROT_TYPE_IPV4);
2027 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2028 MLX5_L4_PROT_TYPE_UDP);
2030 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2031 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2035 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2039 case MLX5E_TT_IPV6_UDP:
2040 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2041 MLX5_L3_PROT_TYPE_IPV6);
2042 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2043 MLX5_L4_PROT_TYPE_UDP);
2045 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2046 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2050 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2054 case MLX5E_TT_IPV4_IPSEC_AH:
2055 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2056 MLX5_L3_PROT_TYPE_IPV4);
2057 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2058 MLX5_HASH_IP_IPSEC_SPI);
2061 case MLX5E_TT_IPV6_IPSEC_AH:
2062 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2063 MLX5_L3_PROT_TYPE_IPV6);
2064 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2065 MLX5_HASH_IP_IPSEC_SPI);
2068 case MLX5E_TT_IPV4_IPSEC_ESP:
2069 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2070 MLX5_L3_PROT_TYPE_IPV4);
2071 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2072 MLX5_HASH_IP_IPSEC_SPI);
2075 case MLX5E_TT_IPV6_IPSEC_ESP:
2076 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2077 MLX5_L3_PROT_TYPE_IPV6);
2078 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2079 MLX5_HASH_IP_IPSEC_SPI);
2083 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2084 MLX5_L3_PROT_TYPE_IPV4);
2085 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2090 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2091 MLX5_L3_PROT_TYPE_IPV6);
2092 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2102 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2104 struct mlx5_core_dev *mdev = priv->mdev;
2110 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2111 in = mlx5_vzalloc(inlen);
2114 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2116 mlx5e_build_tir_ctx(priv, tirc, tt);
2118 err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2126 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2128 mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2132 mlx5e_open_tirs(struct mlx5e_priv *priv)
2137 for (i = 0; i < MLX5E_NUM_TT; i++) {
2138 err = mlx5e_open_tir(priv, i);
2140 goto err_close_tirs;
2146 for (i--; i >= 0; i--)
2147 mlx5e_close_tir(priv, i);
2153 mlx5e_close_tirs(struct mlx5e_priv *priv)
2157 for (i = 0; i < MLX5E_NUM_TT; i++)
2158 mlx5e_close_tir(priv, i);
2162 * SW MTU does not include headers,
2163 * HW MTU includes all headers and checksums.
2166 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2168 struct mlx5e_priv *priv = ifp->if_softc;
2169 struct mlx5_core_dev *mdev = priv->mdev;
2173 err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(sw_mtu));
2175 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n",
2176 __func__, sw_mtu, err);
2179 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2181 if_printf(ifp, "Query port MTU, after setting new "
2182 "MTU value, failed\n");
2183 } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
2185 if_printf(ifp, "Port MTU %d is smaller than "
2186 "ifp mtu %d\n", hw_mtu, sw_mtu);
2187 } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
2189 if_printf(ifp, "Port MTU %d is bigger than "
2190 "ifp mtu %d\n", hw_mtu, sw_mtu);
2192 ifp->if_mtu = sw_mtu;
2197 mlx5e_open_locked(struct ifnet *ifp)
2199 struct mlx5e_priv *priv = ifp->if_softc;
2203 /* check if already opened */
2204 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2208 if (rss_getnumbuckets() > priv->params.num_channels) {
2209 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than "
2210 "channels(%u) available\n", rss_getnumbuckets(),
2211 priv->params.num_channels);
2214 err = mlx5e_open_tises(priv);
2216 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n",
2220 err = mlx5_vport_alloc_q_counter(priv->mdev,
2221 MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
2223 if_printf(priv->ifp,
2224 "%s: mlx5_vport_alloc_q_counter failed: %d\n",
2226 goto err_close_tises;
2228 /* store counter set ID */
2229 priv->counter_set_id = set_id;
2231 err = mlx5e_open_channels(priv);
2233 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n",
2235 goto err_dalloc_q_counter;
2237 err = mlx5e_open_rqt(priv);
2239 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n",
2241 goto err_close_channels;
2243 err = mlx5e_open_tirs(priv);
2245 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n",
2247 goto err_close_rqls;
2249 err = mlx5e_open_flow_table(priv);
2251 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n",
2253 goto err_close_tirs;
2255 err = mlx5e_add_all_vlan_rules(priv);
2257 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
2259 goto err_close_flow_table;
2261 set_bit(MLX5E_STATE_OPENED, &priv->state);
2263 mlx5e_update_carrier(priv);
2264 mlx5e_set_rx_mode_core(priv);
2268 err_close_flow_table:
2269 mlx5e_close_flow_table(priv);
2272 mlx5e_close_tirs(priv);
2275 mlx5e_close_rqt(priv);
2278 mlx5e_close_channels(priv);
2280 err_dalloc_q_counter:
2281 mlx5_vport_dealloc_q_counter(priv->mdev,
2282 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2285 mlx5e_close_tises(priv);
2291 mlx5e_open(void *arg)
2293 struct mlx5e_priv *priv = arg;
2296 if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
2297 if_printf(priv->ifp,
2298 "%s: Setting port status to up failed\n",
2301 mlx5e_open_locked(priv->ifp);
2302 priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
2307 mlx5e_close_locked(struct ifnet *ifp)
2309 struct mlx5e_priv *priv = ifp->if_softc;
2311 /* check if already closed */
2312 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2315 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2317 mlx5e_set_rx_mode_core(priv);
2318 mlx5e_del_all_vlan_rules(priv);
2319 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
2320 mlx5e_close_flow_table(priv);
2321 mlx5e_close_tirs(priv);
2322 mlx5e_close_rqt(priv);
2323 mlx5e_close_channels(priv);
2324 mlx5_vport_dealloc_q_counter(priv->mdev,
2325 MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2326 mlx5e_close_tises(priv);
2331 #if (__FreeBSD_version >= 1100000)
2333 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
2335 struct mlx5e_priv *priv = ifp->if_softc;
2338 /* PRIV_LOCK(priv); XXX not allowed */
2340 case IFCOUNTER_IPACKETS:
2341 retval = priv->stats.vport.rx_packets;
2343 case IFCOUNTER_IERRORS:
2344 retval = priv->stats.vport.rx_error_packets;
2346 case IFCOUNTER_IQDROPS:
2347 retval = priv->stats.vport.rx_out_of_buffer;
2349 case IFCOUNTER_OPACKETS:
2350 retval = priv->stats.vport.tx_packets;
2352 case IFCOUNTER_OERRORS:
2353 retval = priv->stats.vport.tx_error_packets;
2355 case IFCOUNTER_IBYTES:
2356 retval = priv->stats.vport.rx_bytes;
2358 case IFCOUNTER_OBYTES:
2359 retval = priv->stats.vport.tx_bytes;
2361 case IFCOUNTER_IMCASTS:
2362 retval = priv->stats.vport.rx_multicast_packets;
2364 case IFCOUNTER_OMCASTS:
2365 retval = priv->stats.vport.tx_multicast_packets;
2367 case IFCOUNTER_OQDROPS:
2368 retval = priv->stats.vport.tx_queue_dropped;
2371 retval = if_get_counter_default(ifp, cnt);
2374 /* PRIV_UNLOCK(priv); XXX not allowed */
2380 mlx5e_set_rx_mode(struct ifnet *ifp)
2382 struct mlx5e_priv *priv = ifp->if_softc;
2384 schedule_work(&priv->set_rx_mode_work);
2388 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2390 struct mlx5e_priv *priv;
2392 struct ifi2creq i2c;
2400 priv = ifp->if_softc;
2402 /* check if detaching */
2403 if (priv == NULL || priv->gone != 0)
2408 ifr = (struct ifreq *)data;
2411 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
2413 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
2414 ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
2417 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2419 mlx5e_close_locked(ifp);
2422 mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
2425 mlx5e_open_locked(ifp);
2428 if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n",
2429 MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
2434 if ((ifp->if_flags & IFF_UP) &&
2435 (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2436 mlx5e_set_rx_mode(ifp);
2440 if (ifp->if_flags & IFF_UP) {
2441 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2442 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2443 mlx5e_open_locked(ifp);
2444 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2445 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
2448 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2449 mlx5_set_port_status(priv->mdev,
2451 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2452 mlx5e_close_locked(ifp);
2453 mlx5e_update_carrier(priv);
2454 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2461 mlx5e_set_rx_mode(ifp);
2466 ifr = (struct ifreq *)data;
2467 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
2470 ifr = (struct ifreq *)data;
2472 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2474 if (mask & IFCAP_TXCSUM) {
2475 ifp->if_capenable ^= IFCAP_TXCSUM;
2476 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2478 if (IFCAP_TSO4 & ifp->if_capenable &&
2479 !(IFCAP_TXCSUM & ifp->if_capenable)) {
2480 ifp->if_capenable &= ~IFCAP_TSO4;
2481 ifp->if_hwassist &= ~CSUM_IP_TSO;
2483 "tso4 disabled due to -txcsum.\n");
2486 if (mask & IFCAP_TXCSUM_IPV6) {
2487 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
2488 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2490 if (IFCAP_TSO6 & ifp->if_capenable &&
2491 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2492 ifp->if_capenable &= ~IFCAP_TSO6;
2493 ifp->if_hwassist &= ~CSUM_IP6_TSO;
2495 "tso6 disabled due to -txcsum6.\n");
2498 if (mask & IFCAP_RXCSUM)
2499 ifp->if_capenable ^= IFCAP_RXCSUM;
2500 if (mask & IFCAP_RXCSUM_IPV6)
2501 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
2502 if (mask & IFCAP_TSO4) {
2503 if (!(IFCAP_TSO4 & ifp->if_capenable) &&
2504 !(IFCAP_TXCSUM & ifp->if_capenable)) {
2505 if_printf(ifp, "enable txcsum first.\n");
2509 ifp->if_capenable ^= IFCAP_TSO4;
2510 ifp->if_hwassist ^= CSUM_IP_TSO;
2512 if (mask & IFCAP_TSO6) {
2513 if (!(IFCAP_TSO6 & ifp->if_capenable) &&
2514 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2515 if_printf(ifp, "enable txcsum6 first.\n");
2519 ifp->if_capenable ^= IFCAP_TSO6;
2520 ifp->if_hwassist ^= CSUM_IP6_TSO;
2522 if (mask & IFCAP_VLAN_HWFILTER) {
2523 if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
2524 mlx5e_disable_vlan_filter(priv);
2526 mlx5e_enable_vlan_filter(priv);
2528 ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
2530 if (mask & IFCAP_VLAN_HWTAGGING)
2531 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2532 if (mask & IFCAP_WOL_MAGIC)
2533 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2535 VLAN_CAPABILITIES(ifp);
2536 /* turn off LRO means also turn of HW LRO - if it's on */
2537 if (mask & IFCAP_LRO) {
2538 int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2539 bool need_restart = false;
2541 ifp->if_capenable ^= IFCAP_LRO;
2542 if (!(ifp->if_capenable & IFCAP_LRO)) {
2543 if (priv->params.hw_lro_en) {
2544 priv->params.hw_lro_en = false;
2545 need_restart = true;
2546 /* Not sure this is the correct way */
2547 priv->params_ethtool.hw_lro = priv->params.hw_lro_en;
2550 if (was_opened && need_restart) {
2551 mlx5e_close_locked(ifp);
2552 mlx5e_open_locked(ifp);
2560 ifr = (struct ifreq *)data;
2563 * Copy from the user-space address ifr_data to the
2564 * kernel-space address i2c
2566 error = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
2570 if (i2c.len > sizeof(i2c.data)) {
2576 /* Get module_num which is required for the query_eeprom */
2577 error = mlx5_query_module_num(priv->mdev, &module_num);
2579 if_printf(ifp, "Query module num failed, eeprom "
2580 "reading is not supported\n");
2584 /* Check if module is present before doing an access */
2585 if (mlx5_query_module_status(priv->mdev, module_num) !=
2586 MLX5_MODULE_STATUS_PLUGGED) {
2591 * Currently 0XA0 and 0xA2 are the only addresses permitted.
2592 * The internal conversion is as follows:
2594 if (i2c.dev_addr == 0xA0)
2595 read_addr = MLX5E_I2C_ADDR_LOW;
2596 else if (i2c.dev_addr == 0xA2)
2597 read_addr = MLX5E_I2C_ADDR_HIGH;
2599 if_printf(ifp, "Query eeprom failed, "
2600 "Invalid Address: %X\n", i2c.dev_addr);
2604 error = mlx5_query_eeprom(priv->mdev,
2605 read_addr, MLX5E_EEPROM_LOW_PAGE,
2606 (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
2607 (uint32_t *)i2c.data, &size_read);
2609 if_printf(ifp, "Query eeprom failed, eeprom "
2610 "reading is not supported\n");
2615 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
2616 error = mlx5_query_eeprom(priv->mdev,
2617 read_addr, MLX5E_EEPROM_LOW_PAGE,
2618 (uint32_t)(i2c.offset + size_read),
2619 (uint32_t)(i2c.len - size_read), module_num,
2620 (uint32_t *)(i2c.data + size_read), &size_read);
2623 if_printf(ifp, "Query eeprom failed, eeprom "
2624 "reading is not supported\n");
2629 error = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
2635 error = ether_ioctl(ifp, command, data);
2642 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2645 * TODO: uncoment once FW really sets all these bits if
2646 * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
2647 * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
2648 * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
2652 /* TODO: add more must-to-have features */
2654 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2661 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
2662 struct mlx5e_priv *priv,
2663 int num_comp_vectors)
2666 * TODO: Consider link speed for setting "log_sq_size",
2667 * "log_rq_size" and "cq_moderation_xxx":
2669 priv->params.log_sq_size =
2670 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2671 priv->params.log_rq_size =
2672 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2673 priv->params.rx_cq_moderation_usec =
2674 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
2675 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
2676 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2677 priv->params.rx_cq_moderation_mode =
2678 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
2679 priv->params.rx_cq_moderation_pkts =
2680 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2681 priv->params.tx_cq_moderation_usec =
2682 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2683 priv->params.tx_cq_moderation_pkts =
2684 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2685 priv->params.min_rx_wqes =
2686 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
2687 priv->params.rx_hash_log_tbl_sz =
2688 (order_base_2(num_comp_vectors) >
2689 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
2690 order_base_2(num_comp_vectors) :
2691 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
2692 priv->params.num_tc = 1;
2693 priv->params.default_vlan_prio = 0;
2694 priv->counter_set_id = -1;
2697 * hw lro is currently defaulted to off. when it won't anymore we
2698 * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
2700 priv->params.hw_lro_en = false;
2701 priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2703 priv->params.cqe_zipping_en = !!MLX5_CAP_GEN(mdev, cqe_compression);
2706 priv->params.num_channels = num_comp_vectors;
2707 priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
2708 priv->queue_mapping_channel_mask =
2709 roundup_pow_of_two(num_comp_vectors) - 1;
2710 priv->num_tc = priv->params.num_tc;
2711 priv->default_vlan_prio = priv->params.default_vlan_prio;
2713 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2714 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2715 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2719 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2720 struct mlx5_core_mr *mr)
2722 struct ifnet *ifp = priv->ifp;
2723 struct mlx5_core_dev *mdev = priv->mdev;
2724 struct mlx5_create_mkey_mbox_in *in;
2727 in = mlx5_vzalloc(sizeof(*in));
2729 if_printf(ifp, "%s: failed to allocate inbox\n", __func__);
2732 in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2733 MLX5_PERM_LOCAL_READ |
2734 MLX5_ACCESS_MODE_PA;
2735 in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2736 in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2738 err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL,
2741 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n",
2749 static const char *mlx5e_vport_stats_desc[] = {
2750 MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
2753 static const char *mlx5e_pport_stats_desc[] = {
2754 MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
2758 mlx5e_priv_mtx_init(struct mlx5e_priv *priv)
2760 mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
2761 sx_init(&priv->state_lock, "mlx5state");
2762 callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
2763 MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
2767 mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv)
2769 mtx_destroy(&priv->async_events_mtx);
2770 sx_destroy(&priv->state_lock);
2774 sysctl_firmware(SYSCTL_HANDLER_ARGS)
2777 * %d.%d%.d the string format.
2778 * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
2779 * We need at most 5 chars to store that.
2780 * It also has: two "." and NULL at the end, which means we need 18
2781 * (5*3 + 3) chars at most.
2784 struct mlx5e_priv *priv = arg1;
2787 snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
2788 fw_rev_sub(priv->mdev));
2789 error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
2794 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
2796 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
2797 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
2798 sysctl_firmware, "A", "HCA firmware version");
2800 SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
2801 OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
2806 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
2808 #if (__FreeBSD_version < 1100000)
2812 /* Only receiving pauseframes is enabled by default */
2813 priv->params.tx_pauseframe_control = 0;
2814 priv->params.rx_pauseframe_control = 1;
2816 #if (__FreeBSD_version < 1100000)
2817 /* compute path for sysctl */
2818 snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
2819 device_get_unit(priv->mdev->pdev->dev.bsddev));
2821 /* try to fetch tunable, if any */
2822 TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
2824 /* compute path for sysctl */
2825 snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
2826 device_get_unit(priv->mdev->pdev->dev.bsddev));
2828 /* try to fetch tunable, if any */
2829 TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
2832 /* register pausframe SYSCTLs */
2833 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2834 OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
2835 &priv->params.tx_pauseframe_control, 0,
2836 "Set to enable TX pause frames. Clear to disable.");
2838 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2839 OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
2840 &priv->params.rx_pauseframe_control, 0,
2841 "Set to enable RX pause frames. Clear to disable.");
2844 priv->params.tx_pauseframe_control =
2845 priv->params.tx_pauseframe_control ? 1 : 0;
2846 priv->params.rx_pauseframe_control =
2847 priv->params.rx_pauseframe_control ? 1 : 0;
2849 /* update firmware */
2850 mlx5_set_port_pause(priv->mdev, 1,
2851 priv->params.rx_pauseframe_control,
2852 priv->params.tx_pauseframe_control);
2856 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
2858 static volatile int mlx5_en_unit;
2860 struct mlx5e_priv *priv;
2861 u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
2862 struct sysctl_oid_list *child;
2863 int ncv = mdev->priv.eq_table.num_comp_vectors;
2869 if (mlx5e_check_required_hca_cap(mdev)) {
2870 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
2873 priv = malloc(sizeof(*priv), M_MLX5EN, M_WAITOK | M_ZERO);
2875 mlx5_core_err(mdev, "malloc() failed\n");
2878 mlx5e_priv_mtx_init(priv);
2880 ifp = priv->ifp = if_alloc(IFT_ETHER);
2882 mlx5_core_err(mdev, "if_alloc() failed\n");
2885 ifp->if_softc = priv;
2886 if_initname(ifp, "mce", atomic_fetchadd_int(&mlx5_en_unit, 1));
2887 ifp->if_mtu = ETHERMTU;
2888 ifp->if_init = mlx5e_open;
2889 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2890 ifp->if_ioctl = mlx5e_ioctl;
2891 ifp->if_transmit = mlx5e_xmit;
2892 ifp->if_qflush = if_qflush;
2893 #if (__FreeBSD_version >= 1100000)
2894 ifp->if_get_counter = mlx5e_get_counter;
2896 ifp->if_snd.ifq_maxlen = ifqmaxlen;
2898 * Set driver features
2900 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
2901 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
2902 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
2903 ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
2904 ifp->if_capabilities |= IFCAP_LRO;
2905 ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
2906 ifp->if_capabilities |= IFCAP_HWSTATS;
2908 /* set TSO limits so that we don't have to drop TX packets */
2909 ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
2910 ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
2911 ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
2913 ifp->if_capenable = ifp->if_capabilities;
2914 ifp->if_hwassist = 0;
2915 if (ifp->if_capenable & IFCAP_TSO)
2916 ifp->if_hwassist |= CSUM_TSO;
2917 if (ifp->if_capenable & IFCAP_TXCSUM)
2918 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2919 if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
2920 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2922 /* ifnet sysctl tree */
2923 sysctl_ctx_init(&priv->sysctl_ctx);
2924 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
2925 OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
2926 if (priv->sysctl_ifnet == NULL) {
2927 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
2928 goto err_free_sysctl;
2930 snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
2931 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2932 OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
2933 if (priv->sysctl_ifnet == NULL) {
2934 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
2935 goto err_free_sysctl;
2938 /* HW sysctl tree */
2939 child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
2940 priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
2941 OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
2942 if (priv->sysctl_hw == NULL) {
2943 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
2944 goto err_free_sysctl;
2946 mlx5e_build_ifp_priv(mdev, priv, ncv);
2947 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
2949 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n",
2951 goto err_free_sysctl;
2953 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2955 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n",
2957 goto err_unmap_free_uar;
2959 err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
2961 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n",
2963 goto err_dealloc_pd;
2965 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
2967 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n",
2969 goto err_dealloc_transport_domain;
2971 mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
2973 /* check if we should generate a random MAC address */
2974 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
2975 is_zero_ether_addr(dev_addr)) {
2976 random_ether_addr(dev_addr);
2977 if_printf(ifp, "Assigned random MAC address\n");
2980 /* set default MTU */
2981 mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
2984 device_set_desc(mdev->pdev->dev.bsddev, mlx5e_version);
2986 /* Set default media status */
2987 priv->media_status_last = IFM_AVALID;
2988 priv->media_active_last = IFM_ETHER | IFM_AUTO |
2989 IFM_ETH_RXPAUSE | IFM_FDX;
2991 /* setup default pauseframes configuration */
2992 mlx5e_setup_pauseframes(priv);
2994 err = mlx5_query_port_proto_cap(mdev, ð_proto_cap, MLX5_PTYS_EN);
2997 if_printf(ifp, "%s: Query port media capability failed, %d\n",
3001 /* Setup supported medias */
3002 ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
3003 mlx5e_media_change, mlx5e_media_status);
3005 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
3006 if (mlx5e_mode_table[i].baudrate == 0)
3008 if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
3009 ifmedia_add(&priv->media,
3010 mlx5e_mode_table[i].subtype |
3011 IFM_ETHER, 0, NULL);
3012 ifmedia_add(&priv->media,
3013 mlx5e_mode_table[i].subtype |
3014 IFM_ETHER | IFM_FDX |
3015 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3019 ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
3020 ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3021 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3023 /* Set autoselect by default */
3024 ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3025 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
3026 ether_ifattach(ifp, dev_addr);
3028 /* Register for VLAN events */
3029 priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
3030 mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
3031 priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
3032 mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
3034 /* Link is down by default */
3035 if_link_state_change(ifp, LINK_STATE_DOWN);
3037 mlx5e_enable_async_events(priv);
3039 mlx5e_add_hw_stats(priv);
3041 mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3042 "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
3043 priv->stats.vport.arg);
3045 mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3046 "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
3047 priv->stats.pport.arg);
3049 mlx5e_create_ethtool(priv);
3051 mtx_lock(&priv->async_events_mtx);
3052 mlx5e_update_stats(priv);
3053 mtx_unlock(&priv->async_events_mtx);
3057 err_dealloc_transport_domain:
3058 mlx5_dealloc_transport_domain(mdev, priv->tdn);
3061 mlx5_core_dealloc_pd(mdev, priv->pdn);
3064 mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3067 sysctl_ctx_free(&priv->sysctl_ctx);
3072 mlx5e_priv_mtx_destroy(priv);
3073 free(priv, M_MLX5EN);
3078 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
3080 struct mlx5e_priv *priv = vpriv;
3081 struct ifnet *ifp = priv->ifp;
3083 /* don't allow more IOCTLs */
3087 * Clear the device description to avoid use after free,
3088 * because the bsddev is not destroyed when this module is
3091 device_set_desc(mdev->pdev->dev.bsddev, NULL);
3093 /* XXX wait a bit to allow IOCTL handlers to complete */
3096 /* stop watchdog timer */
3097 callout_drain(&priv->watchdog);
3099 if (priv->vlan_attach != NULL)
3100 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
3101 if (priv->vlan_detach != NULL)
3102 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
3104 /* make sure device gets closed */
3106 mlx5e_close_locked(ifp);
3109 /* unregister device */
3110 ifmedia_removeall(&priv->media);
3111 ether_ifdetach(ifp);
3114 /* destroy all remaining sysctl nodes */
3115 if (priv->sysctl_debug)
3116 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
3117 sysctl_ctx_free(&priv->stats.vport.ctx);
3118 sysctl_ctx_free(&priv->stats.pport.ctx);
3119 sysctl_ctx_free(&priv->sysctl_ctx);
3121 mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
3122 mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
3123 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3124 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
3125 mlx5e_disable_async_events(priv);
3126 flush_scheduled_work();
3127 mlx5e_priv_mtx_destroy(priv);
3128 free(priv, M_MLX5EN);
3132 mlx5e_get_ifp(void *vpriv)
3134 struct mlx5e_priv *priv = vpriv;
3139 static struct mlx5_interface mlx5e_interface = {
3140 .add = mlx5e_create_ifp,
3141 .remove = mlx5e_destroy_ifp,
3142 .event = mlx5e_async_event,
3143 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3144 .get_dev = mlx5e_get_ifp,
3150 mlx5_register_interface(&mlx5e_interface);
3156 mlx5_unregister_interface(&mlx5e_interface);
3159 module_init_order(mlx5e_init, SI_ORDER_THIRD);
3160 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
3162 #if (__FreeBSD_version >= 1100000)
3163 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
3165 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
3166 MODULE_VERSION(mlx5en, 1);