sys/dev/mlx5/mlx5_en/mlx5_en_main.c

   1 /*-
   2  * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include "en.h"
  29
  30 #include <sys/sockio.h>
  31 #include <machine/atomic.h>
  32
  33 #ifndef ETH_DRIVER_VERSION
  34 #define ETH_DRIVER_VERSION      "3.5.0"
  35 #endif
  36 #define DRIVER_RELDATE  "November 2018"
  37
  38 static const char mlx5e_version[] = "mlx5en: Mellanox Ethernet driver "
  39         ETH_DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
  40
  41 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs);
  42
  43 struct mlx5e_channel_param {
  44         struct mlx5e_rq_param rq;
  45         struct mlx5e_sq_param sq;
  46         struct mlx5e_cq_param rx_cq;
  47         struct mlx5e_cq_param tx_cq;
  48 };
  49
  50 static const struct {
  51         u32     subtype;
  52         u64     baudrate;
  53 }       mlx5e_mode_table[MLX5E_LINK_MODES_NUMBER] = {
  54
  55         [MLX5E_1000BASE_CX_SGMII] = {
  56                 .subtype = IFM_1000_CX_SGMII,
  57                 .baudrate = IF_Mbps(1000ULL),
  58         },
  59         [MLX5E_1000BASE_KX] = {
  60                 .subtype = IFM_1000_KX,
  61                 .baudrate = IF_Mbps(1000ULL),
  62         },
  63         [MLX5E_10GBASE_CX4] = {
  64                 .subtype = IFM_10G_CX4,
  65                 .baudrate = IF_Gbps(10ULL),
  66         },
  67         [MLX5E_10GBASE_KX4] = {
  68                 .subtype = IFM_10G_KX4,
  69                 .baudrate = IF_Gbps(10ULL),
  70         },
  71         [MLX5E_10GBASE_KR] = {
  72                 .subtype = IFM_10G_KR,
  73                 .baudrate = IF_Gbps(10ULL),
  74         },
  75         [MLX5E_20GBASE_KR2] = {
  76                 .subtype = IFM_20G_KR2,
  77                 .baudrate = IF_Gbps(20ULL),
  78         },
  79         [MLX5E_40GBASE_CR4] = {
  80                 .subtype = IFM_40G_CR4,
  81                 .baudrate = IF_Gbps(40ULL),
  82         },
  83         [MLX5E_40GBASE_KR4] = {
  84                 .subtype = IFM_40G_KR4,
  85                 .baudrate = IF_Gbps(40ULL),
  86         },
  87         [MLX5E_56GBASE_R4] = {
  88                 .subtype = IFM_56G_R4,
  89                 .baudrate = IF_Gbps(56ULL),
  90         },
  91         [MLX5E_10GBASE_CR] = {
  92                 .subtype = IFM_10G_CR1,
  93                 .baudrate = IF_Gbps(10ULL),
  94         },
  95         [MLX5E_10GBASE_SR] = {
  96                 .subtype = IFM_10G_SR,
  97                 .baudrate = IF_Gbps(10ULL),
  98         },
  99         [MLX5E_10GBASE_ER] = {
 100                 .subtype = IFM_10G_ER,
 101                 .baudrate = IF_Gbps(10ULL),
 102         },
 103         [MLX5E_40GBASE_SR4] = {
 104                 .subtype = IFM_40G_SR4,
 105                 .baudrate = IF_Gbps(40ULL),
 106         },
 107         [MLX5E_40GBASE_LR4] = {
 108                 .subtype = IFM_40G_LR4,
 109                 .baudrate = IF_Gbps(40ULL),
 110         },
 111         [MLX5E_100GBASE_CR4] = {
 112                 .subtype = IFM_100G_CR4,
 113                 .baudrate = IF_Gbps(100ULL),
 114         },
 115         [MLX5E_100GBASE_SR4] = {
 116                 .subtype = IFM_100G_SR4,
 117                 .baudrate = IF_Gbps(100ULL),
 118         },
 119         [MLX5E_100GBASE_KR4] = {
 120                 .subtype = IFM_100G_KR4,
 121                 .baudrate = IF_Gbps(100ULL),
 122         },
 123         [MLX5E_100GBASE_LR4] = {
 124                 .subtype = IFM_100G_LR4,
 125                 .baudrate = IF_Gbps(100ULL),
 126         },
 127         [MLX5E_100BASE_TX] = {
 128                 .subtype = IFM_100_TX,
 129                 .baudrate = IF_Mbps(100ULL),
 130         },
 131         [MLX5E_1000BASE_T] = {
 132                 .subtype = IFM_1000_T,
 133                 .baudrate = IF_Mbps(1000ULL),
 134         },
 135         [MLX5E_10GBASE_T] = {
 136                 .subtype = IFM_10G_T,
 137                 .baudrate = IF_Gbps(10ULL),
 138         },
 139         [MLX5E_25GBASE_CR] = {
 140                 .subtype = IFM_25G_CR,
 141                 .baudrate = IF_Gbps(25ULL),
 142         },
 143         [MLX5E_25GBASE_KR] = {
 144                 .subtype = IFM_25G_KR,
 145                 .baudrate = IF_Gbps(25ULL),
 146         },
 147         [MLX5E_25GBASE_SR] = {
 148                 .subtype = IFM_25G_SR,
 149                 .baudrate = IF_Gbps(25ULL),
 150         },
 151         [MLX5E_50GBASE_CR2] = {
 152                 .subtype = IFM_50G_CR2,
 153                 .baudrate = IF_Gbps(50ULL),
 154         },
 155         [MLX5E_50GBASE_KR2] = {
 156                 .subtype = IFM_50G_KR2,
 157                 .baudrate = IF_Gbps(50ULL),
 158         },
 159 };
 160
 161 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
 162
 163 static void
 164 mlx5e_update_carrier(struct mlx5e_priv *priv)
 165 {
 166         struct mlx5_core_dev *mdev = priv->mdev;
 167         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 168         u32 eth_proto_oper;
 169         int error;
 170         u8 port_state;
 171         u8 is_er_type;
 172         u8 i;
 173
 174         port_state = mlx5_query_vport_state(mdev,
 175             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 176
 177         if (port_state == VPORT_STATE_UP) {
 178                 priv->media_status_last |= IFM_ACTIVE;
 179         } else {
 180                 priv->media_status_last &= ~IFM_ACTIVE;
 181                 priv->media_active_last = IFM_ETHER;
 182                 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
 183                 return;
 184         }
 185
 186         error = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
 187         if (error) {
 188                 priv->media_active_last = IFM_ETHER;
 189                 priv->ifp->if_baudrate = 1;
 190                 if_printf(priv->ifp, "%s: query port ptys failed: 0x%x\n",
 191                     __func__, error);
 192                 return;
 193         }
 194         eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
 195
 196         for (i = 0; i != MLX5E_LINK_MODES_NUMBER; i++) {
 197                 if (mlx5e_mode_table[i].baudrate == 0)
 198                         continue;
 199                 if (MLX5E_PROT_MASK(i) & eth_proto_oper) {
 200                         u32 subtype = mlx5e_mode_table[i].subtype;
 201
 202                         priv->ifp->if_baudrate =
 203                             mlx5e_mode_table[i].baudrate;
 204
 205                         switch (subtype) {
 206                         case IFM_10G_ER:
 207                                 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
 208                                 if (error != 0) {
 209                                         if_printf(priv->ifp, "%s: query port pddr failed: %d\n",
 210                                             __func__, error);
 211                                 }
 212                                 if (error != 0 || is_er_type == 0)
 213                                         subtype = IFM_10G_LR;
 214                                 break;
 215                         case IFM_40G_LR4:
 216                                 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
 217                                 if (error != 0) {
 218                                         if_printf(priv->ifp, "%s: query port pddr failed: %d\n",
 219                                             __func__, error);
 220                                 }
 221                                 if (error == 0 && is_er_type != 0)
 222                                         subtype = IFM_40G_ER4;
 223                                 break;
 224                         }
 225                         priv->media_active_last = subtype | IFM_ETHER | IFM_FDX;
 226                         break;
 227                 }
 228         }
 229         if_link_state_change(priv->ifp, LINK_STATE_UP);
 230 }
 231
 232 static void
 233 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
 234 {
 235         struct mlx5e_priv *priv = dev->if_softc;
 236
 237         ifmr->ifm_status = priv->media_status_last;
 238         ifmr->ifm_active = priv->media_active_last |
 239             (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
 240             (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
 241
 242 }
 243
 244 static u32
 245 mlx5e_find_link_mode(u32 subtype)
 246 {
 247         u32 i;
 248         u32 link_mode = 0;
 249
 250         switch (subtype) {
 251         case IFM_10G_LR:
 252                 subtype = IFM_10G_ER;
 253                 break;
 254         case IFM_40G_ER4:
 255                 subtype = IFM_40G_LR4;
 256                 break;
 257         }
 258
 259         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
 260                 if (mlx5e_mode_table[i].baudrate == 0)
 261                         continue;
 262                 if (mlx5e_mode_table[i].subtype == subtype)
 263                         link_mode |= MLX5E_PROT_MASK(i);
 264         }
 265
 266         return (link_mode);
 267 }
 268
 269 static int
 270 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv)
 271 {
 272         return (mlx5_set_port_pause_and_pfc(priv->mdev, 1,
 273             priv->params.rx_pauseframe_control,
 274             priv->params.tx_pauseframe_control,
 275             priv->params.rx_priority_flow_control,
 276             priv->params.tx_priority_flow_control));
 277 }
 278
 279 static int
 280 mlx5e_set_port_pfc(struct mlx5e_priv *priv)
 281 {
 282         int error;
 283
 284         if (priv->gone != 0) {
 285                 error = -ENXIO;
 286         } else if (priv->params.rx_pauseframe_control ||
 287             priv->params.tx_pauseframe_control) {
 288                 if_printf(priv->ifp,
 289                     "Global pauseframes must be disabled before enabling PFC.\n");
 290                 error = -EINVAL;
 291         } else {
 292                 error = mlx5e_set_port_pause_and_pfc(priv);
 293         }
 294         return (error);
 295 }
 296
 297 static int
 298 mlx5e_media_change(struct ifnet *dev)
 299 {
 300         struct mlx5e_priv *priv = dev->if_softc;
 301         struct mlx5_core_dev *mdev = priv->mdev;
 302         u32 eth_proto_cap;
 303         u32 link_mode;
 304         int was_opened;
 305         int locked;
 306         int error;
 307
 308         locked = PRIV_LOCKED(priv);
 309         if (!locked)
 310                 PRIV_LOCK(priv);
 311
 312         if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
 313                 error = EINVAL;
 314                 goto done;
 315         }
 316         link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media));
 317
 318         /* query supported capabilities */
 319         error = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
 320         if (error != 0) {
 321                 if_printf(dev, "Query port media capability failed\n");
 322                 goto done;
 323         }
 324         /* check for autoselect */
 325         if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
 326                 link_mode = eth_proto_cap;
 327                 if (link_mode == 0) {
 328                         if_printf(dev, "Port media capability is zero\n");
 329                         error = EINVAL;
 330                         goto done;
 331                 }
 332         } else {
 333                 link_mode = link_mode & eth_proto_cap;
 334                 if (link_mode == 0) {
 335                         if_printf(dev, "Not supported link mode requested\n");
 336                         error = EINVAL;
 337                         goto done;
 338                 }
 339         }
 340         if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
 341                 /* check if PFC is enabled */
 342                 if (priv->params.rx_priority_flow_control ||
 343                     priv->params.tx_priority_flow_control) {
 344                         if_printf(dev, "PFC must be disabled before enabling global pauseframes.\n");
 345                         error = EINVAL;
 346                         goto done;
 347                 }
 348         }
 349         /* update pauseframe control bits */
 350         priv->params.rx_pauseframe_control =
 351             (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
 352         priv->params.tx_pauseframe_control =
 353             (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
 354
 355         /* check if device is opened */
 356         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
 357
 358         /* reconfigure the hardware */
 359         mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
 360         mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN);
 361         error = -mlx5e_set_port_pause_and_pfc(priv);
 362         if (was_opened)
 363                 mlx5_set_port_status(mdev, MLX5_PORT_UP);
 364
 365 done:
 366         if (!locked)
 367                 PRIV_UNLOCK(priv);
 368         return (error);
 369 }
 370
 371 static void
 372 mlx5e_update_carrier_work(struct work_struct *work)
 373 {
 374         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 375             update_carrier_work);
 376
 377         PRIV_LOCK(priv);
 378         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 379                 mlx5e_update_carrier(priv);
 380         PRIV_UNLOCK(priv);
 381 }
 382
 383 /*
 384  * This function reads the physical port counters from the firmware
 385  * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
 386  * macros. The output is converted from big-endian 64-bit values into
 387  * host endian ones and stored in the "priv->stats.pport" structure.
 388  */
 389 static void
 390 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 391 {
 392         struct mlx5_core_dev *mdev = priv->mdev;
 393         struct mlx5e_pport_stats *s = &priv->stats.pport;
 394         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 395         u32 *in;
 396         u32 *out;
 397         const u64 *ptr;
 398         unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 399         unsigned x;
 400         unsigned y;
 401         unsigned z;
 402
 403         /* allocate firmware request structures */
 404         in = mlx5_vzalloc(sz);
 405         out = mlx5_vzalloc(sz);
 406         if (in == NULL || out == NULL)
 407                 goto free_out;
 408
 409         /*
 410          * Get pointer to the 64-bit counter set which is located at a
 411          * fixed offset in the output firmware request structure:
 412          */
 413         ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
 414
 415         MLX5_SET(ppcnt_reg, in, local_port, 1);
 416
 417         /* read IEEE802_3 counter group using predefined counter layout */
 418         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 419         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 420         for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM;
 421              x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
 422                 s->arg[y] = be64toh(ptr[x]);
 423
 424         /* read RFC2819 counter group using predefined counter layout */
 425         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 426         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 427         for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
 428                 s->arg[y] = be64toh(ptr[x]);
 429         for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
 430             MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
 431                 s_debug->arg[y] = be64toh(ptr[x]);
 432
 433         /* read RFC2863 counter group using predefined counter layout */
 434         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 435         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 436         for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
 437                 s_debug->arg[y] = be64toh(ptr[x]);
 438
 439         /* read physical layer stats counter group using predefined counter layout */
 440         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 441         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 442         for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
 443                 s_debug->arg[y] = be64toh(ptr[x]);
 444
 445         /* read Extended Ethernet counter group using predefined counter layout */
 446         MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
 447         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 448         for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++)
 449                 s_debug->arg[y] = be64toh(ptr[x]);
 450
 451         /* read per-priority counters */
 452         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 453
 454         /* iterate all the priorities */
 455         for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) {
 456                 MLX5_SET(ppcnt_reg, in, prio_tc, z);
 457                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 458
 459                 /* read per priority stats counter group using predefined counter layout */
 460                 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM /
 461                     MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++)
 462                         s->arg[y] = be64toh(ptr[x]);
 463         }
 464
 465 free_out:
 466         /* free firmware request structures */
 467         kvfree(in);
 468         kvfree(out);
 469 }
 470
 471 /*
 472  * This function is called regularly to collect all statistics
 473  * counters from the firmware. The values can be viewed through the
 474  * sysctl interface. Execution is serialized using the priv's global
 475  * configuration lock.
 476  */
 477 static void
 478 mlx5e_update_stats_locked(struct mlx5e_priv *priv)
 479 {
 480         struct mlx5_core_dev *mdev = priv->mdev;
 481         struct mlx5e_vport_stats *s = &priv->stats.vport;
 482         struct mlx5e_sq_stats *sq_stats;
 483         struct buf_ring *sq_br;
 484 #if (__FreeBSD_version < 1100000)
 485         struct ifnet *ifp = priv->ifp;
 486 #endif
 487
 488         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 489         u32 *out;
 490         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 491         u64 tso_packets = 0;
 492         u64 tso_bytes = 0;
 493         u64 tx_queue_dropped = 0;
 494         u64 tx_defragged = 0;
 495         u64 tx_offload_none = 0;
 496         u64 lro_packets = 0;
 497         u64 lro_bytes = 0;
 498         u64 sw_lro_queued = 0;
 499         u64 sw_lro_flushed = 0;
 500         u64 rx_csum_none = 0;
 501         u64 rx_wqe_err = 0;
 502         u64 rx_packets = 0;
 503         u64 rx_bytes = 0;
 504         u32 rx_out_of_buffer = 0;
 505         int i;
 506         int j;
 507
 508         out = mlx5_vzalloc(outlen);
 509         if (out == NULL)
 510                 goto free_out;
 511
 512         /* Collect firts the SW counters and then HW for consistency */
 513         for (i = 0; i < priv->params.num_channels; i++) {
 514                 struct mlx5e_channel *pch = priv->channel + i;
 515                 struct mlx5e_rq *rq = &pch->rq;
 516                 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats;
 517
 518                 /* collect stats from LRO */
 519                 rq_stats->sw_lro_queued = rq->lro.lro_queued;
 520                 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
 521                 sw_lro_queued += rq_stats->sw_lro_queued;
 522                 sw_lro_flushed += rq_stats->sw_lro_flushed;
 523                 lro_packets += rq_stats->lro_packets;
 524                 lro_bytes += rq_stats->lro_bytes;
 525                 rx_csum_none += rq_stats->csum_none;
 526                 rx_wqe_err += rq_stats->wqe_err;
 527                 rx_packets += rq_stats->packets;
 528                 rx_bytes += rq_stats->bytes;
 529
 530                 for (j = 0; j < priv->num_tc; j++) {
 531                         sq_stats = &pch->sq[j].stats;
 532                         sq_br = pch->sq[j].br;
 533
 534                         tso_packets += sq_stats->tso_packets;
 535                         tso_bytes += sq_stats->tso_bytes;
 536                         tx_queue_dropped += sq_stats->dropped;
 537                         if (sq_br != NULL)
 538                                 tx_queue_dropped += sq_br->br_drops;
 539                         tx_defragged += sq_stats->defragged;
 540                         tx_offload_none += sq_stats->csum_offload_none;
 541                 }
 542         }
 543
 544         /* update counters */
 545         s->tso_packets = tso_packets;
 546         s->tso_bytes = tso_bytes;
 547         s->tx_queue_dropped = tx_queue_dropped;
 548         s->tx_defragged = tx_defragged;
 549         s->lro_packets = lro_packets;
 550         s->lro_bytes = lro_bytes;
 551         s->sw_lro_queued = sw_lro_queued;
 552         s->sw_lro_flushed = sw_lro_flushed;
 553         s->rx_csum_none = rx_csum_none;
 554         s->rx_wqe_err = rx_wqe_err;
 555         s->rx_packets = rx_packets;
 556         s->rx_bytes = rx_bytes;
 557
 558         /* HW counters */
 559         memset(in, 0, sizeof(in));
 560
 561         MLX5_SET(query_vport_counter_in, in, opcode,
 562             MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 563         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 564         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 565
 566         memset(out, 0, outlen);
 567
 568         /* get number of out-of-buffer drops first */
 569         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 &&
 570             mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
 571             &rx_out_of_buffer) == 0) {
 572                 /* accumulate difference into a 64-bit counter */
 573                 s->rx_out_of_buffer += (u64)(u32)(rx_out_of_buffer -
 574                     s->rx_out_of_buffer_prev);
 575                 s->rx_out_of_buffer_prev = rx_out_of_buffer;
 576         }
 577
 578         /* get port statistics */
 579         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen) == 0) {
 580 #define MLX5_GET_CTR(out, x) \
 581         MLX5_GET64(query_vport_counter_out, out, x)
 582
 583                 s->rx_error_packets =
 584                     MLX5_GET_CTR(out, received_errors.packets);
 585                 s->rx_error_bytes =
 586                     MLX5_GET_CTR(out, received_errors.octets);
 587                 s->tx_error_packets =
 588                     MLX5_GET_CTR(out, transmit_errors.packets);
 589                 s->tx_error_bytes =
 590                     MLX5_GET_CTR(out, transmit_errors.octets);
 591
 592                 s->rx_unicast_packets =
 593                     MLX5_GET_CTR(out, received_eth_unicast.packets);
 594                 s->rx_unicast_bytes =
 595                     MLX5_GET_CTR(out, received_eth_unicast.octets);
 596                 s->tx_unicast_packets =
 597                     MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 598                 s->tx_unicast_bytes =
 599                     MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 600
 601                 s->rx_multicast_packets =
 602                     MLX5_GET_CTR(out, received_eth_multicast.packets);
 603                 s->rx_multicast_bytes =
 604                     MLX5_GET_CTR(out, received_eth_multicast.octets);
 605                 s->tx_multicast_packets =
 606                     MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 607                 s->tx_multicast_bytes =
 608                     MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 609
 610                 s->rx_broadcast_packets =
 611                     MLX5_GET_CTR(out, received_eth_broadcast.packets);
 612                 s->rx_broadcast_bytes =
 613                     MLX5_GET_CTR(out, received_eth_broadcast.octets);
 614                 s->tx_broadcast_packets =
 615                     MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 616                 s->tx_broadcast_bytes =
 617                     MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 618
 619                 s->tx_packets = s->tx_unicast_packets +
 620                     s->tx_multicast_packets + s->tx_broadcast_packets;
 621                 s->tx_bytes = s->tx_unicast_bytes + s->tx_multicast_bytes +
 622                     s->tx_broadcast_bytes;
 623
 624                 /* Update calculated offload counters */
 625                 s->tx_csum_offload = s->tx_packets - tx_offload_none;
 626                 s->rx_csum_good = s->rx_packets - s->rx_csum_none;
 627         }
 628
 629         /* Get physical port counters */
 630         mlx5e_update_pport_counters(priv);
 631
 632         s->tx_jumbo_packets =
 633             priv->stats.port_stats_debug.tx_stat_p1519to2047octets +
 634             priv->stats.port_stats_debug.tx_stat_p2048to4095octets +
 635             priv->stats.port_stats_debug.tx_stat_p4096to8191octets +
 636             priv->stats.port_stats_debug.tx_stat_p8192to10239octets;
 637
 638 #if (__FreeBSD_version < 1100000)
 639         /* no get_counters interface in fbsd 10 */
 640         ifp->if_ipackets = s->rx_packets;
 641         ifp->if_ierrors = priv->stats.pport.in_range_len_errors +
 642             priv->stats.pport.out_of_range_len +
 643             priv->stats.pport.too_long_errors +
 644             priv->stats.pport.check_seq_err +
 645             priv->stats.pport.alignment_err;
 646         ifp->if_iqdrops = s->rx_out_of_buffer;
 647         ifp->if_opackets = s->tx_packets;
 648         ifp->if_oerrors = priv->stats.port_stats_debug.out_discards;
 649         ifp->if_snd.ifq_drops = s->tx_queue_dropped;
 650         ifp->if_ibytes = s->rx_bytes;
 651         ifp->if_obytes = s->tx_bytes;
 652         ifp->if_collisions =
 653             priv->stats.pport.collisions;
 654 #endif
 655
 656 free_out:
 657         kvfree(out);
 658
 659         /* Update diagnostics, if any */
 660         if (priv->params_ethtool.diag_pci_enable ||
 661             priv->params_ethtool.diag_general_enable) {
 662                 int error = mlx5_core_get_diagnostics_full(mdev,
 663                     priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL,
 664                     priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL);
 665                 if (error != 0)
 666                         if_printf(priv->ifp, "Failed reading diagnostics: %d\n", error);
 667         }
 668 }
 669
 670 static void
 671 mlx5e_update_stats_work(struct work_struct *work)
 672 {
 673         struct mlx5e_priv *priv;
 674
 675         priv  = container_of(work, struct mlx5e_priv, update_stats_work);
 676         PRIV_LOCK(priv);
 677         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
 678                 mlx5e_update_stats_locked(priv);
 679         PRIV_UNLOCK(priv);
 680 }
 681
 682 static void
 683 mlx5e_update_stats(void *arg)
 684 {
 685         struct mlx5e_priv *priv = arg;
 686
 687         queue_work(priv->wq, &priv->update_stats_work);
 688
 689         callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
 690 }
 691
 692 static void
 693 mlx5e_async_event_sub(struct mlx5e_priv *priv,
 694     enum mlx5_dev_event event)
 695 {
 696         switch (event) {
 697         case MLX5_DEV_EVENT_PORT_UP:
 698         case MLX5_DEV_EVENT_PORT_DOWN:
 699                 queue_work(priv->wq, &priv->update_carrier_work);
 700                 break;
 701
 702         default:
 703                 break;
 704         }
 705 }
 706
 707 static void
 708 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 709     enum mlx5_dev_event event, unsigned long param)
 710 {
 711         struct mlx5e_priv *priv = vpriv;
 712
 713         mtx_lock(&priv->async_events_mtx);
 714         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 715                 mlx5e_async_event_sub(priv, event);
 716         mtx_unlock(&priv->async_events_mtx);
 717 }
 718
 719 static void
 720 mlx5e_enable_async_events(struct mlx5e_priv *priv)
 721 {
 722         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 723 }
 724
 725 static void
 726 mlx5e_disable_async_events(struct mlx5e_priv *priv)
 727 {
 728         mtx_lock(&priv->async_events_mtx);
 729         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 730         mtx_unlock(&priv->async_events_mtx);
 731 }
 732
 733 static void mlx5e_calibration_callout(void *arg);
 734 static int mlx5e_calibration_duration = 20;
 735 static int mlx5e_fast_calibration = 1;
 736 static int mlx5e_normal_calibration = 30;
 737
 738 static SYSCTL_NODE(_hw_mlx5, OID_AUTO, calibr, CTLFLAG_RW, 0,
 739     "MLX5 timestamp calibration parameteres");
 740
 741 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, duration, CTLFLAG_RWTUN,
 742     &mlx5e_calibration_duration, 0,
 743     "Duration of initial calibration");
 744 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, fast, CTLFLAG_RWTUN,
 745     &mlx5e_fast_calibration, 0,
 746     "Recalibration interval during initial calibration");
 747 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, normal, CTLFLAG_RWTUN,
 748     &mlx5e_normal_calibration, 0,
 749     "Recalibration interval during normal operations");
 750
 751 /*
 752  * Ignites the calibration process.
 753  */
 754 static void
 755 mlx5e_reset_calibration_callout(struct mlx5e_priv *priv)
 756 {
 757
 758         if (priv->clbr_done == 0)
 759                 mlx5e_calibration_callout(priv);
 760         else
 761                 callout_reset_curcpu(&priv->tstmp_clbr, (priv->clbr_done <
 762                     mlx5e_calibration_duration ? mlx5e_fast_calibration :
 763                     mlx5e_normal_calibration) * hz, mlx5e_calibration_callout,
 764                     priv);
 765 }
 766
 767 static uint64_t
 768 mlx5e_timespec2usec(const struct timespec *ts)
 769 {
 770
 771         return ((uint64_t)ts->tv_sec * 1000000000 + ts->tv_nsec);
 772 }
 773
 774 static uint64_t
 775 mlx5e_hw_clock(struct mlx5e_priv *priv)
 776 {
 777         struct mlx5_init_seg *iseg;
 778         uint32_t hw_h, hw_h1, hw_l;
 779
 780         iseg = priv->mdev->iseg;
 781         do {
 782                 hw_h = ioread32be(&iseg->internal_timer_h);
 783                 hw_l = ioread32be(&iseg->internal_timer_l);
 784                 hw_h1 = ioread32be(&iseg->internal_timer_h);
 785         } while (hw_h1 != hw_h);
 786         return (((uint64_t)hw_h << 32) | hw_l);
 787 }
 788
 789 /*
 790  * The calibration callout, it runs either in the context of the
 791  * thread which enables calibration, or in callout.  It takes the
 792  * snapshot of system and adapter clocks, then advances the pointers to
 793  * the calibration point to allow rx path to read the consistent data
 794  * lockless.
 795  */
 796 static void
 797 mlx5e_calibration_callout(void *arg)
 798 {
 799         struct mlx5e_priv *priv;
 800         struct mlx5e_clbr_point *next, *curr;
 801         struct timespec ts;
 802         int clbr_curr_next;
 803
 804         priv = arg;
 805         curr = &priv->clbr_points[priv->clbr_curr];
 806         clbr_curr_next = priv->clbr_curr + 1;
 807         if (clbr_curr_next >= nitems(priv->clbr_points))
 808                 clbr_curr_next = 0;
 809         next = &priv->clbr_points[clbr_curr_next];
 810
 811         next->base_prev = curr->base_curr;
 812         next->clbr_hw_prev = curr->clbr_hw_curr;
 813
 814         next->clbr_hw_curr = mlx5e_hw_clock(priv);
 815         if (((next->clbr_hw_curr - curr->clbr_hw_prev) >> MLX5E_TSTMP_PREC) ==
 816             0) {
 817                 if_printf(priv->ifp, "HW failed tstmp frozen %#jx %#jx,"
 818                     "disabling\n", next->clbr_hw_curr, curr->clbr_hw_prev);
 819                 priv->clbr_done = 0;
 820                 return;
 821         }
 822
 823         nanouptime(&ts);
 824         next->base_curr = mlx5e_timespec2usec(&ts);
 825
 826         curr->clbr_gen = 0;
 827         atomic_thread_fence_rel();
 828         priv->clbr_curr = clbr_curr_next;
 829         atomic_store_rel_int(&next->clbr_gen, ++(priv->clbr_gen));
 830
 831         if (priv->clbr_done < mlx5e_calibration_duration)
 832                 priv->clbr_done++;
 833         mlx5e_reset_calibration_callout(priv);
 834 }
 835
 836 static const char *mlx5e_rq_stats_desc[] = {
 837         MLX5E_RQ_STATS(MLX5E_STATS_DESC)
 838 };
 839
 840 static int
 841 mlx5e_create_rq(struct mlx5e_channel *c,
 842     struct mlx5e_rq_param *param,
 843     struct mlx5e_rq *rq)
 844 {
 845         struct mlx5e_priv *priv = c->priv;
 846         struct mlx5_core_dev *mdev = priv->mdev;
 847         char buffer[16];
 848         void *rqc = param->rqc;
 849         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 850         int wq_sz;
 851         int err;
 852         int i;
 853         u32 nsegs, wqe_sz;
 854
 855         err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
 856         if (err != 0)
 857                 goto done;
 858
 859         /* Create DMA descriptor TAG */
 860         if ((err = -bus_dma_tag_create(
 861             bus_get_dma_tag(mdev->pdev->dev.bsddev),
 862             1,                          /* any alignment */
 863             0,                          /* no boundary */
 864             BUS_SPACE_MAXADDR,          /* lowaddr */
 865             BUS_SPACE_MAXADDR,          /* highaddr */
 866             NULL, NULL,                 /* filter, filterarg */
 867             nsegs * MLX5E_MAX_RX_BYTES, /* maxsize */
 868             nsegs,                      /* nsegments */
 869             nsegs * MLX5E_MAX_RX_BYTES, /* maxsegsize */
 870             0,                          /* flags */
 871             NULL, NULL,                 /* lockfunc, lockfuncarg */
 872             &rq->dma_tag)))
 873                 goto done;
 874
 875         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 876             &rq->wq_ctrl);
 877         if (err)
 878                 goto err_free_dma_tag;
 879
 880         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 881
 882         err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs);
 883         if (err != 0)
 884                 goto err_rq_wq_destroy;
 885
 886         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 887
 888         err = -tcp_lro_init_args(&rq->lro, c->tag.m_snd_tag.ifp, TCP_LRO_ENTRIES, wq_sz);
 889         if (err)
 890                 goto err_rq_wq_destroy;
 891
 892         rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
 893         for (i = 0; i != wq_sz; i++) {
 894                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 895 #if (MLX5E_MAX_RX_SEGS == 1)
 896                 uint32_t byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 897 #else
 898                 int j;
 899 #endif
 900
 901                 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
 902                 if (err != 0) {
 903                         while (i--)
 904                                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 905                         goto err_rq_mbuf_free;
 906                 }
 907
 908                 /* set value for constant fields */
 909 #if (MLX5E_MAX_RX_SEGS == 1)
 910                 wqe->data[0].lkey = c->mkey_be;
 911                 wqe->data[0].byte_count = cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
 912 #else
 913                 for (j = 0; j < rq->nsegs; j++)
 914                         wqe->data[j].lkey = c->mkey_be;
 915 #endif
 916         }
 917
 918         INIT_WORK(&rq->dim.work, mlx5e_dim_work);
 919         if (priv->params.rx_cq_moderation_mode < 2) {
 920                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
 921         } else {
 922                 void *cqc = container_of(param,
 923                     struct mlx5e_channel_param, rq)->rx_cq.cqc;
 924
 925                 switch (MLX5_GET(cqc, cqc, cq_period_mode)) {
 926                 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 927                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 928                         break;
 929                 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 930                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 931                         break;
 932                 default:
 933                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
 934                         break;
 935                 }
 936         }
 937
 938         rq->ifp = c->tag.m_snd_tag.ifp;
 939         rq->channel = c;
 940         rq->ix = c->ix;
 941
 942         snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
 943         mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
 944             buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
 945             rq->stats.arg);
 946         return (0);
 947
 948 err_rq_mbuf_free:
 949         free(rq->mbuf, M_MLX5EN);
 950         tcp_lro_free(&rq->lro);
 951 err_rq_wq_destroy:
 952         mlx5_wq_destroy(&rq->wq_ctrl);
 953 err_free_dma_tag:
 954         bus_dma_tag_destroy(rq->dma_tag);
 955 done:
 956         return (err);
 957 }
 958
 959 static void
 960 mlx5e_destroy_rq(struct mlx5e_rq *rq)
 961 {
 962         int wq_sz;
 963         int i;
 964
 965         /* destroy all sysctl nodes */
 966         sysctl_ctx_free(&rq->stats.ctx);
 967
 968         /* free leftover LRO packets, if any */
 969         tcp_lro_free(&rq->lro);
 970
 971         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 972         for (i = 0; i != wq_sz; i++) {
 973                 if (rq->mbuf[i].mbuf != NULL) {
 974                         bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map);
 975                         m_freem(rq->mbuf[i].mbuf);
 976                 }
 977                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 978         }
 979         free(rq->mbuf, M_MLX5EN);
 980         mlx5_wq_destroy(&rq->wq_ctrl);
 981 }
 982
 983 static int
 984 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 985 {
 986         struct mlx5e_channel *c = rq->channel;
 987         struct mlx5e_priv *priv = c->priv;
 988         struct mlx5_core_dev *mdev = priv->mdev;
 989
 990         void *in;
 991         void *rqc;
 992         void *wq;
 993         int inlen;
 994         int err;
 995
 996         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 997             sizeof(u64) * rq->wq_ctrl.buf.npages;
 998         in = mlx5_vzalloc(inlen);
 999         if (in == NULL)
1000                 return (-ENOMEM);
1001
1002         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1003         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1004
1005         memcpy(rqc, param->rqc, sizeof(param->rqc));
1006
1007         MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
1008         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1009         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1010         if (priv->counter_set_id >= 0)
1011                 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
1012         MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
1013             PAGE_SHIFT);
1014         MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
1015
1016         mlx5_fill_page_array(&rq->wq_ctrl.buf,
1017             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1018
1019         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
1020
1021         kvfree(in);
1022
1023         return (err);
1024 }
1025
1026 static int
1027 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
1028 {
1029         struct mlx5e_channel *c = rq->channel;
1030         struct mlx5e_priv *priv = c->priv;
1031         struct mlx5_core_dev *mdev = priv->mdev;
1032
1033         void *in;
1034         void *rqc;
1035         int inlen;
1036         int err;
1037
1038         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1039         in = mlx5_vzalloc(inlen);
1040         if (in == NULL)
1041                 return (-ENOMEM);
1042
1043         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1044
1045         MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
1046         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
1047         MLX5_SET(rqc, rqc, state, next_state);
1048
1049         err = mlx5_core_modify_rq(mdev, in, inlen);
1050
1051         kvfree(in);
1052
1053         return (err);
1054 }
1055
1056 static void
1057 mlx5e_disable_rq(struct mlx5e_rq *rq)
1058 {
1059         struct mlx5e_channel *c = rq->channel;
1060         struct mlx5e_priv *priv = c->priv;
1061         struct mlx5_core_dev *mdev = priv->mdev;
1062
1063         mlx5_core_destroy_rq(mdev, rq->rqn);
1064 }
1065
1066 static int
1067 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
1068 {
1069         struct mlx5e_channel *c = rq->channel;
1070         struct mlx5e_priv *priv = c->priv;
1071         struct mlx5_wq_ll *wq = &rq->wq;
1072         int i;
1073
1074         for (i = 0; i < 1000; i++) {
1075                 if (wq->cur_sz >= priv->params.min_rx_wqes)
1076                         return (0);
1077
1078                 msleep(4);
1079         }
1080         return (-ETIMEDOUT);
1081 }
1082
1083 static int
1084 mlx5e_open_rq(struct mlx5e_channel *c,
1085     struct mlx5e_rq_param *param,
1086     struct mlx5e_rq *rq)
1087 {
1088         int err;
1089
1090         err = mlx5e_create_rq(c, param, rq);
1091         if (err)
1092                 return (err);
1093
1094         err = mlx5e_enable_rq(rq, param);
1095         if (err)
1096                 goto err_destroy_rq;
1097
1098         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1099         if (err)
1100                 goto err_disable_rq;
1101
1102         c->rq.enabled = 1;
1103
1104         return (0);
1105
1106 err_disable_rq:
1107         mlx5e_disable_rq(rq);
1108 err_destroy_rq:
1109         mlx5e_destroy_rq(rq);
1110
1111         return (err);
1112 }
1113
1114 static void
1115 mlx5e_close_rq(struct mlx5e_rq *rq)
1116 {
1117         mtx_lock(&rq->mtx);
1118         rq->enabled = 0;
1119         callout_stop(&rq->watchdog);
1120         mtx_unlock(&rq->mtx);
1121
1122         callout_drain(&rq->watchdog);
1123
1124         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
1125 }
1126
1127 static void
1128 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
1129 {
1130
1131         mlx5e_disable_rq(rq);
1132         mlx5e_close_cq(&rq->cq);
1133         cancel_work_sync(&rq->dim.work);
1134         mlx5e_destroy_rq(rq);
1135 }
1136
1137 void
1138 mlx5e_free_sq_db(struct mlx5e_sq *sq)
1139 {
1140         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1141         int x;
1142
1143         for (x = 0; x != wq_sz; x++) {
1144                 if (sq->mbuf[x].mbuf != NULL) {
1145                         bus_dmamap_unload(sq->dma_tag, sq->mbuf[x].dma_map);
1146                         m_freem(sq->mbuf[x].mbuf);
1147                 }
1148                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1149         }
1150         free(sq->mbuf, M_MLX5EN);
1151 }
1152
1153 int
1154 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
1155 {
1156         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1157         int err;
1158         int x;
1159
1160         sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1161
1162         /* Create DMA descriptor MAPs */
1163         for (x = 0; x != wq_sz; x++) {
1164                 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
1165                 if (err != 0) {
1166                         while (x--)
1167                                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1168                         free(sq->mbuf, M_MLX5EN);
1169                         return (err);
1170                 }
1171         }
1172         return (0);
1173 }
1174
1175 static const char *mlx5e_sq_stats_desc[] = {
1176         MLX5E_SQ_STATS(MLX5E_STATS_DESC)
1177 };
1178
1179 void
1180 mlx5e_update_sq_inline(struct mlx5e_sq *sq)
1181 {
1182         sq->max_inline = sq->priv->params.tx_max_inline;
1183         sq->min_inline_mode = sq->priv->params.tx_min_inline_mode;
1184
1185         /*
1186          * Check if trust state is DSCP or if inline mode is NONE which
1187          * indicates CX-5 or newer hardware.
1188          */
1189         if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP ||
1190             sq->min_inline_mode == MLX5_INLINE_MODE_NONE) {
1191                 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert))
1192                         sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN;
1193                 else
1194                         sq->min_insert_caps = MLX5E_INSERT_NON_VLAN;
1195         } else {
1196                 sq->min_insert_caps = 0;
1197         }
1198 }
1199
1200 static void
1201 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1202 {
1203         int i;
1204
1205         for (i = 0; i != c->num_tc; i++) {
1206                 mtx_lock(&c->sq[i].lock);
1207                 mlx5e_update_sq_inline(&c->sq[i]);
1208                 mtx_unlock(&c->sq[i].lock);
1209         }
1210 }
1211
1212 void
1213 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv)
1214 {
1215         int i;
1216
1217         /* check if channels are closed */
1218         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
1219                 return;
1220
1221         for (i = 0; i < priv->params.num_channels; i++)
1222                 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]);
1223 }
1224
1225 static int
1226 mlx5e_create_sq(struct mlx5e_channel *c,
1227     int tc,
1228     struct mlx5e_sq_param *param,
1229     struct mlx5e_sq *sq)
1230 {
1231         struct mlx5e_priv *priv = c->priv;
1232         struct mlx5_core_dev *mdev = priv->mdev;
1233         char buffer[16];
1234         void *sqc = param->sqc;
1235         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1236         int err;
1237
1238         /* Create DMA descriptor TAG */
1239         if ((err = -bus_dma_tag_create(
1240             bus_get_dma_tag(mdev->pdev->dev.bsddev),
1241             1,                          /* any alignment */
1242             0,                          /* no boundary */
1243             BUS_SPACE_MAXADDR,          /* lowaddr */
1244             BUS_SPACE_MAXADDR,          /* highaddr */
1245             NULL, NULL,                 /* filter, filterarg */
1246             MLX5E_MAX_TX_PAYLOAD_SIZE,  /* maxsize */
1247             MLX5E_MAX_TX_MBUF_FRAGS,    /* nsegments */
1248             MLX5E_MAX_TX_MBUF_SIZE,     /* maxsegsize */
1249             0,                          /* flags */
1250             NULL, NULL,                 /* lockfunc, lockfuncarg */
1251             &sq->dma_tag)))
1252                 goto done;
1253
1254         err = mlx5_alloc_map_uar(mdev, &sq->uar);
1255         if (err)
1256                 goto err_free_dma_tag;
1257
1258         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
1259             &sq->wq_ctrl);
1260         if (err)
1261                 goto err_unmap_free_uar;
1262
1263         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1264         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1265
1266         err = mlx5e_alloc_sq_db(sq);
1267         if (err)
1268                 goto err_sq_wq_destroy;
1269
1270         sq->mkey_be = c->mkey_be;
1271         sq->ifp = priv->ifp;
1272         sq->priv = priv;
1273         sq->tc = tc;
1274
1275         mlx5e_update_sq_inline(sq);
1276
1277         snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1278         mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1279             buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1280             sq->stats.arg);
1281
1282         return (0);
1283
1284 err_sq_wq_destroy:
1285         mlx5_wq_destroy(&sq->wq_ctrl);
1286
1287 err_unmap_free_uar:
1288         mlx5_unmap_free_uar(mdev, &sq->uar);
1289
1290 err_free_dma_tag:
1291         bus_dma_tag_destroy(sq->dma_tag);
1292 done:
1293         return (err);
1294 }
1295
1296 static void
1297 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1298 {
1299         /* destroy all sysctl nodes */
1300         sysctl_ctx_free(&sq->stats.ctx);
1301
1302         mlx5e_free_sq_db(sq);
1303         mlx5_wq_destroy(&sq->wq_ctrl);
1304         mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1305 }
1306
1307 int
1308 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1309     int tis_num)
1310 {
1311         void *in;
1312         void *sqc;
1313         void *wq;
1314         int inlen;
1315         int err;
1316
1317         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1318             sizeof(u64) * sq->wq_ctrl.buf.npages;
1319         in = mlx5_vzalloc(inlen);
1320         if (in == NULL)
1321                 return (-ENOMEM);
1322
1323         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1324         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1325
1326         memcpy(sqc, param->sqc, sizeof(param->sqc));
1327
1328         MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1329         MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1330         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1331         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1332         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1333
1334         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1335         MLX5_SET(wq, wq, uar_page, sq->uar.index);
1336         MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1337             PAGE_SHIFT);
1338         MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1339
1340         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1341             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1342
1343         err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1344
1345         kvfree(in);
1346
1347         return (err);
1348 }
1349
1350 int
1351 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1352 {
1353         void *in;
1354         void *sqc;
1355         int inlen;
1356         int err;
1357
1358         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1359         in = mlx5_vzalloc(inlen);
1360         if (in == NULL)
1361                 return (-ENOMEM);
1362
1363         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1364
1365         MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1366         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1367         MLX5_SET(sqc, sqc, state, next_state);
1368
1369         err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1370
1371         kvfree(in);
1372
1373         return (err);
1374 }
1375
1376 void
1377 mlx5e_disable_sq(struct mlx5e_sq *sq)
1378 {
1379
1380         mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1381 }
1382
1383 static int
1384 mlx5e_open_sq(struct mlx5e_channel *c,
1385     int tc,
1386     struct mlx5e_sq_param *param,
1387     struct mlx5e_sq *sq)
1388 {
1389         int err;
1390
1391         err = mlx5e_create_sq(c, tc, param, sq);
1392         if (err)
1393                 return (err);
1394
1395         err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1396         if (err)
1397                 goto err_destroy_sq;
1398
1399         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1400         if (err)
1401                 goto err_disable_sq;
1402
1403         WRITE_ONCE(sq->running, 1);
1404
1405         return (0);
1406
1407 err_disable_sq:
1408         mlx5e_disable_sq(sq);
1409 err_destroy_sq:
1410         mlx5e_destroy_sq(sq);
1411
1412         return (err);
1413 }
1414
1415 static void
1416 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1417 {
1418         /* fill up remainder with NOPs */
1419         while (sq->cev_counter != 0) {
1420                 while (!mlx5e_sq_has_room_for(sq, 1)) {
1421                         if (can_sleep != 0) {
1422                                 mtx_unlock(&sq->lock);
1423                                 msleep(4);
1424                                 mtx_lock(&sq->lock);
1425                         } else {
1426                                 goto done;
1427                         }
1428                 }
1429                 /* send a single NOP */
1430                 mlx5e_send_nop(sq, 1);
1431                 atomic_thread_fence_rel();
1432         }
1433 done:
1434         /* Check if we need to write the doorbell */
1435         if (likely(sq->doorbell.d64 != 0)) {
1436                 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1437                 sq->doorbell.d64 = 0;
1438         }
1439 }
1440
1441 void
1442 mlx5e_sq_cev_timeout(void *arg)
1443 {
1444         struct mlx5e_sq *sq = arg;
1445
1446         mtx_assert(&sq->lock, MA_OWNED);
1447
1448         /* check next state */
1449         switch (sq->cev_next_state) {
1450         case MLX5E_CEV_STATE_SEND_NOPS:
1451                 /* fill TX ring with NOPs, if any */
1452                 mlx5e_sq_send_nops_locked(sq, 0);
1453
1454                 /* check if completed */
1455                 if (sq->cev_counter == 0) {
1456                         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1457                         return;
1458                 }
1459                 break;
1460         default:
1461                 /* send NOPs on next timeout */
1462                 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1463                 break;
1464         }
1465
1466         /* restart timer */
1467         callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1468 }
1469
1470 void
1471 mlx5e_drain_sq(struct mlx5e_sq *sq)
1472 {
1473         int error;
1474         struct mlx5_core_dev *mdev= sq->priv->mdev;
1475
1476         /*
1477          * Check if already stopped.
1478          *
1479          * NOTE: Serialization of this function is managed by the
1480          * caller ensuring the priv's state lock is locked or in case
1481          * of rate limit support, a single thread manages drain and
1482          * resume of SQs. The "running" variable can therefore safely
1483          * be read without any locks.
1484          */
1485         if (READ_ONCE(sq->running) == 0)
1486                 return;
1487
1488         /* don't put more packets into the SQ */
1489         WRITE_ONCE(sq->running, 0);
1490
1491         /* serialize access to DMA rings */
1492         mtx_lock(&sq->lock);
1493
1494         /* teardown event factor timer, if any */
1495         sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1496         callout_stop(&sq->cev_callout);
1497
1498         /* send dummy NOPs in order to flush the transmit ring */
1499         mlx5e_sq_send_nops_locked(sq, 1);
1500         mtx_unlock(&sq->lock);
1501
1502         /* make sure it is safe to free the callout */
1503         callout_drain(&sq->cev_callout);
1504
1505         /* wait till SQ is empty or link is down */
1506         mtx_lock(&sq->lock);
1507         while (sq->cc != sq->pc &&
1508             (sq->priv->media_status_last & IFM_ACTIVE) != 0 &&
1509             mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1510                 mtx_unlock(&sq->lock);
1511                 msleep(1);
1512                 sq->cq.mcq.comp(&sq->cq.mcq);
1513                 mtx_lock(&sq->lock);
1514         }
1515         mtx_unlock(&sq->lock);
1516
1517         /* error out remaining requests */
1518         error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1519         if (error != 0) {
1520                 if_printf(sq->ifp,
1521                     "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error);
1522         }
1523
1524         /* wait till SQ is empty */
1525         mtx_lock(&sq->lock);
1526         while (sq->cc != sq->pc &&
1527                mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1528                 mtx_unlock(&sq->lock);
1529                 msleep(1);
1530                 sq->cq.mcq.comp(&sq->cq.mcq);
1531                 mtx_lock(&sq->lock);
1532         }
1533         mtx_unlock(&sq->lock);
1534 }
1535
1536 static void
1537 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1538 {
1539
1540         mlx5e_drain_sq(sq);
1541         mlx5e_disable_sq(sq);
1542         mlx5e_destroy_sq(sq);
1543 }
1544
1545 static int
1546 mlx5e_create_cq(struct mlx5e_priv *priv,
1547     struct mlx5e_cq_param *param,
1548     struct mlx5e_cq *cq,
1549     mlx5e_cq_comp_t *comp,
1550     int eq_ix)
1551 {
1552         struct mlx5_core_dev *mdev = priv->mdev;
1553         struct mlx5_core_cq *mcq = &cq->mcq;
1554         int eqn_not_used;
1555         int irqn;
1556         int err;
1557         u32 i;
1558
1559         param->wq.buf_numa_node = 0;
1560         param->wq.db_numa_node = 0;
1561
1562         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1563             &cq->wq_ctrl);
1564         if (err)
1565                 return (err);
1566
1567         mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1568
1569         mcq->cqe_sz = 64;
1570         mcq->set_ci_db = cq->wq_ctrl.db.db;
1571         mcq->arm_db = cq->wq_ctrl.db.db + 1;
1572         *mcq->set_ci_db = 0;
1573         *mcq->arm_db = 0;
1574         mcq->vector = eq_ix;
1575         mcq->comp = comp;
1576         mcq->event = mlx5e_cq_error_event;
1577         mcq->irqn = irqn;
1578         mcq->uar = &priv->cq_uar;
1579
1580         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1581                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1582
1583                 cqe->op_own = 0xf1;
1584         }
1585
1586         cq->priv = priv;
1587
1588         return (0);
1589 }
1590
1591 static void
1592 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1593 {
1594         mlx5_wq_destroy(&cq->wq_ctrl);
1595 }
1596
1597 static int
1598 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1599 {
1600         struct mlx5_core_cq *mcq = &cq->mcq;
1601         void *in;
1602         void *cqc;
1603         int inlen;
1604         int irqn_not_used;
1605         int eqn;
1606         int err;
1607
1608         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1609             sizeof(u64) * cq->wq_ctrl.buf.npages;
1610         in = mlx5_vzalloc(inlen);
1611         if (in == NULL)
1612                 return (-ENOMEM);
1613
1614         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1615
1616         memcpy(cqc, param->cqc, sizeof(param->cqc));
1617
1618         mlx5_fill_page_array(&cq->wq_ctrl.buf,
1619             (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1620
1621         mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
1622
1623         MLX5_SET(cqc, cqc, c_eqn, eqn);
1624         MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1625         MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1626             PAGE_SHIFT);
1627         MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1628
1629         err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
1630
1631         kvfree(in);
1632
1633         if (err)
1634                 return (err);
1635
1636         mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock));
1637
1638         return (0);
1639 }
1640
1641 static void
1642 mlx5e_disable_cq(struct mlx5e_cq *cq)
1643 {
1644
1645         mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
1646 }
1647
1648 int
1649 mlx5e_open_cq(struct mlx5e_priv *priv,
1650     struct mlx5e_cq_param *param,
1651     struct mlx5e_cq *cq,
1652     mlx5e_cq_comp_t *comp,
1653     int eq_ix)
1654 {
1655         int err;
1656
1657         err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
1658         if (err)
1659                 return (err);
1660
1661         err = mlx5e_enable_cq(cq, param, eq_ix);
1662         if (err)
1663                 goto err_destroy_cq;
1664
1665         return (0);
1666
1667 err_destroy_cq:
1668         mlx5e_destroy_cq(cq);
1669
1670         return (err);
1671 }
1672
1673 void
1674 mlx5e_close_cq(struct mlx5e_cq *cq)
1675 {
1676         mlx5e_disable_cq(cq);
1677         mlx5e_destroy_cq(cq);
1678 }
1679
1680 static int
1681 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1682     struct mlx5e_channel_param *cparam)
1683 {
1684         int err;
1685         int tc;
1686
1687         for (tc = 0; tc < c->num_tc; tc++) {
1688                 /* open completion queue */
1689                 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
1690                     &mlx5e_tx_cq_comp, c->ix);
1691                 if (err)
1692                         goto err_close_tx_cqs;
1693         }
1694         return (0);
1695
1696 err_close_tx_cqs:
1697         for (tc--; tc >= 0; tc--)
1698                 mlx5e_close_cq(&c->sq[tc].cq);
1699
1700         return (err);
1701 }
1702
1703 static void
1704 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1705 {
1706         int tc;
1707
1708         for (tc = 0; tc < c->num_tc; tc++)
1709                 mlx5e_close_cq(&c->sq[tc].cq);
1710 }
1711
1712 static int
1713 mlx5e_open_sqs(struct mlx5e_channel *c,
1714     struct mlx5e_channel_param *cparam)
1715 {
1716         int err;
1717         int tc;
1718
1719         for (tc = 0; tc < c->num_tc; tc++) {
1720                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1721                 if (err)
1722                         goto err_close_sqs;
1723         }
1724
1725         return (0);
1726
1727 err_close_sqs:
1728         for (tc--; tc >= 0; tc--)
1729                 mlx5e_close_sq_wait(&c->sq[tc]);
1730
1731         return (err);
1732 }
1733
1734 static void
1735 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
1736 {
1737         int tc;
1738
1739         for (tc = 0; tc < c->num_tc; tc++)
1740                 mlx5e_close_sq_wait(&c->sq[tc]);
1741 }
1742
1743 static void
1744 mlx5e_chan_mtx_init(struct mlx5e_channel *c)
1745 {
1746         int tc;
1747
1748         mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
1749
1750         callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
1751
1752         for (tc = 0; tc < c->num_tc; tc++) {
1753                 struct mlx5e_sq *sq = c->sq + tc;
1754
1755                 mtx_init(&sq->lock, "mlx5tx",
1756                     MTX_NETWORK_LOCK " TX", MTX_DEF);
1757                 mtx_init(&sq->comp_lock, "mlx5comp",
1758                     MTX_NETWORK_LOCK " TX", MTX_DEF);
1759
1760                 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
1761
1762                 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1763
1764                 /* ensure the TX completion event factor is not zero */
1765                 if (sq->cev_factor == 0)
1766                         sq->cev_factor = 1;
1767         }
1768 }
1769
1770 static void
1771 mlx5e_chan_mtx_destroy(struct mlx5e_channel *c)
1772 {
1773         int tc;
1774
1775         mtx_destroy(&c->rq.mtx);
1776
1777         for (tc = 0; tc < c->num_tc; tc++) {
1778                 mtx_destroy(&c->sq[tc].lock);
1779                 mtx_destroy(&c->sq[tc].comp_lock);
1780         }
1781 }
1782
1783 static int
1784 mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1785     struct mlx5e_channel_param *cparam,
1786     struct mlx5e_channel *c)
1787 {
1788         int err;
1789
1790         memset(c, 0, sizeof(*c));
1791
1792         c->priv = priv;
1793         c->ix = ix;
1794         /* setup send tag */
1795         c->tag.m_snd_tag.ifp = priv->ifp;
1796         c->tag.type = IF_SND_TAG_TYPE_UNLIMITED;
1797         c->mkey_be = cpu_to_be32(priv->mr.key);
1798         c->num_tc = priv->num_tc;
1799
1800         /* init mutexes */
1801         mlx5e_chan_mtx_init(c);
1802
1803         /* open transmit completion queue */
1804         err = mlx5e_open_tx_cqs(c, cparam);
1805         if (err)
1806                 goto err_free;
1807
1808         /* open receive completion queue */
1809         err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
1810             &mlx5e_rx_cq_comp, c->ix);
1811         if (err)
1812                 goto err_close_tx_cqs;
1813
1814         err = mlx5e_open_sqs(c, cparam);
1815         if (err)
1816                 goto err_close_rx_cq;
1817
1818         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1819         if (err)
1820                 goto err_close_sqs;
1821
1822         /* poll receive queue initially */
1823         c->rq.cq.mcq.comp(&c->rq.cq.mcq);
1824
1825         return (0);
1826
1827 err_close_sqs:
1828         mlx5e_close_sqs_wait(c);
1829
1830 err_close_rx_cq:
1831         mlx5e_close_cq(&c->rq.cq);
1832
1833 err_close_tx_cqs:
1834         mlx5e_close_tx_cqs(c);
1835
1836 err_free:
1837         /* destroy mutexes */
1838         mlx5e_chan_mtx_destroy(c);
1839         return (err);
1840 }
1841
1842 static void
1843 mlx5e_close_channel(struct mlx5e_channel *c)
1844 {
1845         mlx5e_close_rq(&c->rq);
1846 }
1847
1848 static void
1849 mlx5e_close_channel_wait(struct mlx5e_channel *c)
1850 {
1851         mlx5e_close_rq_wait(&c->rq);
1852         mlx5e_close_sqs_wait(c);
1853         mlx5e_close_tx_cqs(c);
1854         /* destroy mutexes */
1855         mlx5e_chan_mtx_destroy(c);
1856 }
1857
1858 static int
1859 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs)
1860 {
1861         u32 r, n;
1862
1863         r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz :
1864             MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
1865         if (r > MJUM16BYTES)
1866                 return (-ENOMEM);
1867
1868         if (r > MJUM9BYTES)
1869                 r = MJUM16BYTES;
1870         else if (r > MJUMPAGESIZE)
1871                 r = MJUM9BYTES;
1872         else if (r > MCLBYTES)
1873                 r = MJUMPAGESIZE;
1874         else
1875                 r = MCLBYTES;
1876
1877         /*
1878          * n + 1 must be a power of two, because stride size must be.
1879          * Stride size is 16 * (n + 1), as the first segment is
1880          * control.
1881          */
1882         for (n = howmany(r, MLX5E_MAX_RX_BYTES); !powerof2(n + 1); n++)
1883                 ;
1884
1885         *wqe_sz = r;
1886         *nsegs = n;
1887         return (0);
1888 }
1889
1890 static void
1891 mlx5e_build_rq_param(struct mlx5e_priv *priv,
1892     struct mlx5e_rq_param *param)
1893 {
1894         void *rqc = param->rqc;
1895         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1896         u32 wqe_sz, nsegs;
1897
1898         mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
1899         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1900         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1901         MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) +
1902             nsegs * sizeof(struct mlx5_wqe_data_seg)));
1903         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1904         MLX5_SET(wq, wq, pd, priv->pdn);
1905
1906         param->wq.buf_numa_node = 0;
1907         param->wq.db_numa_node = 0;
1908         param->wq.linear = 1;
1909 }
1910
1911 static void
1912 mlx5e_build_sq_param(struct mlx5e_priv *priv,
1913     struct mlx5e_sq_param *param)
1914 {
1915         void *sqc = param->sqc;
1916         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1917
1918         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1919         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1920         MLX5_SET(wq, wq, pd, priv->pdn);
1921
1922         param->wq.buf_numa_node = 0;
1923         param->wq.db_numa_node = 0;
1924         param->wq.linear = 1;
1925 }
1926
1927 static void
1928 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1929     struct mlx5e_cq_param *param)
1930 {
1931         void *cqc = param->cqc;
1932
1933         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1934 }
1935
1936 static void
1937 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr)
1938 {
1939
1940         *ptr = net_dim_get_profile(mode, MLX5E_DIM_DEFAULT_PROFILE);
1941
1942         /* apply LRO restrictions */
1943         if (priv->params.hw_lro_en &&
1944             ptr->pkts > MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO) {
1945                 ptr->pkts = MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO;
1946         }
1947 }
1948
1949 static void
1950 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1951     struct mlx5e_cq_param *param)
1952 {
1953         struct net_dim_cq_moder curr;
1954         void *cqc = param->cqc;
1955
1956         /*
1957          * We use MLX5_CQE_FORMAT_HASH because the RX hash mini CQE
1958          * format is more beneficial for FreeBSD use case.
1959          *
1960          * Adding support for MLX5_CQE_FORMAT_CSUM will require changes
1961          * in mlx5e_decompress_cqe.
1962          */
1963         if (priv->params.cqe_zipping_en) {
1964                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_HASH);
1965                 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
1966         }
1967
1968         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1969
1970         switch (priv->params.rx_cq_moderation_mode) {
1971         case 0:
1972                 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1973                 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1974                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1975                 break;
1976         case 1:
1977                 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1978                 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1979                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1980                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1981                 else
1982                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1983                 break;
1984         case 2:
1985                 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr);
1986                 MLX5_SET(cqc, cqc, cq_period, curr.usec);
1987                 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
1988                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1989                 break;
1990         case 3:
1991                 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr);
1992                 MLX5_SET(cqc, cqc, cq_period, curr.usec);
1993                 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
1994                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1995                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1996                 else
1997                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1998                 break;
1999         default:
2000                 break;
2001         }
2002
2003         mlx5e_dim_build_cq_param(priv, param);
2004
2005         mlx5e_build_common_cq_param(priv, param);
2006 }
2007
2008 static void
2009 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2010     struct mlx5e_cq_param *param)
2011 {
2012         void *cqc = param->cqc;
2013
2014         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
2015         MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
2016         MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
2017
2018         switch (priv->params.tx_cq_moderation_mode) {
2019         case 0:
2020                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2021                 break;
2022         default:
2023                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2024                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2025                 else
2026                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2027                 break;
2028         }
2029
2030         mlx5e_build_common_cq_param(priv, param);
2031 }
2032
2033 static void
2034 mlx5e_build_channel_param(struct mlx5e_priv *priv,
2035     struct mlx5e_channel_param *cparam)
2036 {
2037         memset(cparam, 0, sizeof(*cparam));
2038
2039         mlx5e_build_rq_param(priv, &cparam->rq);
2040         mlx5e_build_sq_param(priv, &cparam->sq);
2041         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
2042         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
2043 }
2044
2045 static int
2046 mlx5e_open_channels(struct mlx5e_priv *priv)
2047 {
2048         struct mlx5e_channel_param cparam;
2049         int err;
2050         int i;
2051         int j;
2052
2053         mlx5e_build_channel_param(priv, &cparam);
2054         for (i = 0; i < priv->params.num_channels; i++) {
2055                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
2056                 if (err)
2057                         goto err_close_channels;
2058         }
2059
2060         for (j = 0; j < priv->params.num_channels; j++) {
2061                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j].rq);
2062                 if (err)
2063                         goto err_close_channels;
2064         }
2065         return (0);
2066
2067 err_close_channels:
2068         while (i--) {
2069                 mlx5e_close_channel(&priv->channel[i]);
2070                 mlx5e_close_channel_wait(&priv->channel[i]);
2071         }
2072         return (err);
2073 }
2074
2075 static void
2076 mlx5e_close_channels(struct mlx5e_priv *priv)
2077 {
2078         int i;
2079
2080         for (i = 0; i < priv->params.num_channels; i++)
2081                 mlx5e_close_channel(&priv->channel[i]);
2082         for (i = 0; i < priv->params.num_channels; i++)
2083                 mlx5e_close_channel_wait(&priv->channel[i]);
2084 }
2085
2086 static int
2087 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
2088 {
2089
2090         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2091                 uint8_t cq_mode;
2092
2093                 switch (priv->params.tx_cq_moderation_mode) {
2094                 case 0:
2095                 case 2:
2096                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2097                         break;
2098                 default:
2099                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2100                         break;
2101                 }
2102
2103                 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq,
2104                     priv->params.tx_cq_moderation_usec,
2105                     priv->params.tx_cq_moderation_pkts,
2106                     cq_mode));
2107         }
2108
2109         return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
2110             priv->params.tx_cq_moderation_usec,
2111             priv->params.tx_cq_moderation_pkts));
2112 }
2113
2114 static int
2115 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
2116 {
2117
2118         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2119                 uint8_t cq_mode;
2120                 uint8_t dim_mode;
2121                 int retval;
2122
2123                 switch (priv->params.rx_cq_moderation_mode) {
2124                 case 0:
2125                 case 2:
2126                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2127                         dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2128                         break;
2129                 default:
2130                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2131                         dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
2132                         break;
2133                 }
2134
2135                 /* tear down dynamic interrupt moderation */
2136                 mtx_lock(&rq->mtx);
2137                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
2138                 mtx_unlock(&rq->mtx);
2139
2140                 /* wait for dynamic interrupt moderation work task, if any */
2141                 cancel_work_sync(&rq->dim.work);
2142
2143                 if (priv->params.rx_cq_moderation_mode >= 2) {
2144                         struct net_dim_cq_moder curr;
2145
2146                         mlx5e_get_default_profile(priv, dim_mode, &curr);
2147
2148                         retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2149                             curr.usec, curr.pkts, cq_mode);
2150
2151                         /* set dynamic interrupt moderation mode and zero defaults */
2152                         mtx_lock(&rq->mtx);
2153                         rq->dim.mode = dim_mode;
2154                         rq->dim.state = 0;
2155                         rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE;
2156                         mtx_unlock(&rq->mtx);
2157                 } else {
2158                         retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2159                             priv->params.rx_cq_moderation_usec,
2160                             priv->params.rx_cq_moderation_pkts,
2161                             cq_mode);
2162                 }
2163                 return (retval);
2164         }
2165
2166         return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
2167             priv->params.rx_cq_moderation_usec,
2168             priv->params.rx_cq_moderation_pkts));
2169 }
2170
2171 static int
2172 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
2173 {
2174         int err;
2175         int i;
2176
2177         err = mlx5e_refresh_rq_params(priv, &c->rq);
2178         if (err)
2179                 goto done;
2180
2181         for (i = 0; i != c->num_tc; i++) {
2182                 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
2183                 if (err)
2184                         goto done;
2185         }
2186 done:
2187         return (err);
2188 }
2189
2190 int
2191 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
2192 {
2193         int i;
2194
2195         /* check if channels are closed */
2196         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2197                 return (EINVAL);
2198
2199         for (i = 0; i < priv->params.num_channels; i++) {
2200                 int err;
2201
2202                 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]);
2203                 if (err)
2204                         return (err);
2205         }
2206         return (0);
2207 }
2208
2209 static int
2210 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
2211 {
2212         struct mlx5_core_dev *mdev = priv->mdev;
2213         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
2214         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2215
2216         memset(in, 0, sizeof(in));
2217
2218         MLX5_SET(tisc, tisc, prio, tc);
2219         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
2220
2221         return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
2222 }
2223
2224 static void
2225 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
2226 {
2227         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2228 }
2229
2230 static int
2231 mlx5e_open_tises(struct mlx5e_priv *priv)
2232 {
2233         int num_tc = priv->num_tc;
2234         int err;
2235         int tc;
2236
2237         for (tc = 0; tc < num_tc; tc++) {
2238                 err = mlx5e_open_tis(priv, tc);
2239                 if (err)
2240                         goto err_close_tises;
2241         }
2242
2243         return (0);
2244
2245 err_close_tises:
2246         for (tc--; tc >= 0; tc--)
2247                 mlx5e_close_tis(priv, tc);
2248
2249         return (err);
2250 }
2251
2252 static void
2253 mlx5e_close_tises(struct mlx5e_priv *priv)
2254 {
2255         int num_tc = priv->num_tc;
2256         int tc;
2257
2258         for (tc = 0; tc < num_tc; tc++)
2259                 mlx5e_close_tis(priv, tc);
2260 }
2261
2262 static int
2263 mlx5e_open_rqt(struct mlx5e_priv *priv)
2264 {
2265         struct mlx5_core_dev *mdev = priv->mdev;
2266         u32 *in;
2267         u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
2268         void *rqtc;
2269         int inlen;
2270         int err;
2271         int sz;
2272         int i;
2273
2274         sz = 1 << priv->params.rx_hash_log_tbl_sz;
2275
2276         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2277         in = mlx5_vzalloc(inlen);
2278         if (in == NULL)
2279                 return (-ENOMEM);
2280         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2281
2282         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2283         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2284
2285         for (i = 0; i < sz; i++) {
2286                 int ix = i;
2287 #ifdef RSS
2288                 ix = rss_get_indirection_to_bucket(ix);
2289 #endif
2290                 /* ensure we don't overflow */
2291                 ix %= priv->params.num_channels;
2292
2293                 /* apply receive side scaling stride, if any */
2294                 ix -= ix % (int)priv->params.channels_rsss;
2295
2296                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn);
2297         }
2298
2299         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
2300
2301         err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
2302         if (!err)
2303                 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
2304
2305         kvfree(in);
2306
2307         return (err);
2308 }
2309
2310 static void
2311 mlx5e_close_rqt(struct mlx5e_priv *priv)
2312 {
2313         u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0};
2314         u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0};
2315
2316         MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
2317         MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
2318
2319         mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out));
2320 }
2321
2322 static void
2323 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
2324 {
2325         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2326         __be32 *hkey;
2327
2328         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2329
2330 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2331
2332 #define MLX5_HASH_IP     (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2333                           MLX5_HASH_FIELD_SEL_DST_IP)
2334
2335 #define MLX5_HASH_ALL    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2336                           MLX5_HASH_FIELD_SEL_DST_IP   |\
2337                           MLX5_HASH_FIELD_SEL_L4_SPORT |\
2338                           MLX5_HASH_FIELD_SEL_L4_DPORT)
2339
2340 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2341                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2342                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2343
2344         if (priv->params.hw_lro_en) {
2345                 MLX5_SET(tirc, tirc, lro_enable_mask,
2346                     MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2347                     MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2348                 MLX5_SET(tirc, tirc, lro_max_msg_sz,
2349                     (priv->params.lro_wqe_sz -
2350                     ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2351                 /* TODO: add the option to choose timer value dynamically */
2352                 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
2353                     MLX5_CAP_ETH(priv->mdev,
2354                     lro_timer_supported_periods[2]));
2355         }
2356
2357         /* setup parameters for hashing TIR type, if any */
2358         switch (tt) {
2359         case MLX5E_TT_ANY:
2360                 MLX5_SET(tirc, tirc, disp_type,
2361                     MLX5_TIRC_DISP_TYPE_DIRECT);
2362                 MLX5_SET(tirc, tirc, inline_rqn,
2363                     priv->channel[0].rq.rqn);
2364                 break;
2365         default:
2366                 MLX5_SET(tirc, tirc, disp_type,
2367                     MLX5_TIRC_DISP_TYPE_INDIRECT);
2368                 MLX5_SET(tirc, tirc, indirect_table,
2369                     priv->rqtn);
2370                 MLX5_SET(tirc, tirc, rx_hash_fn,
2371                     MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
2372                 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
2373 #ifdef RSS
2374                 /*
2375                  * The FreeBSD RSS implementation does currently not
2376                  * support symmetric Toeplitz hashes:
2377                  */
2378                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
2379                 rss_getkey((uint8_t *)hkey);
2380 #else
2381                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2382                 hkey[0] = cpu_to_be32(0xD181C62C);
2383                 hkey[1] = cpu_to_be32(0xF7F4DB5B);
2384                 hkey[2] = cpu_to_be32(0x1983A2FC);
2385                 hkey[3] = cpu_to_be32(0x943E1ADB);
2386                 hkey[4] = cpu_to_be32(0xD9389E6B);
2387                 hkey[5] = cpu_to_be32(0xD1039C2C);
2388                 hkey[6] = cpu_to_be32(0xA74499AD);
2389                 hkey[7] = cpu_to_be32(0x593D56D9);
2390                 hkey[8] = cpu_to_be32(0xF3253C06);
2391                 hkey[9] = cpu_to_be32(0x2ADC1FFC);
2392 #endif
2393                 break;
2394         }
2395
2396         switch (tt) {
2397         case MLX5E_TT_IPV4_TCP:
2398                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2399                     MLX5_L3_PROT_TYPE_IPV4);
2400                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2401                     MLX5_L4_PROT_TYPE_TCP);
2402 #ifdef RSS
2403                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2404                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2405                             MLX5_HASH_IP);
2406                 } else
2407 #endif
2408                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2409                     MLX5_HASH_ALL);
2410                 break;
2411
2412         case MLX5E_TT_IPV6_TCP:
2413                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2414                     MLX5_L3_PROT_TYPE_IPV6);
2415                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2416                     MLX5_L4_PROT_TYPE_TCP);
2417 #ifdef RSS
2418                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2419                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2420                             MLX5_HASH_IP);
2421                 } else
2422 #endif
2423                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2424                     MLX5_HASH_ALL);
2425                 break;
2426
2427         case MLX5E_TT_IPV4_UDP:
2428                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2429                     MLX5_L3_PROT_TYPE_IPV4);
2430                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2431                     MLX5_L4_PROT_TYPE_UDP);
2432 #ifdef RSS
2433                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2434                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2435                             MLX5_HASH_IP);
2436                 } else
2437 #endif
2438                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2439                     MLX5_HASH_ALL);
2440                 break;
2441
2442         case MLX5E_TT_IPV6_UDP:
2443                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2444                     MLX5_L3_PROT_TYPE_IPV6);
2445                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2446                     MLX5_L4_PROT_TYPE_UDP);
2447 #ifdef RSS
2448                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2449                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2450                             MLX5_HASH_IP);
2451                 } else
2452 #endif
2453                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2454                     MLX5_HASH_ALL);
2455                 break;
2456
2457         case MLX5E_TT_IPV4_IPSEC_AH:
2458                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2459                     MLX5_L3_PROT_TYPE_IPV4);
2460                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2461                     MLX5_HASH_IP_IPSEC_SPI);
2462                 break;
2463
2464         case MLX5E_TT_IPV6_IPSEC_AH:
2465                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2466                     MLX5_L3_PROT_TYPE_IPV6);
2467                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2468                     MLX5_HASH_IP_IPSEC_SPI);
2469                 break;
2470
2471         case MLX5E_TT_IPV4_IPSEC_ESP:
2472                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2473                     MLX5_L3_PROT_TYPE_IPV4);
2474                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2475                     MLX5_HASH_IP_IPSEC_SPI);
2476                 break;
2477
2478         case MLX5E_TT_IPV6_IPSEC_ESP:
2479                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2480                     MLX5_L3_PROT_TYPE_IPV6);
2481                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2482                     MLX5_HASH_IP_IPSEC_SPI);
2483                 break;
2484
2485         case MLX5E_TT_IPV4:
2486                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2487                     MLX5_L3_PROT_TYPE_IPV4);
2488                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2489                     MLX5_HASH_IP);
2490                 break;
2491
2492         case MLX5E_TT_IPV6:
2493                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2494                     MLX5_L3_PROT_TYPE_IPV6);
2495                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2496                     MLX5_HASH_IP);
2497                 break;
2498
2499         default:
2500                 break;
2501         }
2502 }
2503
2504 static int
2505 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2506 {
2507         struct mlx5_core_dev *mdev = priv->mdev;
2508         u32 *in;
2509         void *tirc;
2510         int inlen;
2511         int err;
2512
2513         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2514         in = mlx5_vzalloc(inlen);
2515         if (in == NULL)
2516                 return (-ENOMEM);
2517         tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2518
2519         mlx5e_build_tir_ctx(priv, tirc, tt);
2520
2521         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2522
2523         kvfree(in);
2524
2525         return (err);
2526 }
2527
2528 static void
2529 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2530 {
2531         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2532 }
2533
2534 static int
2535 mlx5e_open_tirs(struct mlx5e_priv *priv)
2536 {
2537         int err;
2538         int i;
2539
2540         for (i = 0; i < MLX5E_NUM_TT; i++) {
2541                 err = mlx5e_open_tir(priv, i);
2542                 if (err)
2543                         goto err_close_tirs;
2544         }
2545
2546         return (0);
2547
2548 err_close_tirs:
2549         for (i--; i >= 0; i--)
2550                 mlx5e_close_tir(priv, i);
2551
2552         return (err);
2553 }
2554
2555 static void
2556 mlx5e_close_tirs(struct mlx5e_priv *priv)
2557 {
2558         int i;
2559
2560         for (i = 0; i < MLX5E_NUM_TT; i++)
2561                 mlx5e_close_tir(priv, i);
2562 }
2563
2564 /*
2565  * SW MTU does not include headers,
2566  * HW MTU includes all headers and checksums.
2567  */
2568 static int
2569 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2570 {
2571         struct mlx5e_priv *priv = ifp->if_softc;
2572         struct mlx5_core_dev *mdev = priv->mdev;
2573         int hw_mtu;
2574         int err;
2575
2576         hw_mtu = MLX5E_SW2HW_MTU(sw_mtu);
2577
2578         err = mlx5_set_port_mtu(mdev, hw_mtu);
2579         if (err) {
2580                 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n",
2581                     __func__, sw_mtu, err);
2582                 return (err);
2583         }
2584
2585         /* Update vport context MTU */
2586         err = mlx5_set_vport_mtu(mdev, hw_mtu);
2587         if (err) {
2588                 if_printf(ifp, "%s: Failed updating vport context with MTU size, err=%d\n",
2589                     __func__, err);
2590         }
2591
2592         ifp->if_mtu = sw_mtu;
2593
2594         err = mlx5_query_vport_mtu(mdev, &hw_mtu);
2595         if (err || !hw_mtu) {
2596                 /* fallback to port oper mtu */
2597                 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2598         }
2599         if (err) {
2600                 if_printf(ifp, "Query port MTU, after setting new "
2601                     "MTU value, failed\n");
2602                 return (err);
2603         } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
2604                 err = -E2BIG,
2605                 if_printf(ifp, "Port MTU %d is smaller than "
2606                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2607         } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
2608                 err = -EINVAL;
2609                 if_printf(ifp, "Port MTU %d is bigger than "
2610                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2611         }
2612         priv->params_ethtool.hw_mtu = hw_mtu;
2613
2614         return (err);
2615 }
2616
2617 int
2618 mlx5e_open_locked(struct ifnet *ifp)
2619 {
2620         struct mlx5e_priv *priv = ifp->if_softc;
2621         int err;
2622         u16 set_id;
2623
2624         /* check if already opened */
2625         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2626                 return (0);
2627
2628 #ifdef RSS
2629         if (rss_getnumbuckets() > priv->params.num_channels) {
2630                 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than "
2631                     "channels(%u) available\n", rss_getnumbuckets(),
2632                     priv->params.num_channels);
2633         }
2634 #endif
2635         err = mlx5e_open_tises(priv);
2636         if (err) {
2637                 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n",
2638                     __func__, err);
2639                 return (err);
2640         }
2641         err = mlx5_vport_alloc_q_counter(priv->mdev,
2642             MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
2643         if (err) {
2644                 if_printf(priv->ifp,
2645                     "%s: mlx5_vport_alloc_q_counter failed: %d\n",
2646                     __func__, err);
2647                 goto err_close_tises;
2648         }
2649         /* store counter set ID */
2650         priv->counter_set_id = set_id;
2651
2652         err = mlx5e_open_channels(priv);
2653         if (err) {
2654                 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n",
2655                     __func__, err);
2656                 goto err_dalloc_q_counter;
2657         }
2658         err = mlx5e_open_rqt(priv);
2659         if (err) {
2660                 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n",
2661                     __func__, err);
2662                 goto err_close_channels;
2663         }
2664         err = mlx5e_open_tirs(priv);
2665         if (err) {
2666                 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n",
2667                     __func__, err);
2668                 goto err_close_rqls;
2669         }
2670         err = mlx5e_open_flow_table(priv);
2671         if (err) {
2672                 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n",
2673                     __func__, err);
2674                 goto err_close_tirs;
2675         }
2676         err = mlx5e_add_all_vlan_rules(priv);
2677         if (err) {
2678                 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
2679                     __func__, err);
2680                 goto err_close_flow_table;
2681         }
2682         set_bit(MLX5E_STATE_OPENED, &priv->state);
2683
2684         mlx5e_update_carrier(priv);
2685         mlx5e_set_rx_mode_core(priv);
2686
2687         return (0);
2688
2689 err_close_flow_table:
2690         mlx5e_close_flow_table(priv);
2691
2692 err_close_tirs:
2693         mlx5e_close_tirs(priv);
2694
2695 err_close_rqls:
2696         mlx5e_close_rqt(priv);
2697
2698 err_close_channels:
2699         mlx5e_close_channels(priv);
2700
2701 err_dalloc_q_counter:
2702         mlx5_vport_dealloc_q_counter(priv->mdev,
2703             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2704
2705 err_close_tises:
2706         mlx5e_close_tises(priv);
2707
2708         return (err);
2709 }
2710
2711 static void
2712 mlx5e_open(void *arg)
2713 {
2714         struct mlx5e_priv *priv = arg;
2715
2716         PRIV_LOCK(priv);
2717         if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
2718                 if_printf(priv->ifp,
2719                     "%s: Setting port status to up failed\n",
2720                     __func__);
2721
2722         mlx5e_open_locked(priv->ifp);
2723         priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
2724         PRIV_UNLOCK(priv);
2725 }
2726
2727 int
2728 mlx5e_close_locked(struct ifnet *ifp)
2729 {
2730         struct mlx5e_priv *priv = ifp->if_softc;
2731
2732         /* check if already closed */
2733         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2734                 return (0);
2735
2736         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2737
2738         mlx5e_set_rx_mode_core(priv);
2739         mlx5e_del_all_vlan_rules(priv);
2740         if_link_state_change(priv->ifp, LINK_STATE_DOWN);
2741         mlx5e_close_flow_table(priv);
2742         mlx5e_close_tirs(priv);
2743         mlx5e_close_rqt(priv);
2744         mlx5e_close_channels(priv);
2745         mlx5_vport_dealloc_q_counter(priv->mdev,
2746             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2747         mlx5e_close_tises(priv);
2748
2749         return (0);
2750 }
2751
2752 #if (__FreeBSD_version >= 1100000)
2753 static uint64_t
2754 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
2755 {
2756         struct mlx5e_priv *priv = ifp->if_softc;
2757         u64 retval;
2758
2759         /* PRIV_LOCK(priv); XXX not allowed */
2760         switch (cnt) {
2761         case IFCOUNTER_IPACKETS:
2762                 retval = priv->stats.vport.rx_packets;
2763                 break;
2764         case IFCOUNTER_IERRORS:
2765                 retval = priv->stats.pport.in_range_len_errors +
2766                     priv->stats.pport.out_of_range_len +
2767                     priv->stats.pport.too_long_errors +
2768                     priv->stats.pport.check_seq_err +
2769                     priv->stats.pport.alignment_err;
2770                 break;
2771         case IFCOUNTER_IQDROPS:
2772                 retval = priv->stats.vport.rx_out_of_buffer;
2773                 break;
2774         case IFCOUNTER_OPACKETS:
2775                 retval = priv->stats.vport.tx_packets;
2776                 break;
2777         case IFCOUNTER_OERRORS:
2778                 retval = priv->stats.port_stats_debug.out_discards;
2779                 break;
2780         case IFCOUNTER_IBYTES:
2781                 retval = priv->stats.vport.rx_bytes;
2782                 break;
2783         case IFCOUNTER_OBYTES:
2784                 retval = priv->stats.vport.tx_bytes;
2785                 break;
2786         case IFCOUNTER_IMCASTS:
2787                 retval = priv->stats.vport.rx_multicast_packets;
2788                 break;
2789         case IFCOUNTER_OMCASTS:
2790                 retval = priv->stats.vport.tx_multicast_packets;
2791                 break;
2792         case IFCOUNTER_OQDROPS:
2793                 retval = priv->stats.vport.tx_queue_dropped;
2794                 break;
2795         case IFCOUNTER_COLLISIONS:
2796                 retval = priv->stats.pport.collisions;
2797                 break;
2798         default:
2799                 retval = if_get_counter_default(ifp, cnt);
2800                 break;
2801         }
2802         /* PRIV_UNLOCK(priv); XXX not allowed */
2803         return (retval);
2804 }
2805 #endif
2806
2807 static void
2808 mlx5e_set_rx_mode(struct ifnet *ifp)
2809 {
2810         struct mlx5e_priv *priv = ifp->if_softc;
2811
2812         queue_work(priv->wq, &priv->set_rx_mode_work);
2813 }
2814
2815 static int
2816 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2817 {
2818         struct mlx5e_priv *priv;
2819         struct ifreq *ifr;
2820         struct ifi2creq i2c;
2821         int error = 0;
2822         int mask = 0;
2823         int size_read = 0;
2824         int module_status;
2825         int module_num;
2826         int max_mtu;
2827         uint8_t read_addr;
2828
2829         priv = ifp->if_softc;
2830
2831         /* check if detaching */
2832         if (priv == NULL || priv->gone != 0)
2833                 return (ENXIO);
2834
2835         switch (command) {
2836         case SIOCSIFMTU:
2837                 ifr = (struct ifreq *)data;
2838
2839                 PRIV_LOCK(priv);
2840                 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
2841
2842                 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
2843                     ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
2844                         int was_opened;
2845
2846                         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2847                         if (was_opened)
2848                                 mlx5e_close_locked(ifp);
2849
2850                         /* set new MTU */
2851                         mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
2852
2853                         if (was_opened)
2854                                 mlx5e_open_locked(ifp);
2855                 } else {
2856                         error = EINVAL;
2857                         if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n",
2858                             MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
2859                 }
2860                 PRIV_UNLOCK(priv);
2861                 break;
2862         case SIOCSIFFLAGS:
2863                 if ((ifp->if_flags & IFF_UP) &&
2864                     (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2865                         mlx5e_set_rx_mode(ifp);
2866                         break;
2867                 }
2868                 PRIV_LOCK(priv);
2869                 if (ifp->if_flags & IFF_UP) {
2870                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2871                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2872                                         mlx5e_open_locked(ifp);
2873                                 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2874                                 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
2875                         }
2876                 } else {
2877                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2878                                 mlx5_set_port_status(priv->mdev,
2879                                     MLX5_PORT_DOWN);
2880                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2881                                         mlx5e_close_locked(ifp);
2882                                 mlx5e_update_carrier(priv);
2883                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2884                         }
2885                 }
2886                 PRIV_UNLOCK(priv);
2887                 break;
2888         case SIOCADDMULTI:
2889         case SIOCDELMULTI:
2890                 mlx5e_set_rx_mode(ifp);
2891                 break;
2892         case SIOCSIFMEDIA:
2893         case SIOCGIFMEDIA:
2894         case SIOCGIFXMEDIA:
2895                 ifr = (struct ifreq *)data;
2896                 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
2897                 break;
2898         case SIOCSIFCAP:
2899                 ifr = (struct ifreq *)data;
2900                 PRIV_LOCK(priv);
2901                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2902
2903                 if (mask & IFCAP_TXCSUM) {
2904                         ifp->if_capenable ^= IFCAP_TXCSUM;
2905                         ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2906
2907                         if (IFCAP_TSO4 & ifp->if_capenable &&
2908                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2909                                 ifp->if_capenable &= ~IFCAP_TSO4;
2910                                 ifp->if_hwassist &= ~CSUM_IP_TSO;
2911                                 if_printf(ifp,
2912                                     "tso4 disabled due to -txcsum.\n");
2913                         }
2914                 }
2915                 if (mask & IFCAP_TXCSUM_IPV6) {
2916                         ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
2917                         ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2918
2919                         if (IFCAP_TSO6 & ifp->if_capenable &&
2920                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2921                                 ifp->if_capenable &= ~IFCAP_TSO6;
2922                                 ifp->if_hwassist &= ~CSUM_IP6_TSO;
2923                                 if_printf(ifp,
2924                                     "tso6 disabled due to -txcsum6.\n");
2925                         }
2926                 }
2927                 if (mask & IFCAP_RXCSUM)
2928                         ifp->if_capenable ^= IFCAP_RXCSUM;
2929                 if (mask & IFCAP_RXCSUM_IPV6)
2930                         ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
2931                 if (mask & IFCAP_TSO4) {
2932                         if (!(IFCAP_TSO4 & ifp->if_capenable) &&
2933                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2934                                 if_printf(ifp, "enable txcsum first.\n");
2935                                 error = EAGAIN;
2936                                 goto out;
2937                         }
2938                         ifp->if_capenable ^= IFCAP_TSO4;
2939                         ifp->if_hwassist ^= CSUM_IP_TSO;
2940                 }
2941                 if (mask & IFCAP_TSO6) {
2942                         if (!(IFCAP_TSO6 & ifp->if_capenable) &&
2943                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2944                                 if_printf(ifp, "enable txcsum6 first.\n");
2945                                 error = EAGAIN;
2946                                 goto out;
2947                         }
2948                         ifp->if_capenable ^= IFCAP_TSO6;
2949                         ifp->if_hwassist ^= CSUM_IP6_TSO;
2950                 }
2951                 if (mask & IFCAP_VLAN_HWFILTER) {
2952                         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
2953                                 mlx5e_disable_vlan_filter(priv);
2954                         else
2955                                 mlx5e_enable_vlan_filter(priv);
2956
2957                         ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
2958                 }
2959                 if (mask & IFCAP_VLAN_HWTAGGING)
2960                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2961                 if (mask & IFCAP_WOL_MAGIC)
2962                         ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2963
2964                 VLAN_CAPABILITIES(ifp);
2965                 /* turn off LRO means also turn of HW LRO - if it's on */
2966                 if (mask & IFCAP_LRO) {
2967                         int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2968                         bool need_restart = false;
2969
2970                         ifp->if_capenable ^= IFCAP_LRO;
2971
2972                         /* figure out if updating HW LRO is needed */
2973                         if (!(ifp->if_capenable & IFCAP_LRO)) {
2974                                 if (priv->params.hw_lro_en) {
2975                                         priv->params.hw_lro_en = false;
2976                                         need_restart = true;
2977                                 }
2978                         } else {
2979                                 if (priv->params.hw_lro_en == false &&
2980                                     priv->params_ethtool.hw_lro != 0) {
2981                                         priv->params.hw_lro_en = true;
2982                                         need_restart = true;
2983                                 }
2984                         }
2985                         if (was_opened && need_restart) {
2986                                 mlx5e_close_locked(ifp);
2987                                 mlx5e_open_locked(ifp);
2988                         }
2989                 }
2990                 if (mask & IFCAP_HWRXTSTMP) {
2991                         ifp->if_capenable ^= IFCAP_HWRXTSTMP;
2992                         if (ifp->if_capenable & IFCAP_HWRXTSTMP) {
2993                                 if (priv->clbr_done == 0)
2994                                         mlx5e_reset_calibration_callout(priv);
2995                         } else {
2996                                 callout_drain(&priv->tstmp_clbr);
2997                                 priv->clbr_done = 0;
2998                         }
2999                 }
3000 out:
3001                 PRIV_UNLOCK(priv);
3002                 break;
3003
3004         case SIOCGI2C:
3005                 ifr = (struct ifreq *)data;
3006
3007                 /*
3008                  * Copy from the user-space address ifr_data to the
3009                  * kernel-space address i2c
3010                  */
3011                 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
3012                 if (error)
3013                         break;
3014
3015                 if (i2c.len > sizeof(i2c.data)) {
3016                         error = EINVAL;
3017                         break;
3018                 }
3019
3020                 PRIV_LOCK(priv);
3021                 /* Get module_num which is required for the query_eeprom */
3022                 error = mlx5_query_module_num(priv->mdev, &module_num);
3023                 if (error) {
3024                         if_printf(ifp, "Query module num failed, eeprom "
3025                             "reading is not supported\n");
3026                         error = EINVAL;
3027                         goto err_i2c;
3028                 }
3029                 /* Check if module is present before doing an access */
3030                 module_status = mlx5_query_module_status(priv->mdev, module_num);
3031                 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED &&
3032                     module_status != MLX5_MODULE_STATUS_PLUGGED_DISABLED) {
3033                         error = EINVAL;
3034                         goto err_i2c;
3035                 }
3036                 /*
3037                  * Currently 0XA0 and 0xA2 are the only addresses permitted.
3038                  * The internal conversion is as follows:
3039                  */
3040                 if (i2c.dev_addr == 0xA0)
3041                         read_addr = MLX5E_I2C_ADDR_LOW;
3042                 else if (i2c.dev_addr == 0xA2)
3043                         read_addr = MLX5E_I2C_ADDR_HIGH;
3044                 else {
3045                         if_printf(ifp, "Query eeprom failed, "
3046                             "Invalid Address: %X\n", i2c.dev_addr);
3047                         error = EINVAL;
3048                         goto err_i2c;
3049                 }
3050                 error = mlx5_query_eeprom(priv->mdev,
3051                     read_addr, MLX5E_EEPROM_LOW_PAGE,
3052                     (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
3053                     (uint32_t *)i2c.data, &size_read);
3054                 if (error) {
3055                         if_printf(ifp, "Query eeprom failed, eeprom "
3056                             "reading is not supported\n");
3057                         error = EINVAL;
3058                         goto err_i2c;
3059                 }
3060
3061                 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
3062                         error = mlx5_query_eeprom(priv->mdev,
3063                             read_addr, MLX5E_EEPROM_LOW_PAGE,
3064                             (uint32_t)(i2c.offset + size_read),
3065                             (uint32_t)(i2c.len - size_read), module_num,
3066                             (uint32_t *)(i2c.data + size_read), &size_read);
3067                 }
3068                 if (error) {
3069                         if_printf(ifp, "Query eeprom failed, eeprom "
3070                             "reading is not supported\n");
3071                         error = EINVAL;
3072                         goto err_i2c;
3073                 }
3074
3075                 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
3076 err_i2c:
3077                 PRIV_UNLOCK(priv);
3078                 break;
3079
3080         default:
3081                 error = ether_ioctl(ifp, command, data);
3082                 break;
3083         }
3084         return (error);
3085 }
3086
3087 static int
3088 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3089 {
3090         /*
3091          * TODO: uncoment once FW really sets all these bits if
3092          * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
3093          * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
3094          * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
3095          * -ENOTSUPP;
3096          */
3097
3098         /* TODO: add more must-to-have features */
3099
3100         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3101                 return (-ENODEV);
3102
3103         return (0);
3104 }
3105
3106 static u16
3107 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3108 {
3109         uint32_t bf_buf_size = (1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U;
3110
3111         bf_buf_size -= sizeof(struct mlx5e_tx_wqe) - 2;
3112
3113         /* verify against driver hardware limit */
3114         if (bf_buf_size > MLX5E_MAX_TX_INLINE)
3115                 bf_buf_size = MLX5E_MAX_TX_INLINE;
3116
3117         return (bf_buf_size);
3118 }
3119
3120 static int
3121 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
3122     struct mlx5e_priv *priv,
3123     int num_comp_vectors)
3124 {
3125         int err;
3126
3127         /*
3128          * TODO: Consider link speed for setting "log_sq_size",
3129          * "log_rq_size" and "cq_moderation_xxx":
3130          */
3131         priv->params.log_sq_size =
3132             MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3133         priv->params.log_rq_size =
3134             MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3135         priv->params.rx_cq_moderation_usec =
3136             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3137             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
3138             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3139         priv->params.rx_cq_moderation_mode =
3140             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
3141         priv->params.rx_cq_moderation_pkts =
3142             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3143         priv->params.tx_cq_moderation_usec =
3144             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3145         priv->params.tx_cq_moderation_pkts =
3146             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3147         priv->params.min_rx_wqes =
3148             MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
3149         priv->params.rx_hash_log_tbl_sz =
3150             (order_base_2(num_comp_vectors) >
3151             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
3152             order_base_2(num_comp_vectors) :
3153             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
3154         priv->params.num_tc = 1;
3155         priv->params.default_vlan_prio = 0;
3156         priv->counter_set_id = -1;
3157         priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3158
3159         err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3160         if (err)
3161                 return (err);
3162
3163         /*
3164          * hw lro is currently defaulted to off. when it won't anymore we
3165          * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
3166          */
3167         priv->params.hw_lro_en = false;
3168         priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3169
3170         /*
3171          * CQE zipping is currently defaulted to off. when it won't
3172          * anymore we will consider the HW capability:
3173          * "!!MLX5_CAP_GEN(mdev, cqe_compression)"
3174          */
3175         priv->params.cqe_zipping_en = false;
3176
3177         priv->mdev = mdev;
3178         priv->params.num_channels = num_comp_vectors;
3179         priv->params.channels_rsss = 1;
3180         priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
3181         priv->queue_mapping_channel_mask =
3182             roundup_pow_of_two(num_comp_vectors) - 1;
3183         priv->num_tc = priv->params.num_tc;
3184         priv->default_vlan_prio = priv->params.default_vlan_prio;
3185
3186         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3187         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3188         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3189
3190         return (0);
3191 }
3192
3193 static int
3194 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
3195                   struct mlx5_core_mr *mkey)
3196 {
3197         struct ifnet *ifp = priv->ifp;
3198         struct mlx5_core_dev *mdev = priv->mdev;
3199         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3200         void *mkc;
3201         u32 *in;
3202         int err;
3203
3204         in = mlx5_vzalloc(inlen);
3205         if (in == NULL) {
3206                 if_printf(ifp, "%s: failed to allocate inbox\n", __func__);
3207                 return (-ENOMEM);
3208         }
3209
3210         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3211         MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA);
3212         MLX5_SET(mkc, mkc, lw, 1);
3213         MLX5_SET(mkc, mkc, lr, 1);
3214
3215         MLX5_SET(mkc, mkc, pd, pdn);
3216         MLX5_SET(mkc, mkc, length64, 1);
3217         MLX5_SET(mkc, mkc, qpn, 0xffffff);
3218
3219         err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
3220         if (err)
3221                 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n",
3222                     __func__, err);
3223
3224         kvfree(in);
3225         return (err);
3226 }
3227
3228 static const char *mlx5e_vport_stats_desc[] = {
3229         MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
3230 };
3231
3232 static const char *mlx5e_pport_stats_desc[] = {
3233         MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
3234 };
3235
3236 static void
3237 mlx5e_priv_mtx_init(struct mlx5e_priv *priv)
3238 {
3239         mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
3240         sx_init(&priv->state_lock, "mlx5state");
3241         callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
3242         MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
3243 }
3244
3245 static void
3246 mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv)
3247 {
3248         mtx_destroy(&priv->async_events_mtx);
3249         sx_destroy(&priv->state_lock);
3250 }
3251
3252 static int
3253 sysctl_firmware(SYSCTL_HANDLER_ARGS)
3254 {
3255         /*
3256          * %d.%d%.d the string format.
3257          * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
3258          * We need at most 5 chars to store that.
3259          * It also has: two "." and NULL at the end, which means we need 18
3260          * (5*3 + 3) chars at most.
3261          */
3262         char fw[18];
3263         struct mlx5e_priv *priv = arg1;
3264         int error;
3265
3266         snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
3267             fw_rev_sub(priv->mdev));
3268         error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
3269         return (error);
3270 }
3271
3272 static void
3273 mlx5e_disable_tx_dma(struct mlx5e_channel *ch)
3274 {
3275         int i;
3276
3277         for (i = 0; i < ch->num_tc; i++)
3278                 mlx5e_drain_sq(&ch->sq[i]);
3279 }
3280
3281 static void
3282 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq)
3283 {
3284
3285         sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP);
3286         sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8);
3287         mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
3288         sq->doorbell.d64 = 0;
3289 }
3290
3291 void
3292 mlx5e_resume_sq(struct mlx5e_sq *sq)
3293 {
3294         int err;
3295
3296         /* check if already enabled */
3297         if (READ_ONCE(sq->running) != 0)
3298                 return;
3299
3300         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR,
3301             MLX5_SQC_STATE_RST);
3302         if (err != 0) {
3303                 if_printf(sq->ifp,
3304                     "mlx5e_modify_sq() from ERR to RST failed: %d\n", err);
3305         }
3306
3307         sq->cc = 0;
3308         sq->pc = 0;
3309
3310         /* reset doorbell prior to moving from RST to RDY */
3311         mlx5e_reset_sq_doorbell_record(sq);
3312
3313         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST,
3314             MLX5_SQC_STATE_RDY);
3315         if (err != 0) {
3316                 if_printf(sq->ifp,
3317                     "mlx5e_modify_sq() from RST to RDY failed: %d\n", err);
3318         }
3319
3320         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
3321         WRITE_ONCE(sq->running, 1);
3322 }
3323
3324 static void
3325 mlx5e_enable_tx_dma(struct mlx5e_channel *ch)
3326 {
3327         int i;
3328
3329         for (i = 0; i < ch->num_tc; i++)
3330                 mlx5e_resume_sq(&ch->sq[i]);
3331 }
3332
3333 static void
3334 mlx5e_disable_rx_dma(struct mlx5e_channel *ch)
3335 {
3336         struct mlx5e_rq *rq = &ch->rq;
3337         int err;
3338
3339         mtx_lock(&rq->mtx);
3340         rq->enabled = 0;
3341         callout_stop(&rq->watchdog);
3342         mtx_unlock(&rq->mtx);
3343
3344         callout_drain(&rq->watchdog);
3345
3346         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
3347         if (err != 0) {
3348                 if_printf(rq->ifp,
3349                     "mlx5e_modify_rq() from RDY to RST failed: %d\n", err);
3350         }
3351
3352         while (!mlx5_wq_ll_is_empty(&rq->wq)) {
3353                 msleep(1);
3354                 rq->cq.mcq.comp(&rq->cq.mcq);
3355         }
3356
3357         /*
3358          * Transitioning into RST state will allow the FW to track less ERR state queues,
3359          * thus reducing the recv queue flushing time
3360          */
3361         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST);
3362         if (err != 0) {
3363                 if_printf(rq->ifp,
3364                     "mlx5e_modify_rq() from ERR to RST failed: %d\n", err);
3365         }
3366 }
3367
3368 static void
3369 mlx5e_enable_rx_dma(struct mlx5e_channel *ch)
3370 {
3371         struct mlx5e_rq *rq = &ch->rq;
3372         int err;
3373
3374         rq->wq.wqe_ctr = 0;
3375         mlx5_wq_ll_update_db_record(&rq->wq);
3376         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3377         if (err != 0) {
3378                 if_printf(rq->ifp,
3379                     "mlx5e_modify_rq() from RST to RDY failed: %d\n", err);
3380         }
3381
3382         rq->enabled = 1;
3383
3384         rq->cq.mcq.comp(&rq->cq.mcq);
3385 }
3386
3387 void
3388 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value)
3389 {
3390         int i;
3391
3392         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3393                 return;
3394
3395         for (i = 0; i < priv->params.num_channels; i++) {
3396                 if (value)
3397                         mlx5e_disable_tx_dma(&priv->channel[i]);
3398                 else
3399                         mlx5e_enable_tx_dma(&priv->channel[i]);
3400         }
3401 }
3402
3403 void
3404 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value)
3405 {
3406         int i;
3407
3408         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3409                 return;
3410
3411         for (i = 0; i < priv->params.num_channels; i++) {
3412                 if (value)
3413                         mlx5e_disable_rx_dma(&priv->channel[i]);
3414                 else
3415                         mlx5e_enable_rx_dma(&priv->channel[i]);
3416         }
3417 }
3418
3419 static void
3420 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
3421 {
3422         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3423             OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
3424             sysctl_firmware, "A", "HCA firmware version");
3425
3426         SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3427             OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
3428             "Board ID");
3429 }
3430
3431 static int
3432 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3433 {
3434         struct mlx5e_priv *priv = arg1;
3435         uint8_t temp[MLX5E_MAX_PRIORITY];
3436         uint32_t tx_pfc;
3437         int err;
3438         int i;
3439
3440         PRIV_LOCK(priv);
3441
3442         tx_pfc = priv->params.tx_priority_flow_control;
3443
3444         for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3445                 temp[i] = (tx_pfc >> i) & 1;
3446
3447         err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3448         if (err || !req->newptr)
3449                 goto done;
3450         err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3451         if (err)
3452                 goto done;
3453
3454         priv->params.tx_priority_flow_control = 0;
3455
3456         /* range check input value */
3457         for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3458                 if (temp[i] > 1) {
3459                         err = ERANGE;
3460                         goto done;
3461                 }
3462                 priv->params.tx_priority_flow_control |= (temp[i] << i);
3463         }
3464
3465         /* check if update is required */
3466         if (tx_pfc != priv->params.tx_priority_flow_control)
3467                 err = -mlx5e_set_port_pfc(priv);
3468 done:
3469         if (err != 0)
3470                 priv->params.tx_priority_flow_control= tx_pfc;
3471         PRIV_UNLOCK(priv);
3472
3473         return (err);
3474 }
3475
3476 static int
3477 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3478 {
3479         struct mlx5e_priv *priv = arg1;
3480         uint8_t temp[MLX5E_MAX_PRIORITY];
3481         uint32_t rx_pfc;
3482         int err;
3483         int i;
3484
3485         PRIV_LOCK(priv);
3486
3487         rx_pfc = priv->params.rx_priority_flow_control;
3488
3489         for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3490                 temp[i] = (rx_pfc >> i) & 1;
3491
3492         err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3493         if (err || !req->newptr)
3494                 goto done;
3495         err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3496         if (err)
3497                 goto done;
3498
3499         priv->params.rx_priority_flow_control = 0;
3500
3501         /* range check input value */
3502         for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3503                 if (temp[i] > 1) {
3504                         err = ERANGE;
3505                         goto done;
3506                 }
3507                 priv->params.rx_priority_flow_control |= (temp[i] << i);
3508         }
3509
3510         /* check if update is required */
3511         if (rx_pfc != priv->params.rx_priority_flow_control)
3512                 err = -mlx5e_set_port_pfc(priv);
3513 done:
3514         if (err != 0)
3515                 priv->params.rx_priority_flow_control= rx_pfc;
3516         PRIV_UNLOCK(priv);
3517
3518         return (err);
3519 }
3520
3521 static void
3522 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
3523 {
3524 #if (__FreeBSD_version < 1100000)
3525         char path[96];
3526 #endif
3527         int error;
3528
3529         /* enable pauseframes by default */
3530         priv->params.tx_pauseframe_control = 1;
3531         priv->params.rx_pauseframe_control = 1;
3532
3533         /* disable ports flow control, PFC, by default */
3534         priv->params.tx_priority_flow_control = 0;
3535         priv->params.rx_priority_flow_control = 0;
3536
3537 #if (__FreeBSD_version < 1100000)
3538         /* compute path for sysctl */
3539         snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
3540             device_get_unit(priv->mdev->pdev->dev.bsddev));
3541
3542         /* try to fetch tunable, if any */
3543         TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
3544
3545         /* compute path for sysctl */
3546         snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
3547             device_get_unit(priv->mdev->pdev->dev.bsddev));
3548
3549         /* try to fetch tunable, if any */
3550         TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
3551 #endif
3552
3553         /* register pauseframe SYSCTLs */
3554         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3555             OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
3556             &priv->params.tx_pauseframe_control, 0,
3557             "Set to enable TX pause frames. Clear to disable.");
3558
3559         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3560             OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
3561             &priv->params.rx_pauseframe_control, 0,
3562             "Set to enable RX pause frames. Clear to disable.");
3563
3564         /* register priority flow control, PFC, SYSCTLs */
3565         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3566             OID_AUTO, "tx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
3567             CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_tx_priority_flow_control, "CU",
3568             "Set to enable TX ports flow control frames for priorities 0..7. Clear to disable.");
3569
3570         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3571             OID_AUTO, "rx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
3572             CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_rx_priority_flow_control, "CU",
3573             "Set to enable RX ports flow control frames for priorities 0..7. Clear to disable.");
3574
3575         PRIV_LOCK(priv);
3576
3577         /* range check */
3578         priv->params.tx_pauseframe_control =
3579             priv->params.tx_pauseframe_control ? 1 : 0;
3580         priv->params.rx_pauseframe_control =
3581             priv->params.rx_pauseframe_control ? 1 : 0;
3582
3583         /* update firmware */
3584         error = mlx5e_set_port_pause_and_pfc(priv);
3585         if (error == -EINVAL) {
3586                 if_printf(priv->ifp,
3587                     "Global pauseframes must be disabled before enabling PFC.\n");
3588                 priv->params.rx_priority_flow_control = 0;
3589                 priv->params.tx_priority_flow_control = 0;
3590
3591                 /* update firmware */
3592                 (void) mlx5e_set_port_pause_and_pfc(priv);
3593         }
3594         PRIV_UNLOCK(priv);
3595 }
3596
3597 static int
3598 mlx5e_ul_snd_tag_alloc(struct ifnet *ifp,
3599     union if_snd_tag_alloc_params *params,
3600     struct m_snd_tag **ppmt)
3601 {
3602         struct mlx5e_priv *priv;
3603         struct mlx5e_channel *pch;
3604
3605         priv = ifp->if_softc;
3606
3607         if (unlikely(priv->gone || params->hdr.flowtype == M_HASHTYPE_NONE)) {
3608                 return (EOPNOTSUPP);
3609         } else {
3610                 /* keep this code synced with mlx5e_select_queue() */
3611                 u32 ch = priv->params.num_channels;
3612 #ifdef RSS
3613                 u32 temp;
3614
3615                 if (rss_hash2bucket(params->hdr.flowid,
3616                     params->hdr.flowtype, &temp) == 0)
3617                         ch = temp % ch;
3618                 else
3619 #endif
3620                         ch = (params->hdr.flowid % 128) % ch;
3621
3622                 /*
3623                  * NOTE: The channels array is only freed at detach
3624                  * and it safe to return a pointer to the send tag
3625                  * inside the channels structure as long as we
3626                  * reference the priv.
3627                  */
3628                 pch = priv->channel + ch;
3629
3630                 /* check if send queue is not running */
3631                 if (unlikely(pch->sq[0].running == 0))
3632                         return (ENXIO);
3633                 mlx5e_ref_channel(priv);
3634                 *ppmt = &pch->tag.m_snd_tag;
3635                 return (0);
3636         }
3637 }
3638
3639 static int
3640 mlx5e_ul_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
3641 {
3642         struct mlx5e_channel *pch =
3643             container_of(pmt, struct mlx5e_channel, tag.m_snd_tag);
3644
3645         params->unlimited.max_rate = -1ULL;
3646         params->unlimited.queue_level = mlx5e_sq_queue_level(&pch->sq[0]);
3647         return (0);
3648 }
3649
3650 static void
3651 mlx5e_ul_snd_tag_free(struct m_snd_tag *pmt)
3652 {
3653         struct mlx5e_channel *pch =
3654             container_of(pmt, struct mlx5e_channel, tag.m_snd_tag);
3655
3656         mlx5e_unref_channel(pch->priv);
3657 }
3658
3659 static int
3660 mlx5e_snd_tag_alloc(struct ifnet *ifp,
3661     union if_snd_tag_alloc_params *params,
3662     struct m_snd_tag **ppmt)
3663 {
3664
3665         switch (params->hdr.type) {
3666 #ifdef RATELIMIT
3667         case IF_SND_TAG_TYPE_RATE_LIMIT:
3668                 return (mlx5e_rl_snd_tag_alloc(ifp, params, ppmt));
3669 #endif
3670         case IF_SND_TAG_TYPE_UNLIMITED:
3671                 return (mlx5e_ul_snd_tag_alloc(ifp, params, ppmt));
3672         default:
3673                 return (EOPNOTSUPP);
3674         }
3675 }
3676
3677 static int
3678 mlx5e_snd_tag_modify(struct m_snd_tag *pmt, union if_snd_tag_modify_params *params)
3679 {
3680         struct mlx5e_snd_tag *tag =
3681             container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
3682
3683         switch (tag->type) {
3684 #ifdef RATELIMIT
3685         case IF_SND_TAG_TYPE_RATE_LIMIT:
3686                 return (mlx5e_rl_snd_tag_modify(pmt, params));
3687 #endif
3688         case IF_SND_TAG_TYPE_UNLIMITED:
3689         default:
3690                 return (EOPNOTSUPP);
3691         }
3692 }
3693
3694 static int
3695 mlx5e_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
3696 {
3697         struct mlx5e_snd_tag *tag =
3698             container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
3699
3700         switch (tag->type) {
3701 #ifdef RATELIMIT
3702         case IF_SND_TAG_TYPE_RATE_LIMIT:
3703                 return (mlx5e_rl_snd_tag_query(pmt, params));
3704 #endif
3705         case IF_SND_TAG_TYPE_UNLIMITED:
3706                 return (mlx5e_ul_snd_tag_query(pmt, params));
3707         default:
3708                 return (EOPNOTSUPP);
3709         }
3710 }
3711
3712 static void
3713 mlx5e_snd_tag_free(struct m_snd_tag *pmt)
3714 {
3715         struct mlx5e_snd_tag *tag =
3716             container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
3717
3718         switch (tag->type) {
3719 #ifdef RATELIMIT
3720         case IF_SND_TAG_TYPE_RATE_LIMIT:
3721                 mlx5e_rl_snd_tag_free(pmt);
3722                 break;
3723 #endif
3724         case IF_SND_TAG_TYPE_UNLIMITED:
3725                 mlx5e_ul_snd_tag_free(pmt);
3726                 break;
3727         default:
3728                 break;
3729         }
3730 }
3731
3732 static void *
3733 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
3734 {
3735         struct ifnet *ifp;
3736         struct mlx5e_priv *priv;
3737         u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
3738         struct sysctl_oid_list *child;
3739         int ncv = mdev->priv.eq_table.num_comp_vectors;
3740         char unit[16];
3741         int err;
3742         int i;
3743         u32 eth_proto_cap;
3744
3745         if (mlx5e_check_required_hca_cap(mdev)) {
3746                 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
3747                 return (NULL);
3748         }
3749         /*
3750          * Try to allocate the priv and make room for worst-case
3751          * number of channel structures:
3752          */
3753         priv = malloc(sizeof(*priv) +
3754             (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors),
3755             M_MLX5EN, M_WAITOK | M_ZERO);
3756         mlx5e_priv_mtx_init(priv);
3757
3758         ifp = priv->ifp = if_alloc(IFT_ETHER);
3759         if (ifp == NULL) {
3760                 mlx5_core_err(mdev, "if_alloc() failed\n");
3761                 goto err_free_priv;
3762         }
3763         ifp->if_softc = priv;
3764         if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev));
3765         ifp->if_mtu = ETHERMTU;
3766         ifp->if_init = mlx5e_open;
3767         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
3768         ifp->if_ioctl = mlx5e_ioctl;
3769         ifp->if_transmit = mlx5e_xmit;
3770         ifp->if_qflush = if_qflush;
3771 #if (__FreeBSD_version >= 1100000)
3772         ifp->if_get_counter = mlx5e_get_counter;
3773 #endif
3774         ifp->if_snd.ifq_maxlen = ifqmaxlen;
3775         /*
3776          * Set driver features
3777          */
3778         ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
3779         ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
3780         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
3781         ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
3782         ifp->if_capabilities |= IFCAP_LRO;
3783         ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
3784         ifp->if_capabilities |= IFCAP_HWSTATS | IFCAP_HWRXTSTMP;
3785         ifp->if_capabilities |= IFCAP_TXRTLMT;
3786         ifp->if_snd_tag_alloc = mlx5e_snd_tag_alloc;
3787         ifp->if_snd_tag_free = mlx5e_snd_tag_free;
3788         ifp->if_snd_tag_modify = mlx5e_snd_tag_modify;
3789         ifp->if_snd_tag_query = mlx5e_snd_tag_query;
3790
3791         /* set TSO limits so that we don't have to drop TX packets */
3792         ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
3793         ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
3794         ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
3795
3796         ifp->if_capenable = ifp->if_capabilities;
3797         ifp->if_hwassist = 0;
3798         if (ifp->if_capenable & IFCAP_TSO)
3799                 ifp->if_hwassist |= CSUM_TSO;
3800         if (ifp->if_capenable & IFCAP_TXCSUM)
3801                 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
3802         if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
3803                 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3804
3805         /* ifnet sysctl tree */
3806         sysctl_ctx_init(&priv->sysctl_ctx);
3807         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
3808             OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
3809         if (priv->sysctl_ifnet == NULL) {
3810                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3811                 goto err_free_sysctl;
3812         }
3813         snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
3814         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3815             OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
3816         if (priv->sysctl_ifnet == NULL) {
3817                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3818                 goto err_free_sysctl;
3819         }
3820
3821         /* HW sysctl tree */
3822         child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
3823         priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
3824             OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
3825         if (priv->sysctl_hw == NULL) {
3826                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3827                 goto err_free_sysctl;
3828         }
3829
3830         err = mlx5e_build_ifp_priv(mdev, priv, ncv);
3831         if (err) {
3832                 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err);
3833                 goto err_free_sysctl;
3834         }
3835
3836         snprintf(unit, sizeof(unit), "mce%u_wq",
3837             device_get_unit(mdev->pdev->dev.bsddev));
3838         priv->wq = alloc_workqueue(unit, 0, 1);
3839         if (priv->wq == NULL) {
3840                 if_printf(ifp, "%s: alloc_workqueue failed\n", __func__);
3841                 goto err_free_sysctl;
3842         }
3843
3844         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
3845         if (err) {
3846                 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n",
3847                     __func__, err);
3848                 goto err_free_wq;
3849         }
3850         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
3851         if (err) {
3852                 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n",
3853                     __func__, err);
3854                 goto err_unmap_free_uar;
3855         }
3856         err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
3857         if (err) {
3858                 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n",
3859                     __func__, err);
3860                 goto err_dealloc_pd;
3861         }
3862         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
3863         if (err) {
3864                 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n",
3865                     __func__, err);
3866                 goto err_dealloc_transport_domain;
3867         }
3868         mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
3869
3870         /* check if we should generate a random MAC address */
3871         if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
3872             is_zero_ether_addr(dev_addr)) {
3873                 random_ether_addr(dev_addr);
3874                 if_printf(ifp, "Assigned random MAC address\n");
3875         }
3876 #ifdef RATELIMIT
3877         err = mlx5e_rl_init(priv);
3878         if (err) {
3879                 if_printf(ifp, "%s: mlx5e_rl_init failed, %d\n",
3880                     __func__, err);
3881                 goto err_create_mkey;
3882         }
3883 #endif
3884
3885         /* set default MTU */
3886         mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
3887
3888         /* Set default media status */
3889         priv->media_status_last = IFM_AVALID;
3890         priv->media_active_last = IFM_ETHER | IFM_AUTO |
3891             IFM_ETH_RXPAUSE | IFM_FDX;
3892
3893         /* setup default pauseframes configuration */
3894         mlx5e_setup_pauseframes(priv);
3895
3896         err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
3897         if (err) {
3898                 eth_proto_cap = 0;
3899                 if_printf(ifp, "%s: Query port media capability failed, %d\n",
3900                     __func__, err);
3901         }
3902
3903         /* Setup supported medias */
3904         ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
3905             mlx5e_media_change, mlx5e_media_status);
3906
3907         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
3908                 if (mlx5e_mode_table[i].baudrate == 0)
3909                         continue;
3910                 if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
3911                         ifmedia_add(&priv->media,
3912                             mlx5e_mode_table[i].subtype |
3913                             IFM_ETHER, 0, NULL);
3914                         ifmedia_add(&priv->media,
3915                             mlx5e_mode_table[i].subtype |
3916                             IFM_ETHER | IFM_FDX |
3917                             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3918                 }
3919         }
3920
3921         /* Additional supported medias */
3922         ifmedia_add(&priv->media, IFM_10G_LR | IFM_ETHER, 0, NULL);
3923         ifmedia_add(&priv->media, IFM_10G_LR |
3924             IFM_ETHER | IFM_FDX |
3925             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3926
3927         ifmedia_add(&priv->media, IFM_40G_ER4 | IFM_ETHER, 0, NULL);
3928         ifmedia_add(&priv->media, IFM_40G_ER4 |
3929             IFM_ETHER | IFM_FDX |
3930             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3931
3932         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
3933         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3934             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3935
3936         /* Set autoselect by default */
3937         ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3938             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
3939         ether_ifattach(ifp, dev_addr);
3940
3941         /* Register for VLAN events */
3942         priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
3943             mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
3944         priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
3945             mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
3946
3947         /* Link is down by default */
3948         if_link_state_change(ifp, LINK_STATE_DOWN);
3949
3950         mlx5e_enable_async_events(priv);
3951
3952         mlx5e_add_hw_stats(priv);
3953
3954         mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3955             "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
3956             priv->stats.vport.arg);
3957
3958         mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3959             "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
3960             priv->stats.pport.arg);
3961
3962         mlx5e_create_ethtool(priv);
3963
3964         mtx_lock(&priv->async_events_mtx);
3965         mlx5e_update_stats(priv);
3966         mtx_unlock(&priv->async_events_mtx);
3967
3968         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3969             OID_AUTO, "rx_clbr_done", CTLFLAG_RD,
3970             &priv->clbr_done, 0,
3971             "RX timestamps calibration state");
3972         callout_init(&priv->tstmp_clbr, CALLOUT_DIRECT);
3973         mlx5e_reset_calibration_callout(priv);
3974
3975         return (priv);
3976
3977 #ifdef RATELIMIT
3978 err_create_mkey:
3979         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
3980 #endif
3981 err_dealloc_transport_domain:
3982         mlx5_dealloc_transport_domain(mdev, priv->tdn);
3983
3984 err_dealloc_pd:
3985         mlx5_core_dealloc_pd(mdev, priv->pdn);
3986
3987 err_unmap_free_uar:
3988         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3989
3990 err_free_wq:
3991         destroy_workqueue(priv->wq);
3992
3993 err_free_sysctl:
3994         sysctl_ctx_free(&priv->sysctl_ctx);
3995         if (priv->sysctl_debug)
3996                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
3997         if_free(ifp);
3998
3999 err_free_priv:
4000         mlx5e_priv_mtx_destroy(priv);
4001         free(priv, M_MLX5EN);
4002         return (NULL);
4003 }
4004
4005 static void
4006 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
4007 {
4008         struct mlx5e_priv *priv = vpriv;
4009         struct ifnet *ifp = priv->ifp;
4010
4011         /* don't allow more IOCTLs */
4012         priv->gone = 1;
4013
4014         /* XXX wait a bit to allow IOCTL handlers to complete */
4015         pause("W", hz);
4016
4017 #ifdef RATELIMIT
4018         /*
4019          * The kernel can have reference(s) via the m_snd_tag's into
4020          * the ratelimit channels, and these must go away before
4021          * detaching:
4022          */
4023         while (READ_ONCE(priv->rl.stats.tx_active_connections) != 0) {
4024                 if_printf(priv->ifp, "Waiting for all ratelimit connections "
4025                     "to terminate\n");
4026                 pause("W", hz);
4027         }
4028 #endif
4029         /* stop watchdog timer */
4030         callout_drain(&priv->watchdog);
4031
4032         callout_drain(&priv->tstmp_clbr);
4033
4034         if (priv->vlan_attach != NULL)
4035                 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
4036         if (priv->vlan_detach != NULL)
4037                 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
4038
4039         /* make sure device gets closed */
4040         PRIV_LOCK(priv);
4041         mlx5e_close_locked(ifp);
4042         PRIV_UNLOCK(priv);
4043
4044         /* wait for all unlimited send tags to go away */
4045         while (priv->channel_refs != 0) {
4046                 if_printf(priv->ifp, "Waiting for all unlimited connections "
4047                     "to terminate\n");
4048                 pause("W", hz);
4049         }
4050
4051         /* unregister device */
4052         ifmedia_removeall(&priv->media);
4053         ether_ifdetach(ifp);
4054         if_free(ifp);
4055
4056 #ifdef RATELIMIT
4057         mlx5e_rl_cleanup(priv);
4058 #endif
4059         /* destroy all remaining sysctl nodes */
4060         sysctl_ctx_free(&priv->stats.vport.ctx);
4061         sysctl_ctx_free(&priv->stats.pport.ctx);
4062         if (priv->sysctl_debug)
4063                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4064         sysctl_ctx_free(&priv->sysctl_ctx);
4065
4066         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
4067         mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
4068         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
4069         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
4070         mlx5e_disable_async_events(priv);
4071         destroy_workqueue(priv->wq);
4072         mlx5e_priv_mtx_destroy(priv);
4073         free(priv, M_MLX5EN);
4074 }
4075
4076 static void *
4077 mlx5e_get_ifp(void *vpriv)
4078 {
4079         struct mlx5e_priv *priv = vpriv;
4080
4081         return (priv->ifp);
4082 }
4083
4084 static struct mlx5_interface mlx5e_interface = {
4085         .add = mlx5e_create_ifp,
4086         .remove = mlx5e_destroy_ifp,
4087         .event = mlx5e_async_event,
4088         .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4089         .get_dev = mlx5e_get_ifp,
4090 };
4091
4092 void
4093 mlx5e_init(void)
4094 {
4095         mlx5_register_interface(&mlx5e_interface);
4096 }
4097
4098 void
4099 mlx5e_cleanup(void)
4100 {
4101         mlx5_unregister_interface(&mlx5e_interface);
4102 }
4103
4104 static void
4105 mlx5e_show_version(void __unused *arg)
4106 {
4107
4108         printf("%s", mlx5e_version);
4109 }
4110 SYSINIT(mlx5e_show_version, SI_SUB_DRIVERS, SI_ORDER_ANY, mlx5e_show_version, NULL);
4111
4112 module_init_order(mlx5e_init, SI_ORDER_THIRD);
4113 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
4114
4115 #if (__FreeBSD_version >= 1100000)
4116 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
4117 #endif
4118 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
4119 MODULE_VERSION(mlx5en, 1);