sys/dev/mlx5/mlx5_en/mlx5_en_main.c

   1 /*-
   2  * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include "en.h"
  29
  30 #include <sys/sockio.h>
  31 #include <machine/atomic.h>
  32
  33 #ifndef ETH_DRIVER_VERSION
  34 #define ETH_DRIVER_VERSION      "3.5.0"
  35 #endif
  36 #define DRIVER_RELDATE  "November 2018"
  37
  38 static const char mlx5e_version[] = "mlx5en: Mellanox Ethernet driver "
  39         ETH_DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
  40
  41 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs);
  42
  43 struct mlx5e_channel_param {
  44         struct mlx5e_rq_param rq;
  45         struct mlx5e_sq_param sq;
  46         struct mlx5e_cq_param rx_cq;
  47         struct mlx5e_cq_param tx_cq;
  48 };
  49
  50 static const struct {
  51         u32     subtype;
  52         u64     baudrate;
  53 }       mlx5e_mode_table[MLX5E_LINK_MODES_NUMBER] = {
  54
  55         [MLX5E_1000BASE_CX_SGMII] = {
  56                 .subtype = IFM_1000_CX_SGMII,
  57                 .baudrate = IF_Mbps(1000ULL),
  58         },
  59         [MLX5E_1000BASE_KX] = {
  60                 .subtype = IFM_1000_KX,
  61                 .baudrate = IF_Mbps(1000ULL),
  62         },
  63         [MLX5E_10GBASE_CX4] = {
  64                 .subtype = IFM_10G_CX4,
  65                 .baudrate = IF_Gbps(10ULL),
  66         },
  67         [MLX5E_10GBASE_KX4] = {
  68                 .subtype = IFM_10G_KX4,
  69                 .baudrate = IF_Gbps(10ULL),
  70         },
  71         [MLX5E_10GBASE_KR] = {
  72                 .subtype = IFM_10G_KR,
  73                 .baudrate = IF_Gbps(10ULL),
  74         },
  75         [MLX5E_20GBASE_KR2] = {
  76                 .subtype = IFM_20G_KR2,
  77                 .baudrate = IF_Gbps(20ULL),
  78         },
  79         [MLX5E_40GBASE_CR4] = {
  80                 .subtype = IFM_40G_CR4,
  81                 .baudrate = IF_Gbps(40ULL),
  82         },
  83         [MLX5E_40GBASE_KR4] = {
  84                 .subtype = IFM_40G_KR4,
  85                 .baudrate = IF_Gbps(40ULL),
  86         },
  87         [MLX5E_56GBASE_R4] = {
  88                 .subtype = IFM_56G_R4,
  89                 .baudrate = IF_Gbps(56ULL),
  90         },
  91         [MLX5E_10GBASE_CR] = {
  92                 .subtype = IFM_10G_CR1,
  93                 .baudrate = IF_Gbps(10ULL),
  94         },
  95         [MLX5E_10GBASE_SR] = {
  96                 .subtype = IFM_10G_SR,
  97                 .baudrate = IF_Gbps(10ULL),
  98         },
  99         [MLX5E_10GBASE_ER] = {
 100                 .subtype = IFM_10G_ER,
 101                 .baudrate = IF_Gbps(10ULL),
 102         },
 103         [MLX5E_40GBASE_SR4] = {
 104                 .subtype = IFM_40G_SR4,
 105                 .baudrate = IF_Gbps(40ULL),
 106         },
 107         [MLX5E_40GBASE_LR4] = {
 108                 .subtype = IFM_40G_LR4,
 109                 .baudrate = IF_Gbps(40ULL),
 110         },
 111         [MLX5E_100GBASE_CR4] = {
 112                 .subtype = IFM_100G_CR4,
 113                 .baudrate = IF_Gbps(100ULL),
 114         },
 115         [MLX5E_100GBASE_SR4] = {
 116                 .subtype = IFM_100G_SR4,
 117                 .baudrate = IF_Gbps(100ULL),
 118         },
 119         [MLX5E_100GBASE_KR4] = {
 120                 .subtype = IFM_100G_KR4,
 121                 .baudrate = IF_Gbps(100ULL),
 122         },
 123         [MLX5E_100GBASE_LR4] = {
 124                 .subtype = IFM_100G_LR4,
 125                 .baudrate = IF_Gbps(100ULL),
 126         },
 127         [MLX5E_100BASE_TX] = {
 128                 .subtype = IFM_100_TX,
 129                 .baudrate = IF_Mbps(100ULL),
 130         },
 131         [MLX5E_1000BASE_T] = {
 132                 .subtype = IFM_1000_T,
 133                 .baudrate = IF_Mbps(1000ULL),
 134         },
 135         [MLX5E_10GBASE_T] = {
 136                 .subtype = IFM_10G_T,
 137                 .baudrate = IF_Gbps(10ULL),
 138         },
 139         [MLX5E_25GBASE_CR] = {
 140                 .subtype = IFM_25G_CR,
 141                 .baudrate = IF_Gbps(25ULL),
 142         },
 143         [MLX5E_25GBASE_KR] = {
 144                 .subtype = IFM_25G_KR,
 145                 .baudrate = IF_Gbps(25ULL),
 146         },
 147         [MLX5E_25GBASE_SR] = {
 148                 .subtype = IFM_25G_SR,
 149                 .baudrate = IF_Gbps(25ULL),
 150         },
 151         [MLX5E_50GBASE_CR2] = {
 152                 .subtype = IFM_50G_CR2,
 153                 .baudrate = IF_Gbps(50ULL),
 154         },
 155         [MLX5E_50GBASE_KR2] = {
 156                 .subtype = IFM_50G_KR2,
 157                 .baudrate = IF_Gbps(50ULL),
 158         },
 159 };
 160
 161 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
 162
 163 static void
 164 mlx5e_update_carrier(struct mlx5e_priv *priv)
 165 {
 166         struct mlx5_core_dev *mdev = priv->mdev;
 167         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 168         u32 eth_proto_oper;
 169         int error;
 170         u8 port_state;
 171         u8 is_er_type;
 172         u8 i;
 173
 174         port_state = mlx5_query_vport_state(mdev,
 175             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 176
 177         if (port_state == VPORT_STATE_UP) {
 178                 priv->media_status_last |= IFM_ACTIVE;
 179         } else {
 180                 priv->media_status_last &= ~IFM_ACTIVE;
 181                 priv->media_active_last = IFM_ETHER;
 182                 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
 183                 return;
 184         }
 185
 186         error = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
 187         if (error) {
 188                 priv->media_active_last = IFM_ETHER;
 189                 priv->ifp->if_baudrate = 1;
 190                 if_printf(priv->ifp, "%s: query port ptys failed: 0x%x\n",
 191                     __func__, error);
 192                 return;
 193         }
 194         eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
 195
 196         for (i = 0; i != MLX5E_LINK_MODES_NUMBER; i++) {
 197                 if (mlx5e_mode_table[i].baudrate == 0)
 198                         continue;
 199                 if (MLX5E_PROT_MASK(i) & eth_proto_oper) {
 200                         u32 subtype = mlx5e_mode_table[i].subtype;
 201
 202                         priv->ifp->if_baudrate =
 203                             mlx5e_mode_table[i].baudrate;
 204
 205                         switch (subtype) {
 206                         case IFM_10G_ER:
 207                                 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
 208                                 if (error != 0) {
 209                                         if_printf(priv->ifp, "%s: query port pddr failed: %d\n",
 210                                             __func__, error);
 211                                 }
 212                                 if (error != 0 || is_er_type == 0)
 213                                         subtype = IFM_10G_LR;
 214                                 break;
 215                         case IFM_40G_LR4:
 216                                 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
 217                                 if (error != 0) {
 218                                         if_printf(priv->ifp, "%s: query port pddr failed: %d\n",
 219                                             __func__, error);
 220                                 }
 221                                 if (error == 0 && is_er_type != 0)
 222                                         subtype = IFM_40G_ER4;
 223                                 break;
 224                         }
 225                         priv->media_active_last = subtype | IFM_ETHER | IFM_FDX;
 226                         break;
 227                 }
 228         }
 229         if_link_state_change(priv->ifp, LINK_STATE_UP);
 230 }
 231
 232 static void
 233 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
 234 {
 235         struct mlx5e_priv *priv = dev->if_softc;
 236
 237         ifmr->ifm_status = priv->media_status_last;
 238         ifmr->ifm_active = priv->media_active_last |
 239             (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
 240             (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
 241
 242 }
 243
 244 static u32
 245 mlx5e_find_link_mode(u32 subtype)
 246 {
 247         u32 i;
 248         u32 link_mode = 0;
 249
 250         switch (subtype) {
 251         case IFM_10G_LR:
 252                 subtype = IFM_10G_ER;
 253                 break;
 254         case IFM_40G_ER4:
 255                 subtype = IFM_40G_LR4;
 256                 break;
 257         }
 258
 259         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
 260                 if (mlx5e_mode_table[i].baudrate == 0)
 261                         continue;
 262                 if (mlx5e_mode_table[i].subtype == subtype)
 263                         link_mode |= MLX5E_PROT_MASK(i);
 264         }
 265
 266         return (link_mode);
 267 }
 268
 269 static int
 270 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv)
 271 {
 272         return (mlx5_set_port_pause_and_pfc(priv->mdev, 1,
 273             priv->params.rx_pauseframe_control,
 274             priv->params.tx_pauseframe_control,
 275             priv->params.rx_priority_flow_control,
 276             priv->params.tx_priority_flow_control));
 277 }
 278
 279 static int
 280 mlx5e_set_port_pfc(struct mlx5e_priv *priv)
 281 {
 282         int error;
 283
 284         if (priv->gone != 0) {
 285                 error = -ENXIO;
 286         } else if (priv->params.rx_pauseframe_control ||
 287             priv->params.tx_pauseframe_control) {
 288                 if_printf(priv->ifp,
 289                     "Global pauseframes must be disabled before enabling PFC.\n");
 290                 error = -EINVAL;
 291         } else {
 292                 error = mlx5e_set_port_pause_and_pfc(priv);
 293         }
 294         return (error);
 295 }
 296
 297 static int
 298 mlx5e_media_change(struct ifnet *dev)
 299 {
 300         struct mlx5e_priv *priv = dev->if_softc;
 301         struct mlx5_core_dev *mdev = priv->mdev;
 302         u32 eth_proto_cap;
 303         u32 link_mode;
 304         int was_opened;
 305         int locked;
 306         int error;
 307
 308         locked = PRIV_LOCKED(priv);
 309         if (!locked)
 310                 PRIV_LOCK(priv);
 311
 312         if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
 313                 error = EINVAL;
 314                 goto done;
 315         }
 316         link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media));
 317
 318         /* query supported capabilities */
 319         error = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
 320         if (error != 0) {
 321                 if_printf(dev, "Query port media capability failed\n");
 322                 goto done;
 323         }
 324         /* check for autoselect */
 325         if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
 326                 link_mode = eth_proto_cap;
 327                 if (link_mode == 0) {
 328                         if_printf(dev, "Port media capability is zero\n");
 329                         error = EINVAL;
 330                         goto done;
 331                 }
 332         } else {
 333                 link_mode = link_mode & eth_proto_cap;
 334                 if (link_mode == 0) {
 335                         if_printf(dev, "Not supported link mode requested\n");
 336                         error = EINVAL;
 337                         goto done;
 338                 }
 339         }
 340         if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
 341                 /* check if PFC is enabled */
 342                 if (priv->params.rx_priority_flow_control ||
 343                     priv->params.tx_priority_flow_control) {
 344                         if_printf(dev, "PFC must be disabled before enabling global pauseframes.\n");
 345                         error = EINVAL;
 346                         goto done;
 347                 }
 348         }
 349         /* update pauseframe control bits */
 350         priv->params.rx_pauseframe_control =
 351             (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
 352         priv->params.tx_pauseframe_control =
 353             (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
 354
 355         /* check if device is opened */
 356         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
 357
 358         /* reconfigure the hardware */
 359         mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
 360         mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN);
 361         error = -mlx5e_set_port_pause_and_pfc(priv);
 362         if (was_opened)
 363                 mlx5_set_port_status(mdev, MLX5_PORT_UP);
 364
 365 done:
 366         if (!locked)
 367                 PRIV_UNLOCK(priv);
 368         return (error);
 369 }
 370
 371 static void
 372 mlx5e_update_carrier_work(struct work_struct *work)
 373 {
 374         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 375             update_carrier_work);
 376
 377         PRIV_LOCK(priv);
 378         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 379                 mlx5e_update_carrier(priv);
 380         PRIV_UNLOCK(priv);
 381 }
 382
 383 /*
 384  * This function reads the physical port counters from the firmware
 385  * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
 386  * macros. The output is converted from big-endian 64-bit values into
 387  * host endian ones and stored in the "priv->stats.pport" structure.
 388  */
 389 static void
 390 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 391 {
 392         struct mlx5_core_dev *mdev = priv->mdev;
 393         struct mlx5e_pport_stats *s = &priv->stats.pport;
 394         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 395         u32 *in;
 396         u32 *out;
 397         const u64 *ptr;
 398         unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 399         unsigned x;
 400         unsigned y;
 401         unsigned z;
 402
 403         /* allocate firmware request structures */
 404         in = mlx5_vzalloc(sz);
 405         out = mlx5_vzalloc(sz);
 406         if (in == NULL || out == NULL)
 407                 goto free_out;
 408
 409         /*
 410          * Get pointer to the 64-bit counter set which is located at a
 411          * fixed offset in the output firmware request structure:
 412          */
 413         ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
 414
 415         MLX5_SET(ppcnt_reg, in, local_port, 1);
 416
 417         /* read IEEE802_3 counter group using predefined counter layout */
 418         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 419         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 420         for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM;
 421              x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
 422                 s->arg[y] = be64toh(ptr[x]);
 423
 424         /* read RFC2819 counter group using predefined counter layout */
 425         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 426         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 427         for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
 428                 s->arg[y] = be64toh(ptr[x]);
 429         for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
 430             MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
 431                 s_debug->arg[y] = be64toh(ptr[x]);
 432
 433         /* read RFC2863 counter group using predefined counter layout */
 434         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 435         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 436         for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
 437                 s_debug->arg[y] = be64toh(ptr[x]);
 438
 439         /* read physical layer stats counter group using predefined counter layout */
 440         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 441         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 442         for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
 443                 s_debug->arg[y] = be64toh(ptr[x]);
 444
 445         /* read Extended Ethernet counter group using predefined counter layout */
 446         MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
 447         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 448         for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++)
 449                 s_debug->arg[y] = be64toh(ptr[x]);
 450
 451         /* read per-priority counters */
 452         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 453
 454         /* iterate all the priorities */
 455         for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) {
 456                 MLX5_SET(ppcnt_reg, in, prio_tc, z);
 457                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 458
 459                 /* read per priority stats counter group using predefined counter layout */
 460                 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM /
 461                     MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++)
 462                         s->arg[y] = be64toh(ptr[x]);
 463         }
 464
 465 free_out:
 466         /* free firmware request structures */
 467         kvfree(in);
 468         kvfree(out);
 469 }
 470
 471 /*
 472  * This function is called regularly to collect all statistics
 473  * counters from the firmware. The values can be viewed through the
 474  * sysctl interface. Execution is serialized using the priv's global
 475  * configuration lock.
 476  */
 477 static void
 478 mlx5e_update_stats_work(struct work_struct *work)
 479 {
 480         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 481             update_stats_work);
 482         struct mlx5_core_dev *mdev = priv->mdev;
 483         struct mlx5e_vport_stats *s = &priv->stats.vport;
 484         struct mlx5e_sq_stats *sq_stats;
 485         struct buf_ring *sq_br;
 486 #if (__FreeBSD_version < 1100000)
 487         struct ifnet *ifp = priv->ifp;
 488 #endif
 489
 490         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 491         u32 *out;
 492         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 493         u64 tso_packets = 0;
 494         u64 tso_bytes = 0;
 495         u64 tx_queue_dropped = 0;
 496         u64 tx_defragged = 0;
 497         u64 tx_offload_none = 0;
 498         u64 lro_packets = 0;
 499         u64 lro_bytes = 0;
 500         u64 sw_lro_queued = 0;
 501         u64 sw_lro_flushed = 0;
 502         u64 rx_csum_none = 0;
 503         u64 rx_wqe_err = 0;
 504         u32 rx_out_of_buffer = 0;
 505         int i;
 506         int j;
 507
 508         PRIV_LOCK(priv);
 509         out = mlx5_vzalloc(outlen);
 510         if (out == NULL)
 511                 goto free_out;
 512         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
 513                 goto free_out;
 514
 515         /* Collect firts the SW counters and then HW for consistency */
 516         for (i = 0; i < priv->params.num_channels; i++) {
 517                 struct mlx5e_channel *pch = priv->channel + i;
 518                 struct mlx5e_rq *rq = &pch->rq;
 519                 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats;
 520
 521                 /* collect stats from LRO */
 522                 rq_stats->sw_lro_queued = rq->lro.lro_queued;
 523                 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
 524                 sw_lro_queued += rq_stats->sw_lro_queued;
 525                 sw_lro_flushed += rq_stats->sw_lro_flushed;
 526                 lro_packets += rq_stats->lro_packets;
 527                 lro_bytes += rq_stats->lro_bytes;
 528                 rx_csum_none += rq_stats->csum_none;
 529                 rx_wqe_err += rq_stats->wqe_err;
 530
 531                 for (j = 0; j < priv->num_tc; j++) {
 532                         sq_stats = &pch->sq[j].stats;
 533                         sq_br = pch->sq[j].br;
 534
 535                         tso_packets += sq_stats->tso_packets;
 536                         tso_bytes += sq_stats->tso_bytes;
 537                         tx_queue_dropped += sq_stats->dropped;
 538                         if (sq_br != NULL)
 539                                 tx_queue_dropped += sq_br->br_drops;
 540                         tx_defragged += sq_stats->defragged;
 541                         tx_offload_none += sq_stats->csum_offload_none;
 542                 }
 543         }
 544
 545         /* update counters */
 546         s->tso_packets = tso_packets;
 547         s->tso_bytes = tso_bytes;
 548         s->tx_queue_dropped = tx_queue_dropped;
 549         s->tx_defragged = tx_defragged;
 550         s->lro_packets = lro_packets;
 551         s->lro_bytes = lro_bytes;
 552         s->sw_lro_queued = sw_lro_queued;
 553         s->sw_lro_flushed = sw_lro_flushed;
 554         s->rx_csum_none = rx_csum_none;
 555         s->rx_wqe_err = rx_wqe_err;
 556
 557         /* HW counters */
 558         memset(in, 0, sizeof(in));
 559
 560         MLX5_SET(query_vport_counter_in, in, opcode,
 561             MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 562         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 563         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 564
 565         memset(out, 0, outlen);
 566
 567         /* get number of out-of-buffer drops first */
 568         if (mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
 569             &rx_out_of_buffer))
 570                 goto free_out;
 571
 572         /* accumulate difference into a 64-bit counter */
 573         s->rx_out_of_buffer += (u64)(u32)(rx_out_of_buffer - s->rx_out_of_buffer_prev);
 574         s->rx_out_of_buffer_prev = rx_out_of_buffer;
 575
 576         /* get port statistics */
 577         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
 578                 goto free_out;
 579
 580 #define MLX5_GET_CTR(out, x) \
 581         MLX5_GET64(query_vport_counter_out, out, x)
 582
 583         s->rx_error_packets =
 584             MLX5_GET_CTR(out, received_errors.packets);
 585         s->rx_error_bytes =
 586             MLX5_GET_CTR(out, received_errors.octets);
 587         s->tx_error_packets =
 588             MLX5_GET_CTR(out, transmit_errors.packets);
 589         s->tx_error_bytes =
 590             MLX5_GET_CTR(out, transmit_errors.octets);
 591
 592         s->rx_unicast_packets =
 593             MLX5_GET_CTR(out, received_eth_unicast.packets);
 594         s->rx_unicast_bytes =
 595             MLX5_GET_CTR(out, received_eth_unicast.octets);
 596         s->tx_unicast_packets =
 597             MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 598         s->tx_unicast_bytes =
 599             MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 600
 601         s->rx_multicast_packets =
 602             MLX5_GET_CTR(out, received_eth_multicast.packets);
 603         s->rx_multicast_bytes =
 604             MLX5_GET_CTR(out, received_eth_multicast.octets);
 605         s->tx_multicast_packets =
 606             MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 607         s->tx_multicast_bytes =
 608             MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 609
 610         s->rx_broadcast_packets =
 611             MLX5_GET_CTR(out, received_eth_broadcast.packets);
 612         s->rx_broadcast_bytes =
 613             MLX5_GET_CTR(out, received_eth_broadcast.octets);
 614         s->tx_broadcast_packets =
 615             MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 616         s->tx_broadcast_bytes =
 617             MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 618
 619         s->rx_packets =
 620             s->rx_unicast_packets +
 621             s->rx_multicast_packets +
 622             s->rx_broadcast_packets -
 623             s->rx_out_of_buffer;
 624         s->rx_bytes =
 625             s->rx_unicast_bytes +
 626             s->rx_multicast_bytes +
 627             s->rx_broadcast_bytes;
 628         s->tx_packets =
 629             s->tx_unicast_packets +
 630             s->tx_multicast_packets +
 631             s->tx_broadcast_packets;
 632         s->tx_bytes =
 633             s->tx_unicast_bytes +
 634             s->tx_multicast_bytes +
 635             s->tx_broadcast_bytes;
 636
 637         /* Update calculated offload counters */
 638         s->tx_csum_offload = s->tx_packets - tx_offload_none;
 639         s->rx_csum_good = s->rx_packets - s->rx_csum_none;
 640
 641         /* Get physical port counters */
 642         mlx5e_update_pport_counters(priv);
 643
 644         s->tx_jumbo_packets =
 645             priv->stats.port_stats_debug.tx_stat_p1519to2047octets +
 646             priv->stats.port_stats_debug.tx_stat_p2048to4095octets +
 647             priv->stats.port_stats_debug.tx_stat_p4096to8191octets +
 648             priv->stats.port_stats_debug.tx_stat_p8192to10239octets;
 649
 650 #if (__FreeBSD_version < 1100000)
 651         /* no get_counters interface in fbsd 10 */
 652         ifp->if_ipackets = s->rx_packets;
 653         ifp->if_ierrors = s->rx_error_packets +
 654             priv->stats.pport.alignment_err +
 655             priv->stats.pport.check_seq_err +
 656             priv->stats.pport.crc_align_errors +
 657             priv->stats.pport.in_range_len_errors +
 658             priv->stats.pport.jabbers +
 659             priv->stats.pport.out_of_range_len +
 660             priv->stats.pport.oversize_pkts +
 661             priv->stats.pport.symbol_err +
 662             priv->stats.pport.too_long_errors +
 663             priv->stats.pport.undersize_pkts +
 664             priv->stats.pport.unsupported_op_rx;
 665         ifp->if_iqdrops = s->rx_out_of_buffer +
 666             priv->stats.pport.drop_events;
 667         ifp->if_opackets = s->tx_packets;
 668         ifp->if_oerrors = s->tx_error_packets;
 669         ifp->if_snd.ifq_drops = s->tx_queue_dropped;
 670         ifp->if_ibytes = s->rx_bytes;
 671         ifp->if_obytes = s->tx_bytes;
 672         ifp->if_collisions =
 673             priv->stats.pport.collisions;
 674 #endif
 675
 676 free_out:
 677         kvfree(out);
 678
 679         /* Update diagnostics, if any */
 680         if (priv->params_ethtool.diag_pci_enable ||
 681             priv->params_ethtool.diag_general_enable) {
 682                 int error = mlx5_core_get_diagnostics_full(mdev,
 683                     priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL,
 684                     priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL);
 685                 if (error != 0)
 686                         if_printf(priv->ifp, "Failed reading diagnostics: %d\n", error);
 687         }
 688         PRIV_UNLOCK(priv);
 689 }
 690
 691 static void
 692 mlx5e_update_stats(void *arg)
 693 {
 694         struct mlx5e_priv *priv = arg;
 695
 696         queue_work(priv->wq, &priv->update_stats_work);
 697
 698         callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
 699 }
 700
 701 static void
 702 mlx5e_async_event_sub(struct mlx5e_priv *priv,
 703     enum mlx5_dev_event event)
 704 {
 705         switch (event) {
 706         case MLX5_DEV_EVENT_PORT_UP:
 707         case MLX5_DEV_EVENT_PORT_DOWN:
 708                 queue_work(priv->wq, &priv->update_carrier_work);
 709                 break;
 710
 711         default:
 712                 break;
 713         }
 714 }
 715
 716 static void
 717 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 718     enum mlx5_dev_event event, unsigned long param)
 719 {
 720         struct mlx5e_priv *priv = vpriv;
 721
 722         mtx_lock(&priv->async_events_mtx);
 723         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 724                 mlx5e_async_event_sub(priv, event);
 725         mtx_unlock(&priv->async_events_mtx);
 726 }
 727
 728 static void
 729 mlx5e_enable_async_events(struct mlx5e_priv *priv)
 730 {
 731         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 732 }
 733
 734 static void
 735 mlx5e_disable_async_events(struct mlx5e_priv *priv)
 736 {
 737         mtx_lock(&priv->async_events_mtx);
 738         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 739         mtx_unlock(&priv->async_events_mtx);
 740 }
 741
 742 static void mlx5e_calibration_callout(void *arg);
 743 static int mlx5e_calibration_duration = 20;
 744 static int mlx5e_fast_calibration = 1;
 745 static int mlx5e_normal_calibration = 30;
 746
 747 static SYSCTL_NODE(_hw_mlx5, OID_AUTO, calibr, CTLFLAG_RW, 0,
 748     "MLX5 timestamp calibration parameteres");
 749
 750 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, duration, CTLFLAG_RWTUN,
 751     &mlx5e_calibration_duration, 0,
 752     "Duration of initial calibration");
 753 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, fast, CTLFLAG_RWTUN,
 754     &mlx5e_fast_calibration, 0,
 755     "Recalibration interval during initial calibration");
 756 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, normal, CTLFLAG_RWTUN,
 757     &mlx5e_normal_calibration, 0,
 758     "Recalibration interval during normal operations");
 759
 760 /*
 761  * Ignites the calibration process.
 762  */
 763 static void
 764 mlx5e_reset_calibration_callout(struct mlx5e_priv *priv)
 765 {
 766
 767         if (priv->clbr_done == 0)
 768                 mlx5e_calibration_callout(priv);
 769         else
 770                 callout_reset_curcpu(&priv->tstmp_clbr, (priv->clbr_done <
 771                     mlx5e_calibration_duration ? mlx5e_fast_calibration :
 772                     mlx5e_normal_calibration) * hz, mlx5e_calibration_callout,
 773                     priv);
 774 }
 775
 776 static uint64_t
 777 mlx5e_timespec2usec(const struct timespec *ts)
 778 {
 779
 780         return ((uint64_t)ts->tv_sec * 1000000000 + ts->tv_nsec);
 781 }
 782
 783 static uint64_t
 784 mlx5e_hw_clock(struct mlx5e_priv *priv)
 785 {
 786         struct mlx5_init_seg *iseg;
 787         uint32_t hw_h, hw_h1, hw_l;
 788
 789         iseg = priv->mdev->iseg;
 790         do {
 791                 hw_h = ioread32be(&iseg->internal_timer_h);
 792                 hw_l = ioread32be(&iseg->internal_timer_l);
 793                 hw_h1 = ioread32be(&iseg->internal_timer_h);
 794         } while (hw_h1 != hw_h);
 795         return (((uint64_t)hw_h << 32) | hw_l);
 796 }
 797
 798 /*
 799  * The calibration callout, it runs either in the context of the
 800  * thread which enables calibration, or in callout.  It takes the
 801  * snapshot of system and adapter clocks, then advances the pointers to
 802  * the calibration point to allow rx path to read the consistent data
 803  * lockless.
 804  */
 805 static void
 806 mlx5e_calibration_callout(void *arg)
 807 {
 808         struct mlx5e_priv *priv;
 809         struct mlx5e_clbr_point *next, *curr;
 810         struct timespec ts;
 811         int clbr_curr_next;
 812
 813         priv = arg;
 814         curr = &priv->clbr_points[priv->clbr_curr];
 815         clbr_curr_next = priv->clbr_curr + 1;
 816         if (clbr_curr_next >= nitems(priv->clbr_points))
 817                 clbr_curr_next = 0;
 818         next = &priv->clbr_points[clbr_curr_next];
 819
 820         next->base_prev = curr->base_curr;
 821         next->clbr_hw_prev = curr->clbr_hw_curr;
 822
 823         next->clbr_hw_curr = mlx5e_hw_clock(priv);
 824         if (((next->clbr_hw_curr - curr->clbr_hw_prev) >> MLX5E_TSTMP_PREC) ==
 825             0) {
 826                 if_printf(priv->ifp, "HW failed tstmp frozen %#jx %#jx,"
 827                     "disabling\n", next->clbr_hw_curr, curr->clbr_hw_prev);
 828                 priv->clbr_done = 0;
 829                 return;
 830         }
 831
 832         nanouptime(&ts);
 833         next->base_curr = mlx5e_timespec2usec(&ts);
 834
 835         curr->clbr_gen = 0;
 836         atomic_thread_fence_rel();
 837         priv->clbr_curr = clbr_curr_next;
 838         atomic_store_rel_int(&next->clbr_gen, ++(priv->clbr_gen));
 839
 840         if (priv->clbr_done < mlx5e_calibration_duration)
 841                 priv->clbr_done++;
 842         mlx5e_reset_calibration_callout(priv);
 843 }
 844
 845 static const char *mlx5e_rq_stats_desc[] = {
 846         MLX5E_RQ_STATS(MLX5E_STATS_DESC)
 847 };
 848
 849 static int
 850 mlx5e_create_rq(struct mlx5e_channel *c,
 851     struct mlx5e_rq_param *param,
 852     struct mlx5e_rq *rq)
 853 {
 854         struct mlx5e_priv *priv = c->priv;
 855         struct mlx5_core_dev *mdev = priv->mdev;
 856         char buffer[16];
 857         void *rqc = param->rqc;
 858         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 859         int wq_sz;
 860         int err;
 861         int i;
 862         u32 nsegs, wqe_sz;
 863
 864         err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
 865         if (err != 0)
 866                 goto done;
 867
 868         /* Create DMA descriptor TAG */
 869         if ((err = -bus_dma_tag_create(
 870             bus_get_dma_tag(mdev->pdev->dev.bsddev),
 871             1,                          /* any alignment */
 872             0,                          /* no boundary */
 873             BUS_SPACE_MAXADDR,          /* lowaddr */
 874             BUS_SPACE_MAXADDR,          /* highaddr */
 875             NULL, NULL,                 /* filter, filterarg */
 876             nsegs * MLX5E_MAX_RX_BYTES, /* maxsize */
 877             nsegs,                      /* nsegments */
 878             nsegs * MLX5E_MAX_RX_BYTES, /* maxsegsize */
 879             0,                          /* flags */
 880             NULL, NULL,                 /* lockfunc, lockfuncarg */
 881             &rq->dma_tag)))
 882                 goto done;
 883
 884         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 885             &rq->wq_ctrl);
 886         if (err)
 887                 goto err_free_dma_tag;
 888
 889         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 890
 891         err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs);
 892         if (err != 0)
 893                 goto err_rq_wq_destroy;
 894
 895         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 896
 897         err = -tcp_lro_init_args(&rq->lro, c->tag.m_snd_tag.ifp, TCP_LRO_ENTRIES, wq_sz);
 898         if (err)
 899                 goto err_rq_wq_destroy;
 900
 901         rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
 902         for (i = 0; i != wq_sz; i++) {
 903                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 904 #if (MLX5E_MAX_RX_SEGS == 1)
 905                 uint32_t byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 906 #else
 907                 int j;
 908 #endif
 909
 910                 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
 911                 if (err != 0) {
 912                         while (i--)
 913                                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 914                         goto err_rq_mbuf_free;
 915                 }
 916
 917                 /* set value for constant fields */
 918 #if (MLX5E_MAX_RX_SEGS == 1)
 919                 wqe->data[0].lkey = c->mkey_be;
 920                 wqe->data[0].byte_count = cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
 921 #else
 922                 for (j = 0; j < rq->nsegs; j++)
 923                         wqe->data[j].lkey = c->mkey_be;
 924 #endif
 925         }
 926
 927         INIT_WORK(&rq->dim.work, mlx5e_dim_work);
 928         if (priv->params.rx_cq_moderation_mode < 2) {
 929                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
 930         } else {
 931                 void *cqc = container_of(param,
 932                     struct mlx5e_channel_param, rq)->rx_cq.cqc;
 933
 934                 switch (MLX5_GET(cqc, cqc, cq_period_mode)) {
 935                 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 936                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 937                         break;
 938                 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 939                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 940                         break;
 941                 default:
 942                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
 943                         break;
 944                 }
 945         }
 946
 947         rq->ifp = c->tag.m_snd_tag.ifp;
 948         rq->channel = c;
 949         rq->ix = c->ix;
 950
 951         snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
 952         mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
 953             buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
 954             rq->stats.arg);
 955         return (0);
 956
 957 err_rq_mbuf_free:
 958         free(rq->mbuf, M_MLX5EN);
 959         tcp_lro_free(&rq->lro);
 960 err_rq_wq_destroy:
 961         mlx5_wq_destroy(&rq->wq_ctrl);
 962 err_free_dma_tag:
 963         bus_dma_tag_destroy(rq->dma_tag);
 964 done:
 965         return (err);
 966 }
 967
 968 static void
 969 mlx5e_destroy_rq(struct mlx5e_rq *rq)
 970 {
 971         int wq_sz;
 972         int i;
 973
 974         /* destroy all sysctl nodes */
 975         sysctl_ctx_free(&rq->stats.ctx);
 976
 977         /* free leftover LRO packets, if any */
 978         tcp_lro_free(&rq->lro);
 979
 980         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 981         for (i = 0; i != wq_sz; i++) {
 982                 if (rq->mbuf[i].mbuf != NULL) {
 983                         bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map);
 984                         m_freem(rq->mbuf[i].mbuf);
 985                 }
 986                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 987         }
 988         free(rq->mbuf, M_MLX5EN);
 989         mlx5_wq_destroy(&rq->wq_ctrl);
 990 }
 991
 992 static int
 993 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 994 {
 995         struct mlx5e_channel *c = rq->channel;
 996         struct mlx5e_priv *priv = c->priv;
 997         struct mlx5_core_dev *mdev = priv->mdev;
 998
 999         void *in;
1000         void *rqc;
1001         void *wq;
1002         int inlen;
1003         int err;
1004
1005         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
1006             sizeof(u64) * rq->wq_ctrl.buf.npages;
1007         in = mlx5_vzalloc(inlen);
1008         if (in == NULL)
1009                 return (-ENOMEM);
1010
1011         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1012         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1013
1014         memcpy(rqc, param->rqc, sizeof(param->rqc));
1015
1016         MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
1017         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1018         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1019         if (priv->counter_set_id >= 0)
1020                 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
1021         MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
1022             PAGE_SHIFT);
1023         MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
1024
1025         mlx5_fill_page_array(&rq->wq_ctrl.buf,
1026             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1027
1028         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
1029
1030         kvfree(in);
1031
1032         return (err);
1033 }
1034
1035 static int
1036 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
1037 {
1038         struct mlx5e_channel *c = rq->channel;
1039         struct mlx5e_priv *priv = c->priv;
1040         struct mlx5_core_dev *mdev = priv->mdev;
1041
1042         void *in;
1043         void *rqc;
1044         int inlen;
1045         int err;
1046
1047         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1048         in = mlx5_vzalloc(inlen);
1049         if (in == NULL)
1050                 return (-ENOMEM);
1051
1052         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1053
1054         MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
1055         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
1056         MLX5_SET(rqc, rqc, state, next_state);
1057
1058         err = mlx5_core_modify_rq(mdev, in, inlen);
1059
1060         kvfree(in);
1061
1062         return (err);
1063 }
1064
1065 static void
1066 mlx5e_disable_rq(struct mlx5e_rq *rq)
1067 {
1068         struct mlx5e_channel *c = rq->channel;
1069         struct mlx5e_priv *priv = c->priv;
1070         struct mlx5_core_dev *mdev = priv->mdev;
1071
1072         mlx5_core_destroy_rq(mdev, rq->rqn);
1073 }
1074
1075 static int
1076 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
1077 {
1078         struct mlx5e_channel *c = rq->channel;
1079         struct mlx5e_priv *priv = c->priv;
1080         struct mlx5_wq_ll *wq = &rq->wq;
1081         int i;
1082
1083         for (i = 0; i < 1000; i++) {
1084                 if (wq->cur_sz >= priv->params.min_rx_wqes)
1085                         return (0);
1086
1087                 msleep(4);
1088         }
1089         return (-ETIMEDOUT);
1090 }
1091
1092 static int
1093 mlx5e_open_rq(struct mlx5e_channel *c,
1094     struct mlx5e_rq_param *param,
1095     struct mlx5e_rq *rq)
1096 {
1097         int err;
1098
1099         err = mlx5e_create_rq(c, param, rq);
1100         if (err)
1101                 return (err);
1102
1103         err = mlx5e_enable_rq(rq, param);
1104         if (err)
1105                 goto err_destroy_rq;
1106
1107         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1108         if (err)
1109                 goto err_disable_rq;
1110
1111         c->rq.enabled = 1;
1112
1113         return (0);
1114
1115 err_disable_rq:
1116         mlx5e_disable_rq(rq);
1117 err_destroy_rq:
1118         mlx5e_destroy_rq(rq);
1119
1120         return (err);
1121 }
1122
1123 static void
1124 mlx5e_close_rq(struct mlx5e_rq *rq)
1125 {
1126         mtx_lock(&rq->mtx);
1127         rq->enabled = 0;
1128         callout_stop(&rq->watchdog);
1129         mtx_unlock(&rq->mtx);
1130
1131         callout_drain(&rq->watchdog);
1132
1133         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
1134 }
1135
1136 static void
1137 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
1138 {
1139         struct mlx5_core_dev *mdev = rq->channel->priv->mdev;
1140
1141         /* wait till RQ is empty */
1142         while (!mlx5_wq_ll_is_empty(&rq->wq) &&
1143                (mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR)) {
1144                 msleep(4);
1145                 rq->cq.mcq.comp(&rq->cq.mcq);
1146         }
1147
1148         cancel_work_sync(&rq->dim.work);
1149         mlx5e_disable_rq(rq);
1150         mlx5e_destroy_rq(rq);
1151 }
1152
1153 void
1154 mlx5e_free_sq_db(struct mlx5e_sq *sq)
1155 {
1156         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1157         int x;
1158
1159         for (x = 0; x != wq_sz; x++)
1160                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1161         free(sq->mbuf, M_MLX5EN);
1162 }
1163
1164 int
1165 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
1166 {
1167         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1168         int err;
1169         int x;
1170
1171         sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1172
1173         /* Create DMA descriptor MAPs */
1174         for (x = 0; x != wq_sz; x++) {
1175                 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
1176                 if (err != 0) {
1177                         while (x--)
1178                                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1179                         free(sq->mbuf, M_MLX5EN);
1180                         return (err);
1181                 }
1182         }
1183         return (0);
1184 }
1185
1186 static const char *mlx5e_sq_stats_desc[] = {
1187         MLX5E_SQ_STATS(MLX5E_STATS_DESC)
1188 };
1189
1190 void
1191 mlx5e_update_sq_inline(struct mlx5e_sq *sq)
1192 {
1193         sq->max_inline = sq->priv->params.tx_max_inline;
1194         sq->min_inline_mode = sq->priv->params.tx_min_inline_mode;
1195
1196         /*
1197          * Check if trust state is DSCP or if inline mode is NONE which
1198          * indicates CX-5 or newer hardware.
1199          */
1200         if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP ||
1201             sq->min_inline_mode == MLX5_INLINE_MODE_NONE) {
1202                 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert))
1203                         sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN;
1204                 else
1205                         sq->min_insert_caps = MLX5E_INSERT_NON_VLAN;
1206         } else {
1207                 sq->min_insert_caps = 0;
1208         }
1209 }
1210
1211 static void
1212 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1213 {
1214         int i;
1215
1216         for (i = 0; i != c->num_tc; i++) {
1217                 mtx_lock(&c->sq[i].lock);
1218                 mlx5e_update_sq_inline(&c->sq[i]);
1219                 mtx_unlock(&c->sq[i].lock);
1220         }
1221 }
1222
1223 void
1224 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv)
1225 {
1226         int i;
1227
1228         /* check if channels are closed */
1229         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
1230                 return;
1231
1232         for (i = 0; i < priv->params.num_channels; i++)
1233                 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]);
1234 }
1235
1236 static int
1237 mlx5e_create_sq(struct mlx5e_channel *c,
1238     int tc,
1239     struct mlx5e_sq_param *param,
1240     struct mlx5e_sq *sq)
1241 {
1242         struct mlx5e_priv *priv = c->priv;
1243         struct mlx5_core_dev *mdev = priv->mdev;
1244         char buffer[16];
1245         void *sqc = param->sqc;
1246         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1247         int err;
1248
1249         /* Create DMA descriptor TAG */
1250         if ((err = -bus_dma_tag_create(
1251             bus_get_dma_tag(mdev->pdev->dev.bsddev),
1252             1,                          /* any alignment */
1253             0,                          /* no boundary */
1254             BUS_SPACE_MAXADDR,          /* lowaddr */
1255             BUS_SPACE_MAXADDR,          /* highaddr */
1256             NULL, NULL,                 /* filter, filterarg */
1257             MLX5E_MAX_TX_PAYLOAD_SIZE,  /* maxsize */
1258             MLX5E_MAX_TX_MBUF_FRAGS,    /* nsegments */
1259             MLX5E_MAX_TX_MBUF_SIZE,     /* maxsegsize */
1260             0,                          /* flags */
1261             NULL, NULL,                 /* lockfunc, lockfuncarg */
1262             &sq->dma_tag)))
1263                 goto done;
1264
1265         err = mlx5_alloc_map_uar(mdev, &sq->uar);
1266         if (err)
1267                 goto err_free_dma_tag;
1268
1269         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
1270             &sq->wq_ctrl);
1271         if (err)
1272                 goto err_unmap_free_uar;
1273
1274         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1275         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1276
1277         err = mlx5e_alloc_sq_db(sq);
1278         if (err)
1279                 goto err_sq_wq_destroy;
1280
1281         sq->mkey_be = c->mkey_be;
1282         sq->ifp = priv->ifp;
1283         sq->priv = priv;
1284         sq->tc = tc;
1285
1286         mlx5e_update_sq_inline(sq);
1287
1288         snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1289         mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1290             buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1291             sq->stats.arg);
1292
1293         return (0);
1294
1295 err_sq_wq_destroy:
1296         mlx5_wq_destroy(&sq->wq_ctrl);
1297
1298 err_unmap_free_uar:
1299         mlx5_unmap_free_uar(mdev, &sq->uar);
1300
1301 err_free_dma_tag:
1302         bus_dma_tag_destroy(sq->dma_tag);
1303 done:
1304         return (err);
1305 }
1306
1307 static void
1308 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1309 {
1310         /* destroy all sysctl nodes */
1311         sysctl_ctx_free(&sq->stats.ctx);
1312
1313         mlx5e_free_sq_db(sq);
1314         mlx5_wq_destroy(&sq->wq_ctrl);
1315         mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1316 }
1317
1318 int
1319 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1320     int tis_num)
1321 {
1322         void *in;
1323         void *sqc;
1324         void *wq;
1325         int inlen;
1326         int err;
1327
1328         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1329             sizeof(u64) * sq->wq_ctrl.buf.npages;
1330         in = mlx5_vzalloc(inlen);
1331         if (in == NULL)
1332                 return (-ENOMEM);
1333
1334         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1335         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1336
1337         memcpy(sqc, param->sqc, sizeof(param->sqc));
1338
1339         MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1340         MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1341         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1342         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1343         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1344
1345         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1346         MLX5_SET(wq, wq, uar_page, sq->uar.index);
1347         MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1348             PAGE_SHIFT);
1349         MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1350
1351         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1352             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1353
1354         err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1355
1356         kvfree(in);
1357
1358         return (err);
1359 }
1360
1361 int
1362 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1363 {
1364         void *in;
1365         void *sqc;
1366         int inlen;
1367         int err;
1368
1369         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1370         in = mlx5_vzalloc(inlen);
1371         if (in == NULL)
1372                 return (-ENOMEM);
1373
1374         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1375
1376         MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1377         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1378         MLX5_SET(sqc, sqc, state, next_state);
1379
1380         err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1381
1382         kvfree(in);
1383
1384         return (err);
1385 }
1386
1387 void
1388 mlx5e_disable_sq(struct mlx5e_sq *sq)
1389 {
1390
1391         mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1392 }
1393
1394 static int
1395 mlx5e_open_sq(struct mlx5e_channel *c,
1396     int tc,
1397     struct mlx5e_sq_param *param,
1398     struct mlx5e_sq *sq)
1399 {
1400         int err;
1401
1402         err = mlx5e_create_sq(c, tc, param, sq);
1403         if (err)
1404                 return (err);
1405
1406         err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1407         if (err)
1408                 goto err_destroy_sq;
1409
1410         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1411         if (err)
1412                 goto err_disable_sq;
1413
1414         WRITE_ONCE(sq->running, 1);
1415
1416         return (0);
1417
1418 err_disable_sq:
1419         mlx5e_disable_sq(sq);
1420 err_destroy_sq:
1421         mlx5e_destroy_sq(sq);
1422
1423         return (err);
1424 }
1425
1426 static void
1427 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1428 {
1429         /* fill up remainder with NOPs */
1430         while (sq->cev_counter != 0) {
1431                 while (!mlx5e_sq_has_room_for(sq, 1)) {
1432                         if (can_sleep != 0) {
1433                                 mtx_unlock(&sq->lock);
1434                                 msleep(4);
1435                                 mtx_lock(&sq->lock);
1436                         } else {
1437                                 goto done;
1438                         }
1439                 }
1440                 /* send a single NOP */
1441                 mlx5e_send_nop(sq, 1);
1442                 atomic_thread_fence_rel();
1443         }
1444 done:
1445         /* Check if we need to write the doorbell */
1446         if (likely(sq->doorbell.d64 != 0)) {
1447                 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1448                 sq->doorbell.d64 = 0;
1449         }
1450 }
1451
1452 void
1453 mlx5e_sq_cev_timeout(void *arg)
1454 {
1455         struct mlx5e_sq *sq = arg;
1456
1457         mtx_assert(&sq->lock, MA_OWNED);
1458
1459         /* check next state */
1460         switch (sq->cev_next_state) {
1461         case MLX5E_CEV_STATE_SEND_NOPS:
1462                 /* fill TX ring with NOPs, if any */
1463                 mlx5e_sq_send_nops_locked(sq, 0);
1464
1465                 /* check if completed */
1466                 if (sq->cev_counter == 0) {
1467                         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1468                         return;
1469                 }
1470                 break;
1471         default:
1472                 /* send NOPs on next timeout */
1473                 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1474                 break;
1475         }
1476
1477         /* restart timer */
1478         callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1479 }
1480
1481 void
1482 mlx5e_drain_sq(struct mlx5e_sq *sq)
1483 {
1484         int error;
1485         struct mlx5_core_dev *mdev= sq->priv->mdev;
1486
1487         /*
1488          * Check if already stopped.
1489          *
1490          * NOTE: Serialization of this function is managed by the
1491          * caller ensuring the priv's state lock is locked or in case
1492          * of rate limit support, a single thread manages drain and
1493          * resume of SQs. The "running" variable can therefore safely
1494          * be read without any locks.
1495          */
1496         if (READ_ONCE(sq->running) == 0)
1497                 return;
1498
1499         /* don't put more packets into the SQ */
1500         WRITE_ONCE(sq->running, 0);
1501
1502         /* serialize access to DMA rings */
1503         mtx_lock(&sq->lock);
1504
1505         /* teardown event factor timer, if any */
1506         sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1507         callout_stop(&sq->cev_callout);
1508
1509         /* send dummy NOPs in order to flush the transmit ring */
1510         mlx5e_sq_send_nops_locked(sq, 1);
1511         mtx_unlock(&sq->lock);
1512
1513         /* make sure it is safe to free the callout */
1514         callout_drain(&sq->cev_callout);
1515
1516         /* wait till SQ is empty or link is down */
1517         mtx_lock(&sq->lock);
1518         while (sq->cc != sq->pc &&
1519             (sq->priv->media_status_last & IFM_ACTIVE) != 0 &&
1520             mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1521                 mtx_unlock(&sq->lock);
1522                 msleep(1);
1523                 sq->cq.mcq.comp(&sq->cq.mcq);
1524                 mtx_lock(&sq->lock);
1525         }
1526         mtx_unlock(&sq->lock);
1527
1528         /* error out remaining requests */
1529         error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1530         if (error != 0) {
1531                 if_printf(sq->ifp,
1532                     "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error);
1533         }
1534
1535         /* wait till SQ is empty */
1536         mtx_lock(&sq->lock);
1537         while (sq->cc != sq->pc &&
1538                mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1539                 mtx_unlock(&sq->lock);
1540                 msleep(1);
1541                 sq->cq.mcq.comp(&sq->cq.mcq);
1542                 mtx_lock(&sq->lock);
1543         }
1544         mtx_unlock(&sq->lock);
1545 }
1546
1547 static void
1548 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1549 {
1550
1551         mlx5e_drain_sq(sq);
1552         mlx5e_disable_sq(sq);
1553         mlx5e_destroy_sq(sq);
1554 }
1555
1556 static int
1557 mlx5e_create_cq(struct mlx5e_priv *priv,
1558     struct mlx5e_cq_param *param,
1559     struct mlx5e_cq *cq,
1560     mlx5e_cq_comp_t *comp,
1561     int eq_ix)
1562 {
1563         struct mlx5_core_dev *mdev = priv->mdev;
1564         struct mlx5_core_cq *mcq = &cq->mcq;
1565         int eqn_not_used;
1566         int irqn;
1567         int err;
1568         u32 i;
1569
1570         param->wq.buf_numa_node = 0;
1571         param->wq.db_numa_node = 0;
1572
1573         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1574             &cq->wq_ctrl);
1575         if (err)
1576                 return (err);
1577
1578         mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1579
1580         mcq->cqe_sz = 64;
1581         mcq->set_ci_db = cq->wq_ctrl.db.db;
1582         mcq->arm_db = cq->wq_ctrl.db.db + 1;
1583         *mcq->set_ci_db = 0;
1584         *mcq->arm_db = 0;
1585         mcq->vector = eq_ix;
1586         mcq->comp = comp;
1587         mcq->event = mlx5e_cq_error_event;
1588         mcq->irqn = irqn;
1589         mcq->uar = &priv->cq_uar;
1590
1591         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1592                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1593
1594                 cqe->op_own = 0xf1;
1595         }
1596
1597         cq->priv = priv;
1598
1599         return (0);
1600 }
1601
1602 static void
1603 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1604 {
1605         mlx5_wq_destroy(&cq->wq_ctrl);
1606 }
1607
1608 static int
1609 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1610 {
1611         struct mlx5_core_cq *mcq = &cq->mcq;
1612         void *in;
1613         void *cqc;
1614         int inlen;
1615         int irqn_not_used;
1616         int eqn;
1617         int err;
1618
1619         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1620             sizeof(u64) * cq->wq_ctrl.buf.npages;
1621         in = mlx5_vzalloc(inlen);
1622         if (in == NULL)
1623                 return (-ENOMEM);
1624
1625         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1626
1627         memcpy(cqc, param->cqc, sizeof(param->cqc));
1628
1629         mlx5_fill_page_array(&cq->wq_ctrl.buf,
1630             (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1631
1632         mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
1633
1634         MLX5_SET(cqc, cqc, c_eqn, eqn);
1635         MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1636         MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1637             PAGE_SHIFT);
1638         MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1639
1640         err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
1641
1642         kvfree(in);
1643
1644         if (err)
1645                 return (err);
1646
1647         mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock));
1648
1649         return (0);
1650 }
1651
1652 static void
1653 mlx5e_disable_cq(struct mlx5e_cq *cq)
1654 {
1655
1656         mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
1657 }
1658
1659 int
1660 mlx5e_open_cq(struct mlx5e_priv *priv,
1661     struct mlx5e_cq_param *param,
1662     struct mlx5e_cq *cq,
1663     mlx5e_cq_comp_t *comp,
1664     int eq_ix)
1665 {
1666         int err;
1667
1668         err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
1669         if (err)
1670                 return (err);
1671
1672         err = mlx5e_enable_cq(cq, param, eq_ix);
1673         if (err)
1674                 goto err_destroy_cq;
1675
1676         return (0);
1677
1678 err_destroy_cq:
1679         mlx5e_destroy_cq(cq);
1680
1681         return (err);
1682 }
1683
1684 void
1685 mlx5e_close_cq(struct mlx5e_cq *cq)
1686 {
1687         mlx5e_disable_cq(cq);
1688         mlx5e_destroy_cq(cq);
1689 }
1690
1691 static int
1692 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1693     struct mlx5e_channel_param *cparam)
1694 {
1695         int err;
1696         int tc;
1697
1698         for (tc = 0; tc < c->num_tc; tc++) {
1699                 /* open completion queue */
1700                 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
1701                     &mlx5e_tx_cq_comp, c->ix);
1702                 if (err)
1703                         goto err_close_tx_cqs;
1704         }
1705         return (0);
1706
1707 err_close_tx_cqs:
1708         for (tc--; tc >= 0; tc--)
1709                 mlx5e_close_cq(&c->sq[tc].cq);
1710
1711         return (err);
1712 }
1713
1714 static void
1715 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1716 {
1717         int tc;
1718
1719         for (tc = 0; tc < c->num_tc; tc++)
1720                 mlx5e_close_cq(&c->sq[tc].cq);
1721 }
1722
1723 static int
1724 mlx5e_open_sqs(struct mlx5e_channel *c,
1725     struct mlx5e_channel_param *cparam)
1726 {
1727         int err;
1728         int tc;
1729
1730         for (tc = 0; tc < c->num_tc; tc++) {
1731                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1732                 if (err)
1733                         goto err_close_sqs;
1734         }
1735
1736         return (0);
1737
1738 err_close_sqs:
1739         for (tc--; tc >= 0; tc--)
1740                 mlx5e_close_sq_wait(&c->sq[tc]);
1741
1742         return (err);
1743 }
1744
1745 static void
1746 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
1747 {
1748         int tc;
1749
1750         for (tc = 0; tc < c->num_tc; tc++)
1751                 mlx5e_close_sq_wait(&c->sq[tc]);
1752 }
1753
1754 static void
1755 mlx5e_chan_mtx_init(struct mlx5e_channel *c)
1756 {
1757         int tc;
1758
1759         mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
1760
1761         callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
1762
1763         for (tc = 0; tc < c->num_tc; tc++) {
1764                 struct mlx5e_sq *sq = c->sq + tc;
1765
1766                 mtx_init(&sq->lock, "mlx5tx",
1767                     MTX_NETWORK_LOCK " TX", MTX_DEF);
1768                 mtx_init(&sq->comp_lock, "mlx5comp",
1769                     MTX_NETWORK_LOCK " TX", MTX_DEF);
1770
1771                 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
1772
1773                 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1774
1775                 /* ensure the TX completion event factor is not zero */
1776                 if (sq->cev_factor == 0)
1777                         sq->cev_factor = 1;
1778         }
1779 }
1780
1781 static void
1782 mlx5e_chan_mtx_destroy(struct mlx5e_channel *c)
1783 {
1784         int tc;
1785
1786         mtx_destroy(&c->rq.mtx);
1787
1788         for (tc = 0; tc < c->num_tc; tc++) {
1789                 mtx_destroy(&c->sq[tc].lock);
1790                 mtx_destroy(&c->sq[tc].comp_lock);
1791         }
1792 }
1793
1794 static int
1795 mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1796     struct mlx5e_channel_param *cparam,
1797     struct mlx5e_channel *c)
1798 {
1799         int err;
1800
1801         memset(c, 0, sizeof(*c));
1802
1803         c->priv = priv;
1804         c->ix = ix;
1805         /* setup send tag */
1806         c->tag.m_snd_tag.ifp = priv->ifp;
1807         c->tag.type = IF_SND_TAG_TYPE_UNLIMITED;
1808         c->mkey_be = cpu_to_be32(priv->mr.key);
1809         c->num_tc = priv->num_tc;
1810
1811         /* init mutexes */
1812         mlx5e_chan_mtx_init(c);
1813
1814         /* open transmit completion queue */
1815         err = mlx5e_open_tx_cqs(c, cparam);
1816         if (err)
1817                 goto err_free;
1818
1819         /* open receive completion queue */
1820         err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
1821             &mlx5e_rx_cq_comp, c->ix);
1822         if (err)
1823                 goto err_close_tx_cqs;
1824
1825         err = mlx5e_open_sqs(c, cparam);
1826         if (err)
1827                 goto err_close_rx_cq;
1828
1829         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1830         if (err)
1831                 goto err_close_sqs;
1832
1833         /* poll receive queue initially */
1834         c->rq.cq.mcq.comp(&c->rq.cq.mcq);
1835
1836         return (0);
1837
1838 err_close_sqs:
1839         mlx5e_close_sqs_wait(c);
1840
1841 err_close_rx_cq:
1842         mlx5e_close_cq(&c->rq.cq);
1843
1844 err_close_tx_cqs:
1845         mlx5e_close_tx_cqs(c);
1846
1847 err_free:
1848         /* destroy mutexes */
1849         mlx5e_chan_mtx_destroy(c);
1850         return (err);
1851 }
1852
1853 static void
1854 mlx5e_close_channel(struct mlx5e_channel *c)
1855 {
1856         mlx5e_close_rq(&c->rq);
1857 }
1858
1859 static void
1860 mlx5e_close_channel_wait(struct mlx5e_channel *c)
1861 {
1862         mlx5e_close_rq_wait(&c->rq);
1863         mlx5e_close_sqs_wait(c);
1864         mlx5e_close_cq(&c->rq.cq);
1865         mlx5e_close_tx_cqs(c);
1866         /* destroy mutexes */
1867         mlx5e_chan_mtx_destroy(c);
1868 }
1869
1870 static int
1871 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs)
1872 {
1873         u32 r, n;
1874
1875         r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz :
1876             MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
1877         if (r > MJUM16BYTES)
1878                 return (-ENOMEM);
1879
1880         if (r > MJUM9BYTES)
1881                 r = MJUM16BYTES;
1882         else if (r > MJUMPAGESIZE)
1883                 r = MJUM9BYTES;
1884         else if (r > MCLBYTES)
1885                 r = MJUMPAGESIZE;
1886         else
1887                 r = MCLBYTES;
1888
1889         /*
1890          * n + 1 must be a power of two, because stride size must be.
1891          * Stride size is 16 * (n + 1), as the first segment is
1892          * control.
1893          */
1894         for (n = howmany(r, MLX5E_MAX_RX_BYTES); !powerof2(n + 1); n++)
1895                 ;
1896
1897         *wqe_sz = r;
1898         *nsegs = n;
1899         return (0);
1900 }
1901
1902 static void
1903 mlx5e_build_rq_param(struct mlx5e_priv *priv,
1904     struct mlx5e_rq_param *param)
1905 {
1906         void *rqc = param->rqc;
1907         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1908         u32 wqe_sz, nsegs;
1909
1910         mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
1911         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1912         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1913         MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) +
1914             nsegs * sizeof(struct mlx5_wqe_data_seg)));
1915         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1916         MLX5_SET(wq, wq, pd, priv->pdn);
1917
1918         param->wq.buf_numa_node = 0;
1919         param->wq.db_numa_node = 0;
1920         param->wq.linear = 1;
1921 }
1922
1923 static void
1924 mlx5e_build_sq_param(struct mlx5e_priv *priv,
1925     struct mlx5e_sq_param *param)
1926 {
1927         void *sqc = param->sqc;
1928         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1929
1930         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1931         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1932         MLX5_SET(wq, wq, pd, priv->pdn);
1933
1934         param->wq.buf_numa_node = 0;
1935         param->wq.db_numa_node = 0;
1936         param->wq.linear = 1;
1937 }
1938
1939 static void
1940 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1941     struct mlx5e_cq_param *param)
1942 {
1943         void *cqc = param->cqc;
1944
1945         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1946 }
1947
1948 static void
1949 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr)
1950 {
1951
1952         *ptr = net_dim_get_profile(mode, MLX5E_DIM_DEFAULT_PROFILE);
1953
1954         /* apply LRO restrictions */
1955         if (priv->params.hw_lro_en &&
1956             ptr->pkts > MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO) {
1957                 ptr->pkts = MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO;
1958         }
1959 }
1960
1961 static void
1962 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1963     struct mlx5e_cq_param *param)
1964 {
1965         struct net_dim_cq_moder curr;
1966         void *cqc = param->cqc;
1967
1968
1969         /*
1970          * TODO The sysctl to control on/off is a bool value for now, which means
1971          * we only support CSUM, once HASH is implemnted we'll need to address that.
1972          */
1973         if (priv->params.cqe_zipping_en) {
1974                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1975                 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
1976         }
1977
1978         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1979
1980         switch (priv->params.rx_cq_moderation_mode) {
1981         case 0:
1982                 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1983                 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1984                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1985                 break;
1986         case 1:
1987                 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1988                 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1989                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1990                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1991                 else
1992                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1993                 break;
1994         case 2:
1995                 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr);
1996                 MLX5_SET(cqc, cqc, cq_period, curr.usec);
1997                 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
1998                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1999                 break;
2000         case 3:
2001                 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr);
2002                 MLX5_SET(cqc, cqc, cq_period, curr.usec);
2003                 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
2004                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2005                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2006                 else
2007                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2008                 break;
2009         default:
2010                 break;
2011         }
2012
2013         mlx5e_dim_build_cq_param(priv, param);
2014
2015         mlx5e_build_common_cq_param(priv, param);
2016 }
2017
2018 static void
2019 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2020     struct mlx5e_cq_param *param)
2021 {
2022         void *cqc = param->cqc;
2023
2024         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
2025         MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
2026         MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
2027
2028         switch (priv->params.tx_cq_moderation_mode) {
2029         case 0:
2030                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2031                 break;
2032         default:
2033                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2034                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2035                 else
2036                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2037                 break;
2038         }
2039
2040         mlx5e_build_common_cq_param(priv, param);
2041 }
2042
2043 static void
2044 mlx5e_build_channel_param(struct mlx5e_priv *priv,
2045     struct mlx5e_channel_param *cparam)
2046 {
2047         memset(cparam, 0, sizeof(*cparam));
2048
2049         mlx5e_build_rq_param(priv, &cparam->rq);
2050         mlx5e_build_sq_param(priv, &cparam->sq);
2051         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
2052         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
2053 }
2054
2055 static int
2056 mlx5e_open_channels(struct mlx5e_priv *priv)
2057 {
2058         struct mlx5e_channel_param cparam;
2059         int err;
2060         int i;
2061         int j;
2062
2063         mlx5e_build_channel_param(priv, &cparam);
2064         for (i = 0; i < priv->params.num_channels; i++) {
2065                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
2066                 if (err)
2067                         goto err_close_channels;
2068         }
2069
2070         for (j = 0; j < priv->params.num_channels; j++) {
2071                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j].rq);
2072                 if (err)
2073                         goto err_close_channels;
2074         }
2075         return (0);
2076
2077 err_close_channels:
2078         while (i--) {
2079                 mlx5e_close_channel(&priv->channel[i]);
2080                 mlx5e_close_channel_wait(&priv->channel[i]);
2081         }
2082         return (err);
2083 }
2084
2085 static void
2086 mlx5e_close_channels(struct mlx5e_priv *priv)
2087 {
2088         int i;
2089
2090         for (i = 0; i < priv->params.num_channels; i++)
2091                 mlx5e_close_channel(&priv->channel[i]);
2092         for (i = 0; i < priv->params.num_channels; i++)
2093                 mlx5e_close_channel_wait(&priv->channel[i]);
2094 }
2095
2096 static int
2097 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
2098 {
2099
2100         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2101                 uint8_t cq_mode;
2102
2103                 switch (priv->params.tx_cq_moderation_mode) {
2104                 case 0:
2105                 case 2:
2106                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2107                         break;
2108                 default:
2109                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2110                         break;
2111                 }
2112
2113                 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq,
2114                     priv->params.tx_cq_moderation_usec,
2115                     priv->params.tx_cq_moderation_pkts,
2116                     cq_mode));
2117         }
2118
2119         return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
2120             priv->params.tx_cq_moderation_usec,
2121             priv->params.tx_cq_moderation_pkts));
2122 }
2123
2124 static int
2125 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
2126 {
2127
2128         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2129                 uint8_t cq_mode;
2130                 uint8_t dim_mode;
2131                 int retval;
2132
2133                 switch (priv->params.rx_cq_moderation_mode) {
2134                 case 0:
2135                 case 2:
2136                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2137                         dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2138                         break;
2139                 default:
2140                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2141                         dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
2142                         break;
2143                 }
2144
2145                 /* tear down dynamic interrupt moderation */
2146                 mtx_lock(&rq->mtx);
2147                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
2148                 mtx_unlock(&rq->mtx);
2149
2150                 /* wait for dynamic interrupt moderation work task, if any */
2151                 cancel_work_sync(&rq->dim.work);
2152
2153                 if (priv->params.rx_cq_moderation_mode >= 2) {
2154                         struct net_dim_cq_moder curr;
2155
2156                         mlx5e_get_default_profile(priv, dim_mode, &curr);
2157
2158                         retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2159                             curr.usec, curr.pkts, cq_mode);
2160
2161                         /* set dynamic interrupt moderation mode and zero defaults */
2162                         mtx_lock(&rq->mtx);
2163                         rq->dim.mode = dim_mode;
2164                         rq->dim.state = 0;
2165                         rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE;
2166                         mtx_unlock(&rq->mtx);
2167                 } else {
2168                         retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2169                             priv->params.rx_cq_moderation_usec,
2170                             priv->params.rx_cq_moderation_pkts,
2171                             cq_mode);
2172                 }
2173                 return (retval);
2174         }
2175
2176         return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
2177             priv->params.rx_cq_moderation_usec,
2178             priv->params.rx_cq_moderation_pkts));
2179 }
2180
2181 static int
2182 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
2183 {
2184         int err;
2185         int i;
2186
2187         err = mlx5e_refresh_rq_params(priv, &c->rq);
2188         if (err)
2189                 goto done;
2190
2191         for (i = 0; i != c->num_tc; i++) {
2192                 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
2193                 if (err)
2194                         goto done;
2195         }
2196 done:
2197         return (err);
2198 }
2199
2200 int
2201 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
2202 {
2203         int i;
2204
2205         /* check if channels are closed */
2206         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2207                 return (EINVAL);
2208
2209         for (i = 0; i < priv->params.num_channels; i++) {
2210                 int err;
2211
2212                 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]);
2213                 if (err)
2214                         return (err);
2215         }
2216         return (0);
2217 }
2218
2219 static int
2220 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
2221 {
2222         struct mlx5_core_dev *mdev = priv->mdev;
2223         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
2224         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2225
2226         memset(in, 0, sizeof(in));
2227
2228         MLX5_SET(tisc, tisc, prio, tc);
2229         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
2230
2231         return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
2232 }
2233
2234 static void
2235 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
2236 {
2237         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2238 }
2239
2240 static int
2241 mlx5e_open_tises(struct mlx5e_priv *priv)
2242 {
2243         int num_tc = priv->num_tc;
2244         int err;
2245         int tc;
2246
2247         for (tc = 0; tc < num_tc; tc++) {
2248                 err = mlx5e_open_tis(priv, tc);
2249                 if (err)
2250                         goto err_close_tises;
2251         }
2252
2253         return (0);
2254
2255 err_close_tises:
2256         for (tc--; tc >= 0; tc--)
2257                 mlx5e_close_tis(priv, tc);
2258
2259         return (err);
2260 }
2261
2262 static void
2263 mlx5e_close_tises(struct mlx5e_priv *priv)
2264 {
2265         int num_tc = priv->num_tc;
2266         int tc;
2267
2268         for (tc = 0; tc < num_tc; tc++)
2269                 mlx5e_close_tis(priv, tc);
2270 }
2271
2272 static int
2273 mlx5e_open_rqt(struct mlx5e_priv *priv)
2274 {
2275         struct mlx5_core_dev *mdev = priv->mdev;
2276         u32 *in;
2277         u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
2278         void *rqtc;
2279         int inlen;
2280         int err;
2281         int sz;
2282         int i;
2283
2284         sz = 1 << priv->params.rx_hash_log_tbl_sz;
2285
2286         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2287         in = mlx5_vzalloc(inlen);
2288         if (in == NULL)
2289                 return (-ENOMEM);
2290         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2291
2292         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2293         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2294
2295         for (i = 0; i < sz; i++) {
2296                 int ix = i;
2297 #ifdef RSS
2298                 ix = rss_get_indirection_to_bucket(ix);
2299 #endif
2300                 /* ensure we don't overflow */
2301                 ix %= priv->params.num_channels;
2302
2303                 /* apply receive side scaling stride, if any */
2304                 ix -= ix % (int)priv->params.channels_rsss;
2305
2306                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn);
2307         }
2308
2309         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
2310
2311         err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
2312         if (!err)
2313                 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
2314
2315         kvfree(in);
2316
2317         return (err);
2318 }
2319
2320 static void
2321 mlx5e_close_rqt(struct mlx5e_priv *priv)
2322 {
2323         u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0};
2324         u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0};
2325
2326         MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
2327         MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
2328
2329         mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out));
2330 }
2331
2332 static void
2333 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
2334 {
2335         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2336         __be32 *hkey;
2337
2338         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2339
2340 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2341
2342 #define MLX5_HASH_IP     (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2343                           MLX5_HASH_FIELD_SEL_DST_IP)
2344
2345 #define MLX5_HASH_ALL    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2346                           MLX5_HASH_FIELD_SEL_DST_IP   |\
2347                           MLX5_HASH_FIELD_SEL_L4_SPORT |\
2348                           MLX5_HASH_FIELD_SEL_L4_DPORT)
2349
2350 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2351                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2352                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2353
2354         if (priv->params.hw_lro_en) {
2355                 MLX5_SET(tirc, tirc, lro_enable_mask,
2356                     MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2357                     MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2358                 MLX5_SET(tirc, tirc, lro_max_msg_sz,
2359                     (priv->params.lro_wqe_sz -
2360                     ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2361                 /* TODO: add the option to choose timer value dynamically */
2362                 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
2363                     MLX5_CAP_ETH(priv->mdev,
2364                     lro_timer_supported_periods[2]));
2365         }
2366
2367         /* setup parameters for hashing TIR type, if any */
2368         switch (tt) {
2369         case MLX5E_TT_ANY:
2370                 MLX5_SET(tirc, tirc, disp_type,
2371                     MLX5_TIRC_DISP_TYPE_DIRECT);
2372                 MLX5_SET(tirc, tirc, inline_rqn,
2373                     priv->channel[0].rq.rqn);
2374                 break;
2375         default:
2376                 MLX5_SET(tirc, tirc, disp_type,
2377                     MLX5_TIRC_DISP_TYPE_INDIRECT);
2378                 MLX5_SET(tirc, tirc, indirect_table,
2379                     priv->rqtn);
2380                 MLX5_SET(tirc, tirc, rx_hash_fn,
2381                     MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
2382                 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
2383 #ifdef RSS
2384                 /*
2385                  * The FreeBSD RSS implementation does currently not
2386                  * support symmetric Toeplitz hashes:
2387                  */
2388                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
2389                 rss_getkey((uint8_t *)hkey);
2390 #else
2391                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2392                 hkey[0] = cpu_to_be32(0xD181C62C);
2393                 hkey[1] = cpu_to_be32(0xF7F4DB5B);
2394                 hkey[2] = cpu_to_be32(0x1983A2FC);
2395                 hkey[3] = cpu_to_be32(0x943E1ADB);
2396                 hkey[4] = cpu_to_be32(0xD9389E6B);
2397                 hkey[5] = cpu_to_be32(0xD1039C2C);
2398                 hkey[6] = cpu_to_be32(0xA74499AD);
2399                 hkey[7] = cpu_to_be32(0x593D56D9);
2400                 hkey[8] = cpu_to_be32(0xF3253C06);
2401                 hkey[9] = cpu_to_be32(0x2ADC1FFC);
2402 #endif
2403                 break;
2404         }
2405
2406         switch (tt) {
2407         case MLX5E_TT_IPV4_TCP:
2408                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2409                     MLX5_L3_PROT_TYPE_IPV4);
2410                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2411                     MLX5_L4_PROT_TYPE_TCP);
2412 #ifdef RSS
2413                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2414                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2415                             MLX5_HASH_IP);
2416                 } else
2417 #endif
2418                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2419                     MLX5_HASH_ALL);
2420                 break;
2421
2422         case MLX5E_TT_IPV6_TCP:
2423                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2424                     MLX5_L3_PROT_TYPE_IPV6);
2425                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2426                     MLX5_L4_PROT_TYPE_TCP);
2427 #ifdef RSS
2428                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2429                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2430                             MLX5_HASH_IP);
2431                 } else
2432 #endif
2433                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2434                     MLX5_HASH_ALL);
2435                 break;
2436
2437         case MLX5E_TT_IPV4_UDP:
2438                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2439                     MLX5_L3_PROT_TYPE_IPV4);
2440                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2441                     MLX5_L4_PROT_TYPE_UDP);
2442 #ifdef RSS
2443                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2444                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2445                             MLX5_HASH_IP);
2446                 } else
2447 #endif
2448                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2449                     MLX5_HASH_ALL);
2450                 break;
2451
2452         case MLX5E_TT_IPV6_UDP:
2453                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2454                     MLX5_L3_PROT_TYPE_IPV6);
2455                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2456                     MLX5_L4_PROT_TYPE_UDP);
2457 #ifdef RSS
2458                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2459                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2460                             MLX5_HASH_IP);
2461                 } else
2462 #endif
2463                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2464                     MLX5_HASH_ALL);
2465                 break;
2466
2467         case MLX5E_TT_IPV4_IPSEC_AH:
2468                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2469                     MLX5_L3_PROT_TYPE_IPV4);
2470                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2471                     MLX5_HASH_IP_IPSEC_SPI);
2472                 break;
2473
2474         case MLX5E_TT_IPV6_IPSEC_AH:
2475                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2476                     MLX5_L3_PROT_TYPE_IPV6);
2477                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2478                     MLX5_HASH_IP_IPSEC_SPI);
2479                 break;
2480
2481         case MLX5E_TT_IPV4_IPSEC_ESP:
2482                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2483                     MLX5_L3_PROT_TYPE_IPV4);
2484                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2485                     MLX5_HASH_IP_IPSEC_SPI);
2486                 break;
2487
2488         case MLX5E_TT_IPV6_IPSEC_ESP:
2489                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2490                     MLX5_L3_PROT_TYPE_IPV6);
2491                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2492                     MLX5_HASH_IP_IPSEC_SPI);
2493                 break;
2494
2495         case MLX5E_TT_IPV4:
2496                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2497                     MLX5_L3_PROT_TYPE_IPV4);
2498                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2499                     MLX5_HASH_IP);
2500                 break;
2501
2502         case MLX5E_TT_IPV6:
2503                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2504                     MLX5_L3_PROT_TYPE_IPV6);
2505                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2506                     MLX5_HASH_IP);
2507                 break;
2508
2509         default:
2510                 break;
2511         }
2512 }
2513
2514 static int
2515 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2516 {
2517         struct mlx5_core_dev *mdev = priv->mdev;
2518         u32 *in;
2519         void *tirc;
2520         int inlen;
2521         int err;
2522
2523         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2524         in = mlx5_vzalloc(inlen);
2525         if (in == NULL)
2526                 return (-ENOMEM);
2527         tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2528
2529         mlx5e_build_tir_ctx(priv, tirc, tt);
2530
2531         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2532
2533         kvfree(in);
2534
2535         return (err);
2536 }
2537
2538 static void
2539 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2540 {
2541         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2542 }
2543
2544 static int
2545 mlx5e_open_tirs(struct mlx5e_priv *priv)
2546 {
2547         int err;
2548         int i;
2549
2550         for (i = 0; i < MLX5E_NUM_TT; i++) {
2551                 err = mlx5e_open_tir(priv, i);
2552                 if (err)
2553                         goto err_close_tirs;
2554         }
2555
2556         return (0);
2557
2558 err_close_tirs:
2559         for (i--; i >= 0; i--)
2560                 mlx5e_close_tir(priv, i);
2561
2562         return (err);
2563 }
2564
2565 static void
2566 mlx5e_close_tirs(struct mlx5e_priv *priv)
2567 {
2568         int i;
2569
2570         for (i = 0; i < MLX5E_NUM_TT; i++)
2571                 mlx5e_close_tir(priv, i);
2572 }
2573
2574 /*
2575  * SW MTU does not include headers,
2576  * HW MTU includes all headers and checksums.
2577  */
2578 static int
2579 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2580 {
2581         struct mlx5e_priv *priv = ifp->if_softc;
2582         struct mlx5_core_dev *mdev = priv->mdev;
2583         int hw_mtu;
2584         int err;
2585
2586         hw_mtu = MLX5E_SW2HW_MTU(sw_mtu);
2587
2588         err = mlx5_set_port_mtu(mdev, hw_mtu);
2589         if (err) {
2590                 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n",
2591                     __func__, sw_mtu, err);
2592                 return (err);
2593         }
2594
2595         /* Update vport context MTU */
2596         err = mlx5_set_vport_mtu(mdev, hw_mtu);
2597         if (err) {
2598                 if_printf(ifp, "%s: Failed updating vport context with MTU size, err=%d\n",
2599                     __func__, err);
2600         }
2601
2602         ifp->if_mtu = sw_mtu;
2603
2604         err = mlx5_query_vport_mtu(mdev, &hw_mtu);
2605         if (err || !hw_mtu) {
2606                 /* fallback to port oper mtu */
2607                 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2608         }
2609         if (err) {
2610                 if_printf(ifp, "Query port MTU, after setting new "
2611                     "MTU value, failed\n");
2612                 return (err);
2613         } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
2614                 err = -E2BIG,
2615                 if_printf(ifp, "Port MTU %d is smaller than "
2616                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2617         } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
2618                 err = -EINVAL;
2619                 if_printf(ifp, "Port MTU %d is bigger than "
2620                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2621         }
2622         priv->params_ethtool.hw_mtu = hw_mtu;
2623
2624         return (err);
2625 }
2626
2627 int
2628 mlx5e_open_locked(struct ifnet *ifp)
2629 {
2630         struct mlx5e_priv *priv = ifp->if_softc;
2631         int err;
2632         u16 set_id;
2633
2634         /* check if already opened */
2635         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2636                 return (0);
2637
2638 #ifdef RSS
2639         if (rss_getnumbuckets() > priv->params.num_channels) {
2640                 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than "
2641                     "channels(%u) available\n", rss_getnumbuckets(),
2642                     priv->params.num_channels);
2643         }
2644 #endif
2645         err = mlx5e_open_tises(priv);
2646         if (err) {
2647                 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n",
2648                     __func__, err);
2649                 return (err);
2650         }
2651         err = mlx5_vport_alloc_q_counter(priv->mdev,
2652             MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
2653         if (err) {
2654                 if_printf(priv->ifp,
2655                     "%s: mlx5_vport_alloc_q_counter failed: %d\n",
2656                     __func__, err);
2657                 goto err_close_tises;
2658         }
2659         /* store counter set ID */
2660         priv->counter_set_id = set_id;
2661
2662         err = mlx5e_open_channels(priv);
2663         if (err) {
2664                 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n",
2665                     __func__, err);
2666                 goto err_dalloc_q_counter;
2667         }
2668         err = mlx5e_open_rqt(priv);
2669         if (err) {
2670                 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n",
2671                     __func__, err);
2672                 goto err_close_channels;
2673         }
2674         err = mlx5e_open_tirs(priv);
2675         if (err) {
2676                 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n",
2677                     __func__, err);
2678                 goto err_close_rqls;
2679         }
2680         err = mlx5e_open_flow_table(priv);
2681         if (err) {
2682                 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n",
2683                     __func__, err);
2684                 goto err_close_tirs;
2685         }
2686         err = mlx5e_add_all_vlan_rules(priv);
2687         if (err) {
2688                 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
2689                     __func__, err);
2690                 goto err_close_flow_table;
2691         }
2692         set_bit(MLX5E_STATE_OPENED, &priv->state);
2693
2694         mlx5e_update_carrier(priv);
2695         mlx5e_set_rx_mode_core(priv);
2696
2697         return (0);
2698
2699 err_close_flow_table:
2700         mlx5e_close_flow_table(priv);
2701
2702 err_close_tirs:
2703         mlx5e_close_tirs(priv);
2704
2705 err_close_rqls:
2706         mlx5e_close_rqt(priv);
2707
2708 err_close_channels:
2709         mlx5e_close_channels(priv);
2710
2711 err_dalloc_q_counter:
2712         mlx5_vport_dealloc_q_counter(priv->mdev,
2713             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2714
2715 err_close_tises:
2716         mlx5e_close_tises(priv);
2717
2718         return (err);
2719 }
2720
2721 static void
2722 mlx5e_open(void *arg)
2723 {
2724         struct mlx5e_priv *priv = arg;
2725
2726         PRIV_LOCK(priv);
2727         if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
2728                 if_printf(priv->ifp,
2729                     "%s: Setting port status to up failed\n",
2730                     __func__);
2731
2732         mlx5e_open_locked(priv->ifp);
2733         priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
2734         PRIV_UNLOCK(priv);
2735 }
2736
2737 int
2738 mlx5e_close_locked(struct ifnet *ifp)
2739 {
2740         struct mlx5e_priv *priv = ifp->if_softc;
2741
2742         /* check if already closed */
2743         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2744                 return (0);
2745
2746         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2747
2748         mlx5e_set_rx_mode_core(priv);
2749         mlx5e_del_all_vlan_rules(priv);
2750         if_link_state_change(priv->ifp, LINK_STATE_DOWN);
2751         mlx5e_close_flow_table(priv);
2752         mlx5e_close_tirs(priv);
2753         mlx5e_close_rqt(priv);
2754         mlx5e_close_channels(priv);
2755         mlx5_vport_dealloc_q_counter(priv->mdev,
2756             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2757         mlx5e_close_tises(priv);
2758
2759         return (0);
2760 }
2761
2762 #if (__FreeBSD_version >= 1100000)
2763 static uint64_t
2764 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
2765 {
2766         struct mlx5e_priv *priv = ifp->if_softc;
2767         u64 retval;
2768
2769         /* PRIV_LOCK(priv); XXX not allowed */
2770         switch (cnt) {
2771         case IFCOUNTER_IPACKETS:
2772                 retval = priv->stats.vport.rx_packets;
2773                 break;
2774         case IFCOUNTER_IERRORS:
2775                 retval = priv->stats.vport.rx_error_packets +
2776                     priv->stats.pport.alignment_err +
2777                     priv->stats.pport.check_seq_err +
2778                     priv->stats.pport.crc_align_errors +
2779                     priv->stats.pport.in_range_len_errors +
2780                     priv->stats.pport.jabbers +
2781                     priv->stats.pport.out_of_range_len +
2782                     priv->stats.pport.oversize_pkts +
2783                     priv->stats.pport.symbol_err +
2784                     priv->stats.pport.too_long_errors +
2785                     priv->stats.pport.undersize_pkts +
2786                     priv->stats.pport.unsupported_op_rx;
2787                 break;
2788         case IFCOUNTER_IQDROPS:
2789                 retval = priv->stats.vport.rx_out_of_buffer +
2790                     priv->stats.pport.drop_events;
2791                 break;
2792         case IFCOUNTER_OPACKETS:
2793                 retval = priv->stats.vport.tx_packets;
2794                 break;
2795         case IFCOUNTER_OERRORS:
2796                 retval = priv->stats.vport.tx_error_packets;
2797                 break;
2798         case IFCOUNTER_IBYTES:
2799                 retval = priv->stats.vport.rx_bytes;
2800                 break;
2801         case IFCOUNTER_OBYTES:
2802                 retval = priv->stats.vport.tx_bytes;
2803                 break;
2804         case IFCOUNTER_IMCASTS:
2805                 retval = priv->stats.vport.rx_multicast_packets;
2806                 break;
2807         case IFCOUNTER_OMCASTS:
2808                 retval = priv->stats.vport.tx_multicast_packets;
2809                 break;
2810         case IFCOUNTER_OQDROPS:
2811                 retval = priv->stats.vport.tx_queue_dropped;
2812                 break;
2813         case IFCOUNTER_COLLISIONS:
2814                 retval = priv->stats.pport.collisions;
2815                 break;
2816         default:
2817                 retval = if_get_counter_default(ifp, cnt);
2818                 break;
2819         }
2820         /* PRIV_UNLOCK(priv); XXX not allowed */
2821         return (retval);
2822 }
2823 #endif
2824
2825 static void
2826 mlx5e_set_rx_mode(struct ifnet *ifp)
2827 {
2828         struct mlx5e_priv *priv = ifp->if_softc;
2829
2830         queue_work(priv->wq, &priv->set_rx_mode_work);
2831 }
2832
2833 static int
2834 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2835 {
2836         struct mlx5e_priv *priv;
2837         struct ifreq *ifr;
2838         struct ifi2creq i2c;
2839         int error = 0;
2840         int mask = 0;
2841         int size_read = 0;
2842         int module_status;
2843         int module_num;
2844         int max_mtu;
2845         uint8_t read_addr;
2846
2847         priv = ifp->if_softc;
2848
2849         /* check if detaching */
2850         if (priv == NULL || priv->gone != 0)
2851                 return (ENXIO);
2852
2853         switch (command) {
2854         case SIOCSIFMTU:
2855                 ifr = (struct ifreq *)data;
2856
2857                 PRIV_LOCK(priv);
2858                 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
2859
2860                 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
2861                     ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
2862                         int was_opened;
2863
2864                         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2865                         if (was_opened)
2866                                 mlx5e_close_locked(ifp);
2867
2868                         /* set new MTU */
2869                         mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
2870
2871                         if (was_opened)
2872                                 mlx5e_open_locked(ifp);
2873                 } else {
2874                         error = EINVAL;
2875                         if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n",
2876                             MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
2877                 }
2878                 PRIV_UNLOCK(priv);
2879                 break;
2880         case SIOCSIFFLAGS:
2881                 if ((ifp->if_flags & IFF_UP) &&
2882                     (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2883                         mlx5e_set_rx_mode(ifp);
2884                         break;
2885                 }
2886                 PRIV_LOCK(priv);
2887                 if (ifp->if_flags & IFF_UP) {
2888                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2889                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2890                                         mlx5e_open_locked(ifp);
2891                                 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2892                                 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
2893                         }
2894                 } else {
2895                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2896                                 mlx5_set_port_status(priv->mdev,
2897                                     MLX5_PORT_DOWN);
2898                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2899                                         mlx5e_close_locked(ifp);
2900                                 mlx5e_update_carrier(priv);
2901                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2902                         }
2903                 }
2904                 PRIV_UNLOCK(priv);
2905                 break;
2906         case SIOCADDMULTI:
2907         case SIOCDELMULTI:
2908                 mlx5e_set_rx_mode(ifp);
2909                 break;
2910         case SIOCSIFMEDIA:
2911         case SIOCGIFMEDIA:
2912         case SIOCGIFXMEDIA:
2913                 ifr = (struct ifreq *)data;
2914                 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
2915                 break;
2916         case SIOCSIFCAP:
2917                 ifr = (struct ifreq *)data;
2918                 PRIV_LOCK(priv);
2919                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2920
2921                 if (mask & IFCAP_TXCSUM) {
2922                         ifp->if_capenable ^= IFCAP_TXCSUM;
2923                         ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2924
2925                         if (IFCAP_TSO4 & ifp->if_capenable &&
2926                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2927                                 ifp->if_capenable &= ~IFCAP_TSO4;
2928                                 ifp->if_hwassist &= ~CSUM_IP_TSO;
2929                                 if_printf(ifp,
2930                                     "tso4 disabled due to -txcsum.\n");
2931                         }
2932                 }
2933                 if (mask & IFCAP_TXCSUM_IPV6) {
2934                         ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
2935                         ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2936
2937                         if (IFCAP_TSO6 & ifp->if_capenable &&
2938                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2939                                 ifp->if_capenable &= ~IFCAP_TSO6;
2940                                 ifp->if_hwassist &= ~CSUM_IP6_TSO;
2941                                 if_printf(ifp,
2942                                     "tso6 disabled due to -txcsum6.\n");
2943                         }
2944                 }
2945                 if (mask & IFCAP_RXCSUM)
2946                         ifp->if_capenable ^= IFCAP_RXCSUM;
2947                 if (mask & IFCAP_RXCSUM_IPV6)
2948                         ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
2949                 if (mask & IFCAP_TSO4) {
2950                         if (!(IFCAP_TSO4 & ifp->if_capenable) &&
2951                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2952                                 if_printf(ifp, "enable txcsum first.\n");
2953                                 error = EAGAIN;
2954                                 goto out;
2955                         }
2956                         ifp->if_capenable ^= IFCAP_TSO4;
2957                         ifp->if_hwassist ^= CSUM_IP_TSO;
2958                 }
2959                 if (mask & IFCAP_TSO6) {
2960                         if (!(IFCAP_TSO6 & ifp->if_capenable) &&
2961                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2962                                 if_printf(ifp, "enable txcsum6 first.\n");
2963                                 error = EAGAIN;
2964                                 goto out;
2965                         }
2966                         ifp->if_capenable ^= IFCAP_TSO6;
2967                         ifp->if_hwassist ^= CSUM_IP6_TSO;
2968                 }
2969                 if (mask & IFCAP_VLAN_HWFILTER) {
2970                         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
2971                                 mlx5e_disable_vlan_filter(priv);
2972                         else
2973                                 mlx5e_enable_vlan_filter(priv);
2974
2975                         ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
2976                 }
2977                 if (mask & IFCAP_VLAN_HWTAGGING)
2978                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2979                 if (mask & IFCAP_WOL_MAGIC)
2980                         ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2981
2982                 VLAN_CAPABILITIES(ifp);
2983                 /* turn off LRO means also turn of HW LRO - if it's on */
2984                 if (mask & IFCAP_LRO) {
2985                         int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2986                         bool need_restart = false;
2987
2988                         ifp->if_capenable ^= IFCAP_LRO;
2989
2990                         /* figure out if updating HW LRO is needed */
2991                         if (!(ifp->if_capenable & IFCAP_LRO)) {
2992                                 if (priv->params.hw_lro_en) {
2993                                         priv->params.hw_lro_en = false;
2994                                         need_restart = true;
2995                                 }
2996                         } else {
2997                                 if (priv->params.hw_lro_en == false &&
2998                                     priv->params_ethtool.hw_lro != 0) {
2999                                         priv->params.hw_lro_en = true;
3000                                         need_restart = true;
3001                                 }
3002                         }
3003                         if (was_opened && need_restart) {
3004                                 mlx5e_close_locked(ifp);
3005                                 mlx5e_open_locked(ifp);
3006                         }
3007                 }
3008                 if (mask & IFCAP_HWRXTSTMP) {
3009                         ifp->if_capenable ^= IFCAP_HWRXTSTMP;
3010                         if (ifp->if_capenable & IFCAP_HWRXTSTMP) {
3011                                 if (priv->clbr_done == 0)
3012                                         mlx5e_reset_calibration_callout(priv);
3013                         } else {
3014                                 callout_drain(&priv->tstmp_clbr);
3015                                 priv->clbr_done = 0;
3016                         }
3017                 }
3018 out:
3019                 PRIV_UNLOCK(priv);
3020                 break;
3021
3022         case SIOCGI2C:
3023                 ifr = (struct ifreq *)data;
3024
3025                 /*
3026                  * Copy from the user-space address ifr_data to the
3027                  * kernel-space address i2c
3028                  */
3029                 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
3030                 if (error)
3031                         break;
3032
3033                 if (i2c.len > sizeof(i2c.data)) {
3034                         error = EINVAL;
3035                         break;
3036                 }
3037
3038                 PRIV_LOCK(priv);
3039                 /* Get module_num which is required for the query_eeprom */
3040                 error = mlx5_query_module_num(priv->mdev, &module_num);
3041                 if (error) {
3042                         if_printf(ifp, "Query module num failed, eeprom "
3043                             "reading is not supported\n");
3044                         error = EINVAL;
3045                         goto err_i2c;
3046                 }
3047                 /* Check if module is present before doing an access */
3048                 module_status = mlx5_query_module_status(priv->mdev, module_num);
3049                 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED &&
3050                     module_status != MLX5_MODULE_STATUS_PLUGGED_DISABLED) {
3051                         error = EINVAL;
3052                         goto err_i2c;
3053                 }
3054                 /*
3055                  * Currently 0XA0 and 0xA2 are the only addresses permitted.
3056                  * The internal conversion is as follows:
3057                  */
3058                 if (i2c.dev_addr == 0xA0)
3059                         read_addr = MLX5E_I2C_ADDR_LOW;
3060                 else if (i2c.dev_addr == 0xA2)
3061                         read_addr = MLX5E_I2C_ADDR_HIGH;
3062                 else {
3063                         if_printf(ifp, "Query eeprom failed, "
3064                             "Invalid Address: %X\n", i2c.dev_addr);
3065                         error = EINVAL;
3066                         goto err_i2c;
3067                 }
3068                 error = mlx5_query_eeprom(priv->mdev,
3069                     read_addr, MLX5E_EEPROM_LOW_PAGE,
3070                     (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
3071                     (uint32_t *)i2c.data, &size_read);
3072                 if (error) {
3073                         if_printf(ifp, "Query eeprom failed, eeprom "
3074                             "reading is not supported\n");
3075                         error = EINVAL;
3076                         goto err_i2c;
3077                 }
3078
3079                 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
3080                         error = mlx5_query_eeprom(priv->mdev,
3081                             read_addr, MLX5E_EEPROM_LOW_PAGE,
3082                             (uint32_t)(i2c.offset + size_read),
3083                             (uint32_t)(i2c.len - size_read), module_num,
3084                             (uint32_t *)(i2c.data + size_read), &size_read);
3085                 }
3086                 if (error) {
3087                         if_printf(ifp, "Query eeprom failed, eeprom "
3088                             "reading is not supported\n");
3089                         error = EINVAL;
3090                         goto err_i2c;
3091                 }
3092
3093                 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
3094 err_i2c:
3095                 PRIV_UNLOCK(priv);
3096                 break;
3097
3098         default:
3099                 error = ether_ioctl(ifp, command, data);
3100                 break;
3101         }
3102         return (error);
3103 }
3104
3105 static int
3106 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3107 {
3108         /*
3109          * TODO: uncoment once FW really sets all these bits if
3110          * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
3111          * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
3112          * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
3113          * -ENOTSUPP;
3114          */
3115
3116         /* TODO: add more must-to-have features */
3117
3118         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3119                 return (-ENODEV);
3120
3121         return (0);
3122 }
3123
3124 static u16
3125 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3126 {
3127         uint32_t bf_buf_size = (1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U;
3128
3129         bf_buf_size -= sizeof(struct mlx5e_tx_wqe) - 2;
3130
3131         /* verify against driver hardware limit */
3132         if (bf_buf_size > MLX5E_MAX_TX_INLINE)
3133                 bf_buf_size = MLX5E_MAX_TX_INLINE;
3134
3135         return (bf_buf_size);
3136 }
3137
3138 static int
3139 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
3140     struct mlx5e_priv *priv,
3141     int num_comp_vectors)
3142 {
3143         int err;
3144
3145         /*
3146          * TODO: Consider link speed for setting "log_sq_size",
3147          * "log_rq_size" and "cq_moderation_xxx":
3148          */
3149         priv->params.log_sq_size =
3150             MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3151         priv->params.log_rq_size =
3152             MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3153         priv->params.rx_cq_moderation_usec =
3154             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3155             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
3156             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3157         priv->params.rx_cq_moderation_mode =
3158             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
3159         priv->params.rx_cq_moderation_pkts =
3160             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3161         priv->params.tx_cq_moderation_usec =
3162             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3163         priv->params.tx_cq_moderation_pkts =
3164             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3165         priv->params.min_rx_wqes =
3166             MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
3167         priv->params.rx_hash_log_tbl_sz =
3168             (order_base_2(num_comp_vectors) >
3169             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
3170             order_base_2(num_comp_vectors) :
3171             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
3172         priv->params.num_tc = 1;
3173         priv->params.default_vlan_prio = 0;
3174         priv->counter_set_id = -1;
3175         priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3176
3177         err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3178         if (err)
3179                 return (err);
3180
3181         /*
3182          * hw lro is currently defaulted to off. when it won't anymore we
3183          * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
3184          */
3185         priv->params.hw_lro_en = false;
3186         priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3187
3188         priv->params.cqe_zipping_en = !!MLX5_CAP_GEN(mdev, cqe_compression);
3189
3190         priv->mdev = mdev;
3191         priv->params.num_channels = num_comp_vectors;
3192         priv->params.channels_rsss = 1;
3193         priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
3194         priv->queue_mapping_channel_mask =
3195             roundup_pow_of_two(num_comp_vectors) - 1;
3196         priv->num_tc = priv->params.num_tc;
3197         priv->default_vlan_prio = priv->params.default_vlan_prio;
3198
3199         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3200         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3201         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3202
3203         return (0);
3204 }
3205
3206 static int
3207 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
3208                   struct mlx5_core_mr *mkey)
3209 {
3210         struct ifnet *ifp = priv->ifp;
3211         struct mlx5_core_dev *mdev = priv->mdev;
3212         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3213         void *mkc;
3214         u32 *in;
3215         int err;
3216
3217         in = mlx5_vzalloc(inlen);
3218         if (in == NULL) {
3219                 if_printf(ifp, "%s: failed to allocate inbox\n", __func__);
3220                 return (-ENOMEM);
3221         }
3222
3223         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3224         MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA);
3225         MLX5_SET(mkc, mkc, lw, 1);
3226         MLX5_SET(mkc, mkc, lr, 1);
3227
3228         MLX5_SET(mkc, mkc, pd, pdn);
3229         MLX5_SET(mkc, mkc, length64, 1);
3230         MLX5_SET(mkc, mkc, qpn, 0xffffff);
3231
3232         err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
3233         if (err)
3234                 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n",
3235                     __func__, err);
3236
3237         kvfree(in);
3238         return (err);
3239 }
3240
3241 static const char *mlx5e_vport_stats_desc[] = {
3242         MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
3243 };
3244
3245 static const char *mlx5e_pport_stats_desc[] = {
3246         MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
3247 };
3248
3249 static void
3250 mlx5e_priv_mtx_init(struct mlx5e_priv *priv)
3251 {
3252         mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
3253         sx_init(&priv->state_lock, "mlx5state");
3254         callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
3255         MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
3256 }
3257
3258 static void
3259 mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv)
3260 {
3261         mtx_destroy(&priv->async_events_mtx);
3262         sx_destroy(&priv->state_lock);
3263 }
3264
3265 static int
3266 sysctl_firmware(SYSCTL_HANDLER_ARGS)
3267 {
3268         /*
3269          * %d.%d%.d the string format.
3270          * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
3271          * We need at most 5 chars to store that.
3272          * It also has: two "." and NULL at the end, which means we need 18
3273          * (5*3 + 3) chars at most.
3274          */
3275         char fw[18];
3276         struct mlx5e_priv *priv = arg1;
3277         int error;
3278
3279         snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
3280             fw_rev_sub(priv->mdev));
3281         error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
3282         return (error);
3283 }
3284
3285 static void
3286 mlx5e_disable_tx_dma(struct mlx5e_channel *ch)
3287 {
3288         int i;
3289
3290         for (i = 0; i < ch->num_tc; i++)
3291                 mlx5e_drain_sq(&ch->sq[i]);
3292 }
3293
3294 static void
3295 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq)
3296 {
3297
3298         sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP);
3299         sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8);
3300         mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
3301         sq->doorbell.d64 = 0;
3302 }
3303
3304 void
3305 mlx5e_resume_sq(struct mlx5e_sq *sq)
3306 {
3307         int err;
3308
3309         /* check if already enabled */
3310         if (READ_ONCE(sq->running) != 0)
3311                 return;
3312
3313         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR,
3314             MLX5_SQC_STATE_RST);
3315         if (err != 0) {
3316                 if_printf(sq->ifp,
3317                     "mlx5e_modify_sq() from ERR to RST failed: %d\n", err);
3318         }
3319
3320         sq->cc = 0;
3321         sq->pc = 0;
3322
3323         /* reset doorbell prior to moving from RST to RDY */
3324         mlx5e_reset_sq_doorbell_record(sq);
3325
3326         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST,
3327             MLX5_SQC_STATE_RDY);
3328         if (err != 0) {
3329                 if_printf(sq->ifp,
3330                     "mlx5e_modify_sq() from RST to RDY failed: %d\n", err);
3331         }
3332
3333         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
3334         WRITE_ONCE(sq->running, 1);
3335 }
3336
3337 static void
3338 mlx5e_enable_tx_dma(struct mlx5e_channel *ch)
3339 {
3340         int i;
3341
3342         for (i = 0; i < ch->num_tc; i++)
3343                 mlx5e_resume_sq(&ch->sq[i]);
3344 }
3345
3346 static void
3347 mlx5e_disable_rx_dma(struct mlx5e_channel *ch)
3348 {
3349         struct mlx5e_rq *rq = &ch->rq;
3350         int err;
3351
3352         mtx_lock(&rq->mtx);
3353         rq->enabled = 0;
3354         callout_stop(&rq->watchdog);
3355         mtx_unlock(&rq->mtx);
3356
3357         callout_drain(&rq->watchdog);
3358
3359         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
3360         if (err != 0) {
3361                 if_printf(rq->ifp,
3362                     "mlx5e_modify_rq() from RDY to RST failed: %d\n", err);
3363         }
3364
3365         while (!mlx5_wq_ll_is_empty(&rq->wq)) {
3366                 msleep(1);
3367                 rq->cq.mcq.comp(&rq->cq.mcq);
3368         }
3369
3370         /*
3371          * Transitioning into RST state will allow the FW to track less ERR state queues,
3372          * thus reducing the recv queue flushing time
3373          */
3374         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST);
3375         if (err != 0) {
3376                 if_printf(rq->ifp,
3377                     "mlx5e_modify_rq() from ERR to RST failed: %d\n", err);
3378         }
3379 }
3380
3381 static void
3382 mlx5e_enable_rx_dma(struct mlx5e_channel *ch)
3383 {
3384         struct mlx5e_rq *rq = &ch->rq;
3385         int err;
3386
3387         rq->wq.wqe_ctr = 0;
3388         mlx5_wq_ll_update_db_record(&rq->wq);
3389         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3390         if (err != 0) {
3391                 if_printf(rq->ifp,
3392                     "mlx5e_modify_rq() from RST to RDY failed: %d\n", err);
3393         }
3394
3395         rq->enabled = 1;
3396
3397         rq->cq.mcq.comp(&rq->cq.mcq);
3398 }
3399
3400 void
3401 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value)
3402 {
3403         int i;
3404
3405         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3406                 return;
3407
3408         for (i = 0; i < priv->params.num_channels; i++) {
3409                 if (value)
3410                         mlx5e_disable_tx_dma(&priv->channel[i]);
3411                 else
3412                         mlx5e_enable_tx_dma(&priv->channel[i]);
3413         }
3414 }
3415
3416 void
3417 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value)
3418 {
3419         int i;
3420
3421         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3422                 return;
3423
3424         for (i = 0; i < priv->params.num_channels; i++) {
3425                 if (value)
3426                         mlx5e_disable_rx_dma(&priv->channel[i]);
3427                 else
3428                         mlx5e_enable_rx_dma(&priv->channel[i]);
3429         }
3430 }
3431
3432 static void
3433 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
3434 {
3435         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3436             OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
3437             sysctl_firmware, "A", "HCA firmware version");
3438
3439         SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3440             OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
3441             "Board ID");
3442 }
3443
3444 static int
3445 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3446 {
3447         struct mlx5e_priv *priv = arg1;
3448         uint8_t temp[MLX5E_MAX_PRIORITY];
3449         uint32_t tx_pfc;
3450         int err;
3451         int i;
3452
3453         PRIV_LOCK(priv);
3454
3455         tx_pfc = priv->params.tx_priority_flow_control;
3456
3457         for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3458                 temp[i] = (tx_pfc >> i) & 1;
3459
3460         err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3461         if (err || !req->newptr)
3462                 goto done;
3463         err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3464         if (err)
3465                 goto done;
3466
3467         priv->params.tx_priority_flow_control = 0;
3468
3469         /* range check input value */
3470         for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3471                 if (temp[i] > 1) {
3472                         err = ERANGE;
3473                         goto done;
3474                 }
3475                 priv->params.tx_priority_flow_control |= (temp[i] << i);
3476         }
3477
3478         /* check if update is required */
3479         if (tx_pfc != priv->params.tx_priority_flow_control)
3480                 err = -mlx5e_set_port_pfc(priv);
3481 done:
3482         if (err != 0)
3483                 priv->params.tx_priority_flow_control= tx_pfc;
3484         PRIV_UNLOCK(priv);
3485
3486         return (err);
3487 }
3488
3489 static int
3490 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3491 {
3492         struct mlx5e_priv *priv = arg1;
3493         uint8_t temp[MLX5E_MAX_PRIORITY];
3494         uint32_t rx_pfc;
3495         int err;
3496         int i;
3497
3498         PRIV_LOCK(priv);
3499
3500         rx_pfc = priv->params.rx_priority_flow_control;
3501
3502         for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3503                 temp[i] = (rx_pfc >> i) & 1;
3504
3505         err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3506         if (err || !req->newptr)
3507                 goto done;
3508         err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3509         if (err)
3510                 goto done;
3511
3512         priv->params.rx_priority_flow_control = 0;
3513
3514         /* range check input value */
3515         for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3516                 if (temp[i] > 1) {
3517                         err = ERANGE;
3518                         goto done;
3519                 }
3520                 priv->params.rx_priority_flow_control |= (temp[i] << i);
3521         }
3522
3523         /* check if update is required */
3524         if (rx_pfc != priv->params.rx_priority_flow_control)
3525                 err = -mlx5e_set_port_pfc(priv);
3526 done:
3527         if (err != 0)
3528                 priv->params.rx_priority_flow_control= rx_pfc;
3529         PRIV_UNLOCK(priv);
3530
3531         return (err);
3532 }
3533
3534 static void
3535 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
3536 {
3537 #if (__FreeBSD_version < 1100000)
3538         char path[96];
3539 #endif
3540         int error;
3541
3542         /* enable pauseframes by default */
3543         priv->params.tx_pauseframe_control = 1;
3544         priv->params.rx_pauseframe_control = 1;
3545
3546         /* disable ports flow control, PFC, by default */
3547         priv->params.tx_priority_flow_control = 0;
3548         priv->params.rx_priority_flow_control = 0;
3549
3550 #if (__FreeBSD_version < 1100000)
3551         /* compute path for sysctl */
3552         snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
3553             device_get_unit(priv->mdev->pdev->dev.bsddev));
3554
3555         /* try to fetch tunable, if any */
3556         TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
3557
3558         /* compute path for sysctl */
3559         snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
3560             device_get_unit(priv->mdev->pdev->dev.bsddev));
3561
3562         /* try to fetch tunable, if any */
3563         TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
3564 #endif
3565
3566         /* register pauseframe SYSCTLs */
3567         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3568             OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
3569             &priv->params.tx_pauseframe_control, 0,
3570             "Set to enable TX pause frames. Clear to disable.");
3571
3572         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3573             OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
3574             &priv->params.rx_pauseframe_control, 0,
3575             "Set to enable RX pause frames. Clear to disable.");
3576
3577         /* register priority flow control, PFC, SYSCTLs */
3578         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3579             OID_AUTO, "tx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
3580             CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_tx_priority_flow_control, "CU",
3581             "Set to enable TX ports flow control frames for priorities 0..7. Clear to disable.");
3582
3583         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3584             OID_AUTO, "rx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
3585             CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_rx_priority_flow_control, "CU",
3586             "Set to enable RX ports flow control frames for priorities 0..7. Clear to disable.");
3587
3588         PRIV_LOCK(priv);
3589
3590         /* range check */
3591         priv->params.tx_pauseframe_control =
3592             priv->params.tx_pauseframe_control ? 1 : 0;
3593         priv->params.rx_pauseframe_control =
3594             priv->params.rx_pauseframe_control ? 1 : 0;
3595
3596         /* update firmware */
3597         error = mlx5e_set_port_pause_and_pfc(priv);
3598         if (error == -EINVAL) {
3599                 if_printf(priv->ifp,
3600                     "Global pauseframes must be disabled before enabling PFC.\n");
3601                 priv->params.rx_priority_flow_control = 0;
3602                 priv->params.tx_priority_flow_control = 0;
3603
3604                 /* update firmware */
3605                 (void) mlx5e_set_port_pause_and_pfc(priv);
3606         }
3607         PRIV_UNLOCK(priv);
3608 }
3609
3610 static int
3611 mlx5e_ul_snd_tag_alloc(struct ifnet *ifp,
3612     union if_snd_tag_alloc_params *params,
3613     struct m_snd_tag **ppmt)
3614 {
3615         struct mlx5e_priv *priv;
3616         struct mlx5e_channel *pch;
3617
3618         priv = ifp->if_softc;
3619
3620         if (unlikely(priv->gone || params->hdr.flowtype == M_HASHTYPE_NONE)) {
3621                 return (EOPNOTSUPP);
3622         } else {
3623                 /* keep this code synced with mlx5e_select_queue() */
3624                 u32 ch = priv->params.num_channels;
3625 #ifdef RSS
3626                 u32 temp;
3627
3628                 if (rss_hash2bucket(params->hdr.flowid,
3629                     params->hdr.flowtype, &temp) == 0)
3630                         ch = temp % ch;
3631                 else
3632 #endif
3633                         ch = (params->hdr.flowid % 128) % ch;
3634
3635                 /*
3636                  * NOTE: The channels array is only freed at detach
3637                  * and it safe to return a pointer to the send tag
3638                  * inside the channels structure as long as we
3639                  * reference the priv.
3640                  */
3641                 pch = priv->channel + ch;
3642
3643                 /* check if send queue is not running */
3644                 if (unlikely(pch->sq[0].running == 0))
3645                         return (ENXIO);
3646                 mlx5e_ref_channel(priv);
3647                 *ppmt = &pch->tag.m_snd_tag;
3648                 return (0);
3649         }
3650 }
3651
3652 static int
3653 mlx5e_ul_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
3654 {
3655         struct mlx5e_channel *pch =
3656             container_of(pmt, struct mlx5e_channel, tag.m_snd_tag);
3657
3658         params->unlimited.max_rate = -1ULL;
3659         params->unlimited.queue_level = mlx5e_sq_queue_level(&pch->sq[0]);
3660         return (0);
3661 }
3662
3663 static void
3664 mlx5e_ul_snd_tag_free(struct m_snd_tag *pmt)
3665 {
3666         struct mlx5e_channel *pch =
3667             container_of(pmt, struct mlx5e_channel, tag.m_snd_tag);
3668
3669         mlx5e_unref_channel(pch->priv);
3670 }
3671
3672 static int
3673 mlx5e_snd_tag_alloc(struct ifnet *ifp,
3674     union if_snd_tag_alloc_params *params,
3675     struct m_snd_tag **ppmt)
3676 {
3677
3678         switch (params->hdr.type) {
3679 #ifdef RATELIMIT
3680         case IF_SND_TAG_TYPE_RATE_LIMIT:
3681                 return (mlx5e_rl_snd_tag_alloc(ifp, params, ppmt));
3682 #endif
3683         case IF_SND_TAG_TYPE_UNLIMITED:
3684                 return (mlx5e_ul_snd_tag_alloc(ifp, params, ppmt));
3685         default:
3686                 return (EOPNOTSUPP);
3687         }
3688 }
3689
3690 static int
3691 mlx5e_snd_tag_modify(struct m_snd_tag *pmt, union if_snd_tag_modify_params *params)
3692 {
3693         struct mlx5e_snd_tag *tag =
3694             container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
3695
3696         switch (tag->type) {
3697 #ifdef RATELIMIT
3698         case IF_SND_TAG_TYPE_RATE_LIMIT:
3699                 return (mlx5e_rl_snd_tag_modify(pmt, params));
3700 #endif
3701         case IF_SND_TAG_TYPE_UNLIMITED:
3702         default:
3703                 return (EOPNOTSUPP);
3704         }
3705 }
3706
3707 static int
3708 mlx5e_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
3709 {
3710         struct mlx5e_snd_tag *tag =
3711             container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
3712
3713         switch (tag->type) {
3714 #ifdef RATELIMIT
3715         case IF_SND_TAG_TYPE_RATE_LIMIT:
3716                 return (mlx5e_rl_snd_tag_query(pmt, params));
3717 #endif
3718         case IF_SND_TAG_TYPE_UNLIMITED:
3719                 return (mlx5e_ul_snd_tag_query(pmt, params));
3720         default:
3721                 return (EOPNOTSUPP);
3722         }
3723 }
3724
3725 static void
3726 mlx5e_snd_tag_free(struct m_snd_tag *pmt)
3727 {
3728         struct mlx5e_snd_tag *tag =
3729             container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
3730
3731         switch (tag->type) {
3732 #ifdef RATELIMIT
3733         case IF_SND_TAG_TYPE_RATE_LIMIT:
3734                 mlx5e_rl_snd_tag_free(pmt);
3735                 break;
3736 #endif
3737         case IF_SND_TAG_TYPE_UNLIMITED:
3738                 mlx5e_ul_snd_tag_free(pmt);
3739                 break;
3740         default:
3741                 break;
3742         }
3743 }
3744
3745 static void *
3746 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
3747 {
3748         struct ifnet *ifp;
3749         struct mlx5e_priv *priv;
3750         u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
3751         struct sysctl_oid_list *child;
3752         int ncv = mdev->priv.eq_table.num_comp_vectors;
3753         char unit[16];
3754         int err;
3755         int i;
3756         u32 eth_proto_cap;
3757
3758         if (mlx5e_check_required_hca_cap(mdev)) {
3759                 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
3760                 return (NULL);
3761         }
3762         /*
3763          * Try to allocate the priv and make room for worst-case
3764          * number of channel structures:
3765          */
3766         priv = malloc(sizeof(*priv) +
3767             (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors),
3768             M_MLX5EN, M_WAITOK | M_ZERO);
3769         mlx5e_priv_mtx_init(priv);
3770
3771         ifp = priv->ifp = if_alloc(IFT_ETHER);
3772         if (ifp == NULL) {
3773                 mlx5_core_err(mdev, "if_alloc() failed\n");
3774                 goto err_free_priv;
3775         }
3776         ifp->if_softc = priv;
3777         if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev));
3778         ifp->if_mtu = ETHERMTU;
3779         ifp->if_init = mlx5e_open;
3780         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
3781         ifp->if_ioctl = mlx5e_ioctl;
3782         ifp->if_transmit = mlx5e_xmit;
3783         ifp->if_qflush = if_qflush;
3784 #if (__FreeBSD_version >= 1100000)
3785         ifp->if_get_counter = mlx5e_get_counter;
3786 #endif
3787         ifp->if_snd.ifq_maxlen = ifqmaxlen;
3788         /*
3789          * Set driver features
3790          */
3791         ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
3792         ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
3793         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
3794         ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
3795         ifp->if_capabilities |= IFCAP_LRO;
3796         ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
3797         ifp->if_capabilities |= IFCAP_HWSTATS | IFCAP_HWRXTSTMP;
3798         ifp->if_capabilities |= IFCAP_TXRTLMT;
3799         ifp->if_snd_tag_alloc = mlx5e_snd_tag_alloc;
3800         ifp->if_snd_tag_free = mlx5e_snd_tag_free;
3801         ifp->if_snd_tag_modify = mlx5e_snd_tag_modify;
3802         ifp->if_snd_tag_query = mlx5e_snd_tag_query;
3803
3804         /* set TSO limits so that we don't have to drop TX packets */
3805         ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
3806         ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
3807         ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
3808
3809         ifp->if_capenable = ifp->if_capabilities;
3810         ifp->if_hwassist = 0;
3811         if (ifp->if_capenable & IFCAP_TSO)
3812                 ifp->if_hwassist |= CSUM_TSO;
3813         if (ifp->if_capenable & IFCAP_TXCSUM)
3814                 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
3815         if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
3816                 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3817
3818         /* ifnet sysctl tree */
3819         sysctl_ctx_init(&priv->sysctl_ctx);
3820         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
3821             OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
3822         if (priv->sysctl_ifnet == NULL) {
3823                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3824                 goto err_free_sysctl;
3825         }
3826         snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
3827         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3828             OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
3829         if (priv->sysctl_ifnet == NULL) {
3830                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3831                 goto err_free_sysctl;
3832         }
3833
3834         /* HW sysctl tree */
3835         child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
3836         priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
3837             OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
3838         if (priv->sysctl_hw == NULL) {
3839                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3840                 goto err_free_sysctl;
3841         }
3842
3843         err = mlx5e_build_ifp_priv(mdev, priv, ncv);
3844         if (err) {
3845                 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err);
3846                 goto err_free_sysctl;
3847         }
3848
3849         snprintf(unit, sizeof(unit), "mce%u_wq",
3850             device_get_unit(mdev->pdev->dev.bsddev));
3851         priv->wq = alloc_workqueue(unit, 0, 1);
3852         if (priv->wq == NULL) {
3853                 if_printf(ifp, "%s: alloc_workqueue failed\n", __func__);
3854                 goto err_free_sysctl;
3855         }
3856
3857         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
3858         if (err) {
3859                 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n",
3860                     __func__, err);
3861                 goto err_free_wq;
3862         }
3863         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
3864         if (err) {
3865                 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n",
3866                     __func__, err);
3867                 goto err_unmap_free_uar;
3868         }
3869         err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
3870         if (err) {
3871                 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n",
3872                     __func__, err);
3873                 goto err_dealloc_pd;
3874         }
3875         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
3876         if (err) {
3877                 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n",
3878                     __func__, err);
3879                 goto err_dealloc_transport_domain;
3880         }
3881         mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
3882
3883         /* check if we should generate a random MAC address */
3884         if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
3885             is_zero_ether_addr(dev_addr)) {
3886                 random_ether_addr(dev_addr);
3887                 if_printf(ifp, "Assigned random MAC address\n");
3888         }
3889 #ifdef RATELIMIT
3890         err = mlx5e_rl_init(priv);
3891         if (err) {
3892                 if_printf(ifp, "%s: mlx5e_rl_init failed, %d\n",
3893                     __func__, err);
3894                 goto err_create_mkey;
3895         }
3896 #endif
3897
3898         /* set default MTU */
3899         mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
3900
3901         /* Set default media status */
3902         priv->media_status_last = IFM_AVALID;
3903         priv->media_active_last = IFM_ETHER | IFM_AUTO |
3904             IFM_ETH_RXPAUSE | IFM_FDX;
3905
3906         /* setup default pauseframes configuration */
3907         mlx5e_setup_pauseframes(priv);
3908
3909         err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
3910         if (err) {
3911                 eth_proto_cap = 0;
3912                 if_printf(ifp, "%s: Query port media capability failed, %d\n",
3913                     __func__, err);
3914         }
3915
3916         /* Setup supported medias */
3917         ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
3918             mlx5e_media_change, mlx5e_media_status);
3919
3920         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
3921                 if (mlx5e_mode_table[i].baudrate == 0)
3922                         continue;
3923                 if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
3924                         ifmedia_add(&priv->media,
3925                             mlx5e_mode_table[i].subtype |
3926                             IFM_ETHER, 0, NULL);
3927                         ifmedia_add(&priv->media,
3928                             mlx5e_mode_table[i].subtype |
3929                             IFM_ETHER | IFM_FDX |
3930                             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3931                 }
3932         }
3933
3934         /* Additional supported medias */
3935         ifmedia_add(&priv->media, IFM_10G_LR | IFM_ETHER, 0, NULL);
3936         ifmedia_add(&priv->media, IFM_10G_LR |
3937             IFM_ETHER | IFM_FDX |
3938             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3939
3940         ifmedia_add(&priv->media, IFM_40G_ER4 | IFM_ETHER, 0, NULL);
3941         ifmedia_add(&priv->media, IFM_40G_ER4 |
3942             IFM_ETHER | IFM_FDX |
3943             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3944
3945         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
3946         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3947             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3948
3949         /* Set autoselect by default */
3950         ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3951             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
3952         ether_ifattach(ifp, dev_addr);
3953
3954         /* Register for VLAN events */
3955         priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
3956             mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
3957         priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
3958             mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
3959
3960         /* Link is down by default */
3961         if_link_state_change(ifp, LINK_STATE_DOWN);
3962
3963         mlx5e_enable_async_events(priv);
3964
3965         mlx5e_add_hw_stats(priv);
3966
3967         mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3968             "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
3969             priv->stats.vport.arg);
3970
3971         mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3972             "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
3973             priv->stats.pport.arg);
3974
3975         mlx5e_create_ethtool(priv);
3976
3977         mtx_lock(&priv->async_events_mtx);
3978         mlx5e_update_stats(priv);
3979         mtx_unlock(&priv->async_events_mtx);
3980
3981         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3982             OID_AUTO, "rx_clbr_done", CTLFLAG_RD,
3983             &priv->clbr_done, 0,
3984             "RX timestamps calibration state");
3985         callout_init(&priv->tstmp_clbr, CALLOUT_DIRECT);
3986         mlx5e_reset_calibration_callout(priv);
3987
3988         return (priv);
3989
3990 #ifdef RATELIMIT
3991 err_create_mkey:
3992         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
3993 #endif
3994 err_dealloc_transport_domain:
3995         mlx5_dealloc_transport_domain(mdev, priv->tdn);
3996
3997 err_dealloc_pd:
3998         mlx5_core_dealloc_pd(mdev, priv->pdn);
3999
4000 err_unmap_free_uar:
4001         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
4002
4003 err_free_wq:
4004         destroy_workqueue(priv->wq);
4005
4006 err_free_sysctl:
4007         sysctl_ctx_free(&priv->sysctl_ctx);
4008         if (priv->sysctl_debug)
4009                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4010         if_free(ifp);
4011
4012 err_free_priv:
4013         mlx5e_priv_mtx_destroy(priv);
4014         free(priv, M_MLX5EN);
4015         return (NULL);
4016 }
4017
4018 static void
4019 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
4020 {
4021         struct mlx5e_priv *priv = vpriv;
4022         struct ifnet *ifp = priv->ifp;
4023
4024         /* don't allow more IOCTLs */
4025         priv->gone = 1;
4026
4027         /* XXX wait a bit to allow IOCTL handlers to complete */
4028         pause("W", hz);
4029
4030 #ifdef RATELIMIT
4031         /*
4032          * The kernel can have reference(s) via the m_snd_tag's into
4033          * the ratelimit channels, and these must go away before
4034          * detaching:
4035          */
4036         while (READ_ONCE(priv->rl.stats.tx_active_connections) != 0) {
4037                 if_printf(priv->ifp, "Waiting for all ratelimit connections "
4038                     "to terminate\n");
4039                 pause("W", hz);
4040         }
4041 #endif
4042         /* stop watchdog timer */
4043         callout_drain(&priv->watchdog);
4044
4045         callout_drain(&priv->tstmp_clbr);
4046
4047         if (priv->vlan_attach != NULL)
4048                 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
4049         if (priv->vlan_detach != NULL)
4050                 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
4051
4052         /* make sure device gets closed */
4053         PRIV_LOCK(priv);
4054         mlx5e_close_locked(ifp);
4055         PRIV_UNLOCK(priv);
4056
4057         /* wait for all unlimited send tags to go away */
4058         while (priv->channel_refs != 0) {
4059                 if_printf(priv->ifp, "Waiting for all unlimited connections "
4060                     "to terminate\n");
4061                 pause("W", hz);
4062         }
4063
4064         /* unregister device */
4065         ifmedia_removeall(&priv->media);
4066         ether_ifdetach(ifp);
4067         if_free(ifp);
4068
4069 #ifdef RATELIMIT
4070         mlx5e_rl_cleanup(priv);
4071 #endif
4072         /* destroy all remaining sysctl nodes */
4073         sysctl_ctx_free(&priv->stats.vport.ctx);
4074         sysctl_ctx_free(&priv->stats.pport.ctx);
4075         if (priv->sysctl_debug)
4076                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4077         sysctl_ctx_free(&priv->sysctl_ctx);
4078
4079         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
4080         mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
4081         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
4082         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
4083         mlx5e_disable_async_events(priv);
4084         destroy_workqueue(priv->wq);
4085         mlx5e_priv_mtx_destroy(priv);
4086         free(priv, M_MLX5EN);
4087 }
4088
4089 static void *
4090 mlx5e_get_ifp(void *vpriv)
4091 {
4092         struct mlx5e_priv *priv = vpriv;
4093
4094         return (priv->ifp);
4095 }
4096
4097 static struct mlx5_interface mlx5e_interface = {
4098         .add = mlx5e_create_ifp,
4099         .remove = mlx5e_destroy_ifp,
4100         .event = mlx5e_async_event,
4101         .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4102         .get_dev = mlx5e_get_ifp,
4103 };
4104
4105 void
4106 mlx5e_init(void)
4107 {
4108         mlx5_register_interface(&mlx5e_interface);
4109 }
4110
4111 void
4112 mlx5e_cleanup(void)
4113 {
4114         mlx5_unregister_interface(&mlx5e_interface);
4115 }
4116
4117 static void
4118 mlx5e_show_version(void __unused *arg)
4119 {
4120
4121         printf("%s", mlx5e_version);
4122 }
4123 SYSINIT(mlx5e_show_version, SI_SUB_DRIVERS, SI_ORDER_ANY, mlx5e_show_version, NULL);
4124
4125 module_init_order(mlx5e_init, SI_ORDER_THIRD);
4126 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
4127
4128 #if (__FreeBSD_version >= 1100000)
4129 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
4130 #endif
4131 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
4132 MODULE_VERSION(mlx5en, 1);