sys/dev/mlx5/mlx5_en/mlx5_en_main.c

   1 /*-
   2  * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include "opt_kern_tls.h"
  29
  30 #include "en.h"
  31
  32 #include <sys/eventhandler.h>
  33 #include <sys/sockio.h>
  34 #include <machine/atomic.h>
  35
  36 #include <net/debugnet.h>
  37
  38 #ifndef ETH_DRIVER_VERSION
  39 #define ETH_DRIVER_VERSION      "3.5.2"
  40 #endif
  41 #define DRIVER_RELDATE  "September 2019"
  42
  43 static const char mlx5e_version[] = "mlx5en: Mellanox Ethernet driver "
  44         ETH_DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
  45
  46 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs);
  47
  48 struct mlx5e_channel_param {
  49         struct mlx5e_rq_param rq;
  50         struct mlx5e_sq_param sq;
  51         struct mlx5e_cq_param rx_cq;
  52         struct mlx5e_cq_param tx_cq;
  53 };
  54
  55 struct media {
  56         u32     subtype;
  57         u64     baudrate;
  58 };
  59
  60 static const struct media mlx5e_mode_table[MLX5E_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = {
  61
  62         [MLX5E_1000BASE_CX_SGMII][MLX5E_SGMII] = {
  63                 .subtype = IFM_1000_CX_SGMII,
  64                 .baudrate = IF_Mbps(1000ULL),
  65         },
  66         [MLX5E_1000BASE_KX][MLX5E_KX] = {
  67                 .subtype = IFM_1000_KX,
  68                 .baudrate = IF_Mbps(1000ULL),
  69         },
  70         [MLX5E_10GBASE_CX4][MLX5E_CX4] = {
  71                 .subtype = IFM_10G_CX4,
  72                 .baudrate = IF_Gbps(10ULL),
  73         },
  74         [MLX5E_10GBASE_KX4][MLX5E_KX4] = {
  75                 .subtype = IFM_10G_KX4,
  76                 .baudrate = IF_Gbps(10ULL),
  77         },
  78         [MLX5E_10GBASE_KR][MLX5E_KR] = {
  79                 .subtype = IFM_10G_KR,
  80                 .baudrate = IF_Gbps(10ULL),
  81         },
  82         [MLX5E_20GBASE_KR2][MLX5E_KR2] = {
  83                 .subtype = IFM_20G_KR2,
  84                 .baudrate = IF_Gbps(20ULL),
  85         },
  86         [MLX5E_40GBASE_CR4][MLX5E_CR4] = {
  87                 .subtype = IFM_40G_CR4,
  88                 .baudrate = IF_Gbps(40ULL),
  89         },
  90         [MLX5E_40GBASE_KR4][MLX5E_KR4] = {
  91                 .subtype = IFM_40G_KR4,
  92                 .baudrate = IF_Gbps(40ULL),
  93         },
  94         [MLX5E_56GBASE_R4][MLX5E_R] = {
  95                 .subtype = IFM_56G_R4,
  96                 .baudrate = IF_Gbps(56ULL),
  97         },
  98         [MLX5E_10GBASE_CR][MLX5E_CR1] = {
  99                 .subtype = IFM_10G_CR1,
 100                 .baudrate = IF_Gbps(10ULL),
 101         },
 102         [MLX5E_10GBASE_SR][MLX5E_SR] = {
 103                 .subtype = IFM_10G_SR,
 104                 .baudrate = IF_Gbps(10ULL),
 105         },
 106         [MLX5E_10GBASE_ER_LR][MLX5E_ER] = {
 107                 .subtype = IFM_10G_ER,
 108                 .baudrate = IF_Gbps(10ULL),
 109         },
 110         [MLX5E_10GBASE_ER_LR][MLX5E_LR] = {
 111                 .subtype = IFM_10G_LR,
 112                 .baudrate = IF_Gbps(10ULL),
 113         },
 114         [MLX5E_40GBASE_SR4][MLX5E_SR4] = {
 115                 .subtype = IFM_40G_SR4,
 116                 .baudrate = IF_Gbps(40ULL),
 117         },
 118         [MLX5E_40GBASE_LR4_ER4][MLX5E_LR4] = {
 119                 .subtype = IFM_40G_LR4,
 120                 .baudrate = IF_Gbps(40ULL),
 121         },
 122         [MLX5E_40GBASE_LR4_ER4][MLX5E_ER4] = {
 123                 .subtype = IFM_40G_ER4,
 124                 .baudrate = IF_Gbps(40ULL),
 125         },
 126         [MLX5E_100GBASE_CR4][MLX5E_CR4] = {
 127                 .subtype = IFM_100G_CR4,
 128                 .baudrate = IF_Gbps(100ULL),
 129         },
 130         [MLX5E_100GBASE_SR4][MLX5E_SR4] = {
 131                 .subtype = IFM_100G_SR4,
 132                 .baudrate = IF_Gbps(100ULL),
 133         },
 134         [MLX5E_100GBASE_KR4][MLX5E_KR4] = {
 135                 .subtype = IFM_100G_KR4,
 136                 .baudrate = IF_Gbps(100ULL),
 137         },
 138         [MLX5E_100GBASE_LR4][MLX5E_LR4] = {
 139                 .subtype = IFM_100G_LR4,
 140                 .baudrate = IF_Gbps(100ULL),
 141         },
 142         [MLX5E_100BASE_TX][MLX5E_TX] = {
 143                 .subtype = IFM_100_TX,
 144                 .baudrate = IF_Mbps(100ULL),
 145         },
 146         [MLX5E_1000BASE_T][MLX5E_T] = {
 147                 .subtype = IFM_1000_T,
 148                 .baudrate = IF_Mbps(1000ULL),
 149         },
 150         [MLX5E_10GBASE_T][MLX5E_T] = {
 151                 .subtype = IFM_10G_T,
 152                 .baudrate = IF_Gbps(10ULL),
 153         },
 154         [MLX5E_25GBASE_CR][MLX5E_CR] = {
 155                 .subtype = IFM_25G_CR,
 156                 .baudrate = IF_Gbps(25ULL),
 157         },
 158         [MLX5E_25GBASE_KR][MLX5E_KR] = {
 159                 .subtype = IFM_25G_KR,
 160                 .baudrate = IF_Gbps(25ULL),
 161         },
 162         [MLX5E_25GBASE_SR][MLX5E_SR] = {
 163                 .subtype = IFM_25G_SR,
 164                 .baudrate = IF_Gbps(25ULL),
 165         },
 166         [MLX5E_50GBASE_CR2][MLX5E_CR2] = {
 167                 .subtype = IFM_50G_CR2,
 168                 .baudrate = IF_Gbps(50ULL),
 169         },
 170         [MLX5E_50GBASE_KR2][MLX5E_KR2] = {
 171                 .subtype = IFM_50G_KR2,
 172                 .baudrate = IF_Gbps(50ULL),
 173         },
 174 };
 175
 176 static const struct media mlx5e_ext_mode_table[MLX5E_EXT_LINK_SPEEDS_NUMBER][MLX5E_LINK_MODES_NUMBER] = {
 177         [MLX5E_SGMII_100M][MLX5E_SGMII] = {
 178                 .subtype = IFM_100_SGMII,
 179                 .baudrate = IF_Mbps(100),
 180         },
 181         [MLX5E_1000BASE_X_SGMII][MLX5E_KX] = {
 182                 .subtype = IFM_1000_KX,
 183                 .baudrate = IF_Mbps(1000),
 184         },
 185         [MLX5E_1000BASE_X_SGMII][MLX5E_CX_SGMII] = {
 186                 .subtype = IFM_1000_CX_SGMII,
 187                 .baudrate = IF_Mbps(1000),
 188         },
 189         [MLX5E_1000BASE_X_SGMII][MLX5E_CX] = {
 190                 .subtype = IFM_1000_CX,
 191                 .baudrate = IF_Mbps(1000),
 192         },
 193         [MLX5E_1000BASE_X_SGMII][MLX5E_LX] = {
 194                 .subtype = IFM_1000_LX,
 195                 .baudrate = IF_Mbps(1000),
 196         },
 197         [MLX5E_1000BASE_X_SGMII][MLX5E_SX] = {
 198                 .subtype = IFM_1000_SX,
 199                 .baudrate = IF_Mbps(1000),
 200         },
 201         [MLX5E_1000BASE_X_SGMII][MLX5E_T] = {
 202                 .subtype = IFM_1000_T,
 203                 .baudrate = IF_Mbps(1000),
 204         },
 205         [MLX5E_5GBASE_R][MLX5E_T] = {
 206                 .subtype = IFM_5000_T,
 207                 .baudrate = IF_Mbps(5000),
 208         },
 209         [MLX5E_5GBASE_R][MLX5E_KR] = {
 210                 .subtype = IFM_5000_KR,
 211                 .baudrate = IF_Mbps(5000),
 212         },
 213         [MLX5E_5GBASE_R][MLX5E_KR1] = {
 214                 .subtype = IFM_5000_KR1,
 215                 .baudrate = IF_Mbps(5000),
 216         },
 217         [MLX5E_5GBASE_R][MLX5E_KR_S] = {
 218                 .subtype = IFM_5000_KR_S,
 219                 .baudrate = IF_Mbps(5000),
 220         },
 221         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_ER] = {
 222                 .subtype = IFM_10G_ER,
 223                 .baudrate = IF_Gbps(10ULL),
 224         },
 225         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_KR] = {
 226                 .subtype = IFM_10G_KR,
 227                 .baudrate = IF_Gbps(10ULL),
 228         },
 229         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_LR] = {
 230                 .subtype = IFM_10G_LR,
 231                 .baudrate = IF_Gbps(10ULL),
 232         },
 233         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_SR] = {
 234                 .subtype = IFM_10G_SR,
 235                 .baudrate = IF_Gbps(10ULL),
 236         },
 237         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_T] = {
 238                 .subtype = IFM_10G_T,
 239                 .baudrate = IF_Gbps(10ULL),
 240         },
 241         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_AOC] = {
 242                 .subtype = IFM_10G_AOC,
 243                 .baudrate = IF_Gbps(10ULL),
 244         },
 245         [MLX5E_10GBASE_XFI_XAUI_1][MLX5E_CR1] = {
 246                 .subtype = IFM_10G_CR1,
 247                 .baudrate = IF_Gbps(10ULL),
 248         },
 249         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_CR4] = {
 250                 .subtype = IFM_40G_CR4,
 251                 .baudrate = IF_Gbps(40ULL),
 252         },
 253         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_KR4] = {
 254                 .subtype = IFM_40G_KR4,
 255                 .baudrate = IF_Gbps(40ULL),
 256         },
 257         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_LR4] = {
 258                 .subtype = IFM_40G_LR4,
 259                 .baudrate = IF_Gbps(40ULL),
 260         },
 261         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_SR4] = {
 262                 .subtype = IFM_40G_SR4,
 263                 .baudrate = IF_Gbps(40ULL),
 264         },
 265         [MLX5E_40GBASE_XLAUI_4_XLPPI_4][MLX5E_ER4] = {
 266                 .subtype = IFM_40G_ER4,
 267                 .baudrate = IF_Gbps(40ULL),
 268         },
 269
 270         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR] = {
 271                 .subtype = IFM_25G_CR,
 272                 .baudrate = IF_Gbps(25ULL),
 273         },
 274         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR] = {
 275                 .subtype = IFM_25G_KR,
 276                 .baudrate = IF_Gbps(25ULL),
 277         },
 278         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_SR] = {
 279                 .subtype = IFM_25G_SR,
 280                 .baudrate = IF_Gbps(25ULL),
 281         },
 282         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_ACC] = {
 283                 .subtype = IFM_25G_ACC,
 284                 .baudrate = IF_Gbps(25ULL),
 285         },
 286         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_AOC] = {
 287                 .subtype = IFM_25G_AOC,
 288                 .baudrate = IF_Gbps(25ULL),
 289         },
 290         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR1] = {
 291                 .subtype = IFM_25G_CR1,
 292                 .baudrate = IF_Gbps(25ULL),
 293         },
 294         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_CR_S] = {
 295                 .subtype = IFM_25G_CR_S,
 296                 .baudrate = IF_Gbps(25ULL),
 297         },
 298         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR1] = {
 299                 .subtype = IFM_5000_KR1,
 300                 .baudrate = IF_Gbps(25ULL),
 301         },
 302         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_KR_S] = {
 303                 .subtype = IFM_25G_KR_S,
 304                 .baudrate = IF_Gbps(25ULL),
 305         },
 306         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_LR] = {
 307                 .subtype = IFM_25G_LR,
 308                 .baudrate = IF_Gbps(25ULL),
 309         },
 310         [MLX5E_25GAUI_1_25GBASE_CR_KR][MLX5E_T] = {
 311                 .subtype = IFM_25G_T,
 312                 .baudrate = IF_Gbps(25ULL),
 313         },
 314         [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_CR2] = {
 315                 .subtype = IFM_50G_CR2,
 316                 .baudrate = IF_Gbps(50ULL),
 317         },
 318         [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_KR2] = {
 319                 .subtype = IFM_50G_KR2,
 320                 .baudrate = IF_Gbps(50ULL),
 321         },
 322         [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_SR2] = {
 323                 .subtype = IFM_50G_SR2,
 324                 .baudrate = IF_Gbps(50ULL),
 325         },
 326         [MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2][MLX5E_LR2] = {
 327                 .subtype = IFM_50G_LR2,
 328                 .baudrate = IF_Gbps(50ULL),
 329         },
 330         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_LR] = {
 331                 .subtype = IFM_50G_LR,
 332                 .baudrate = IF_Gbps(50ULL),
 333         },
 334         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_SR] = {
 335                 .subtype = IFM_50G_SR,
 336                 .baudrate = IF_Gbps(50ULL),
 337         },
 338         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_CP] = {
 339                 .subtype = IFM_50G_CP,
 340                 .baudrate = IF_Gbps(50ULL),
 341         },
 342         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_FR] = {
 343                 .subtype = IFM_50G_FR,
 344                 .baudrate = IF_Gbps(50ULL),
 345         },
 346         [MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR][MLX5E_KR_PAM4] = {
 347                 .subtype = IFM_50G_KR_PAM4,
 348                 .baudrate = IF_Gbps(50ULL),
 349         },
 350         [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_CR4] = {
 351                 .subtype = IFM_100G_CR4,
 352                 .baudrate = IF_Gbps(100ULL),
 353         },
 354         [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_KR4] = {
 355                 .subtype = IFM_100G_KR4,
 356                 .baudrate = IF_Gbps(100ULL),
 357         },
 358         [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_LR4] = {
 359                 .subtype = IFM_100G_LR4,
 360                 .baudrate = IF_Gbps(100ULL),
 361         },
 362         [MLX5E_CAUI_4_100GBASE_CR4_KR4][MLX5E_SR4] = {
 363                 .subtype = IFM_100G_SR4,
 364                 .baudrate = IF_Gbps(100ULL),
 365         },
 366         [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_SR2] = {
 367                 .subtype = IFM_100G_SR2,
 368                 .baudrate = IF_Gbps(100ULL),
 369         },
 370         [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_CP2] = {
 371                 .subtype = IFM_100G_CP2,
 372                 .baudrate = IF_Gbps(100ULL),
 373         },
 374         [MLX5E_100GAUI_2_100GBASE_CR2_KR2][MLX5E_KR2_PAM4] = {
 375                 .subtype = IFM_100G_KR2_PAM4,
 376                 .baudrate = IF_Gbps(100ULL),
 377         },
 378         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_DR4] = {
 379                 .subtype = IFM_200G_DR4,
 380                 .baudrate = IF_Gbps(200ULL),
 381         },
 382         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_LR4] = {
 383                 .subtype = IFM_200G_LR4,
 384                 .baudrate = IF_Gbps(200ULL),
 385         },
 386         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_SR4] = {
 387                 .subtype = IFM_200G_SR4,
 388                 .baudrate = IF_Gbps(200ULL),
 389         },
 390         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_FR4] = {
 391                 .subtype = IFM_200G_FR4,
 392                 .baudrate = IF_Gbps(200ULL),
 393         },
 394         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_CR4_PAM4] = {
 395                 .subtype = IFM_200G_CR4_PAM4,
 396                 .baudrate = IF_Gbps(200ULL),
 397         },
 398         [MLX5E_200GAUI_4_200GBASE_CR4_KR4][MLX5E_KR4_PAM4] = {
 399                 .subtype = IFM_200G_KR4_PAM4,
 400                 .baudrate = IF_Gbps(200ULL),
 401         },
 402 };
 403
 404 DEBUGNET_DEFINE(mlx5_en);
 405
 406 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
 407
 408 static void
 409 mlx5e_update_carrier(struct mlx5e_priv *priv)
 410 {
 411         struct mlx5_core_dev *mdev = priv->mdev;
 412         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 413         u32 eth_proto_oper;
 414         int error;
 415         u8 port_state;
 416         u8 is_er_type;
 417         u8 i, j;
 418         bool ext;
 419         struct media media_entry = {};
 420
 421         port_state = mlx5_query_vport_state(mdev,
 422             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 423
 424         if (port_state == VPORT_STATE_UP) {
 425                 priv->media_status_last |= IFM_ACTIVE;
 426         } else {
 427                 priv->media_status_last &= ~IFM_ACTIVE;
 428                 priv->media_active_last = IFM_ETHER;
 429                 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
 430                 return;
 431         }
 432
 433         error = mlx5_query_port_ptys(mdev, out, sizeof(out),
 434             MLX5_PTYS_EN, 1);
 435         if (error) {
 436                 priv->media_active_last = IFM_ETHER;
 437                 priv->ifp->if_baudrate = 1;
 438                 mlx5_en_err(priv->ifp, "query port ptys failed: 0x%x\n",
 439                     error);
 440                 return;
 441         }
 442
 443         ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
 444         eth_proto_oper = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
 445             eth_proto_oper);
 446
 447         i = ilog2(eth_proto_oper);
 448
 449         for (j = 0; j != MLX5E_LINK_MODES_NUMBER; j++) {
 450                 media_entry = ext ? mlx5e_ext_mode_table[i][j] :
 451                     mlx5e_mode_table[i][j];
 452                 if (media_entry.baudrate != 0)
 453                         break;
 454         }
 455
 456         if (media_entry.subtype == 0) {
 457                 mlx5_en_err(priv->ifp,
 458                     "Could not find operational media subtype\n");
 459                 return;
 460         }
 461
 462         switch (media_entry.subtype) {
 463         case IFM_10G_ER:
 464                 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
 465                 if (error != 0) {
 466                         mlx5_en_err(priv->ifp,
 467                             "query port pddr failed: %d\n", error);
 468                 }
 469                 if (error != 0 || is_er_type == 0)
 470                         media_entry.subtype = IFM_10G_LR;
 471                 break;
 472         case IFM_40G_LR4:
 473                 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
 474                 if (error != 0) {
 475                         mlx5_en_err(priv->ifp,
 476                             "query port pddr failed: %d\n", error);
 477                 }
 478                 if (error == 0 && is_er_type != 0)
 479                         media_entry.subtype = IFM_40G_ER4;
 480                 break;
 481         }
 482         priv->media_active_last = media_entry.subtype | IFM_ETHER | IFM_FDX;
 483         priv->ifp->if_baudrate = media_entry.baudrate;
 484
 485         if_link_state_change(priv->ifp, LINK_STATE_UP);
 486 }
 487
 488 static void
 489 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
 490 {
 491         struct mlx5e_priv *priv = dev->if_softc;
 492
 493         ifmr->ifm_status = priv->media_status_last;
 494         ifmr->ifm_active = priv->media_active_last |
 495             (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
 496             (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
 497
 498 }
 499
 500 static u32
 501 mlx5e_find_link_mode(u32 subtype, bool ext)
 502 {
 503         u32 i;
 504         u32 j;
 505         u32 link_mode = 0;
 506         u32 speeds_num = 0;
 507         struct media media_entry = {};
 508
 509         switch (subtype) {
 510         case IFM_10G_LR:
 511                 subtype = IFM_10G_ER;
 512                 break;
 513         case IFM_40G_ER4:
 514                 subtype = IFM_40G_LR4;
 515                 break;
 516         }
 517
 518         speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER :
 519             MLX5E_LINK_SPEEDS_NUMBER;
 520
 521         for (i = 0; i != speeds_num; i++) {
 522                 for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) {
 523                         media_entry = ext ? mlx5e_ext_mode_table[i][j] :
 524                             mlx5e_mode_table[i][j];
 525                         if (media_entry.baudrate == 0)
 526                                 continue;
 527                         if (media_entry.subtype == subtype) {
 528                                 link_mode |= MLX5E_PROT_MASK(i);
 529                         }
 530                 }
 531         }
 532
 533         return (link_mode);
 534 }
 535
 536 static int
 537 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv)
 538 {
 539         return (mlx5_set_port_pause_and_pfc(priv->mdev, 1,
 540             priv->params.rx_pauseframe_control,
 541             priv->params.tx_pauseframe_control,
 542             priv->params.rx_priority_flow_control,
 543             priv->params.tx_priority_flow_control));
 544 }
 545
 546 static int
 547 mlx5e_set_port_pfc(struct mlx5e_priv *priv)
 548 {
 549         int error;
 550
 551         if (priv->gone != 0) {
 552                 error = -ENXIO;
 553         } else if (priv->params.rx_pauseframe_control ||
 554             priv->params.tx_pauseframe_control) {
 555                 mlx5_en_err(priv->ifp,
 556                     "Global pauseframes must be disabled before enabling PFC.\n");
 557                 error = -EINVAL;
 558         } else {
 559                 error = mlx5e_set_port_pause_and_pfc(priv);
 560         }
 561         return (error);
 562 }
 563
 564 static int
 565 mlx5e_media_change(struct ifnet *dev)
 566 {
 567         struct mlx5e_priv *priv = dev->if_softc;
 568         struct mlx5_core_dev *mdev = priv->mdev;
 569         u32 eth_proto_cap;
 570         u32 link_mode;
 571         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 572         int was_opened;
 573         int locked;
 574         int error;
 575         bool ext;
 576
 577         locked = PRIV_LOCKED(priv);
 578         if (!locked)
 579                 PRIV_LOCK(priv);
 580
 581         if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
 582                 error = EINVAL;
 583                 goto done;
 584         }
 585
 586         error = mlx5_query_port_ptys(mdev, out, sizeof(out),
 587             MLX5_PTYS_EN, 1);
 588         if (error != 0) {
 589                 mlx5_en_err(dev, "Query port media capability failed\n");
 590                 goto done;
 591         }
 592
 593         ext = MLX5_CAP_PCAM_FEATURE(mdev, ptys_extended_ethernet);
 594         link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media), ext);
 595
 596         /* query supported capabilities */
 597         eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
 598             eth_proto_capability);
 599
 600         /* check for autoselect */
 601         if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
 602                 link_mode = eth_proto_cap;
 603                 if (link_mode == 0) {
 604                         mlx5_en_err(dev, "Port media capability is zero\n");
 605                         error = EINVAL;
 606                         goto done;
 607                 }
 608         } else {
 609                 link_mode = link_mode & eth_proto_cap;
 610                 if (link_mode == 0) {
 611                         mlx5_en_err(dev, "Not supported link mode requested\n");
 612                         error = EINVAL;
 613                         goto done;
 614                 }
 615         }
 616         if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
 617                 /* check if PFC is enabled */
 618                 if (priv->params.rx_priority_flow_control ||
 619                     priv->params.tx_priority_flow_control) {
 620                         mlx5_en_err(dev, "PFC must be disabled before enabling global pauseframes.\n");
 621                         error = EINVAL;
 622                         goto done;
 623                 }
 624         }
 625         /* update pauseframe control bits */
 626         priv->params.rx_pauseframe_control =
 627             (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
 628         priv->params.tx_pauseframe_control =
 629             (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
 630
 631         /* check if device is opened */
 632         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
 633
 634         /* reconfigure the hardware */
 635         mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
 636         mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN, ext);
 637         error = -mlx5e_set_port_pause_and_pfc(priv);
 638         if (was_opened)
 639                 mlx5_set_port_status(mdev, MLX5_PORT_UP);
 640
 641 done:
 642         if (!locked)
 643                 PRIV_UNLOCK(priv);
 644         return (error);
 645 }
 646
 647 static void
 648 mlx5e_update_carrier_work(struct work_struct *work)
 649 {
 650         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 651             update_carrier_work);
 652
 653         PRIV_LOCK(priv);
 654         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 655                 mlx5e_update_carrier(priv);
 656         PRIV_UNLOCK(priv);
 657 }
 658
 659 #define MLX5E_PCIE_PERF_GET_64(a,b,c,d,e,f)    \
 660         s_debug->c = MLX5_GET64(mpcnt_reg, out, counter_set.f.c);
 661
 662 #define MLX5E_PCIE_PERF_GET_32(a,b,c,d,e,f)    \
 663         s_debug->c = MLX5_GET(mpcnt_reg, out, counter_set.f.c);
 664
 665 static void
 666 mlx5e_update_pcie_counters(struct mlx5e_priv *priv)
 667 {
 668         struct mlx5_core_dev *mdev = priv->mdev;
 669         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 670         const unsigned sz = MLX5_ST_SZ_BYTES(mpcnt_reg);
 671         void *out;
 672         void *in;
 673         int err;
 674
 675         /* allocate firmware request structures */
 676         in = mlx5_vzalloc(sz);
 677         out = mlx5_vzalloc(sz);
 678         if (in == NULL || out == NULL)
 679                 goto free_out;
 680
 681         MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP);
 682         err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
 683         if (err != 0)
 684                 goto free_out;
 685
 686         MLX5E_PCIE_PERFORMANCE_COUNTERS_64(MLX5E_PCIE_PERF_GET_64)
 687         MLX5E_PCIE_PERFORMANCE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
 688
 689         MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP);
 690         err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
 691         if (err != 0)
 692                 goto free_out;
 693
 694         MLX5E_PCIE_TIMERS_AND_STATES_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
 695
 696         MLX5_SET(mpcnt_reg, in, grp, MLX5_PCIE_LANE_COUNTERS_GROUP);
 697         err = mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_MPCNT, 0, 0);
 698         if (err != 0)
 699                 goto free_out;
 700
 701         MLX5E_PCIE_LANE_COUNTERS_32(MLX5E_PCIE_PERF_GET_32)
 702
 703 free_out:
 704         /* free firmware request structures */
 705         kvfree(in);
 706         kvfree(out);
 707 }
 708
 709 /*
 710  * This function reads the physical port counters from the firmware
 711  * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
 712  * macros. The output is converted from big-endian 64-bit values into
 713  * host endian ones and stored in the "priv->stats.pport" structure.
 714  */
 715 static void
 716 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 717 {
 718         struct mlx5_core_dev *mdev = priv->mdev;
 719         struct mlx5e_pport_stats *s = &priv->stats.pport;
 720         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 721         u32 *in;
 722         u32 *out;
 723         const u64 *ptr;
 724         unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 725         unsigned x;
 726         unsigned y;
 727         unsigned z;
 728
 729         /* allocate firmware request structures */
 730         in = mlx5_vzalloc(sz);
 731         out = mlx5_vzalloc(sz);
 732         if (in == NULL || out == NULL)
 733                 goto free_out;
 734
 735         /*
 736          * Get pointer to the 64-bit counter set which is located at a
 737          * fixed offset in the output firmware request structure:
 738          */
 739         ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
 740
 741         MLX5_SET(ppcnt_reg, in, local_port, 1);
 742
 743         /* read IEEE802_3 counter group using predefined counter layout */
 744         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 745         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 746         for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM;
 747              x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
 748                 s->arg[y] = be64toh(ptr[x]);
 749
 750         /* read RFC2819 counter group using predefined counter layout */
 751         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 752         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 753         for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
 754                 s->arg[y] = be64toh(ptr[x]);
 755
 756         for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
 757             MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
 758                 s_debug->arg[y] = be64toh(ptr[x]);
 759
 760         /* read RFC2863 counter group using predefined counter layout */
 761         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 762         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 763         for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
 764                 s_debug->arg[y] = be64toh(ptr[x]);
 765
 766         /* read physical layer stats counter group using predefined counter layout */
 767         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 768         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 769         for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
 770                 s_debug->arg[y] = be64toh(ptr[x]);
 771
 772         /* read Extended Ethernet counter group using predefined counter layout */
 773         MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
 774         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 775         for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++)
 776                 s_debug->arg[y] = be64toh(ptr[x]);
 777
 778         /* read Extended Statistical Group */
 779         if (MLX5_CAP_GEN(mdev, pcam_reg) &&
 780             MLX5_CAP_PCAM_FEATURE(mdev, ppcnt_statistical_group) &&
 781             MLX5_CAP_PCAM_FEATURE(mdev, per_lane_error_counters)) {
 782                 /* read Extended Statistical counter group using predefined counter layout */
 783                 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_STATISTICAL_GROUP);
 784                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 785
 786                 for (x = 0; x != MLX5E_PPORT_STATISTICAL_DEBUG_NUM; x++, y++)
 787                         s_debug->arg[y] = be64toh(ptr[x]);
 788         }
 789
 790         /* read PCIE counters */
 791         mlx5e_update_pcie_counters(priv);
 792
 793         /* read per-priority counters */
 794         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 795
 796         /* iterate all the priorities */
 797         for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) {
 798                 MLX5_SET(ppcnt_reg, in, prio_tc, z);
 799                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 800
 801                 /* read per priority stats counter group using predefined counter layout */
 802                 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM /
 803                     MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++)
 804                         s->arg[y] = be64toh(ptr[x]);
 805         }
 806
 807 free_out:
 808         /* free firmware request structures */
 809         kvfree(in);
 810         kvfree(out);
 811 }
 812
 813 static void
 814 mlx5e_grp_vnic_env_update_stats(struct mlx5e_priv *priv)
 815 {
 816         u32 out[MLX5_ST_SZ_DW(query_vnic_env_out)] = {};
 817         u32 in[MLX5_ST_SZ_DW(query_vnic_env_in)] = {};
 818
 819         if (!MLX5_CAP_GEN(priv->mdev, nic_receive_steering_discard))
 820                 return;
 821
 822         MLX5_SET(query_vnic_env_in, in, opcode,
 823             MLX5_CMD_OP_QUERY_VNIC_ENV);
 824         MLX5_SET(query_vnic_env_in, in, op_mod, 0);
 825         MLX5_SET(query_vnic_env_in, in, other_vport, 0);
 826
 827         if (mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out)) != 0)
 828                 return;
 829
 830         priv->stats.vport.rx_steer_missed_packets =
 831             MLX5_GET64(query_vnic_env_out, out,
 832             vport_env.nic_receive_steering_discard);
 833 }
 834
 835 /*
 836  * This function is called regularly to collect all statistics
 837  * counters from the firmware. The values can be viewed through the
 838  * sysctl interface. Execution is serialized using the priv's global
 839  * configuration lock.
 840  */
 841 static void
 842 mlx5e_update_stats_locked(struct mlx5e_priv *priv)
 843 {
 844         struct mlx5_core_dev *mdev = priv->mdev;
 845         struct mlx5e_vport_stats *s = &priv->stats.vport;
 846         struct mlx5e_sq_stats *sq_stats;
 847         struct buf_ring *sq_br;
 848 #if (__FreeBSD_version < 1100000)
 849         struct ifnet *ifp = priv->ifp;
 850 #endif
 851
 852         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 853         u32 *out;
 854         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 855         u64 tso_packets = 0;
 856         u64 tso_bytes = 0;
 857         u64 tx_queue_dropped = 0;
 858         u64 tx_defragged = 0;
 859         u64 tx_offload_none = 0;
 860         u64 lro_packets = 0;
 861         u64 lro_bytes = 0;
 862         u64 sw_lro_queued = 0;
 863         u64 sw_lro_flushed = 0;
 864         u64 rx_csum_none = 0;
 865         u64 rx_wqe_err = 0;
 866         u64 rx_packets = 0;
 867         u64 rx_bytes = 0;
 868         u32 rx_out_of_buffer = 0;
 869         int error;
 870         int i;
 871         int j;
 872
 873         out = mlx5_vzalloc(outlen);
 874         if (out == NULL)
 875                 goto free_out;
 876
 877         /* Collect firts the SW counters and then HW for consistency */
 878         for (i = 0; i < priv->params.num_channels; i++) {
 879                 struct mlx5e_channel *pch = priv->channel + i;
 880                 struct mlx5e_rq *rq = &pch->rq;
 881                 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats;
 882
 883                 /* collect stats from LRO */
 884                 rq_stats->sw_lro_queued = rq->lro.lro_queued;
 885                 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
 886                 sw_lro_queued += rq_stats->sw_lro_queued;
 887                 sw_lro_flushed += rq_stats->sw_lro_flushed;
 888                 lro_packets += rq_stats->lro_packets;
 889                 lro_bytes += rq_stats->lro_bytes;
 890                 rx_csum_none += rq_stats->csum_none;
 891                 rx_wqe_err += rq_stats->wqe_err;
 892                 rx_packets += rq_stats->packets;
 893                 rx_bytes += rq_stats->bytes;
 894
 895                 for (j = 0; j < priv->num_tc; j++) {
 896                         sq_stats = &pch->sq[j].stats;
 897                         sq_br = pch->sq[j].br;
 898
 899                         tso_packets += sq_stats->tso_packets;
 900                         tso_bytes += sq_stats->tso_bytes;
 901                         tx_queue_dropped += sq_stats->dropped;
 902                         if (sq_br != NULL)
 903                                 tx_queue_dropped += sq_br->br_drops;
 904                         tx_defragged += sq_stats->defragged;
 905                         tx_offload_none += sq_stats->csum_offload_none;
 906                 }
 907         }
 908
 909         /* update counters */
 910         s->tso_packets = tso_packets;
 911         s->tso_bytes = tso_bytes;
 912         s->tx_queue_dropped = tx_queue_dropped;
 913         s->tx_defragged = tx_defragged;
 914         s->lro_packets = lro_packets;
 915         s->lro_bytes = lro_bytes;
 916         s->sw_lro_queued = sw_lro_queued;
 917         s->sw_lro_flushed = sw_lro_flushed;
 918         s->rx_csum_none = rx_csum_none;
 919         s->rx_wqe_err = rx_wqe_err;
 920         s->rx_packets = rx_packets;
 921         s->rx_bytes = rx_bytes;
 922
 923         mlx5e_grp_vnic_env_update_stats(priv);
 924
 925         /* HW counters */
 926         memset(in, 0, sizeof(in));
 927
 928         MLX5_SET(query_vport_counter_in, in, opcode,
 929             MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 930         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 931         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 932
 933         memset(out, 0, outlen);
 934
 935         /* get number of out-of-buffer drops first */
 936         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 &&
 937             mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
 938             &rx_out_of_buffer) == 0) {
 939                 s->rx_out_of_buffer = rx_out_of_buffer;
 940         }
 941
 942         /* get port statistics */
 943         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen) == 0) {
 944 #define MLX5_GET_CTR(out, x) \
 945         MLX5_GET64(query_vport_counter_out, out, x)
 946
 947                 s->rx_error_packets =
 948                     MLX5_GET_CTR(out, received_errors.packets);
 949                 s->rx_error_bytes =
 950                     MLX5_GET_CTR(out, received_errors.octets);
 951                 s->tx_error_packets =
 952                     MLX5_GET_CTR(out, transmit_errors.packets);
 953                 s->tx_error_bytes =
 954                     MLX5_GET_CTR(out, transmit_errors.octets);
 955
 956                 s->rx_unicast_packets =
 957                     MLX5_GET_CTR(out, received_eth_unicast.packets);
 958                 s->rx_unicast_bytes =
 959                     MLX5_GET_CTR(out, received_eth_unicast.octets);
 960                 s->tx_unicast_packets =
 961                     MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 962                 s->tx_unicast_bytes =
 963                     MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 964
 965                 s->rx_multicast_packets =
 966                     MLX5_GET_CTR(out, received_eth_multicast.packets);
 967                 s->rx_multicast_bytes =
 968                     MLX5_GET_CTR(out, received_eth_multicast.octets);
 969                 s->tx_multicast_packets =
 970                     MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 971                 s->tx_multicast_bytes =
 972                     MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 973
 974                 s->rx_broadcast_packets =
 975                     MLX5_GET_CTR(out, received_eth_broadcast.packets);
 976                 s->rx_broadcast_bytes =
 977                     MLX5_GET_CTR(out, received_eth_broadcast.octets);
 978                 s->tx_broadcast_packets =
 979                     MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 980                 s->tx_broadcast_bytes =
 981                     MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 982
 983                 s->tx_packets = s->tx_unicast_packets +
 984                     s->tx_multicast_packets + s->tx_broadcast_packets;
 985                 s->tx_bytes = s->tx_unicast_bytes + s->tx_multicast_bytes +
 986                     s->tx_broadcast_bytes;
 987
 988                 /* Update calculated offload counters */
 989                 s->tx_csum_offload = s->tx_packets - tx_offload_none;
 990                 s->rx_csum_good = s->rx_packets - s->rx_csum_none;
 991         }
 992
 993         /* Get physical port counters */
 994         mlx5e_update_pport_counters(priv);
 995
 996         s->tx_jumbo_packets =
 997             priv->stats.port_stats_debug.tx_stat_p1519to2047octets +
 998             priv->stats.port_stats_debug.tx_stat_p2048to4095octets +
 999             priv->stats.port_stats_debug.tx_stat_p4096to8191octets +
1000             priv->stats.port_stats_debug.tx_stat_p8192to10239octets;
1001
1002 #if (__FreeBSD_version < 1100000)
1003         /* no get_counters interface in fbsd 10 */
1004         ifp->if_ipackets = s->rx_packets;
1005         ifp->if_ierrors = priv->stats.pport.in_range_len_errors +
1006             priv->stats.pport.out_of_range_len +
1007             priv->stats.pport.too_long_errors +
1008             priv->stats.pport.check_seq_err +
1009             priv->stats.pport.alignment_err;
1010         ifp->if_iqdrops = s->rx_out_of_buffer;
1011         ifp->if_opackets = s->tx_packets;
1012         ifp->if_oerrors = priv->stats.port_stats_debug.out_discards;
1013         ifp->if_snd.ifq_drops = s->tx_queue_dropped;
1014         ifp->if_ibytes = s->rx_bytes;
1015         ifp->if_obytes = s->tx_bytes;
1016         ifp->if_collisions =
1017             priv->stats.pport.collisions;
1018 #endif
1019
1020 free_out:
1021         kvfree(out);
1022
1023         /* Update diagnostics, if any */
1024         if (priv->params_ethtool.diag_pci_enable ||
1025             priv->params_ethtool.diag_general_enable) {
1026                 error = mlx5_core_get_diagnostics_full(mdev,
1027                     priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL,
1028                     priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL);
1029                 if (error != 0)
1030                         mlx5_en_err(priv->ifp,
1031                             "Failed reading diagnostics: %d\n", error);
1032         }
1033
1034         /* Update FEC, if any */
1035         error = mlx5e_fec_update(priv);
1036         if (error != 0 && error != EOPNOTSUPP) {
1037                 mlx5_en_err(priv->ifp,
1038                     "Updating FEC failed: %d\n", error);
1039         }
1040 }
1041
1042 static void
1043 mlx5e_update_stats_work(struct work_struct *work)
1044 {
1045         struct mlx5e_priv *priv;
1046
1047         priv = container_of(work, struct mlx5e_priv, update_stats_work);
1048         PRIV_LOCK(priv);
1049         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 &&
1050             !test_bit(MLX5_INTERFACE_STATE_TEARDOWN, &priv->mdev->intf_state))
1051                 mlx5e_update_stats_locked(priv);
1052         PRIV_UNLOCK(priv);
1053 }
1054
1055 static void
1056 mlx5e_update_stats(void *arg)
1057 {
1058         struct mlx5e_priv *priv = arg;
1059
1060         queue_work(priv->wq, &priv->update_stats_work);
1061
1062         callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
1063 }
1064
1065 static void
1066 mlx5e_async_event_sub(struct mlx5e_priv *priv,
1067     enum mlx5_dev_event event)
1068 {
1069         switch (event) {
1070         case MLX5_DEV_EVENT_PORT_UP:
1071         case MLX5_DEV_EVENT_PORT_DOWN:
1072                 queue_work(priv->wq, &priv->update_carrier_work);
1073                 break;
1074
1075         default:
1076                 break;
1077         }
1078 }
1079
1080 static void
1081 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
1082     enum mlx5_dev_event event, unsigned long param)
1083 {
1084         struct mlx5e_priv *priv = vpriv;
1085
1086         mtx_lock(&priv->async_events_mtx);
1087         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
1088                 mlx5e_async_event_sub(priv, event);
1089         mtx_unlock(&priv->async_events_mtx);
1090 }
1091
1092 static void
1093 mlx5e_enable_async_events(struct mlx5e_priv *priv)
1094 {
1095         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
1096 }
1097
1098 static void
1099 mlx5e_disable_async_events(struct mlx5e_priv *priv)
1100 {
1101         mtx_lock(&priv->async_events_mtx);
1102         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
1103         mtx_unlock(&priv->async_events_mtx);
1104 }
1105
1106 static void mlx5e_calibration_callout(void *arg);
1107 static int mlx5e_calibration_duration = 20;
1108 static int mlx5e_fast_calibration = 1;
1109 static int mlx5e_normal_calibration = 30;
1110
1111 static SYSCTL_NODE(_hw_mlx5, OID_AUTO, calibr, CTLFLAG_RW, 0,
1112     "MLX5 timestamp calibration parameteres");
1113
1114 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, duration, CTLFLAG_RWTUN,
1115     &mlx5e_calibration_duration, 0,
1116     "Duration of initial calibration");
1117 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, fast, CTLFLAG_RWTUN,
1118     &mlx5e_fast_calibration, 0,
1119     "Recalibration interval during initial calibration");
1120 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, normal, CTLFLAG_RWTUN,
1121     &mlx5e_normal_calibration, 0,
1122     "Recalibration interval during normal operations");
1123
1124 /*
1125  * Ignites the calibration process.
1126  */
1127 static void
1128 mlx5e_reset_calibration_callout(struct mlx5e_priv *priv)
1129 {
1130
1131         if (priv->clbr_done == 0)
1132                 mlx5e_calibration_callout(priv);
1133         else
1134                 callout_reset_curcpu(&priv->tstmp_clbr, (priv->clbr_done <
1135                     mlx5e_calibration_duration ? mlx5e_fast_calibration :
1136                     mlx5e_normal_calibration) * hz, mlx5e_calibration_callout,
1137                     priv);
1138 }
1139
1140 static uint64_t
1141 mlx5e_timespec2usec(const struct timespec *ts)
1142 {
1143
1144         return ((uint64_t)ts->tv_sec * 1000000000 + ts->tv_nsec);
1145 }
1146
1147 static uint64_t
1148 mlx5e_hw_clock(struct mlx5e_priv *priv)
1149 {
1150         struct mlx5_init_seg *iseg;
1151         uint32_t hw_h, hw_h1, hw_l;
1152
1153         iseg = priv->mdev->iseg;
1154         do {
1155                 hw_h = ioread32be(&iseg->internal_timer_h);
1156                 hw_l = ioread32be(&iseg->internal_timer_l);
1157                 hw_h1 = ioread32be(&iseg->internal_timer_h);
1158         } while (hw_h1 != hw_h);
1159         return (((uint64_t)hw_h << 32) | hw_l);
1160 }
1161
1162 /*
1163  * The calibration callout, it runs either in the context of the
1164  * thread which enables calibration, or in callout.  It takes the
1165  * snapshot of system and adapter clocks, then advances the pointers to
1166  * the calibration point to allow rx path to read the consistent data
1167  * lockless.
1168  */
1169 static void
1170 mlx5e_calibration_callout(void *arg)
1171 {
1172         struct mlx5e_priv *priv;
1173         struct mlx5e_clbr_point *next, *curr;
1174         struct timespec ts;
1175         int clbr_curr_next;
1176
1177         priv = arg;
1178         curr = &priv->clbr_points[priv->clbr_curr];
1179         clbr_curr_next = priv->clbr_curr + 1;
1180         if (clbr_curr_next >= nitems(priv->clbr_points))
1181                 clbr_curr_next = 0;
1182         next = &priv->clbr_points[clbr_curr_next];
1183
1184         next->base_prev = curr->base_curr;
1185         next->clbr_hw_prev = curr->clbr_hw_curr;
1186
1187         next->clbr_hw_curr = mlx5e_hw_clock(priv);
1188         if (((next->clbr_hw_curr - curr->clbr_hw_curr) >> MLX5E_TSTMP_PREC) ==
1189             0) {
1190                 if (priv->clbr_done != 0) {
1191                         mlx5_en_err(priv->ifp,
1192                             "HW failed tstmp frozen %#jx %#jx, disabling\n",
1193                              next->clbr_hw_curr, curr->clbr_hw_prev);
1194                         priv->clbr_done = 0;
1195                 }
1196                 atomic_store_rel_int(&curr->clbr_gen, 0);
1197                 return;
1198         }
1199
1200         nanouptime(&ts);
1201         next->base_curr = mlx5e_timespec2usec(&ts);
1202
1203         curr->clbr_gen = 0;
1204         atomic_thread_fence_rel();
1205         priv->clbr_curr = clbr_curr_next;
1206         atomic_store_rel_int(&next->clbr_gen, ++(priv->clbr_gen));
1207
1208         if (priv->clbr_done < mlx5e_calibration_duration)
1209                 priv->clbr_done++;
1210         mlx5e_reset_calibration_callout(priv);
1211 }
1212
1213 static const char *mlx5e_rq_stats_desc[] = {
1214         MLX5E_RQ_STATS(MLX5E_STATS_DESC)
1215 };
1216
1217 static int
1218 mlx5e_create_rq(struct mlx5e_channel *c,
1219     struct mlx5e_rq_param *param,
1220     struct mlx5e_rq *rq)
1221 {
1222         struct mlx5e_priv *priv = c->priv;
1223         struct mlx5_core_dev *mdev = priv->mdev;
1224         char buffer[16];
1225         void *rqc = param->rqc;
1226         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
1227         int wq_sz;
1228         int err;
1229         int i;
1230         u32 nsegs, wqe_sz;
1231
1232         err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
1233         if (err != 0)
1234                 goto done;
1235
1236         /* Create DMA descriptor TAG */
1237         if ((err = -bus_dma_tag_create(
1238             bus_get_dma_tag(mdev->pdev->dev.bsddev),
1239             1,                          /* any alignment */
1240             0,                          /* no boundary */
1241             BUS_SPACE_MAXADDR,          /* lowaddr */
1242             BUS_SPACE_MAXADDR,          /* highaddr */
1243             NULL, NULL,                 /* filter, filterarg */
1244             nsegs * MLX5E_MAX_RX_BYTES, /* maxsize */
1245             nsegs,                      /* nsegments */
1246             nsegs * MLX5E_MAX_RX_BYTES, /* maxsegsize */
1247             0,                          /* flags */
1248             NULL, NULL,                 /* lockfunc, lockfuncarg */
1249             &rq->dma_tag)))
1250                 goto done;
1251
1252         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
1253             &rq->wq_ctrl);
1254         if (err)
1255                 goto err_free_dma_tag;
1256
1257         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
1258
1259         err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs);
1260         if (err != 0)
1261                 goto err_rq_wq_destroy;
1262
1263         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
1264
1265         err = -tcp_lro_init_args(&rq->lro, priv->ifp, TCP_LRO_ENTRIES, wq_sz);
1266         if (err)
1267                 goto err_rq_wq_destroy;
1268
1269         rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1270         for (i = 0; i != wq_sz; i++) {
1271                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
1272                 int j;
1273
1274                 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
1275                 if (err != 0) {
1276                         while (i--)
1277                                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
1278                         goto err_rq_mbuf_free;
1279                 }
1280
1281                 /* set value for constant fields */
1282                 for (j = 0; j < rq->nsegs; j++)
1283                         wqe->data[j].lkey = cpu_to_be32(priv->mr.key);
1284         }
1285
1286         INIT_WORK(&rq->dim.work, mlx5e_dim_work);
1287         if (priv->params.rx_cq_moderation_mode < 2) {
1288                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
1289         } else {
1290                 void *cqc = container_of(param,
1291                     struct mlx5e_channel_param, rq)->rx_cq.cqc;
1292
1293                 switch (MLX5_GET(cqc, cqc, cq_period_mode)) {
1294                 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
1295                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
1296                         break;
1297                 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
1298                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
1299                         break;
1300                 default:
1301                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
1302                         break;
1303                 }
1304         }
1305
1306         rq->ifp = priv->ifp;
1307         rq->channel = c;
1308         rq->ix = c->ix;
1309
1310         snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
1311         mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1312             buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
1313             rq->stats.arg);
1314         return (0);
1315
1316 err_rq_mbuf_free:
1317         free(rq->mbuf, M_MLX5EN);
1318         tcp_lro_free(&rq->lro);
1319 err_rq_wq_destroy:
1320         mlx5_wq_destroy(&rq->wq_ctrl);
1321 err_free_dma_tag:
1322         bus_dma_tag_destroy(rq->dma_tag);
1323 done:
1324         return (err);
1325 }
1326
1327 static void
1328 mlx5e_destroy_rq(struct mlx5e_rq *rq)
1329 {
1330         int wq_sz;
1331         int i;
1332
1333         /* destroy all sysctl nodes */
1334         sysctl_ctx_free(&rq->stats.ctx);
1335
1336         /* free leftover LRO packets, if any */
1337         tcp_lro_free(&rq->lro);
1338
1339         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
1340         for (i = 0; i != wq_sz; i++) {
1341                 if (rq->mbuf[i].mbuf != NULL) {
1342                         bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map);
1343                         m_freem(rq->mbuf[i].mbuf);
1344                 }
1345                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
1346         }
1347         free(rq->mbuf, M_MLX5EN);
1348         mlx5_wq_destroy(&rq->wq_ctrl);
1349         bus_dma_tag_destroy(rq->dma_tag);
1350 }
1351
1352 static int
1353 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
1354 {
1355         struct mlx5e_channel *c = rq->channel;
1356         struct mlx5e_priv *priv = c->priv;
1357         struct mlx5_core_dev *mdev = priv->mdev;
1358
1359         void *in;
1360         void *rqc;
1361         void *wq;
1362         int inlen;
1363         int err;
1364
1365         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
1366             sizeof(u64) * rq->wq_ctrl.buf.npages;
1367         in = mlx5_vzalloc(inlen);
1368         if (in == NULL)
1369                 return (-ENOMEM);
1370
1371         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1372         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1373
1374         memcpy(rqc, param->rqc, sizeof(param->rqc));
1375
1376         MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
1377         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1378         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1379         if (priv->counter_set_id >= 0)
1380                 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
1381         MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
1382             PAGE_SHIFT);
1383         MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
1384
1385         mlx5_fill_page_array(&rq->wq_ctrl.buf,
1386             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1387
1388         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
1389
1390         kvfree(in);
1391
1392         return (err);
1393 }
1394
1395 static int
1396 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
1397 {
1398         struct mlx5e_channel *c = rq->channel;
1399         struct mlx5e_priv *priv = c->priv;
1400         struct mlx5_core_dev *mdev = priv->mdev;
1401
1402         void *in;
1403         void *rqc;
1404         int inlen;
1405         int err;
1406
1407         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1408         in = mlx5_vzalloc(inlen);
1409         if (in == NULL)
1410                 return (-ENOMEM);
1411
1412         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1413
1414         MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
1415         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
1416         MLX5_SET(rqc, rqc, state, next_state);
1417
1418         err = mlx5_core_modify_rq(mdev, in, inlen);
1419
1420         kvfree(in);
1421
1422         return (err);
1423 }
1424
1425 static void
1426 mlx5e_disable_rq(struct mlx5e_rq *rq)
1427 {
1428         struct mlx5e_channel *c = rq->channel;
1429         struct mlx5e_priv *priv = c->priv;
1430         struct mlx5_core_dev *mdev = priv->mdev;
1431
1432         mlx5_core_destroy_rq(mdev, rq->rqn);
1433 }
1434
1435 static int
1436 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
1437 {
1438         struct mlx5e_channel *c = rq->channel;
1439         struct mlx5e_priv *priv = c->priv;
1440         struct mlx5_wq_ll *wq = &rq->wq;
1441         int i;
1442
1443         for (i = 0; i < 1000; i++) {
1444                 if (wq->cur_sz >= priv->params.min_rx_wqes)
1445                         return (0);
1446
1447                 msleep(4);
1448         }
1449         return (-ETIMEDOUT);
1450 }
1451
1452 static int
1453 mlx5e_open_rq(struct mlx5e_channel *c,
1454     struct mlx5e_rq_param *param,
1455     struct mlx5e_rq *rq)
1456 {
1457         int err;
1458
1459         err = mlx5e_create_rq(c, param, rq);
1460         if (err)
1461                 return (err);
1462
1463         err = mlx5e_enable_rq(rq, param);
1464         if (err)
1465                 goto err_destroy_rq;
1466
1467         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1468         if (err)
1469                 goto err_disable_rq;
1470
1471         c->rq.enabled = 1;
1472
1473         return (0);
1474
1475 err_disable_rq:
1476         mlx5e_disable_rq(rq);
1477 err_destroy_rq:
1478         mlx5e_destroy_rq(rq);
1479
1480         return (err);
1481 }
1482
1483 static void
1484 mlx5e_close_rq(struct mlx5e_rq *rq)
1485 {
1486         mtx_lock(&rq->mtx);
1487         rq->enabled = 0;
1488         callout_stop(&rq->watchdog);
1489         mtx_unlock(&rq->mtx);
1490
1491         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
1492 }
1493
1494 static void
1495 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
1496 {
1497
1498         mlx5e_disable_rq(rq);
1499         mlx5e_close_cq(&rq->cq);
1500         cancel_work_sync(&rq->dim.work);
1501         mlx5e_destroy_rq(rq);
1502 }
1503
1504 void
1505 mlx5e_free_sq_db(struct mlx5e_sq *sq)
1506 {
1507         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1508         int x;
1509
1510         for (x = 0; x != wq_sz; x++) {
1511                 if (unlikely(sq->mbuf[x].p_refcount != NULL)) {
1512                         atomic_add_int(sq->mbuf[x].p_refcount, -1);
1513                         sq->mbuf[x].p_refcount = NULL;
1514                 }
1515                 if (sq->mbuf[x].mbuf != NULL) {
1516                         bus_dmamap_unload(sq->dma_tag, sq->mbuf[x].dma_map);
1517                         m_freem(sq->mbuf[x].mbuf);
1518                 }
1519                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1520         }
1521         free(sq->mbuf, M_MLX5EN);
1522 }
1523
1524 int
1525 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
1526 {
1527         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1528         int err;
1529         int x;
1530
1531         sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1532
1533         /* Create DMA descriptor MAPs */
1534         for (x = 0; x != wq_sz; x++) {
1535                 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
1536                 if (err != 0) {
1537                         while (x--)
1538                                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1539                         free(sq->mbuf, M_MLX5EN);
1540                         return (err);
1541                 }
1542         }
1543         return (0);
1544 }
1545
1546 static const char *mlx5e_sq_stats_desc[] = {
1547         MLX5E_SQ_STATS(MLX5E_STATS_DESC)
1548 };
1549
1550 void
1551 mlx5e_update_sq_inline(struct mlx5e_sq *sq)
1552 {
1553         sq->max_inline = sq->priv->params.tx_max_inline;
1554         sq->min_inline_mode = sq->priv->params.tx_min_inline_mode;
1555
1556         /*
1557          * Check if trust state is DSCP or if inline mode is NONE which
1558          * indicates CX-5 or newer hardware.
1559          */
1560         if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP ||
1561             sq->min_inline_mode == MLX5_INLINE_MODE_NONE) {
1562                 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert))
1563                         sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN;
1564                 else
1565                         sq->min_insert_caps = MLX5E_INSERT_NON_VLAN;
1566         } else {
1567                 sq->min_insert_caps = 0;
1568         }
1569 }
1570
1571 static void
1572 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1573 {
1574         int i;
1575
1576         for (i = 0; i != priv->num_tc; i++) {
1577                 mtx_lock(&c->sq[i].lock);
1578                 mlx5e_update_sq_inline(&c->sq[i]);
1579                 mtx_unlock(&c->sq[i].lock);
1580         }
1581 }
1582
1583 void
1584 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv)
1585 {
1586         int i;
1587
1588         /* check if channels are closed */
1589         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
1590                 return;
1591
1592         for (i = 0; i < priv->params.num_channels; i++)
1593                 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]);
1594 }
1595
1596 static int
1597 mlx5e_create_sq(struct mlx5e_channel *c,
1598     int tc,
1599     struct mlx5e_sq_param *param,
1600     struct mlx5e_sq *sq)
1601 {
1602         struct mlx5e_priv *priv = c->priv;
1603         struct mlx5_core_dev *mdev = priv->mdev;
1604         char buffer[16];
1605         void *sqc = param->sqc;
1606         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1607         int err;
1608
1609         /* Create DMA descriptor TAG */
1610         if ((err = -bus_dma_tag_create(
1611             bus_get_dma_tag(mdev->pdev->dev.bsddev),
1612             1,                          /* any alignment */
1613             0,                          /* no boundary */
1614             BUS_SPACE_MAXADDR,          /* lowaddr */
1615             BUS_SPACE_MAXADDR,          /* highaddr */
1616             NULL, NULL,                 /* filter, filterarg */
1617             MLX5E_MAX_TX_PAYLOAD_SIZE,  /* maxsize */
1618             MLX5E_MAX_TX_MBUF_FRAGS,    /* nsegments */
1619             MLX5E_MAX_TX_MBUF_SIZE,     /* maxsegsize */
1620             0,                          /* flags */
1621             NULL, NULL,                 /* lockfunc, lockfuncarg */
1622             &sq->dma_tag)))
1623                 goto done;
1624
1625         err = mlx5_alloc_map_uar(mdev, &sq->uar);
1626         if (err)
1627                 goto err_free_dma_tag;
1628
1629         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
1630             &sq->wq_ctrl);
1631         if (err)
1632                 goto err_unmap_free_uar;
1633
1634         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1635         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1636
1637         err = mlx5e_alloc_sq_db(sq);
1638         if (err)
1639                 goto err_sq_wq_destroy;
1640
1641         sq->mkey_be = cpu_to_be32(priv->mr.key);
1642         sq->ifp = priv->ifp;
1643         sq->priv = priv;
1644         sq->tc = tc;
1645
1646         mlx5e_update_sq_inline(sq);
1647
1648         snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1649         mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1650             buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1651             sq->stats.arg);
1652
1653         return (0);
1654
1655 err_sq_wq_destroy:
1656         mlx5_wq_destroy(&sq->wq_ctrl);
1657
1658 err_unmap_free_uar:
1659         mlx5_unmap_free_uar(mdev, &sq->uar);
1660
1661 err_free_dma_tag:
1662         bus_dma_tag_destroy(sq->dma_tag);
1663 done:
1664         return (err);
1665 }
1666
1667 static void
1668 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1669 {
1670         /* destroy all sysctl nodes */
1671         sysctl_ctx_free(&sq->stats.ctx);
1672
1673         mlx5e_free_sq_db(sq);
1674         mlx5_wq_destroy(&sq->wq_ctrl);
1675         mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1676         bus_dma_tag_destroy(sq->dma_tag);
1677 }
1678
1679 int
1680 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1681     int tis_num)
1682 {
1683         void *in;
1684         void *sqc;
1685         void *wq;
1686         int inlen;
1687         int err;
1688
1689         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1690             sizeof(u64) * sq->wq_ctrl.buf.npages;
1691         in = mlx5_vzalloc(inlen);
1692         if (in == NULL)
1693                 return (-ENOMEM);
1694
1695         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1696         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1697
1698         memcpy(sqc, param->sqc, sizeof(param->sqc));
1699
1700         MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1701         MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1702         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1703         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1704         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1705
1706         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1707         MLX5_SET(wq, wq, uar_page, sq->uar.index);
1708         MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1709             PAGE_SHIFT);
1710         MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1711
1712         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1713             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1714
1715         err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1716
1717         kvfree(in);
1718
1719         return (err);
1720 }
1721
1722 int
1723 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1724 {
1725         void *in;
1726         void *sqc;
1727         int inlen;
1728         int err;
1729
1730         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1731         in = mlx5_vzalloc(inlen);
1732         if (in == NULL)
1733                 return (-ENOMEM);
1734
1735         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1736
1737         MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1738         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1739         MLX5_SET(sqc, sqc, state, next_state);
1740
1741         err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1742
1743         kvfree(in);
1744
1745         return (err);
1746 }
1747
1748 void
1749 mlx5e_disable_sq(struct mlx5e_sq *sq)
1750 {
1751
1752         mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1753 }
1754
1755 static int
1756 mlx5e_open_sq(struct mlx5e_channel *c,
1757     int tc,
1758     struct mlx5e_sq_param *param,
1759     struct mlx5e_sq *sq)
1760 {
1761         int err;
1762
1763         sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1764
1765         /* ensure the TX completion event factor is not zero */
1766         if (sq->cev_factor == 0)
1767                 sq->cev_factor = 1;
1768
1769         err = mlx5e_create_sq(c, tc, param, sq);
1770         if (err)
1771                 return (err);
1772
1773         err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1774         if (err)
1775                 goto err_destroy_sq;
1776
1777         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1778         if (err)
1779                 goto err_disable_sq;
1780
1781         WRITE_ONCE(sq->running, 1);
1782
1783         return (0);
1784
1785 err_disable_sq:
1786         mlx5e_disable_sq(sq);
1787 err_destroy_sq:
1788         mlx5e_destroy_sq(sq);
1789
1790         return (err);
1791 }
1792
1793 static void
1794 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1795 {
1796         /* fill up remainder with NOPs */
1797         while (sq->cev_counter != 0) {
1798                 while (!mlx5e_sq_has_room_for(sq, 1)) {
1799                         if (can_sleep != 0) {
1800                                 mtx_unlock(&sq->lock);
1801                                 msleep(4);
1802                                 mtx_lock(&sq->lock);
1803                         } else {
1804                                 goto done;
1805                         }
1806                 }
1807                 /* send a single NOP */
1808                 mlx5e_send_nop(sq, 1);
1809                 atomic_thread_fence_rel();
1810         }
1811 done:
1812         /* Check if we need to write the doorbell */
1813         if (likely(sq->doorbell.d64 != 0)) {
1814                 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1815                 sq->doorbell.d64 = 0;
1816         }
1817 }
1818
1819 void
1820 mlx5e_sq_cev_timeout(void *arg)
1821 {
1822         struct mlx5e_sq *sq = arg;
1823
1824         mtx_assert(&sq->lock, MA_OWNED);
1825
1826         /* check next state */
1827         switch (sq->cev_next_state) {
1828         case MLX5E_CEV_STATE_SEND_NOPS:
1829                 /* fill TX ring with NOPs, if any */
1830                 mlx5e_sq_send_nops_locked(sq, 0);
1831
1832                 /* check if completed */
1833                 if (sq->cev_counter == 0) {
1834                         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1835                         return;
1836                 }
1837                 break;
1838         default:
1839                 /* send NOPs on next timeout */
1840                 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1841                 break;
1842         }
1843
1844         /* restart timer */
1845         callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1846 }
1847
1848 void
1849 mlx5e_drain_sq(struct mlx5e_sq *sq)
1850 {
1851         int error;
1852         struct mlx5_core_dev *mdev= sq->priv->mdev;
1853
1854         /*
1855          * Check if already stopped.
1856          *
1857          * NOTE: Serialization of this function is managed by the
1858          * caller ensuring the priv's state lock is locked or in case
1859          * of rate limit support, a single thread manages drain and
1860          * resume of SQs. The "running" variable can therefore safely
1861          * be read without any locks.
1862          */
1863         if (READ_ONCE(sq->running) == 0)
1864                 return;
1865
1866         /* don't put more packets into the SQ */
1867         WRITE_ONCE(sq->running, 0);
1868
1869         /* serialize access to DMA rings */
1870         mtx_lock(&sq->lock);
1871
1872         /* teardown event factor timer, if any */
1873         sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1874         callout_stop(&sq->cev_callout);
1875
1876         /* send dummy NOPs in order to flush the transmit ring */
1877         mlx5e_sq_send_nops_locked(sq, 1);
1878         mtx_unlock(&sq->lock);
1879
1880         /* wait till SQ is empty or link is down */
1881         mtx_lock(&sq->lock);
1882         while (sq->cc != sq->pc &&
1883             (sq->priv->media_status_last & IFM_ACTIVE) != 0 &&
1884             mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1885                 mtx_unlock(&sq->lock);
1886                 msleep(1);
1887                 sq->cq.mcq.comp(&sq->cq.mcq);
1888                 mtx_lock(&sq->lock);
1889         }
1890         mtx_unlock(&sq->lock);
1891
1892         /* error out remaining requests */
1893         error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1894         if (error != 0) {
1895                 mlx5_en_err(sq->ifp,
1896                     "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error);
1897         }
1898
1899         /* wait till SQ is empty */
1900         mtx_lock(&sq->lock);
1901         while (sq->cc != sq->pc &&
1902                mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1903                 mtx_unlock(&sq->lock);
1904                 msleep(1);
1905                 sq->cq.mcq.comp(&sq->cq.mcq);
1906                 mtx_lock(&sq->lock);
1907         }
1908         mtx_unlock(&sq->lock);
1909 }
1910
1911 static void
1912 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1913 {
1914
1915         mlx5e_drain_sq(sq);
1916         mlx5e_disable_sq(sq);
1917         mlx5e_destroy_sq(sq);
1918 }
1919
1920 static int
1921 mlx5e_create_cq(struct mlx5e_priv *priv,
1922     struct mlx5e_cq_param *param,
1923     struct mlx5e_cq *cq,
1924     mlx5e_cq_comp_t *comp,
1925     int eq_ix)
1926 {
1927         struct mlx5_core_dev *mdev = priv->mdev;
1928         struct mlx5_core_cq *mcq = &cq->mcq;
1929         int eqn_not_used;
1930         int irqn;
1931         int err;
1932         u32 i;
1933
1934         param->wq.buf_numa_node = 0;
1935         param->wq.db_numa_node = 0;
1936
1937         err = mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1938         if (err)
1939                 return (err);
1940
1941         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1942             &cq->wq_ctrl);
1943         if (err)
1944                 return (err);
1945
1946         mcq->cqe_sz = 64;
1947         mcq->set_ci_db = cq->wq_ctrl.db.db;
1948         mcq->arm_db = cq->wq_ctrl.db.db + 1;
1949         *mcq->set_ci_db = 0;
1950         *mcq->arm_db = 0;
1951         mcq->vector = eq_ix;
1952         mcq->comp = comp;
1953         mcq->event = mlx5e_cq_error_event;
1954         mcq->irqn = irqn;
1955         mcq->uar = &priv->cq_uar;
1956
1957         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1958                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1959
1960                 cqe->op_own = 0xf1;
1961         }
1962
1963         cq->priv = priv;
1964
1965         return (0);
1966 }
1967
1968 static void
1969 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1970 {
1971         mlx5_wq_destroy(&cq->wq_ctrl);
1972 }
1973
1974 static int
1975 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1976 {
1977         struct mlx5_core_cq *mcq = &cq->mcq;
1978         void *in;
1979         void *cqc;
1980         int inlen;
1981         int irqn_not_used;
1982         int eqn;
1983         int err;
1984
1985         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1986             sizeof(u64) * cq->wq_ctrl.buf.npages;
1987         in = mlx5_vzalloc(inlen);
1988         if (in == NULL)
1989                 return (-ENOMEM);
1990
1991         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1992
1993         memcpy(cqc, param->cqc, sizeof(param->cqc));
1994
1995         mlx5_fill_page_array(&cq->wq_ctrl.buf,
1996             (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1997
1998         mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
1999
2000         MLX5_SET(cqc, cqc, c_eqn, eqn);
2001         MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
2002         MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
2003             PAGE_SHIFT);
2004         MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
2005
2006         err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
2007
2008         kvfree(in);
2009
2010         if (err)
2011                 return (err);
2012
2013         mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock));
2014
2015         return (0);
2016 }
2017
2018 static void
2019 mlx5e_disable_cq(struct mlx5e_cq *cq)
2020 {
2021
2022         mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
2023 }
2024
2025 int
2026 mlx5e_open_cq(struct mlx5e_priv *priv,
2027     struct mlx5e_cq_param *param,
2028     struct mlx5e_cq *cq,
2029     mlx5e_cq_comp_t *comp,
2030     int eq_ix)
2031 {
2032         int err;
2033
2034         err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
2035         if (err)
2036                 return (err);
2037
2038         err = mlx5e_enable_cq(cq, param, eq_ix);
2039         if (err)
2040                 goto err_destroy_cq;
2041
2042         return (0);
2043
2044 err_destroy_cq:
2045         mlx5e_destroy_cq(cq);
2046
2047         return (err);
2048 }
2049
2050 void
2051 mlx5e_close_cq(struct mlx5e_cq *cq)
2052 {
2053         mlx5e_disable_cq(cq);
2054         mlx5e_destroy_cq(cq);
2055 }
2056
2057 static int
2058 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
2059     struct mlx5e_channel_param *cparam)
2060 {
2061         int err;
2062         int tc;
2063
2064         for (tc = 0; tc < c->priv->num_tc; tc++) {
2065                 /* open completion queue */
2066                 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
2067                     &mlx5e_tx_cq_comp, c->ix);
2068                 if (err)
2069                         goto err_close_tx_cqs;
2070         }
2071         return (0);
2072
2073 err_close_tx_cqs:
2074         for (tc--; tc >= 0; tc--)
2075                 mlx5e_close_cq(&c->sq[tc].cq);
2076
2077         return (err);
2078 }
2079
2080 static void
2081 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
2082 {
2083         int tc;
2084
2085         for (tc = 0; tc < c->priv->num_tc; tc++)
2086                 mlx5e_close_cq(&c->sq[tc].cq);
2087 }
2088
2089 static int
2090 mlx5e_open_sqs(struct mlx5e_channel *c,
2091     struct mlx5e_channel_param *cparam)
2092 {
2093         int err;
2094         int tc;
2095
2096         for (tc = 0; tc < c->priv->num_tc; tc++) {
2097                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
2098                 if (err)
2099                         goto err_close_sqs;
2100         }
2101
2102         return (0);
2103
2104 err_close_sqs:
2105         for (tc--; tc >= 0; tc--)
2106                 mlx5e_close_sq_wait(&c->sq[tc]);
2107
2108         return (err);
2109 }
2110
2111 static void
2112 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
2113 {
2114         int tc;
2115
2116         for (tc = 0; tc < c->priv->num_tc; tc++)
2117                 mlx5e_close_sq_wait(&c->sq[tc]);
2118 }
2119
2120 static void
2121 mlx5e_chan_static_init(struct mlx5e_priv *priv, struct mlx5e_channel *c, int ix)
2122 {
2123         int tc;
2124
2125         /* setup priv and channel number */
2126         c->priv = priv;
2127         c->ix = ix;
2128
2129         /* setup send tag */
2130         c->tag.type = IF_SND_TAG_TYPE_UNLIMITED;
2131         m_snd_tag_init(&c->tag.m_snd_tag, c->priv->ifp);
2132
2133         init_completion(&c->completion);
2134
2135         mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
2136
2137         callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
2138
2139         for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) {
2140                 struct mlx5e_sq *sq = c->sq + tc;
2141
2142                 mtx_init(&sq->lock, "mlx5tx",
2143                     MTX_NETWORK_LOCK " TX", MTX_DEF);
2144                 mtx_init(&sq->comp_lock, "mlx5comp",
2145                     MTX_NETWORK_LOCK " TX", MTX_DEF);
2146
2147                 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
2148         }
2149 }
2150
2151 static void
2152 mlx5e_chan_wait_for_completion(struct mlx5e_channel *c)
2153 {
2154
2155         m_snd_tag_rele(&c->tag.m_snd_tag);
2156         wait_for_completion(&c->completion);
2157 }
2158
2159 static void
2160 mlx5e_priv_wait_for_completion(struct mlx5e_priv *priv, const uint32_t channels)
2161 {
2162         uint32_t x;
2163
2164         for (x = 0; x != channels; x++)
2165                 mlx5e_chan_wait_for_completion(&priv->channel[x]);
2166 }
2167
2168 static void
2169 mlx5e_chan_static_destroy(struct mlx5e_channel *c)
2170 {
2171         int tc;
2172
2173         callout_drain(&c->rq.watchdog);
2174
2175         mtx_destroy(&c->rq.mtx);
2176
2177         for (tc = 0; tc != MLX5E_MAX_TX_NUM_TC; tc++) {
2178                 callout_drain(&c->sq[tc].cev_callout);
2179                 mtx_destroy(&c->sq[tc].lock);
2180                 mtx_destroy(&c->sq[tc].comp_lock);
2181         }
2182 }
2183
2184 static int
2185 mlx5e_open_channel(struct mlx5e_priv *priv,
2186     struct mlx5e_channel_param *cparam,
2187     struct mlx5e_channel *c)
2188 {
2189         struct epoch_tracker et;
2190         int i, err;
2191
2192         /* zero non-persistant data */
2193         MLX5E_ZERO(&c->rq, mlx5e_rq_zero_start);
2194         for (i = 0; i != priv->num_tc; i++)
2195                 MLX5E_ZERO(&c->sq[i], mlx5e_sq_zero_start);
2196
2197         /* open transmit completion queue */
2198         err = mlx5e_open_tx_cqs(c, cparam);
2199         if (err)
2200                 goto err_free;
2201
2202         /* open receive completion queue */
2203         err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
2204             &mlx5e_rx_cq_comp, c->ix);
2205         if (err)
2206                 goto err_close_tx_cqs;
2207
2208         err = mlx5e_open_sqs(c, cparam);
2209         if (err)
2210                 goto err_close_rx_cq;
2211
2212         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
2213         if (err)
2214                 goto err_close_sqs;
2215
2216         /* poll receive queue initially */
2217         NET_EPOCH_ENTER(et);
2218         c->rq.cq.mcq.comp(&c->rq.cq.mcq);
2219         NET_EPOCH_EXIT(et);
2220
2221         return (0);
2222
2223 err_close_sqs:
2224         mlx5e_close_sqs_wait(c);
2225
2226 err_close_rx_cq:
2227         mlx5e_close_cq(&c->rq.cq);
2228
2229 err_close_tx_cqs:
2230         mlx5e_close_tx_cqs(c);
2231
2232 err_free:
2233         return (err);
2234 }
2235
2236 static void
2237 mlx5e_close_channel(struct mlx5e_channel *c)
2238 {
2239         mlx5e_close_rq(&c->rq);
2240 }
2241
2242 static void
2243 mlx5e_close_channel_wait(struct mlx5e_channel *c)
2244 {
2245         mlx5e_close_rq_wait(&c->rq);
2246         mlx5e_close_sqs_wait(c);
2247         mlx5e_close_tx_cqs(c);
2248 }
2249
2250 static int
2251 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs)
2252 {
2253         u32 r, n;
2254
2255         r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz :
2256             MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
2257         if (r > MJUM16BYTES)
2258                 return (-ENOMEM);
2259
2260         if (r > MJUM9BYTES)
2261                 r = MJUM16BYTES;
2262         else if (r > MJUMPAGESIZE)
2263                 r = MJUM9BYTES;
2264         else if (r > MCLBYTES)
2265                 r = MJUMPAGESIZE;
2266         else
2267                 r = MCLBYTES;
2268
2269         /*
2270          * n + 1 must be a power of two, because stride size must be.
2271          * Stride size is 16 * (n + 1), as the first segment is
2272          * control.
2273          */
2274         for (n = howmany(r, MLX5E_MAX_RX_BYTES); !powerof2(n + 1); n++)
2275                 ;
2276
2277         if (n > MLX5E_MAX_BUSDMA_RX_SEGS)
2278                 return (-ENOMEM);
2279
2280         *wqe_sz = r;
2281         *nsegs = n;
2282         return (0);
2283 }
2284
2285 static void
2286 mlx5e_build_rq_param(struct mlx5e_priv *priv,
2287     struct mlx5e_rq_param *param)
2288 {
2289         void *rqc = param->rqc;
2290         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
2291         u32 wqe_sz, nsegs;
2292
2293         mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
2294         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
2295         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
2296         MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) +
2297             nsegs * sizeof(struct mlx5_wqe_data_seg)));
2298         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
2299         MLX5_SET(wq, wq, pd, priv->pdn);
2300
2301         param->wq.buf_numa_node = 0;
2302         param->wq.db_numa_node = 0;
2303         param->wq.linear = 1;
2304 }
2305
2306 static void
2307 mlx5e_build_sq_param(struct mlx5e_priv *priv,
2308     struct mlx5e_sq_param *param)
2309 {
2310         void *sqc = param->sqc;
2311         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2312
2313         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
2314         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
2315         MLX5_SET(wq, wq, pd, priv->pdn);
2316
2317         param->wq.buf_numa_node = 0;
2318         param->wq.db_numa_node = 0;
2319         param->wq.linear = 1;
2320 }
2321
2322 static void
2323 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
2324     struct mlx5e_cq_param *param)
2325 {
2326         void *cqc = param->cqc;
2327
2328         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
2329 }
2330
2331 static void
2332 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr)
2333 {
2334
2335         *ptr = net_dim_get_profile(mode, MLX5E_DIM_DEFAULT_PROFILE);
2336
2337         /* apply LRO restrictions */
2338         if (priv->params.hw_lro_en &&
2339             ptr->pkts > MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO) {
2340                 ptr->pkts = MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO;
2341         }
2342 }
2343
2344 static void
2345 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
2346     struct mlx5e_cq_param *param)
2347 {
2348         struct net_dim_cq_moder curr;
2349         void *cqc = param->cqc;
2350
2351         /*
2352          * We use MLX5_CQE_FORMAT_HASH because the RX hash mini CQE
2353          * format is more beneficial for FreeBSD use case.
2354          *
2355          * Adding support for MLX5_CQE_FORMAT_CSUM will require changes
2356          * in mlx5e_decompress_cqe.
2357          */
2358         if (priv->params.cqe_zipping_en) {
2359                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_HASH);
2360                 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
2361         }
2362
2363         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
2364
2365         switch (priv->params.rx_cq_moderation_mode) {
2366         case 0:
2367                 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
2368                 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
2369                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2370                 break;
2371         case 1:
2372                 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
2373                 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
2374                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2375                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2376                 else
2377                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2378                 break;
2379         case 2:
2380                 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr);
2381                 MLX5_SET(cqc, cqc, cq_period, curr.usec);
2382                 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
2383                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2384                 break;
2385         case 3:
2386                 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr);
2387                 MLX5_SET(cqc, cqc, cq_period, curr.usec);
2388                 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
2389                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2390                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2391                 else
2392                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2393                 break;
2394         default:
2395                 break;
2396         }
2397
2398         mlx5e_dim_build_cq_param(priv, param);
2399
2400         mlx5e_build_common_cq_param(priv, param);
2401 }
2402
2403 static void
2404 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2405     struct mlx5e_cq_param *param)
2406 {
2407         void *cqc = param->cqc;
2408
2409         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
2410         MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
2411         MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
2412
2413         switch (priv->params.tx_cq_moderation_mode) {
2414         case 0:
2415                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2416                 break;
2417         default:
2418                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2419                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2420                 else
2421                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2422                 break;
2423         }
2424
2425         mlx5e_build_common_cq_param(priv, param);
2426 }
2427
2428 static void
2429 mlx5e_build_channel_param(struct mlx5e_priv *priv,
2430     struct mlx5e_channel_param *cparam)
2431 {
2432         memset(cparam, 0, sizeof(*cparam));
2433
2434         mlx5e_build_rq_param(priv, &cparam->rq);
2435         mlx5e_build_sq_param(priv, &cparam->sq);
2436         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
2437         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
2438 }
2439
2440 static int
2441 mlx5e_open_channels(struct mlx5e_priv *priv)
2442 {
2443         struct mlx5e_channel_param *cparam;
2444         int err;
2445         int i;
2446         int j;
2447
2448         cparam = malloc(sizeof(*cparam), M_MLX5EN, M_WAITOK);
2449
2450         mlx5e_build_channel_param(priv, cparam);
2451         for (i = 0; i < priv->params.num_channels; i++) {
2452                 err = mlx5e_open_channel(priv, cparam, &priv->channel[i]);
2453                 if (err)
2454                         goto err_close_channels;
2455         }
2456
2457         for (j = 0; j < priv->params.num_channels; j++) {
2458                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j].rq);
2459                 if (err)
2460                         goto err_close_channels;
2461         }
2462         free(cparam, M_MLX5EN);
2463         return (0);
2464
2465 err_close_channels:
2466         while (i--) {
2467                 mlx5e_close_channel(&priv->channel[i]);
2468                 mlx5e_close_channel_wait(&priv->channel[i]);
2469         }
2470         free(cparam, M_MLX5EN);
2471         return (err);
2472 }
2473
2474 static void
2475 mlx5e_close_channels(struct mlx5e_priv *priv)
2476 {
2477         int i;
2478
2479         for (i = 0; i < priv->params.num_channels; i++)
2480                 mlx5e_close_channel(&priv->channel[i]);
2481         for (i = 0; i < priv->params.num_channels; i++)
2482                 mlx5e_close_channel_wait(&priv->channel[i]);
2483 }
2484
2485 static int
2486 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
2487 {
2488
2489         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2490                 uint8_t cq_mode;
2491
2492                 switch (priv->params.tx_cq_moderation_mode) {
2493                 case 0:
2494                 case 2:
2495                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2496                         break;
2497                 default:
2498                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2499                         break;
2500                 }
2501
2502                 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq,
2503                     priv->params.tx_cq_moderation_usec,
2504                     priv->params.tx_cq_moderation_pkts,
2505                     cq_mode));
2506         }
2507
2508         return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
2509             priv->params.tx_cq_moderation_usec,
2510             priv->params.tx_cq_moderation_pkts));
2511 }
2512
2513 static int
2514 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
2515 {
2516
2517         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2518                 uint8_t cq_mode;
2519                 uint8_t dim_mode;
2520                 int retval;
2521
2522                 switch (priv->params.rx_cq_moderation_mode) {
2523                 case 0:
2524                 case 2:
2525                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2526                         dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2527                         break;
2528                 default:
2529                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2530                         dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
2531                         break;
2532                 }
2533
2534                 /* tear down dynamic interrupt moderation */
2535                 mtx_lock(&rq->mtx);
2536                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
2537                 mtx_unlock(&rq->mtx);
2538
2539                 /* wait for dynamic interrupt moderation work task, if any */
2540                 cancel_work_sync(&rq->dim.work);
2541
2542                 if (priv->params.rx_cq_moderation_mode >= 2) {
2543                         struct net_dim_cq_moder curr;
2544
2545                         mlx5e_get_default_profile(priv, dim_mode, &curr);
2546
2547                         retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2548                             curr.usec, curr.pkts, cq_mode);
2549
2550                         /* set dynamic interrupt moderation mode and zero defaults */
2551                         mtx_lock(&rq->mtx);
2552                         rq->dim.mode = dim_mode;
2553                         rq->dim.state = 0;
2554                         rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE;
2555                         mtx_unlock(&rq->mtx);
2556                 } else {
2557                         retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2558                             priv->params.rx_cq_moderation_usec,
2559                             priv->params.rx_cq_moderation_pkts,
2560                             cq_mode);
2561                 }
2562                 return (retval);
2563         }
2564
2565         return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
2566             priv->params.rx_cq_moderation_usec,
2567             priv->params.rx_cq_moderation_pkts));
2568 }
2569
2570 static int
2571 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
2572 {
2573         int err;
2574         int i;
2575
2576         err = mlx5e_refresh_rq_params(priv, &c->rq);
2577         if (err)
2578                 goto done;
2579
2580         for (i = 0; i != priv->num_tc; i++) {
2581                 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
2582                 if (err)
2583                         goto done;
2584         }
2585 done:
2586         return (err);
2587 }
2588
2589 int
2590 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
2591 {
2592         int i;
2593
2594         /* check if channels are closed */
2595         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2596                 return (EINVAL);
2597
2598         for (i = 0; i < priv->params.num_channels; i++) {
2599                 int err;
2600
2601                 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]);
2602                 if (err)
2603                         return (err);
2604         }
2605         return (0);
2606 }
2607
2608 static int
2609 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
2610 {
2611         struct mlx5_core_dev *mdev = priv->mdev;
2612         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
2613         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2614
2615         memset(in, 0, sizeof(in));
2616
2617         MLX5_SET(tisc, tisc, prio, tc);
2618         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
2619
2620         return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
2621 }
2622
2623 static void
2624 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
2625 {
2626         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2627 }
2628
2629 static int
2630 mlx5e_open_tises(struct mlx5e_priv *priv)
2631 {
2632         int num_tc = priv->num_tc;
2633         int err;
2634         int tc;
2635
2636         for (tc = 0; tc < num_tc; tc++) {
2637                 err = mlx5e_open_tis(priv, tc);
2638                 if (err)
2639                         goto err_close_tises;
2640         }
2641
2642         return (0);
2643
2644 err_close_tises:
2645         for (tc--; tc >= 0; tc--)
2646                 mlx5e_close_tis(priv, tc);
2647
2648         return (err);
2649 }
2650
2651 static void
2652 mlx5e_close_tises(struct mlx5e_priv *priv)
2653 {
2654         int num_tc = priv->num_tc;
2655         int tc;
2656
2657         for (tc = 0; tc < num_tc; tc++)
2658                 mlx5e_close_tis(priv, tc);
2659 }
2660
2661 static int
2662 mlx5e_open_rqt(struct mlx5e_priv *priv)
2663 {
2664         struct mlx5_core_dev *mdev = priv->mdev;
2665         u32 *in;
2666         u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
2667         void *rqtc;
2668         int inlen;
2669         int err;
2670         int sz;
2671         int i;
2672
2673         sz = 1 << priv->params.rx_hash_log_tbl_sz;
2674
2675         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2676         in = mlx5_vzalloc(inlen);
2677         if (in == NULL)
2678                 return (-ENOMEM);
2679         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2680
2681         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2682         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2683
2684         for (i = 0; i < sz; i++) {
2685                 int ix = i;
2686 #ifdef RSS
2687                 ix = rss_get_indirection_to_bucket(ix);
2688 #endif
2689                 /* ensure we don't overflow */
2690                 ix %= priv->params.num_channels;
2691
2692                 /* apply receive side scaling stride, if any */
2693                 ix -= ix % (int)priv->params.channels_rsss;
2694
2695                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn);
2696         }
2697
2698         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
2699
2700         err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
2701         if (!err)
2702                 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
2703
2704         kvfree(in);
2705
2706         return (err);
2707 }
2708
2709 static void
2710 mlx5e_close_rqt(struct mlx5e_priv *priv)
2711 {
2712         u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0};
2713         u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0};
2714
2715         MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
2716         MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
2717
2718         mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out));
2719 }
2720
2721 static void
2722 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
2723 {
2724         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2725         __be32 *hkey;
2726
2727         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2728
2729 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2730
2731 #define MLX5_HASH_IP     (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2732                           MLX5_HASH_FIELD_SEL_DST_IP)
2733
2734 #define MLX5_HASH_ALL    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2735                           MLX5_HASH_FIELD_SEL_DST_IP   |\
2736                           MLX5_HASH_FIELD_SEL_L4_SPORT |\
2737                           MLX5_HASH_FIELD_SEL_L4_DPORT)
2738
2739 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2740                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2741                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2742
2743         if (priv->params.hw_lro_en) {
2744                 MLX5_SET(tirc, tirc, lro_enable_mask,
2745                     MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2746                     MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2747                 MLX5_SET(tirc, tirc, lro_max_msg_sz,
2748                     (priv->params.lro_wqe_sz -
2749                     ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2750                 /* TODO: add the option to choose timer value dynamically */
2751                 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
2752                     MLX5_CAP_ETH(priv->mdev,
2753                     lro_timer_supported_periods[2]));
2754         }
2755
2756         /* setup parameters for hashing TIR type, if any */
2757         switch (tt) {
2758         case MLX5E_TT_ANY:
2759                 MLX5_SET(tirc, tirc, disp_type,
2760                     MLX5_TIRC_DISP_TYPE_DIRECT);
2761                 MLX5_SET(tirc, tirc, inline_rqn,
2762                     priv->channel[0].rq.rqn);
2763                 break;
2764         default:
2765                 MLX5_SET(tirc, tirc, disp_type,
2766                     MLX5_TIRC_DISP_TYPE_INDIRECT);
2767                 MLX5_SET(tirc, tirc, indirect_table,
2768                     priv->rqtn);
2769                 MLX5_SET(tirc, tirc, rx_hash_fn,
2770                     MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
2771                 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
2772 #ifdef RSS
2773                 /*
2774                  * The FreeBSD RSS implementation does currently not
2775                  * support symmetric Toeplitz hashes:
2776                  */
2777                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
2778                 rss_getkey((uint8_t *)hkey);
2779 #else
2780                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2781                 hkey[0] = cpu_to_be32(0xD181C62C);
2782                 hkey[1] = cpu_to_be32(0xF7F4DB5B);
2783                 hkey[2] = cpu_to_be32(0x1983A2FC);
2784                 hkey[3] = cpu_to_be32(0x943E1ADB);
2785                 hkey[4] = cpu_to_be32(0xD9389E6B);
2786                 hkey[5] = cpu_to_be32(0xD1039C2C);
2787                 hkey[6] = cpu_to_be32(0xA74499AD);
2788                 hkey[7] = cpu_to_be32(0x593D56D9);
2789                 hkey[8] = cpu_to_be32(0xF3253C06);
2790                 hkey[9] = cpu_to_be32(0x2ADC1FFC);
2791 #endif
2792                 break;
2793         }
2794
2795         switch (tt) {
2796         case MLX5E_TT_IPV4_TCP:
2797                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2798                     MLX5_L3_PROT_TYPE_IPV4);
2799                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2800                     MLX5_L4_PROT_TYPE_TCP);
2801 #ifdef RSS
2802                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2803                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2804                             MLX5_HASH_IP);
2805                 } else
2806 #endif
2807                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2808                     MLX5_HASH_ALL);
2809                 break;
2810
2811         case MLX5E_TT_IPV6_TCP:
2812                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2813                     MLX5_L3_PROT_TYPE_IPV6);
2814                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2815                     MLX5_L4_PROT_TYPE_TCP);
2816 #ifdef RSS
2817                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2818                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2819                             MLX5_HASH_IP);
2820                 } else
2821 #endif
2822                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2823                     MLX5_HASH_ALL);
2824                 break;
2825
2826         case MLX5E_TT_IPV4_UDP:
2827                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2828                     MLX5_L3_PROT_TYPE_IPV4);
2829                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2830                     MLX5_L4_PROT_TYPE_UDP);
2831 #ifdef RSS
2832                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2833                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2834                             MLX5_HASH_IP);
2835                 } else
2836 #endif
2837                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2838                     MLX5_HASH_ALL);
2839                 break;
2840
2841         case MLX5E_TT_IPV6_UDP:
2842                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2843                     MLX5_L3_PROT_TYPE_IPV6);
2844                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2845                     MLX5_L4_PROT_TYPE_UDP);
2846 #ifdef RSS
2847                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2848                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2849                             MLX5_HASH_IP);
2850                 } else
2851 #endif
2852                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2853                     MLX5_HASH_ALL);
2854                 break;
2855
2856         case MLX5E_TT_IPV4_IPSEC_AH:
2857                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2858                     MLX5_L3_PROT_TYPE_IPV4);
2859                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2860                     MLX5_HASH_IP_IPSEC_SPI);
2861                 break;
2862
2863         case MLX5E_TT_IPV6_IPSEC_AH:
2864                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2865                     MLX5_L3_PROT_TYPE_IPV6);
2866                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2867                     MLX5_HASH_IP_IPSEC_SPI);
2868                 break;
2869
2870         case MLX5E_TT_IPV4_IPSEC_ESP:
2871                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2872                     MLX5_L3_PROT_TYPE_IPV4);
2873                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2874                     MLX5_HASH_IP_IPSEC_SPI);
2875                 break;
2876
2877         case MLX5E_TT_IPV6_IPSEC_ESP:
2878                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2879                     MLX5_L3_PROT_TYPE_IPV6);
2880                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2881                     MLX5_HASH_IP_IPSEC_SPI);
2882                 break;
2883
2884         case MLX5E_TT_IPV4:
2885                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2886                     MLX5_L3_PROT_TYPE_IPV4);
2887                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2888                     MLX5_HASH_IP);
2889                 break;
2890
2891         case MLX5E_TT_IPV6:
2892                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2893                     MLX5_L3_PROT_TYPE_IPV6);
2894                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2895                     MLX5_HASH_IP);
2896                 break;
2897
2898         default:
2899                 break;
2900         }
2901 }
2902
2903 static int
2904 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2905 {
2906         struct mlx5_core_dev *mdev = priv->mdev;
2907         u32 *in;
2908         void *tirc;
2909         int inlen;
2910         int err;
2911
2912         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2913         in = mlx5_vzalloc(inlen);
2914         if (in == NULL)
2915                 return (-ENOMEM);
2916         tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2917
2918         mlx5e_build_tir_ctx(priv, tirc, tt);
2919
2920         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2921
2922         kvfree(in);
2923
2924         return (err);
2925 }
2926
2927 static void
2928 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2929 {
2930         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2931 }
2932
2933 static int
2934 mlx5e_open_tirs(struct mlx5e_priv *priv)
2935 {
2936         int err;
2937         int i;
2938
2939         for (i = 0; i < MLX5E_NUM_TT; i++) {
2940                 err = mlx5e_open_tir(priv, i);
2941                 if (err)
2942                         goto err_close_tirs;
2943         }
2944
2945         return (0);
2946
2947 err_close_tirs:
2948         for (i--; i >= 0; i--)
2949                 mlx5e_close_tir(priv, i);
2950
2951         return (err);
2952 }
2953
2954 static void
2955 mlx5e_close_tirs(struct mlx5e_priv *priv)
2956 {
2957         int i;
2958
2959         for (i = 0; i < MLX5E_NUM_TT; i++)
2960                 mlx5e_close_tir(priv, i);
2961 }
2962
2963 /*
2964  * SW MTU does not include headers,
2965  * HW MTU includes all headers and checksums.
2966  */
2967 static int
2968 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2969 {
2970         struct mlx5e_priv *priv = ifp->if_softc;
2971         struct mlx5_core_dev *mdev = priv->mdev;
2972         int hw_mtu;
2973         int err;
2974
2975         hw_mtu = MLX5E_SW2HW_MTU(sw_mtu);
2976
2977         err = mlx5_set_port_mtu(mdev, hw_mtu);
2978         if (err) {
2979                 mlx5_en_err(ifp, "mlx5_set_port_mtu failed setting %d, err=%d\n",
2980                     sw_mtu, err);
2981                 return (err);
2982         }
2983
2984         /* Update vport context MTU */
2985         err = mlx5_set_vport_mtu(mdev, hw_mtu);
2986         if (err) {
2987                 mlx5_en_err(ifp,
2988                     "Failed updating vport context with MTU size, err=%d\n",
2989                     err);
2990         }
2991
2992         ifp->if_mtu = sw_mtu;
2993
2994         err = mlx5_query_vport_mtu(mdev, &hw_mtu);
2995         if (err || !hw_mtu) {
2996                 /* fallback to port oper mtu */
2997                 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2998         }
2999         if (err) {
3000                 mlx5_en_err(ifp,
3001                     "Query port MTU, after setting new MTU value, failed\n");
3002                 return (err);
3003         } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
3004                 err = -E2BIG,
3005                 mlx5_en_err(ifp,
3006                     "Port MTU %d is smaller than ifp mtu %d\n",
3007                     hw_mtu, sw_mtu);
3008         } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
3009                 err = -EINVAL;
3010                 mlx5_en_err(ifp,
3011                     "Port MTU %d is bigger than ifp mtu %d\n",
3012                     hw_mtu, sw_mtu);
3013         }
3014         priv->params_ethtool.hw_mtu = hw_mtu;
3015
3016         /* compute MSB */
3017         while (hw_mtu & (hw_mtu - 1))
3018                 hw_mtu &= (hw_mtu - 1);
3019         priv->params_ethtool.hw_mtu_msb = hw_mtu;
3020
3021         return (err);
3022 }
3023
3024 int
3025 mlx5e_open_locked(struct ifnet *ifp)
3026 {
3027         struct mlx5e_priv *priv = ifp->if_softc;
3028         int err;
3029         u16 set_id;
3030
3031         /* check if already opened */
3032         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
3033                 return (0);
3034
3035 #ifdef RSS
3036         if (rss_getnumbuckets() > priv->params.num_channels) {
3037                 mlx5_en_info(ifp,
3038                     "NOTE: There are more RSS buckets(%u) than channels(%u) available\n",
3039                     rss_getnumbuckets(), priv->params.num_channels);
3040         }
3041 #endif
3042         err = mlx5e_open_tises(priv);
3043         if (err) {
3044                 mlx5_en_err(ifp, "mlx5e_open_tises failed, %d\n", err);
3045                 return (err);
3046         }
3047         err = mlx5_vport_alloc_q_counter(priv->mdev,
3048             MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
3049         if (err) {
3050                 mlx5_en_err(priv->ifp,
3051                     "mlx5_vport_alloc_q_counter failed: %d\n", err);
3052                 goto err_close_tises;
3053         }
3054         /* store counter set ID */
3055         priv->counter_set_id = set_id;
3056
3057         err = mlx5e_open_channels(priv);
3058         if (err) {
3059                 mlx5_en_err(ifp,
3060                     "mlx5e_open_channels failed, %d\n", err);
3061                 goto err_dalloc_q_counter;
3062         }
3063         err = mlx5e_open_rqt(priv);
3064         if (err) {
3065                 mlx5_en_err(ifp, "mlx5e_open_rqt failed, %d\n", err);
3066                 goto err_close_channels;
3067         }
3068         err = mlx5e_open_tirs(priv);
3069         if (err) {
3070                 mlx5_en_err(ifp, "mlx5e_open_tir failed, %d\n", err);
3071                 goto err_close_rqls;
3072         }
3073         err = mlx5e_open_flow_table(priv);
3074         if (err) {
3075                 mlx5_en_err(ifp,
3076                     "mlx5e_open_flow_table failed, %d\n", err);
3077                 goto err_close_tirs;
3078         }
3079         err = mlx5e_add_all_vlan_rules(priv);
3080         if (err) {
3081                 mlx5_en_err(ifp,
3082                     "mlx5e_add_all_vlan_rules failed, %d\n", err);
3083                 goto err_close_flow_table;
3084         }
3085         set_bit(MLX5E_STATE_OPENED, &priv->state);
3086
3087         mlx5e_update_carrier(priv);
3088         mlx5e_set_rx_mode_core(priv);
3089
3090         return (0);
3091
3092 err_close_flow_table:
3093         mlx5e_close_flow_table(priv);
3094
3095 err_close_tirs:
3096         mlx5e_close_tirs(priv);
3097
3098 err_close_rqls:
3099         mlx5e_close_rqt(priv);
3100
3101 err_close_channels:
3102         mlx5e_close_channels(priv);
3103
3104 err_dalloc_q_counter:
3105         mlx5_vport_dealloc_q_counter(priv->mdev,
3106             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
3107
3108 err_close_tises:
3109         mlx5e_close_tises(priv);
3110
3111         return (err);
3112 }
3113
3114 static void
3115 mlx5e_open(void *arg)
3116 {
3117         struct mlx5e_priv *priv = arg;
3118
3119         PRIV_LOCK(priv);
3120         if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
3121                 mlx5_en_err(priv->ifp,
3122                     "Setting port status to up failed\n");
3123
3124         mlx5e_open_locked(priv->ifp);
3125         priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
3126         PRIV_UNLOCK(priv);
3127 }
3128
3129 int
3130 mlx5e_close_locked(struct ifnet *ifp)
3131 {
3132         struct mlx5e_priv *priv = ifp->if_softc;
3133
3134         /* check if already closed */
3135         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3136                 return (0);
3137
3138         clear_bit(MLX5E_STATE_OPENED, &priv->state);
3139
3140         mlx5e_set_rx_mode_core(priv);
3141         mlx5e_del_all_vlan_rules(priv);
3142         if_link_state_change(priv->ifp, LINK_STATE_DOWN);
3143         mlx5e_close_flow_table(priv);
3144         mlx5e_close_tirs(priv);
3145         mlx5e_close_rqt(priv);
3146         mlx5e_close_channels(priv);
3147         mlx5_vport_dealloc_q_counter(priv->mdev,
3148             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
3149         mlx5e_close_tises(priv);
3150
3151         return (0);
3152 }
3153
3154 #if (__FreeBSD_version >= 1100000)
3155 static uint64_t
3156 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
3157 {
3158         struct mlx5e_priv *priv = ifp->if_softc;
3159         u64 retval;
3160
3161         /* PRIV_LOCK(priv); XXX not allowed */
3162         switch (cnt) {
3163         case IFCOUNTER_IPACKETS:
3164                 retval = priv->stats.vport.rx_packets;
3165                 break;
3166         case IFCOUNTER_IERRORS:
3167                 retval = priv->stats.pport.in_range_len_errors +
3168                     priv->stats.pport.out_of_range_len +
3169                     priv->stats.pport.too_long_errors +
3170                     priv->stats.pport.check_seq_err +
3171                     priv->stats.pport.alignment_err;
3172                 break;
3173         case IFCOUNTER_IQDROPS:
3174                 retval = priv->stats.vport.rx_out_of_buffer;
3175                 break;
3176         case IFCOUNTER_OPACKETS:
3177                 retval = priv->stats.vport.tx_packets;
3178                 break;
3179         case IFCOUNTER_OERRORS:
3180                 retval = priv->stats.port_stats_debug.out_discards;
3181                 break;
3182         case IFCOUNTER_IBYTES:
3183                 retval = priv->stats.vport.rx_bytes;
3184                 break;
3185         case IFCOUNTER_OBYTES:
3186                 retval = priv->stats.vport.tx_bytes;
3187                 break;
3188         case IFCOUNTER_IMCASTS:
3189                 retval = priv->stats.vport.rx_multicast_packets;
3190                 break;
3191         case IFCOUNTER_OMCASTS:
3192                 retval = priv->stats.vport.tx_multicast_packets;
3193                 break;
3194         case IFCOUNTER_OQDROPS:
3195                 retval = priv->stats.vport.tx_queue_dropped;
3196                 break;
3197         case IFCOUNTER_COLLISIONS:
3198                 retval = priv->stats.pport.collisions;
3199                 break;
3200         default:
3201                 retval = if_get_counter_default(ifp, cnt);
3202                 break;
3203         }
3204         /* PRIV_UNLOCK(priv); XXX not allowed */
3205         return (retval);
3206 }
3207 #endif
3208
3209 static void
3210 mlx5e_set_rx_mode(struct ifnet *ifp)
3211 {
3212         struct mlx5e_priv *priv = ifp->if_softc;
3213
3214         queue_work(priv->wq, &priv->set_rx_mode_work);
3215 }
3216
3217 static int
3218 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
3219 {
3220         struct mlx5e_priv *priv;
3221         struct ifreq *ifr;
3222         struct ifi2creq i2c;
3223         int error = 0;
3224         int mask = 0;
3225         int size_read = 0;
3226         int module_status;
3227         int module_num;
3228         int max_mtu;
3229         uint8_t read_addr;
3230
3231         priv = ifp->if_softc;
3232
3233         /* check if detaching */
3234         if (priv == NULL || priv->gone != 0)
3235                 return (ENXIO);
3236
3237         switch (command) {
3238         case SIOCSIFMTU:
3239                 ifr = (struct ifreq *)data;
3240
3241                 PRIV_LOCK(priv);
3242                 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
3243
3244                 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
3245                     ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
3246                         int was_opened;
3247
3248                         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3249                         if (was_opened)
3250                                 mlx5e_close_locked(ifp);
3251
3252                         /* set new MTU */
3253                         mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
3254
3255                         if (was_opened)
3256                                 mlx5e_open_locked(ifp);
3257                 } else {
3258                         error = EINVAL;
3259                         mlx5_en_err(ifp,
3260                             "Invalid MTU value. Min val: %d, Max val: %d\n",
3261                             MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
3262                 }
3263                 PRIV_UNLOCK(priv);
3264                 break;
3265         case SIOCSIFFLAGS:
3266                 if ((ifp->if_flags & IFF_UP) &&
3267                     (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3268                         mlx5e_set_rx_mode(ifp);
3269                         break;
3270                 }
3271                 PRIV_LOCK(priv);
3272                 if (ifp->if_flags & IFF_UP) {
3273                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
3274                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3275                                         mlx5e_open_locked(ifp);
3276                                 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3277                                 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
3278                         }
3279                 } else {
3280                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3281                                 mlx5_set_port_status(priv->mdev,
3282                                     MLX5_PORT_DOWN);
3283                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
3284                                         mlx5e_close_locked(ifp);
3285                                 mlx5e_update_carrier(priv);
3286                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3287                         }
3288                 }
3289                 PRIV_UNLOCK(priv);
3290                 break;
3291         case SIOCADDMULTI:
3292         case SIOCDELMULTI:
3293                 mlx5e_set_rx_mode(ifp);
3294                 break;
3295         case SIOCSIFMEDIA:
3296         case SIOCGIFMEDIA:
3297         case SIOCGIFXMEDIA:
3298                 ifr = (struct ifreq *)data;
3299                 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
3300                 break;
3301         case SIOCSIFCAP:
3302                 ifr = (struct ifreq *)data;
3303                 PRIV_LOCK(priv);
3304                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
3305
3306                 if (mask & IFCAP_TXCSUM) {
3307                         ifp->if_capenable ^= IFCAP_TXCSUM;
3308                         ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
3309
3310                         if (IFCAP_TSO4 & ifp->if_capenable &&
3311                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
3312                                 ifp->if_capenable &= ~IFCAP_TSO4;
3313                                 ifp->if_hwassist &= ~CSUM_IP_TSO;
3314                                 mlx5_en_err(ifp,
3315                                     "tso4 disabled due to -txcsum.\n");
3316                         }
3317                 }
3318                 if (mask & IFCAP_TXCSUM_IPV6) {
3319                         ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
3320                         ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3321
3322                         if (IFCAP_TSO6 & ifp->if_capenable &&
3323                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
3324                                 ifp->if_capenable &= ~IFCAP_TSO6;
3325                                 ifp->if_hwassist &= ~CSUM_IP6_TSO;
3326                                 mlx5_en_err(ifp,
3327                                     "tso6 disabled due to -txcsum6.\n");
3328                         }
3329                 }
3330                 if (mask & IFCAP_NOMAP)
3331                         ifp->if_capenable ^= IFCAP_NOMAP;
3332                 if (mask & IFCAP_TXTLS4)
3333                         ifp->if_capenable ^= IFCAP_TXTLS4;
3334                 if (mask & IFCAP_TXTLS6)
3335                         ifp->if_capenable ^= IFCAP_TXTLS6;
3336                 if (mask & IFCAP_RXCSUM)
3337                         ifp->if_capenable ^= IFCAP_RXCSUM;
3338                 if (mask & IFCAP_RXCSUM_IPV6)
3339                         ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
3340                 if (mask & IFCAP_TSO4) {
3341                         if (!(IFCAP_TSO4 & ifp->if_capenable) &&
3342                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
3343                                 mlx5_en_err(ifp, "enable txcsum first.\n");
3344                                 error = EAGAIN;
3345                                 goto out;
3346                         }
3347                         ifp->if_capenable ^= IFCAP_TSO4;
3348                         ifp->if_hwassist ^= CSUM_IP_TSO;
3349                 }
3350                 if (mask & IFCAP_TSO6) {
3351                         if (!(IFCAP_TSO6 & ifp->if_capenable) &&
3352                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
3353                                 mlx5_en_err(ifp, "enable txcsum6 first.\n");
3354                                 error = EAGAIN;
3355                                 goto out;
3356                         }
3357                         ifp->if_capenable ^= IFCAP_TSO6;
3358                         ifp->if_hwassist ^= CSUM_IP6_TSO;
3359                 }
3360                 if (mask & IFCAP_VLAN_HWFILTER) {
3361                         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
3362                                 mlx5e_disable_vlan_filter(priv);
3363                         else
3364                                 mlx5e_enable_vlan_filter(priv);
3365
3366                         ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
3367                 }
3368                 if (mask & IFCAP_VLAN_HWTAGGING)
3369                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
3370                 if (mask & IFCAP_WOL_MAGIC)
3371                         ifp->if_capenable ^= IFCAP_WOL_MAGIC;
3372
3373                 VLAN_CAPABILITIES(ifp);
3374                 /* turn off LRO means also turn of HW LRO - if it's on */
3375                 if (mask & IFCAP_LRO) {
3376                         int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3377                         bool need_restart = false;
3378
3379                         ifp->if_capenable ^= IFCAP_LRO;
3380
3381                         /* figure out if updating HW LRO is needed */
3382                         if (!(ifp->if_capenable & IFCAP_LRO)) {
3383                                 if (priv->params.hw_lro_en) {
3384                                         priv->params.hw_lro_en = false;
3385                                         need_restart = true;
3386                                 }
3387                         } else {
3388                                 if (priv->params.hw_lro_en == false &&
3389                                     priv->params_ethtool.hw_lro != 0) {
3390                                         priv->params.hw_lro_en = true;
3391                                         need_restart = true;
3392                                 }
3393                         }
3394                         if (was_opened && need_restart) {
3395                                 mlx5e_close_locked(ifp);
3396                                 mlx5e_open_locked(ifp);
3397                         }
3398                 }
3399                 if (mask & IFCAP_HWRXTSTMP) {
3400                         ifp->if_capenable ^= IFCAP_HWRXTSTMP;
3401                         if (ifp->if_capenable & IFCAP_HWRXTSTMP) {
3402                                 if (priv->clbr_done == 0)
3403                                         mlx5e_reset_calibration_callout(priv);
3404                         } else {
3405                                 callout_drain(&priv->tstmp_clbr);
3406                                 priv->clbr_done = 0;
3407                         }
3408                 }
3409 out:
3410                 PRIV_UNLOCK(priv);
3411                 break;
3412
3413         case SIOCGI2C:
3414                 ifr = (struct ifreq *)data;
3415
3416                 /*
3417                  * Copy from the user-space address ifr_data to the
3418                  * kernel-space address i2c
3419                  */
3420                 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
3421                 if (error)
3422                         break;
3423
3424                 if (i2c.len > sizeof(i2c.data)) {
3425                         error = EINVAL;
3426                         break;
3427                 }
3428
3429                 PRIV_LOCK(priv);
3430                 /* Get module_num which is required for the query_eeprom */
3431                 error = mlx5_query_module_num(priv->mdev, &module_num);
3432                 if (error) {
3433                         mlx5_en_err(ifp,
3434                             "Query module num failed, eeprom reading is not supported\n");
3435                         error = EINVAL;
3436                         goto err_i2c;
3437                 }
3438                 /* Check if module is present before doing an access */
3439                 module_status = mlx5_query_module_status(priv->mdev, module_num);
3440                 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED) {
3441                         error = EINVAL;
3442                         goto err_i2c;
3443                 }
3444                 /*
3445                  * Currently 0XA0 and 0xA2 are the only addresses permitted.
3446                  * The internal conversion is as follows:
3447                  */
3448                 if (i2c.dev_addr == 0xA0)
3449                         read_addr = MLX5_I2C_ADDR_LOW;
3450                 else if (i2c.dev_addr == 0xA2)
3451                         read_addr = MLX5_I2C_ADDR_HIGH;
3452                 else {
3453                         mlx5_en_err(ifp,
3454                             "Query eeprom failed, Invalid Address: %X\n",
3455                             i2c.dev_addr);
3456                         error = EINVAL;
3457                         goto err_i2c;
3458                 }
3459                 error = mlx5_query_eeprom(priv->mdev,
3460                     read_addr, MLX5_EEPROM_LOW_PAGE,
3461                     (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
3462                     (uint32_t *)i2c.data, &size_read);
3463                 if (error) {
3464                         mlx5_en_err(ifp,
3465                             "Query eeprom failed, eeprom reading is not supported\n");
3466                         error = EINVAL;
3467                         goto err_i2c;
3468                 }
3469
3470                 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
3471                         error = mlx5_query_eeprom(priv->mdev,
3472                             read_addr, MLX5_EEPROM_LOW_PAGE,
3473                             (uint32_t)(i2c.offset + size_read),
3474                             (uint32_t)(i2c.len - size_read), module_num,
3475                             (uint32_t *)(i2c.data + size_read), &size_read);
3476                 }
3477                 if (error) {
3478                         mlx5_en_err(ifp,
3479                             "Query eeprom failed, eeprom reading is not supported\n");
3480                         error = EINVAL;
3481                         goto err_i2c;
3482                 }
3483
3484                 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
3485 err_i2c:
3486                 PRIV_UNLOCK(priv);
3487                 break;
3488
3489         default:
3490                 error = ether_ioctl(ifp, command, data);
3491                 break;
3492         }
3493         return (error);
3494 }
3495
3496 static int
3497 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3498 {
3499         /*
3500          * TODO: uncoment once FW really sets all these bits if
3501          * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
3502          * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
3503          * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
3504          * -ENOTSUPP;
3505          */
3506
3507         /* TODO: add more must-to-have features */
3508
3509         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3510                 return (-ENODEV);
3511
3512         return (0);
3513 }
3514
3515 static u16
3516 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3517 {
3518         uint32_t bf_buf_size = (1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U;
3519
3520         bf_buf_size -= sizeof(struct mlx5e_tx_wqe) - 2;
3521
3522         /* verify against driver hardware limit */
3523         if (bf_buf_size > MLX5E_MAX_TX_INLINE)
3524                 bf_buf_size = MLX5E_MAX_TX_INLINE;
3525
3526         return (bf_buf_size);
3527 }
3528
3529 static int
3530 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
3531     struct mlx5e_priv *priv,
3532     int num_comp_vectors)
3533 {
3534         int err;
3535
3536         /*
3537          * TODO: Consider link speed for setting "log_sq_size",
3538          * "log_rq_size" and "cq_moderation_xxx":
3539          */
3540         priv->params.log_sq_size =
3541             MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3542         priv->params.log_rq_size =
3543             MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3544         priv->params.rx_cq_moderation_usec =
3545             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3546             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
3547             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3548         priv->params.rx_cq_moderation_mode =
3549             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
3550         priv->params.rx_cq_moderation_pkts =
3551             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3552         priv->params.tx_cq_moderation_usec =
3553             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3554         priv->params.tx_cq_moderation_pkts =
3555             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3556         priv->params.min_rx_wqes =
3557             MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
3558         priv->params.rx_hash_log_tbl_sz =
3559             (order_base_2(num_comp_vectors) >
3560             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
3561             order_base_2(num_comp_vectors) :
3562             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
3563         priv->params.num_tc = 1;
3564         priv->params.default_vlan_prio = 0;
3565         priv->counter_set_id = -1;
3566         priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3567
3568         err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3569         if (err)
3570                 return (err);
3571
3572         /*
3573          * hw lro is currently defaulted to off. when it won't anymore we
3574          * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
3575          */
3576         priv->params.hw_lro_en = false;
3577         priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3578
3579         /*
3580          * CQE zipping is currently defaulted to off. when it won't
3581          * anymore we will consider the HW capability:
3582          * "!!MLX5_CAP_GEN(mdev, cqe_compression)"
3583          */
3584         priv->params.cqe_zipping_en = false;
3585
3586         priv->mdev = mdev;
3587         priv->params.num_channels = num_comp_vectors;
3588         priv->params.channels_rsss = 1;
3589         priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
3590         priv->queue_mapping_channel_mask =
3591             roundup_pow_of_two(num_comp_vectors) - 1;
3592         priv->num_tc = priv->params.num_tc;
3593         priv->default_vlan_prio = priv->params.default_vlan_prio;
3594
3595         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3596         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3597         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3598
3599         return (0);
3600 }
3601
3602 static int
3603 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
3604                   struct mlx5_core_mr *mkey)
3605 {
3606         struct ifnet *ifp = priv->ifp;
3607         struct mlx5_core_dev *mdev = priv->mdev;
3608         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3609         void *mkc;
3610         u32 *in;
3611         int err;
3612
3613         in = mlx5_vzalloc(inlen);
3614         if (in == NULL) {
3615                 mlx5_en_err(ifp, "failed to allocate inbox\n");
3616                 return (-ENOMEM);
3617         }
3618
3619         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3620         MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA);
3621         MLX5_SET(mkc, mkc, umr_en, 1);  /* used by HW TLS */
3622         MLX5_SET(mkc, mkc, lw, 1);
3623         MLX5_SET(mkc, mkc, lr, 1);
3624
3625         MLX5_SET(mkc, mkc, pd, pdn);
3626         MLX5_SET(mkc, mkc, length64, 1);
3627         MLX5_SET(mkc, mkc, qpn, 0xffffff);
3628
3629         err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
3630         if (err)
3631                 mlx5_en_err(ifp, "mlx5_core_create_mkey failed, %d\n",
3632                     err);
3633
3634         kvfree(in);
3635         return (err);
3636 }
3637
3638 static const char *mlx5e_vport_stats_desc[] = {
3639         MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
3640 };
3641
3642 static const char *mlx5e_pport_stats_desc[] = {
3643         MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
3644 };
3645
3646 static void
3647 mlx5e_priv_static_init(struct mlx5e_priv *priv, const uint32_t channels)
3648 {
3649         uint32_t x;
3650
3651         mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
3652         sx_init(&priv->state_lock, "mlx5state");
3653         callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
3654         MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
3655         for (x = 0; x != channels; x++)
3656                 mlx5e_chan_static_init(priv, &priv->channel[x], x);
3657 }
3658
3659 static void
3660 mlx5e_priv_static_destroy(struct mlx5e_priv *priv, const uint32_t channels)
3661 {
3662         uint32_t x;
3663
3664         for (x = 0; x != channels; x++)
3665                 mlx5e_chan_static_destroy(&priv->channel[x]);
3666         callout_drain(&priv->watchdog);
3667         mtx_destroy(&priv->async_events_mtx);
3668         sx_destroy(&priv->state_lock);
3669 }
3670
3671 static int
3672 sysctl_firmware(SYSCTL_HANDLER_ARGS)
3673 {
3674         /*
3675          * %d.%d%.d the string format.
3676          * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
3677          * We need at most 5 chars to store that.
3678          * It also has: two "." and NULL at the end, which means we need 18
3679          * (5*3 + 3) chars at most.
3680          */
3681         char fw[18];
3682         struct mlx5e_priv *priv = arg1;
3683         int error;
3684
3685         snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
3686             fw_rev_sub(priv->mdev));
3687         error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
3688         return (error);
3689 }
3690
3691 static void
3692 mlx5e_disable_tx_dma(struct mlx5e_channel *ch)
3693 {
3694         int i;
3695
3696         for (i = 0; i < ch->priv->num_tc; i++)
3697                 mlx5e_drain_sq(&ch->sq[i]);
3698 }
3699
3700 static void
3701 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq)
3702 {
3703
3704         sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP);
3705         sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8);
3706         mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
3707         sq->doorbell.d64 = 0;
3708 }
3709
3710 void
3711 mlx5e_resume_sq(struct mlx5e_sq *sq)
3712 {
3713         int err;
3714
3715         /* check if already enabled */
3716         if (READ_ONCE(sq->running) != 0)
3717                 return;
3718
3719         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR,
3720             MLX5_SQC_STATE_RST);
3721         if (err != 0) {
3722                 mlx5_en_err(sq->ifp,
3723                     "mlx5e_modify_sq() from ERR to RST failed: %d\n", err);
3724         }
3725
3726         sq->cc = 0;
3727         sq->pc = 0;
3728
3729         /* reset doorbell prior to moving from RST to RDY */
3730         mlx5e_reset_sq_doorbell_record(sq);
3731
3732         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST,
3733             MLX5_SQC_STATE_RDY);
3734         if (err != 0) {
3735                 mlx5_en_err(sq->ifp,
3736                     "mlx5e_modify_sq() from RST to RDY failed: %d\n", err);
3737         }
3738
3739         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
3740         WRITE_ONCE(sq->running, 1);
3741 }
3742
3743 static void
3744 mlx5e_enable_tx_dma(struct mlx5e_channel *ch)
3745 {
3746         int i;
3747
3748         for (i = 0; i < ch->priv->num_tc; i++)
3749                 mlx5e_resume_sq(&ch->sq[i]);
3750 }
3751
3752 static void
3753 mlx5e_disable_rx_dma(struct mlx5e_channel *ch)
3754 {
3755         struct mlx5e_rq *rq = &ch->rq;
3756         struct epoch_tracker et;
3757         int err;
3758
3759         mtx_lock(&rq->mtx);
3760         rq->enabled = 0;
3761         callout_stop(&rq->watchdog);
3762         mtx_unlock(&rq->mtx);
3763
3764         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
3765         if (err != 0) {
3766                 mlx5_en_err(rq->ifp,
3767                     "mlx5e_modify_rq() from RDY to RST failed: %d\n", err);
3768         }
3769
3770         while (!mlx5_wq_ll_is_empty(&rq->wq)) {
3771                 msleep(1);
3772                 NET_EPOCH_ENTER(et);
3773                 rq->cq.mcq.comp(&rq->cq.mcq);
3774                 NET_EPOCH_EXIT(et);
3775         }
3776
3777         /*
3778          * Transitioning into RST state will allow the FW to track less ERR state queues,
3779          * thus reducing the recv queue flushing time
3780          */
3781         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST);
3782         if (err != 0) {
3783                 mlx5_en_err(rq->ifp,
3784                     "mlx5e_modify_rq() from ERR to RST failed: %d\n", err);
3785         }
3786 }
3787
3788 static void
3789 mlx5e_enable_rx_dma(struct mlx5e_channel *ch)
3790 {
3791         struct mlx5e_rq *rq = &ch->rq;
3792         struct epoch_tracker et;
3793         int err;
3794
3795         rq->wq.wqe_ctr = 0;
3796         mlx5_wq_ll_update_db_record(&rq->wq);
3797         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3798         if (err != 0) {
3799                 mlx5_en_err(rq->ifp,
3800                     "mlx5e_modify_rq() from RST to RDY failed: %d\n", err);
3801         }
3802
3803         rq->enabled = 1;
3804
3805         NET_EPOCH_ENTER(et);
3806         rq->cq.mcq.comp(&rq->cq.mcq);
3807         NET_EPOCH_EXIT(et);
3808 }
3809
3810 void
3811 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value)
3812 {
3813         int i;
3814
3815         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3816                 return;
3817
3818         for (i = 0; i < priv->params.num_channels; i++) {
3819                 if (value)
3820                         mlx5e_disable_tx_dma(&priv->channel[i]);
3821                 else
3822                         mlx5e_enable_tx_dma(&priv->channel[i]);
3823         }
3824 }
3825
3826 void
3827 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value)
3828 {
3829         int i;
3830
3831         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3832                 return;
3833
3834         for (i = 0; i < priv->params.num_channels; i++) {
3835                 if (value)
3836                         mlx5e_disable_rx_dma(&priv->channel[i]);
3837                 else
3838                         mlx5e_enable_rx_dma(&priv->channel[i]);
3839         }
3840 }
3841
3842 static void
3843 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
3844 {
3845         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3846             OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
3847             sysctl_firmware, "A", "HCA firmware version");
3848
3849         SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3850             OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
3851             "Board ID");
3852 }
3853
3854 static int
3855 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3856 {
3857         struct mlx5e_priv *priv = arg1;
3858         uint8_t temp[MLX5E_MAX_PRIORITY];
3859         uint32_t tx_pfc;
3860         int err;
3861         int i;
3862
3863         PRIV_LOCK(priv);
3864
3865         tx_pfc = priv->params.tx_priority_flow_control;
3866
3867         for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3868                 temp[i] = (tx_pfc >> i) & 1;
3869
3870         err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3871         if (err || !req->newptr)
3872                 goto done;
3873         err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3874         if (err)
3875                 goto done;
3876
3877         priv->params.tx_priority_flow_control = 0;
3878
3879         /* range check input value */
3880         for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3881                 if (temp[i] > 1) {
3882                         err = ERANGE;
3883                         goto done;
3884                 }
3885                 priv->params.tx_priority_flow_control |= (temp[i] << i);
3886         }
3887
3888         /* check if update is required */
3889         if (tx_pfc != priv->params.tx_priority_flow_control)
3890                 err = -mlx5e_set_port_pfc(priv);
3891 done:
3892         if (err != 0)
3893                 priv->params.tx_priority_flow_control= tx_pfc;
3894         PRIV_UNLOCK(priv);
3895
3896         return (err);
3897 }
3898
3899 static int
3900 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3901 {
3902         struct mlx5e_priv *priv = arg1;
3903         uint8_t temp[MLX5E_MAX_PRIORITY];
3904         uint32_t rx_pfc;
3905         int err;
3906         int i;
3907
3908         PRIV_LOCK(priv);
3909
3910         rx_pfc = priv->params.rx_priority_flow_control;
3911
3912         for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3913                 temp[i] = (rx_pfc >> i) & 1;
3914
3915         err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3916         if (err || !req->newptr)
3917                 goto done;
3918         err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3919         if (err)
3920                 goto done;
3921
3922         priv->params.rx_priority_flow_control = 0;
3923
3924         /* range check input value */
3925         for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3926                 if (temp[i] > 1) {
3927                         err = ERANGE;
3928                         goto done;
3929                 }
3930                 priv->params.rx_priority_flow_control |= (temp[i] << i);
3931         }
3932
3933         /* check if update is required */
3934         if (rx_pfc != priv->params.rx_priority_flow_control) {
3935                 err = -mlx5e_set_port_pfc(priv);
3936                 if (err == 0 && priv->sw_is_port_buf_owner)
3937                         err = mlx5e_update_buf_lossy(priv);
3938         }
3939 done:
3940         if (err != 0)
3941                 priv->params.rx_priority_flow_control= rx_pfc;
3942         PRIV_UNLOCK(priv);
3943
3944         return (err);
3945 }
3946
3947 static void
3948 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
3949 {
3950 #if (__FreeBSD_version < 1100000)
3951         char path[96];
3952 #endif
3953         int error;
3954
3955         /* enable pauseframes by default */
3956         priv->params.tx_pauseframe_control = 1;
3957         priv->params.rx_pauseframe_control = 1;
3958
3959         /* disable ports flow control, PFC, by default */
3960         priv->params.tx_priority_flow_control = 0;
3961         priv->params.rx_priority_flow_control = 0;
3962
3963 #if (__FreeBSD_version < 1100000)
3964         /* compute path for sysctl */
3965         snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
3966             device_get_unit(priv->mdev->pdev->dev.bsddev));
3967
3968         /* try to fetch tunable, if any */
3969         TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
3970
3971         /* compute path for sysctl */
3972         snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
3973             device_get_unit(priv->mdev->pdev->dev.bsddev));
3974
3975         /* try to fetch tunable, if any */
3976         TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
3977 #endif
3978
3979         /* register pauseframe SYSCTLs */
3980         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3981             OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
3982             &priv->params.tx_pauseframe_control, 0,
3983             "Set to enable TX pause frames. Clear to disable.");
3984
3985         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3986             OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
3987             &priv->params.rx_pauseframe_control, 0,
3988             "Set to enable RX pause frames. Clear to disable.");
3989
3990         /* register priority flow control, PFC, SYSCTLs */
3991         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3992             OID_AUTO, "tx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
3993             CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_tx_priority_flow_control, "CU",
3994             "Set to enable TX ports flow control frames for priorities 0..7. Clear to disable.");
3995
3996         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3997             OID_AUTO, "rx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
3998             CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_rx_priority_flow_control, "CU",
3999             "Set to enable RX ports flow control frames for priorities 0..7. Clear to disable.");
4000
4001         PRIV_LOCK(priv);
4002
4003         /* range check */
4004         priv->params.tx_pauseframe_control =
4005             priv->params.tx_pauseframe_control ? 1 : 0;
4006         priv->params.rx_pauseframe_control =
4007             priv->params.rx_pauseframe_control ? 1 : 0;
4008
4009         /* update firmware */
4010         error = mlx5e_set_port_pause_and_pfc(priv);
4011         if (error == -EINVAL) {
4012                 mlx5_en_err(priv->ifp,
4013                     "Global pauseframes must be disabled before enabling PFC.\n");
4014                 priv->params.rx_priority_flow_control = 0;
4015                 priv->params.tx_priority_flow_control = 0;
4016
4017                 /* update firmware */
4018                 (void) mlx5e_set_port_pause_and_pfc(priv);
4019         }
4020         PRIV_UNLOCK(priv);
4021 }
4022
4023 int
4024 mlx5e_ul_snd_tag_alloc(struct ifnet *ifp,
4025     union if_snd_tag_alloc_params *params,
4026     struct m_snd_tag **ppmt)
4027 {
4028         struct mlx5e_priv *priv;
4029         struct mlx5e_channel *pch;
4030
4031         priv = ifp->if_softc;
4032
4033         if (unlikely(priv->gone || params->hdr.flowtype == M_HASHTYPE_NONE)) {
4034                 return (EOPNOTSUPP);
4035         } else {
4036                 /* keep this code synced with mlx5e_select_queue() */
4037                 u32 ch = priv->params.num_channels;
4038 #ifdef RSS
4039                 u32 temp;
4040
4041                 if (rss_hash2bucket(params->hdr.flowid,
4042                     params->hdr.flowtype, &temp) == 0)
4043                         ch = temp % ch;
4044                 else
4045 #endif
4046                         ch = (params->hdr.flowid % 128) % ch;
4047
4048                 /*
4049                  * NOTE: The channels array is only freed at detach
4050                  * and it safe to return a pointer to the send tag
4051                  * inside the channels structure as long as we
4052                  * reference the priv.
4053                  */
4054                 pch = priv->channel + ch;
4055
4056                 /* check if send queue is not running */
4057                 if (unlikely(pch->sq[0].running == 0))
4058                         return (ENXIO);
4059                 m_snd_tag_ref(&pch->tag.m_snd_tag);
4060                 *ppmt = &pch->tag.m_snd_tag;
4061                 return (0);
4062         }
4063 }
4064
4065 int
4066 mlx5e_ul_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
4067 {
4068         struct mlx5e_channel *pch =
4069             container_of(pmt, struct mlx5e_channel, tag.m_snd_tag);
4070
4071         params->unlimited.max_rate = -1ULL;
4072         params->unlimited.queue_level = mlx5e_sq_queue_level(&pch->sq[0]);
4073         return (0);
4074 }
4075
4076 void
4077 mlx5e_ul_snd_tag_free(struct m_snd_tag *pmt)
4078 {
4079         struct mlx5e_channel *pch =
4080             container_of(pmt, struct mlx5e_channel, tag.m_snd_tag);
4081
4082         complete(&pch->completion);
4083 }
4084
4085 static int
4086 mlx5e_snd_tag_alloc(struct ifnet *ifp,
4087     union if_snd_tag_alloc_params *params,
4088     struct m_snd_tag **ppmt)
4089 {
4090
4091         switch (params->hdr.type) {
4092 #ifdef RATELIMIT
4093         case IF_SND_TAG_TYPE_RATE_LIMIT:
4094                 return (mlx5e_rl_snd_tag_alloc(ifp, params, ppmt));
4095 #if defined(KERN_TLS) && defined(IF_SND_TAG_TYPE_TLS_RATE_LIMIT)
4096         case IF_SND_TAG_TYPE_TLS_RATE_LIMIT:
4097                 return (mlx5e_tls_snd_tag_alloc(ifp, params, ppmt));
4098 #endif
4099 #endif
4100         case IF_SND_TAG_TYPE_UNLIMITED:
4101                 return (mlx5e_ul_snd_tag_alloc(ifp, params, ppmt));
4102 #ifdef KERN_TLS
4103         case IF_SND_TAG_TYPE_TLS:
4104                 return (mlx5e_tls_snd_tag_alloc(ifp, params, ppmt));
4105 #endif
4106         default:
4107                 return (EOPNOTSUPP);
4108         }
4109 }
4110
4111 static int
4112 mlx5e_snd_tag_modify(struct m_snd_tag *pmt, union if_snd_tag_modify_params *params)
4113 {
4114         struct mlx5e_snd_tag *tag =
4115             container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
4116
4117         switch (tag->type) {
4118 #ifdef RATELIMIT
4119         case IF_SND_TAG_TYPE_RATE_LIMIT:
4120                 return (mlx5e_rl_snd_tag_modify(pmt, params));
4121 #if defined(KERN_TLS) && defined(IF_SND_TAG_TYPE_TLS_RATE_LIMIT)
4122         case IF_SND_TAG_TYPE_TLS_RATE_LIMIT:
4123                 return (mlx5e_tls_snd_tag_modify(pmt, params));
4124 #endif
4125 #endif
4126         case IF_SND_TAG_TYPE_UNLIMITED:
4127 #ifdef KERN_TLS
4128         case IF_SND_TAG_TYPE_TLS:
4129 #endif
4130         default:
4131                 return (EOPNOTSUPP);
4132         }
4133 }
4134
4135 static int
4136 mlx5e_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
4137 {
4138         struct mlx5e_snd_tag *tag =
4139             container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
4140
4141         switch (tag->type) {
4142 #ifdef RATELIMIT
4143         case IF_SND_TAG_TYPE_RATE_LIMIT:
4144                 return (mlx5e_rl_snd_tag_query(pmt, params));
4145 #if defined(KERN_TLS) && defined(IF_SND_TAG_TYPE_TLS_RATE_LIMIT)
4146         case IF_SND_TAG_TYPE_TLS_RATE_LIMIT:
4147                 return (mlx5e_tls_snd_tag_query(pmt, params));
4148 #endif
4149 #endif
4150         case IF_SND_TAG_TYPE_UNLIMITED:
4151                 return (mlx5e_ul_snd_tag_query(pmt, params));
4152 #ifdef KERN_TLS
4153         case IF_SND_TAG_TYPE_TLS:
4154                 return (mlx5e_tls_snd_tag_query(pmt, params));
4155 #endif
4156         default:
4157                 return (EOPNOTSUPP);
4158         }
4159 }
4160
4161 #ifdef RATELIMIT
4162 #define NUM_HDWR_RATES_MLX 13
4163 static const uint64_t adapter_rates_mlx[NUM_HDWR_RATES_MLX] = {
4164         135375,                 /* 1,083,000 */
4165         180500,                 /* 1,444,000 */
4166         270750,                 /* 2,166,000 */
4167         361000,                 /* 2,888,000 */
4168         541500,                 /* 4,332,000 */
4169         721875,                 /* 5,775,000 */
4170         1082875,                /* 8,663,000 */
4171         1443875,                /* 11,551,000 */
4172         2165750,                /* 17,326,000 */
4173         2887750,                /* 23,102,000 */
4174         4331625,                /* 34,653,000 */
4175         5775500,                /* 46,204,000 */
4176         8663125                 /* 69,305,000 */
4177 };
4178
4179 static void
4180 mlx5e_ratelimit_query(struct ifnet *ifp __unused, struct if_ratelimit_query_results *q)
4181 {
4182         /*
4183          * This function needs updating by the driver maintainer!
4184          * For the MLX card there are currently (ConectX-4?) 13
4185          * pre-set rates and others i.e. ConnectX-5, 6, 7??
4186          *
4187          * This will change based on later adapters
4188          * and this code should be updated to look at ifp
4189          * and figure out the specific adapter type
4190          * settings i.e. how many rates as well
4191          * as if they are fixed (as is shown here) or
4192          * if they are dynamic (example chelsio t4). Also if there
4193          * is a maximum number of flows that the adapter
4194          * can handle that too needs to be updated in
4195          * the max_flows field.
4196          */
4197         q->rate_table = adapter_rates_mlx;
4198         q->flags = RT_IS_FIXED_TABLE;
4199         q->max_flows = 0;       /* mlx has no limit */
4200         q->number_of_rates = NUM_HDWR_RATES_MLX;
4201         q->min_segment_burst = 1;
4202 }
4203 #endif
4204
4205 static void
4206 mlx5e_snd_tag_free(struct m_snd_tag *pmt)
4207 {
4208         struct mlx5e_snd_tag *tag =
4209             container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
4210
4211         switch (tag->type) {
4212 #ifdef RATELIMIT
4213         case IF_SND_TAG_TYPE_RATE_LIMIT:
4214                 mlx5e_rl_snd_tag_free(pmt);
4215                 break;
4216 #if defined(KERN_TLS) && defined(IF_SND_TAG_TYPE_TLS_RATE_LIMIT)
4217         case IF_SND_TAG_TYPE_TLS_RATE_LIMIT:
4218                 mlx5e_tls_snd_tag_free(pmt);
4219                 break;
4220 #endif
4221 #endif
4222         case IF_SND_TAG_TYPE_UNLIMITED:
4223                 mlx5e_ul_snd_tag_free(pmt);
4224                 break;
4225 #ifdef KERN_TLS
4226         case IF_SND_TAG_TYPE_TLS:
4227                 mlx5e_tls_snd_tag_free(pmt);
4228                 break;
4229 #endif
4230         default:
4231                 break;
4232         }
4233 }
4234
4235 static void *
4236 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
4237 {
4238         struct ifnet *ifp;
4239         struct mlx5e_priv *priv;
4240         u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
4241         u8 connector_type;
4242         struct sysctl_oid_list *child;
4243         int ncv = mdev->priv.eq_table.num_comp_vectors;
4244         char unit[16];
4245         struct pfil_head_args pa;
4246         int err;
4247         int i,j;
4248         u32 eth_proto_cap;
4249         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
4250         bool ext = 0;
4251         u32 speeds_num;
4252         struct media media_entry = {};
4253
4254         if (mlx5e_check_required_hca_cap(mdev)) {
4255                 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
4256                 return (NULL);
4257         }
4258         /*
4259          * Try to allocate the priv and make room for worst-case
4260          * number of channel structures:
4261          */
4262         priv = malloc(sizeof(*priv) +
4263             (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors),
4264             M_MLX5EN, M_WAITOK | M_ZERO);
4265
4266         ifp = priv->ifp = if_alloc_dev(IFT_ETHER, mdev->pdev->dev.bsddev);
4267         if (ifp == NULL) {
4268                 mlx5_core_err(mdev, "if_alloc() failed\n");
4269                 goto err_free_priv;
4270         }
4271         /* setup all static fields */
4272         mlx5e_priv_static_init(priv, mdev->priv.eq_table.num_comp_vectors);
4273
4274         ifp->if_softc = priv;
4275         if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev));
4276         ifp->if_mtu = ETHERMTU;
4277         ifp->if_init = mlx5e_open;
4278         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
4279         ifp->if_ioctl = mlx5e_ioctl;
4280         ifp->if_transmit = mlx5e_xmit;
4281         ifp->if_qflush = if_qflush;
4282 #if (__FreeBSD_version >= 1100000)
4283         ifp->if_get_counter = mlx5e_get_counter;
4284 #endif
4285         ifp->if_snd.ifq_maxlen = ifqmaxlen;
4286         /*
4287          * Set driver features
4288          */
4289         ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
4290         ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
4291         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
4292         ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
4293         ifp->if_capabilities |= IFCAP_LRO;
4294         ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
4295         ifp->if_capabilities |= IFCAP_HWSTATS | IFCAP_HWRXTSTMP;
4296         ifp->if_capabilities |= IFCAP_NOMAP;
4297         ifp->if_capabilities |= IFCAP_TXTLS4 | IFCAP_TXTLS6;
4298         ifp->if_capabilities |= IFCAP_TXRTLMT;
4299         ifp->if_snd_tag_alloc = mlx5e_snd_tag_alloc;
4300         ifp->if_snd_tag_free = mlx5e_snd_tag_free;
4301         ifp->if_snd_tag_modify = mlx5e_snd_tag_modify;
4302         ifp->if_snd_tag_query = mlx5e_snd_tag_query;
4303 #ifdef RATELIMIT
4304         ifp->if_ratelimit_query = mlx5e_ratelimit_query;
4305 #endif
4306         /* set TSO limits so that we don't have to drop TX packets */
4307         ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
4308         ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
4309         ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
4310
4311         ifp->if_capenable = ifp->if_capabilities;
4312         ifp->if_hwassist = 0;
4313         if (ifp->if_capenable & IFCAP_TSO)
4314                 ifp->if_hwassist |= CSUM_TSO;
4315         if (ifp->if_capenable & IFCAP_TXCSUM)
4316                 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
4317         if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
4318                 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
4319
4320         /* ifnet sysctl tree */
4321         sysctl_ctx_init(&priv->sysctl_ctx);
4322         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
4323             OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
4324         if (priv->sysctl_ifnet == NULL) {
4325                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4326                 goto err_free_sysctl;
4327         }
4328         snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
4329         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4330             OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
4331         if (priv->sysctl_ifnet == NULL) {
4332                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4333                 goto err_free_sysctl;
4334         }
4335
4336         /* HW sysctl tree */
4337         child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
4338         priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
4339             OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
4340         if (priv->sysctl_hw == NULL) {
4341                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
4342                 goto err_free_sysctl;
4343         }
4344
4345         err = mlx5e_build_ifp_priv(mdev, priv, ncv);
4346         if (err) {
4347                 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err);
4348                 goto err_free_sysctl;
4349         }
4350
4351         /* reuse mlx5core's watchdog workqueue */
4352         priv->wq = mdev->priv.health.wq_watchdog;
4353
4354         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
4355         if (err) {
4356                 mlx5_en_err(ifp, "mlx5_alloc_map_uar failed, %d\n", err);
4357                 goto err_free_wq;
4358         }
4359         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
4360         if (err) {
4361                 mlx5_en_err(ifp, "mlx5_core_alloc_pd failed, %d\n", err);
4362                 goto err_unmap_free_uar;
4363         }
4364         err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
4365         if (err) {
4366                 mlx5_en_err(ifp,
4367                     "mlx5_alloc_transport_domain failed, %d\n", err);
4368                 goto err_dealloc_pd;
4369         }
4370         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
4371         if (err) {
4372                 mlx5_en_err(ifp, "mlx5e_create_mkey failed, %d\n", err);
4373                 goto err_dealloc_transport_domain;
4374         }
4375         mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
4376
4377         /* check if we should generate a random MAC address */
4378         if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
4379             is_zero_ether_addr(dev_addr)) {
4380                 random_ether_addr(dev_addr);
4381                 mlx5_en_err(ifp, "Assigned random MAC address\n");
4382         }
4383
4384         err = mlx5e_rl_init(priv);
4385         if (err) {
4386                 mlx5_en_err(ifp, "mlx5e_rl_init failed, %d\n", err);
4387                 goto err_create_mkey;
4388         }
4389
4390         err = mlx5e_tls_init(priv);
4391         if (err) {
4392                 if_printf(ifp, "%s: mlx5e_tls_init failed\n", __func__);
4393                 goto err_rl_init;
4394         }
4395
4396         /* set default MTU */
4397         mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
4398
4399         /* Set default media status */
4400         priv->media_status_last = IFM_AVALID;
4401         priv->media_active_last = IFM_ETHER | IFM_AUTO |
4402             IFM_ETH_RXPAUSE | IFM_FDX;
4403
4404         /* setup default pauseframes configuration */
4405         mlx5e_setup_pauseframes(priv);
4406
4407         /* Setup supported medias */
4408         //TODO: If we failed to query ptys is it ok to proceed??
4409         if (!mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1)) {
4410                 ext = MLX5_CAP_PCAM_FEATURE(mdev,
4411                     ptys_extended_ethernet);
4412                 eth_proto_cap = MLX5_GET_ETH_PROTO(ptys_reg, out, ext,
4413                     eth_proto_capability);
4414                 if (MLX5_CAP_PCAM_FEATURE(mdev, ptys_connector_type))
4415                         connector_type = MLX5_GET(ptys_reg, out,
4416                             connector_type);
4417         } else {
4418                 eth_proto_cap = 0;
4419                 mlx5_en_err(ifp, "Query port media capability failed, %d\n", err);
4420         }
4421
4422         ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
4423             mlx5e_media_change, mlx5e_media_status);
4424
4425         speeds_num = ext ? MLX5E_EXT_LINK_SPEEDS_NUMBER : MLX5E_LINK_SPEEDS_NUMBER;
4426         for (i = 0; i != speeds_num; i++) {
4427                 for (j = 0; j < MLX5E_LINK_MODES_NUMBER ; ++j) {
4428                         media_entry = ext ? mlx5e_ext_mode_table[i][j] :
4429                             mlx5e_mode_table[i][j];
4430                         if (media_entry.baudrate == 0)
4431                                 continue;
4432                         if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
4433                                 ifmedia_add(&priv->media,
4434                                     media_entry.subtype |
4435                                     IFM_ETHER, 0, NULL);
4436                                 ifmedia_add(&priv->media,
4437                                     media_entry.subtype |
4438                                     IFM_ETHER | IFM_FDX |
4439                                     IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
4440                         }
4441                 }
4442         }
4443
4444         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
4445         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
4446             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
4447
4448         /* Set autoselect by default */
4449         ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
4450             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
4451
4452         DEBUGNET_SET(ifp, mlx5_en);
4453
4454         ether_ifattach(ifp, dev_addr);
4455
4456         /* Register for VLAN events */
4457         priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
4458             mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
4459         priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
4460             mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
4461
4462         /* Link is down by default */
4463         if_link_state_change(ifp, LINK_STATE_DOWN);
4464
4465         mlx5e_enable_async_events(priv);
4466
4467         mlx5e_add_hw_stats(priv);
4468
4469         mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4470             "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
4471             priv->stats.vport.arg);
4472
4473         mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4474             "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
4475             priv->stats.pport.arg);
4476
4477         mlx5e_create_ethtool(priv);
4478
4479         mtx_lock(&priv->async_events_mtx);
4480         mlx5e_update_stats(priv);
4481         mtx_unlock(&priv->async_events_mtx);
4482
4483         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
4484             OID_AUTO, "rx_clbr_done", CTLFLAG_RD,
4485             &priv->clbr_done, 0,
4486             "RX timestamps calibration state");
4487         callout_init(&priv->tstmp_clbr, CALLOUT_DIRECT);
4488         mlx5e_reset_calibration_callout(priv);
4489
4490         pa.pa_version = PFIL_VERSION;
4491         pa.pa_flags = PFIL_IN;
4492         pa.pa_type = PFIL_TYPE_ETHERNET;
4493         pa.pa_headname = ifp->if_xname;
4494         priv->pfil = pfil_head_register(&pa);
4495
4496         return (priv);
4497
4498 err_rl_init:
4499         mlx5e_rl_cleanup(priv);
4500
4501 err_create_mkey:
4502         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
4503
4504 err_dealloc_transport_domain:
4505         mlx5_dealloc_transport_domain(mdev, priv->tdn);
4506
4507 err_dealloc_pd:
4508         mlx5_core_dealloc_pd(mdev, priv->pdn);
4509
4510 err_unmap_free_uar:
4511         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
4512
4513 err_free_wq:
4514         flush_workqueue(priv->wq);
4515
4516 err_free_sysctl:
4517         sysctl_ctx_free(&priv->sysctl_ctx);
4518         if (priv->sysctl_debug)
4519                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4520         mlx5e_priv_static_destroy(priv, mdev->priv.eq_table.num_comp_vectors);
4521         if_free(ifp);
4522
4523 err_free_priv:
4524         free(priv, M_MLX5EN);
4525         return (NULL);
4526 }
4527
4528 static void
4529 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
4530 {
4531         struct mlx5e_priv *priv = vpriv;
4532         struct ifnet *ifp = priv->ifp;
4533
4534         /* don't allow more IOCTLs */
4535         priv->gone = 1;
4536
4537         /* XXX wait a bit to allow IOCTL handlers to complete */
4538         pause("W", hz);
4539
4540 #ifdef RATELIMIT
4541         /*
4542          * The kernel can have reference(s) via the m_snd_tag's into
4543          * the ratelimit channels, and these must go away before
4544          * detaching:
4545          */
4546         while (READ_ONCE(priv->rl.stats.tx_active_connections) != 0) {
4547                 mlx5_en_err(priv->ifp,
4548                     "Waiting for all ratelimit connections to terminate\n");
4549                 pause("W", hz);
4550         }
4551 #endif
4552         /* wait for all unlimited send tags to complete */
4553         mlx5e_priv_wait_for_completion(priv, mdev->priv.eq_table.num_comp_vectors);
4554
4555         /* stop watchdog timer */
4556         callout_drain(&priv->watchdog);
4557
4558         callout_drain(&priv->tstmp_clbr);
4559
4560         if (priv->vlan_attach != NULL)
4561                 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
4562         if (priv->vlan_detach != NULL)
4563                 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
4564
4565         /* make sure device gets closed */
4566         PRIV_LOCK(priv);
4567         mlx5e_close_locked(ifp);
4568         PRIV_UNLOCK(priv);
4569
4570         /* deregister pfil */
4571         if (priv->pfil != NULL) {
4572                 pfil_head_unregister(priv->pfil);
4573                 priv->pfil = NULL;
4574         }
4575
4576         /* unregister device */
4577         ifmedia_removeall(&priv->media);
4578         ether_ifdetach(ifp);
4579
4580         mlx5e_tls_cleanup(priv);
4581         mlx5e_rl_cleanup(priv);
4582
4583         /* destroy all remaining sysctl nodes */
4584         sysctl_ctx_free(&priv->stats.vport.ctx);
4585         sysctl_ctx_free(&priv->stats.pport.ctx);
4586         if (priv->sysctl_debug)
4587                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4588         sysctl_ctx_free(&priv->sysctl_ctx);
4589
4590         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
4591         mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
4592         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
4593         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
4594         mlx5e_disable_async_events(priv);
4595         flush_workqueue(priv->wq);
4596         mlx5e_priv_static_destroy(priv, mdev->priv.eq_table.num_comp_vectors);
4597         if_free(ifp);
4598         free(priv, M_MLX5EN);
4599 }
4600
4601 #ifdef DEBUGNET
4602 static void
4603 mlx5_en_debugnet_init(struct ifnet *dev, int *nrxr, int *ncl, int *clsize)
4604 {
4605         struct mlx5e_priv *priv = if_getsoftc(dev);
4606
4607         PRIV_LOCK(priv);
4608         *nrxr = priv->params.num_channels;
4609         *ncl = DEBUGNET_MAX_IN_FLIGHT;
4610         *clsize = MLX5E_MAX_RX_BYTES;
4611         PRIV_UNLOCK(priv);
4612 }
4613
4614 static void
4615 mlx5_en_debugnet_event(struct ifnet *dev, enum debugnet_ev event)
4616 {
4617 }
4618
4619 static int
4620 mlx5_en_debugnet_transmit(struct ifnet *dev, struct mbuf *m)
4621 {
4622         struct mlx5e_priv *priv = if_getsoftc(dev);
4623         struct mlx5e_sq *sq;
4624         int err;
4625
4626         if ((if_getdrvflags(dev) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
4627             IFF_DRV_RUNNING || (priv->media_status_last & IFM_ACTIVE) == 0)
4628                 return (ENOENT);
4629
4630         sq = &priv->channel[0].sq[0];
4631
4632         if (sq->running == 0) {
4633                 m_freem(m);
4634                 return (ENOENT);
4635         }
4636
4637         if (mlx5e_sq_xmit(sq, &m) != 0) {
4638                 m_freem(m);
4639                 err = ENOBUFS;
4640         } else {
4641                 err = 0;
4642         }
4643
4644         if (likely(sq->doorbell.d64 != 0)) {
4645                 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
4646                 sq->doorbell.d64 = 0;
4647         }
4648         return (err);
4649 }
4650
4651 static int
4652 mlx5_en_debugnet_poll(struct ifnet *dev, int count)
4653 {
4654         struct mlx5e_priv *priv = if_getsoftc(dev);
4655
4656         if ((if_getdrvflags(dev) & IFF_DRV_RUNNING) == 0 ||
4657             (priv->media_status_last & IFM_ACTIVE) == 0)
4658                 return (ENOENT);
4659
4660         mlx5_poll_interrupts(priv->mdev);
4661
4662         return (0);
4663 }
4664 #endif /* DEBUGNET */
4665
4666 static void *
4667 mlx5e_get_ifp(void *vpriv)
4668 {
4669         struct mlx5e_priv *priv = vpriv;
4670
4671         return (priv->ifp);
4672 }
4673
4674 static struct mlx5_interface mlx5e_interface = {
4675         .add = mlx5e_create_ifp,
4676         .remove = mlx5e_destroy_ifp,
4677         .event = mlx5e_async_event,
4678         .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4679         .get_dev = mlx5e_get_ifp,
4680 };
4681
4682 void
4683 mlx5e_init(void)
4684 {
4685         mlx5_register_interface(&mlx5e_interface);
4686 }
4687
4688 void
4689 mlx5e_cleanup(void)
4690 {
4691         mlx5_unregister_interface(&mlx5e_interface);
4692 }
4693
4694 static void
4695 mlx5e_show_version(void __unused *arg)
4696 {
4697
4698         printf("%s", mlx5e_version);
4699 }
4700 SYSINIT(mlx5e_show_version, SI_SUB_DRIVERS, SI_ORDER_ANY, mlx5e_show_version, NULL);
4701
4702 module_init_order(mlx5e_init, SI_ORDER_THIRD);
4703 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
4704
4705 #if (__FreeBSD_version >= 1100000)
4706 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
4707 #endif
4708 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
4709 MODULE_VERSION(mlx5en, 1);