2 * Copyright (c) 2015 Mellanox Technologies. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/sockio.h>
31 #include <machine/atomic.h>
33 #define ETH_DRIVER_VERSION "3.1.0-dev"
34 char mlx5e_version[] = "Mellanox Ethernet driver"
35 " (" ETH_DRIVER_VERSION ")";
37 struct mlx5e_rq_param {
38 u32 rqc [MLX5_ST_SZ_DW(rqc)];
39 struct mlx5_wq_param wq;
42 struct mlx5e_sq_param {
43 u32 sqc [MLX5_ST_SZ_DW(sqc)];
44 struct mlx5_wq_param wq;
47 struct mlx5e_cq_param {
48 u32 cqc [MLX5_ST_SZ_DW(cqc)];
49 struct mlx5_wq_param wq;
53 struct mlx5e_channel_param {
54 struct mlx5e_rq_param rq;
55 struct mlx5e_sq_param sq;
56 struct mlx5e_cq_param rx_cq;
57 struct mlx5e_cq_param tx_cq;
63 } mlx5e_mode_table[MLX5E_LINK_MODES_NUMBER] = {
65 [MLX5E_1000BASE_CX_SGMII] = {
66 .subtype = IFM_1000_CX_SGMII,
67 .baudrate = IF_Mbps(1000ULL),
69 [MLX5E_1000BASE_KX] = {
70 .subtype = IFM_1000_KX,
71 .baudrate = IF_Mbps(1000ULL),
73 [MLX5E_10GBASE_CX4] = {
74 .subtype = IFM_10G_CX4,
75 .baudrate = IF_Gbps(10ULL),
77 [MLX5E_10GBASE_KX4] = {
78 .subtype = IFM_10G_KX4,
79 .baudrate = IF_Gbps(10ULL),
81 [MLX5E_10GBASE_KR] = {
82 .subtype = IFM_10G_KR,
83 .baudrate = IF_Gbps(10ULL),
85 [MLX5E_20GBASE_KR2] = {
86 .subtype = IFM_20G_KR2,
87 .baudrate = IF_Gbps(20ULL),
89 [MLX5E_40GBASE_CR4] = {
90 .subtype = IFM_40G_CR4,
91 .baudrate = IF_Gbps(40ULL),
93 [MLX5E_40GBASE_KR4] = {
94 .subtype = IFM_40G_KR4,
95 .baudrate = IF_Gbps(40ULL),
97 [MLX5E_56GBASE_R4] = {
98 .subtype = IFM_56G_R4,
99 .baudrate = IF_Gbps(56ULL),
101 [MLX5E_10GBASE_CR] = {
102 .subtype = IFM_10G_CR1,
103 .baudrate = IF_Gbps(10ULL),
105 [MLX5E_10GBASE_SR] = {
106 .subtype = IFM_10G_SR,
107 .baudrate = IF_Gbps(10ULL),
109 [MLX5E_10GBASE_LR] = {
110 .subtype = IFM_10G_LR,
111 .baudrate = IF_Gbps(10ULL),
113 [MLX5E_40GBASE_SR4] = {
114 .subtype = IFM_40G_SR4,
115 .baudrate = IF_Gbps(40ULL),
117 [MLX5E_40GBASE_LR4] = {
118 .subtype = IFM_40G_LR4,
119 .baudrate = IF_Gbps(40ULL),
121 [MLX5E_100GBASE_CR4] = {
122 .subtype = IFM_100G_CR4,
123 .baudrate = IF_Gbps(100ULL),
125 [MLX5E_100GBASE_SR4] = {
126 .subtype = IFM_100G_SR4,
127 .baudrate = IF_Gbps(100ULL),
129 [MLX5E_100GBASE_KR4] = {
130 .subtype = IFM_100G_KR4,
131 .baudrate = IF_Gbps(100ULL),
133 [MLX5E_100GBASE_LR4] = {
134 .subtype = IFM_100G_LR4,
135 .baudrate = IF_Gbps(100ULL),
137 [MLX5E_100BASE_TX] = {
138 .subtype = IFM_100_TX,
139 .baudrate = IF_Mbps(100ULL),
141 [MLX5E_100BASE_T] = {
142 .subtype = IFM_100_T,
143 .baudrate = IF_Mbps(100ULL),
145 [MLX5E_10GBASE_T] = {
146 .subtype = IFM_10G_T,
147 .baudrate = IF_Gbps(10ULL),
149 [MLX5E_25GBASE_CR] = {
150 .subtype = IFM_25G_CR,
151 .baudrate = IF_Gbps(25ULL),
153 [MLX5E_25GBASE_KR] = {
154 .subtype = IFM_25G_KR,
155 .baudrate = IF_Gbps(25ULL),
157 [MLX5E_25GBASE_SR] = {
158 .subtype = IFM_25G_SR,
159 .baudrate = IF_Gbps(25ULL),
161 [MLX5E_50GBASE_CR2] = {
162 .subtype = IFM_50G_CR2,
163 .baudrate = IF_Gbps(50ULL),
165 [MLX5E_50GBASE_KR2] = {
166 .subtype = IFM_50G_KR2,
167 .baudrate = IF_Gbps(50ULL),
171 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
174 mlx5e_update_carrier(struct mlx5e_priv *priv)
176 struct mlx5_core_dev *mdev = priv->mdev;
177 u32 out[MLX5_ST_SZ_DW(ptys_reg)];
183 port_state = mlx5_query_vport_state(mdev,
184 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT);
186 if (port_state == VPORT_STATE_UP) {
187 priv->media_status_last |= IFM_ACTIVE;
189 priv->media_status_last &= ~IFM_ACTIVE;
190 priv->media_active_last = IFM_ETHER;
191 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
195 error = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN);
197 priv->media_active_last = IFM_ETHER;
198 priv->ifp->if_baudrate = 1;
199 if_printf(priv->ifp, "%s: query port ptys failed: 0x%x\n",
203 eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
205 for (i = 0; i != MLX5E_LINK_MODES_NUMBER; i++) {
206 if (mlx5e_mode_table[i].baudrate == 0)
208 if (MLX5E_PROT_MASK(i) & eth_proto_oper) {
209 priv->ifp->if_baudrate =
210 mlx5e_mode_table[i].baudrate;
211 priv->media_active_last =
212 mlx5e_mode_table[i].subtype | IFM_ETHER | IFM_FDX;
215 if_link_state_change(priv->ifp, LINK_STATE_UP);
219 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
221 struct mlx5e_priv *priv = dev->if_softc;
223 ifmr->ifm_status = priv->media_status_last;
224 ifmr->ifm_active = priv->media_active_last |
225 (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
226 (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
231 mlx5e_find_link_mode(u32 subtype)
236 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
237 if (mlx5e_mode_table[i].baudrate == 0)
239 if (mlx5e_mode_table[i].subtype == subtype)
240 link_mode |= MLX5E_PROT_MASK(i);
247 mlx5e_media_change(struct ifnet *dev)
249 struct mlx5e_priv *priv = dev->if_softc;
250 struct mlx5_core_dev *mdev = priv->mdev;
257 locked = PRIV_LOCKED(priv);
261 if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
265 link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media));
267 /* query supported capabilities */
268 error = mlx5_query_port_proto_cap(mdev, ð_proto_cap, MLX5_PTYS_EN);
270 if_printf(dev, "Query port media capability failed\n");
273 /* check for autoselect */
274 if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
275 link_mode = eth_proto_cap;
276 if (link_mode == 0) {
277 if_printf(dev, "Port media capability is zero\n");
282 link_mode = link_mode & eth_proto_cap;
283 if (link_mode == 0) {
284 if_printf(dev, "Not supported link mode requested\n");
289 /* update pauseframe control bits */
290 priv->params.rx_pauseframe_control =
291 (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
292 priv->params.tx_pauseframe_control =
293 (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
295 /* check if device is opened */
296 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
298 /* reconfigure the hardware */
299 mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
300 mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN);
301 mlx5_set_port_pause(mdev, 1,
302 priv->params.rx_pauseframe_control,
303 priv->params.tx_pauseframe_control);
305 mlx5_set_port_status(mdev, MLX5_PORT_UP);
314 mlx5e_update_carrier_work(struct work_struct *work)
316 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
317 update_carrier_work);
320 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
321 mlx5e_update_carrier(priv);
326 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
328 struct mlx5_core_dev *mdev = priv->mdev;
329 struct mlx5e_pport_stats *s = &priv->stats.pport;
330 struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
334 unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
338 in = mlx5_vzalloc(sz);
339 out = mlx5_vzalloc(sz);
340 if (in == NULL || out == NULL)
343 ptr = (uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
345 MLX5_SET(ppcnt_reg, in, local_port, 1);
347 MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
348 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
349 for (x = y = 0; x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
350 s->arg[y] = be64toh(ptr[x]);
352 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
353 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
354 for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
355 s->arg[y] = be64toh(ptr[x]);
356 for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
357 MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
358 s_debug->arg[y] = be64toh(ptr[x]);
360 MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
361 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
362 for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
363 s_debug->arg[y] = be64toh(ptr[x]);
365 MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
366 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
367 for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
368 s_debug->arg[y] = be64toh(ptr[x]);
375 mlx5e_update_stats_work(struct work_struct *work)
377 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
379 struct mlx5_core_dev *mdev = priv->mdev;
380 struct mlx5e_vport_stats *s = &priv->stats.vport;
381 struct mlx5e_rq_stats *rq_stats;
382 struct mlx5e_sq_stats *sq_stats;
383 struct buf_ring *sq_br;
384 #if (__FreeBSD_version < 1100000)
385 struct ifnet *ifp = priv->ifp;
388 u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
390 int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
393 u64 tx_queue_dropped = 0;
394 u64 tx_defragged = 0;
395 u64 tx_offload_none = 0;
398 u64 sw_lro_queued = 0;
399 u64 sw_lro_flushed = 0;
400 u64 rx_csum_none = 0;
402 u32 rx_out_of_buffer = 0;
407 out = mlx5_vzalloc(outlen);
410 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
413 /* Collect firts the SW counters and then HW for consistency */
414 for (i = 0; i < priv->params.num_channels; i++) {
415 struct mlx5e_rq *rq = &priv->channel[i]->rq;
417 rq_stats = &priv->channel[i]->rq.stats;
419 /* collect stats from LRO */
420 rq_stats->sw_lro_queued = rq->lro.lro_queued;
421 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
422 sw_lro_queued += rq_stats->sw_lro_queued;
423 sw_lro_flushed += rq_stats->sw_lro_flushed;
424 lro_packets += rq_stats->lro_packets;
425 lro_bytes += rq_stats->lro_bytes;
426 rx_csum_none += rq_stats->csum_none;
427 rx_wqe_err += rq_stats->wqe_err;
429 for (j = 0; j < priv->num_tc; j++) {
430 sq_stats = &priv->channel[i]->sq[j].stats;
431 sq_br = priv->channel[i]->sq[j].br;
433 tso_packets += sq_stats->tso_packets;
434 tso_bytes += sq_stats->tso_bytes;
435 tx_queue_dropped += sq_stats->dropped;
436 tx_queue_dropped += sq_br->br_drops;
437 tx_defragged += sq_stats->defragged;
438 tx_offload_none += sq_stats->csum_offload_none;
442 /* update counters */
443 s->tso_packets = tso_packets;
444 s->tso_bytes = tso_bytes;
445 s->tx_queue_dropped = tx_queue_dropped;
446 s->tx_defragged = tx_defragged;
447 s->lro_packets = lro_packets;
448 s->lro_bytes = lro_bytes;
449 s->sw_lro_queued = sw_lro_queued;
450 s->sw_lro_flushed = sw_lro_flushed;
451 s->rx_csum_none = rx_csum_none;
452 s->rx_wqe_err = rx_wqe_err;
455 memset(in, 0, sizeof(in));
457 MLX5_SET(query_vport_counter_in, in, opcode,
458 MLX5_CMD_OP_QUERY_VPORT_COUNTER);
459 MLX5_SET(query_vport_counter_in, in, op_mod, 0);
460 MLX5_SET(query_vport_counter_in, in, other_vport, 0);
462 memset(out, 0, outlen);
464 /* get number of out-of-buffer drops first */
465 if (mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
469 /* accumulate difference into a 64-bit counter */
470 s->rx_out_of_buffer += (u64)(u32)(rx_out_of_buffer - s->rx_out_of_buffer_prev);
471 s->rx_out_of_buffer_prev = rx_out_of_buffer;
473 /* get port statistics */
474 if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
477 #define MLX5_GET_CTR(out, x) \
478 MLX5_GET64(query_vport_counter_out, out, x)
480 s->rx_error_packets =
481 MLX5_GET_CTR(out, received_errors.packets);
483 MLX5_GET_CTR(out, received_errors.octets);
484 s->tx_error_packets =
485 MLX5_GET_CTR(out, transmit_errors.packets);
487 MLX5_GET_CTR(out, transmit_errors.octets);
489 s->rx_unicast_packets =
490 MLX5_GET_CTR(out, received_eth_unicast.packets);
491 s->rx_unicast_bytes =
492 MLX5_GET_CTR(out, received_eth_unicast.octets);
493 s->tx_unicast_packets =
494 MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
495 s->tx_unicast_bytes =
496 MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
498 s->rx_multicast_packets =
499 MLX5_GET_CTR(out, received_eth_multicast.packets);
500 s->rx_multicast_bytes =
501 MLX5_GET_CTR(out, received_eth_multicast.octets);
502 s->tx_multicast_packets =
503 MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
504 s->tx_multicast_bytes =
505 MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
507 s->rx_broadcast_packets =
508 MLX5_GET_CTR(out, received_eth_broadcast.packets);
509 s->rx_broadcast_bytes =
510 MLX5_GET_CTR(out, received_eth_broadcast.octets);
511 s->tx_broadcast_packets =
512 MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
513 s->tx_broadcast_bytes =
514 MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
517 s->rx_unicast_packets +
518 s->rx_multicast_packets +
519 s->rx_broadcast_packets -
522 s->rx_unicast_bytes +
523 s->rx_multicast_bytes +
524 s->rx_broadcast_bytes;
526 s->tx_unicast_packets +
527 s->tx_multicast_packets +
528 s->tx_broadcast_packets;
530 s->tx_unicast_bytes +
531 s->tx_multicast_bytes +
532 s->tx_broadcast_bytes;
534 /* Update calculated offload counters */
535 s->tx_csum_offload = s->tx_packets - tx_offload_none;
536 s->rx_csum_good = s->rx_packets - s->rx_csum_none;
538 /* Update per port counters */
539 mlx5e_update_pport_counters(priv);
541 #if (__FreeBSD_version < 1100000)
542 /* no get_counters interface in fbsd 10 */
543 ifp->if_ipackets = s->rx_packets;
544 ifp->if_ierrors = s->rx_error_packets;
545 ifp->if_iqdrops = s->rx_out_of_buffer;
546 ifp->if_opackets = s->tx_packets;
547 ifp->if_oerrors = s->tx_error_packets;
548 ifp->if_snd.ifq_drops = s->tx_queue_dropped;
549 ifp->if_ibytes = s->rx_bytes;
550 ifp->if_obytes = s->tx_bytes;
559 mlx5e_update_stats(void *arg)
561 struct mlx5e_priv *priv = arg;
563 schedule_work(&priv->update_stats_work);
565 callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
569 mlx5e_async_event_sub(struct mlx5e_priv *priv,
570 enum mlx5_dev_event event)
573 case MLX5_DEV_EVENT_PORT_UP:
574 case MLX5_DEV_EVENT_PORT_DOWN:
575 schedule_work(&priv->update_carrier_work);
584 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
585 enum mlx5_dev_event event, unsigned long param)
587 struct mlx5e_priv *priv = vpriv;
589 mtx_lock(&priv->async_events_mtx);
590 if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
591 mlx5e_async_event_sub(priv, event);
592 mtx_unlock(&priv->async_events_mtx);
596 mlx5e_enable_async_events(struct mlx5e_priv *priv)
598 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
602 mlx5e_disable_async_events(struct mlx5e_priv *priv)
604 mtx_lock(&priv->async_events_mtx);
605 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
606 mtx_unlock(&priv->async_events_mtx);
609 static const char *mlx5e_rq_stats_desc[] = {
610 MLX5E_RQ_STATS(MLX5E_STATS_DESC)
614 mlx5e_create_rq(struct mlx5e_channel *c,
615 struct mlx5e_rq_param *param,
618 struct mlx5e_priv *priv = c->priv;
619 struct mlx5_core_dev *mdev = priv->mdev;
621 void *rqc = param->rqc;
622 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
627 /* Create DMA descriptor TAG */
628 if ((err = -bus_dma_tag_create(
629 bus_get_dma_tag(mdev->pdev->dev.bsddev),
630 1, /* any alignment */
632 BUS_SPACE_MAXADDR, /* lowaddr */
633 BUS_SPACE_MAXADDR, /* highaddr */
634 NULL, NULL, /* filter, filterarg */
635 MJUM16BYTES, /* maxsize */
637 MJUM16BYTES, /* maxsegsize */
639 NULL, NULL, /* lockfunc, lockfuncarg */
643 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
646 goto err_free_dma_tag;
648 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
650 if (priv->params.hw_lro_en) {
651 rq->wqe_sz = priv->params.lro_wqe_sz;
653 rq->wqe_sz = MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
655 if (rq->wqe_sz > MJUM16BYTES) {
657 goto err_rq_wq_destroy;
658 } else if (rq->wqe_sz > MJUM9BYTES) {
659 rq->wqe_sz = MJUM16BYTES;
660 } else if (rq->wqe_sz > MJUMPAGESIZE) {
661 rq->wqe_sz = MJUM9BYTES;
662 } else if (rq->wqe_sz > MCLBYTES) {
663 rq->wqe_sz = MJUMPAGESIZE;
665 rq->wqe_sz = MCLBYTES;
668 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
669 rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
670 if (rq->mbuf == NULL) {
672 goto err_rq_wq_destroy;
674 for (i = 0; i != wq_sz; i++) {
675 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
676 uint32_t byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
678 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
681 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
682 goto err_rq_mbuf_free;
684 wqe->data.lkey = c->mkey_be;
685 wqe->data.byte_count = cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
693 snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
694 mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
695 buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
698 #ifdef HAVE_TURBO_LRO
699 if (tcp_tlro_init(&rq->lro, c->ifp, MLX5E_BUDGET_MAX) != 0)
702 if (tcp_lro_init(&rq->lro))
705 rq->lro.ifp = c->ifp;
710 free(rq->mbuf, M_MLX5EN);
712 mlx5_wq_destroy(&rq->wq_ctrl);
714 bus_dma_tag_destroy(rq->dma_tag);
720 mlx5e_destroy_rq(struct mlx5e_rq *rq)
725 /* destroy all sysctl nodes */
726 sysctl_ctx_free(&rq->stats.ctx);
728 /* free leftover LRO packets, if any */
729 #ifdef HAVE_TURBO_LRO
730 tcp_tlro_free(&rq->lro);
732 tcp_lro_free(&rq->lro);
734 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
735 for (i = 0; i != wq_sz; i++) {
736 if (rq->mbuf[i].mbuf != NULL) {
737 bus_dmamap_unload(rq->dma_tag,
738 rq->mbuf[i].dma_map);
739 m_freem(rq->mbuf[i].mbuf);
741 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
743 free(rq->mbuf, M_MLX5EN);
744 mlx5_wq_destroy(&rq->wq_ctrl);
748 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
750 struct mlx5e_channel *c = rq->channel;
751 struct mlx5e_priv *priv = c->priv;
752 struct mlx5_core_dev *mdev = priv->mdev;
760 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
761 sizeof(u64) * rq->wq_ctrl.buf.npages;
762 in = mlx5_vzalloc(inlen);
766 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
767 wq = MLX5_ADDR_OF(rqc, rqc, wq);
769 memcpy(rqc, param->rqc, sizeof(param->rqc));
771 MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
772 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
773 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
774 if (priv->counter_set_id >= 0)
775 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
776 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
778 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
780 mlx5_fill_page_array(&rq->wq_ctrl.buf,
781 (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
783 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
791 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
793 struct mlx5e_channel *c = rq->channel;
794 struct mlx5e_priv *priv = c->priv;
795 struct mlx5_core_dev *mdev = priv->mdev;
802 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
803 in = mlx5_vzalloc(inlen);
807 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
809 MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
810 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
811 MLX5_SET(rqc, rqc, state, next_state);
813 err = mlx5_core_modify_rq(mdev, in, inlen);
821 mlx5e_disable_rq(struct mlx5e_rq *rq)
823 struct mlx5e_channel *c = rq->channel;
824 struct mlx5e_priv *priv = c->priv;
825 struct mlx5_core_dev *mdev = priv->mdev;
827 mlx5_core_destroy_rq(mdev, rq->rqn);
831 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
833 struct mlx5e_channel *c = rq->channel;
834 struct mlx5e_priv *priv = c->priv;
835 struct mlx5_wq_ll *wq = &rq->wq;
838 for (i = 0; i < 1000; i++) {
839 if (wq->cur_sz >= priv->params.min_rx_wqes)
848 mlx5e_open_rq(struct mlx5e_channel *c,
849 struct mlx5e_rq_param *param,
854 err = mlx5e_create_rq(c, param, rq);
858 err = mlx5e_enable_rq(rq, param);
862 err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
871 mlx5e_disable_rq(rq);
873 mlx5e_destroy_rq(rq);
879 mlx5e_close_rq(struct mlx5e_rq *rq)
882 mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
886 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
888 /* wait till RQ is empty */
889 while (!mlx5_wq_ll_is_empty(&rq->wq)) {
891 rq->cq.mcq.comp(&rq->cq.mcq);
894 mlx5e_disable_rq(rq);
895 mlx5e_destroy_rq(rq);
899 mlx5e_free_sq_db(struct mlx5e_sq *sq)
901 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
904 for (x = 0; x != wq_sz; x++)
905 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
906 free(sq->mbuf, M_MLX5EN);
910 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
912 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
916 sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
917 if (sq->mbuf == NULL)
920 /* Create DMA descriptor MAPs */
921 for (x = 0; x != wq_sz; x++) {
922 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
925 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
926 free(sq->mbuf, M_MLX5EN);
933 static const char *mlx5e_sq_stats_desc[] = {
934 MLX5E_SQ_STATS(MLX5E_STATS_DESC)
938 mlx5e_create_sq(struct mlx5e_channel *c,
940 struct mlx5e_sq_param *param,
943 struct mlx5e_priv *priv = c->priv;
944 struct mlx5_core_dev *mdev = priv->mdev;
947 void *sqc = param->sqc;
948 void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
955 /* Create DMA descriptor TAG */
956 if ((err = -bus_dma_tag_create(
957 bus_get_dma_tag(mdev->pdev->dev.bsddev),
958 1, /* any alignment */
960 BUS_SPACE_MAXADDR, /* lowaddr */
961 BUS_SPACE_MAXADDR, /* highaddr */
962 NULL, NULL, /* filter, filterarg */
963 MLX5E_MAX_TX_PAYLOAD_SIZE, /* maxsize */
964 MLX5E_MAX_TX_MBUF_FRAGS, /* nsegments */
965 MLX5E_MAX_TX_MBUF_SIZE, /* maxsegsize */
967 NULL, NULL, /* lockfunc, lockfuncarg */
971 err = mlx5_alloc_map_uar(mdev, &sq->uar);
973 goto err_free_dma_tag;
975 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq,
978 goto err_unmap_free_uar;
980 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
981 sq->uar_map = sq->uar.map;
982 sq->uar_bf_map = sq->uar.bf_map;
983 sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
985 err = mlx5e_alloc_sq_db(sq);
987 goto err_sq_wq_destroy;
990 sq->mkey_be = c->mkey_be;
994 sq->br = buf_ring_alloc(MLX5E_SQ_TX_QUEUE_SIZE, M_MLX5EN,
995 M_WAITOK, &sq->lock);
996 if (sq->br == NULL) {
997 if_printf(c->ifp, "%s: Failed allocating sq drbr buffer\n",
1000 goto err_free_sq_db;
1003 sq->sq_tq = taskqueue_create_fast("mlx5e_que", M_WAITOK,
1004 taskqueue_thread_enqueue, &sq->sq_tq);
1005 if (sq->sq_tq == NULL) {
1006 if_printf(c->ifp, "%s: Failed allocating taskqueue\n",
1012 TASK_INIT(&sq->sq_task, 0, mlx5e_tx_que, sq);
1014 cpu_id = rss_getcpu(c->ix % rss_getnumbuckets());
1015 CPU_SETOF(cpu_id, &cpu_mask);
1016 taskqueue_start_threads_cpuset(&sq->sq_tq, 1, PI_NET, &cpu_mask,
1017 "%s TX SQ%d.%d CPU%d", c->ifp->if_xname, c->ix, tc, cpu_id);
1019 taskqueue_start_threads(&sq->sq_tq, 1, PI_NET,
1020 "%s TX SQ%d.%d", c->ifp->if_xname, c->ix, tc);
1022 snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1023 mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1024 buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1030 buf_ring_free(sq->br, M_MLX5EN);
1032 mlx5e_free_sq_db(sq);
1034 mlx5_wq_destroy(&sq->wq_ctrl);
1037 mlx5_unmap_free_uar(mdev, &sq->uar);
1040 bus_dma_tag_destroy(sq->dma_tag);
1046 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1048 struct mlx5e_channel *c = sq->channel;
1049 struct mlx5e_priv *priv = c->priv;
1051 /* destroy all sysctl nodes */
1052 sysctl_ctx_free(&sq->stats.ctx);
1054 mlx5e_free_sq_db(sq);
1055 mlx5_wq_destroy(&sq->wq_ctrl);
1056 mlx5_unmap_free_uar(priv->mdev, &sq->uar);
1057 taskqueue_drain(sq->sq_tq, &sq->sq_task);
1058 taskqueue_free(sq->sq_tq);
1059 buf_ring_free(sq->br, M_MLX5EN);
1063 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param)
1065 struct mlx5e_channel *c = sq->channel;
1066 struct mlx5e_priv *priv = c->priv;
1067 struct mlx5_core_dev *mdev = priv->mdev;
1075 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1076 sizeof(u64) * sq->wq_ctrl.buf.npages;
1077 in = mlx5_vzalloc(inlen);
1081 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1082 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1084 memcpy(sqc, param->sqc, sizeof(param->sqc));
1086 MLX5_SET(sqc, sqc, tis_num_0, priv->tisn[sq->tc]);
1087 MLX5_SET(sqc, sqc, cqn, c->sq[sq->tc].cq.mcq.cqn);
1088 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1089 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1090 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1092 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1093 MLX5_SET(wq, wq, uar_page, sq->uar.index);
1094 MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1096 MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1098 mlx5_fill_page_array(&sq->wq_ctrl.buf,
1099 (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1101 err = mlx5_core_create_sq(mdev, in, inlen, &sq->sqn);
1109 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1111 struct mlx5e_channel *c = sq->channel;
1112 struct mlx5e_priv *priv = c->priv;
1113 struct mlx5_core_dev *mdev = priv->mdev;
1120 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1121 in = mlx5_vzalloc(inlen);
1125 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1127 MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1128 MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1129 MLX5_SET(sqc, sqc, state, next_state);
1131 err = mlx5_core_modify_sq(mdev, in, inlen);
1139 mlx5e_disable_sq(struct mlx5e_sq *sq)
1141 struct mlx5e_channel *c = sq->channel;
1142 struct mlx5e_priv *priv = c->priv;
1143 struct mlx5_core_dev *mdev = priv->mdev;
1145 mlx5_core_destroy_sq(mdev, sq->sqn);
1149 mlx5e_open_sq(struct mlx5e_channel *c,
1151 struct mlx5e_sq_param *param,
1152 struct mlx5e_sq *sq)
1156 err = mlx5e_create_sq(c, tc, param, sq);
1160 err = mlx5e_enable_sq(sq, param);
1162 goto err_destroy_sq;
1164 err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1166 goto err_disable_sq;
1168 atomic_store_rel_int(&sq->queue_state, MLX5E_SQ_READY);
1173 mlx5e_disable_sq(sq);
1175 mlx5e_destroy_sq(sq);
1181 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1183 /* fill up remainder with NOPs */
1184 while (sq->cev_counter != 0) {
1185 while (!mlx5e_sq_has_room_for(sq, 1)) {
1186 if (can_sleep != 0) {
1187 mtx_unlock(&sq->lock);
1189 mtx_lock(&sq->lock);
1194 /* send a single NOP */
1195 mlx5e_send_nop(sq, 1);
1199 /* Check if we need to write the doorbell */
1200 if (likely(sq->doorbell.d64 != 0)) {
1201 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1202 sq->doorbell.d64 = 0;
1208 mlx5e_sq_cev_timeout(void *arg)
1210 struct mlx5e_sq *sq = arg;
1212 mtx_assert(&sq->lock, MA_OWNED);
1214 /* check next state */
1215 switch (sq->cev_next_state) {
1216 case MLX5E_CEV_STATE_SEND_NOPS:
1217 /* fill TX ring with NOPs, if any */
1218 mlx5e_sq_send_nops_locked(sq, 0);
1220 /* check if completed */
1221 if (sq->cev_counter == 0) {
1222 sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1227 /* send NOPs on next timeout */
1228 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1233 callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1237 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1240 mtx_lock(&sq->lock);
1241 /* teardown event factor timer, if any */
1242 sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1243 callout_stop(&sq->cev_callout);
1245 /* send dummy NOPs in order to flush the transmit ring */
1246 mlx5e_sq_send_nops_locked(sq, 1);
1247 mtx_unlock(&sq->lock);
1249 /* make sure it is safe to free the callout */
1250 callout_drain(&sq->cev_callout);
1252 /* error out remaining requests */
1253 mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1255 /* wait till SQ is empty */
1256 mtx_lock(&sq->lock);
1257 while (sq->cc != sq->pc) {
1258 mtx_unlock(&sq->lock);
1260 sq->cq.mcq.comp(&sq->cq.mcq);
1261 mtx_lock(&sq->lock);
1263 mtx_unlock(&sq->lock);
1265 mlx5e_disable_sq(sq);
1266 mlx5e_destroy_sq(sq);
1270 mlx5e_create_cq(struct mlx5e_channel *c,
1271 struct mlx5e_cq_param *param,
1272 struct mlx5e_cq *cq,
1273 mlx5e_cq_comp_t *comp)
1275 struct mlx5e_priv *priv = c->priv;
1276 struct mlx5_core_dev *mdev = priv->mdev;
1277 struct mlx5_core_cq *mcq = &cq->mcq;
1283 param->wq.buf_numa_node = 0;
1284 param->wq.db_numa_node = 0;
1285 param->eq_ix = c->ix;
1287 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1292 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1295 mcq->set_ci_db = cq->wq_ctrl.db.db;
1296 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1297 *mcq->set_ci_db = 0;
1299 mcq->vector = param->eq_ix;
1301 mcq->event = mlx5e_cq_error_event;
1303 mcq->uar = &priv->cq_uar;
1305 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1306 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1317 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1319 mlx5_wq_destroy(&cq->wq_ctrl);
1323 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param,
1326 struct mlx5e_channel *c = cq->channel;
1327 struct mlx5e_priv *priv = c->priv;
1328 struct mlx5_core_dev *mdev = priv->mdev;
1329 struct mlx5_core_cq *mcq = &cq->mcq;
1337 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1338 sizeof(u64) * cq->wq_ctrl.buf.npages;
1339 in = mlx5_vzalloc(inlen);
1343 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1345 memcpy(cqc, param->cqc, sizeof(param->cqc));
1347 mlx5_fill_page_array(&cq->wq_ctrl.buf,
1348 (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1350 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1352 MLX5_SET(cqc, cqc, cq_period_mode, moderation_mode);
1353 MLX5_SET(cqc, cqc, c_eqn, eqn);
1354 MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1355 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1357 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1359 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1372 mlx5e_disable_cq(struct mlx5e_cq *cq)
1374 struct mlx5e_channel *c = cq->channel;
1375 struct mlx5e_priv *priv = c->priv;
1376 struct mlx5_core_dev *mdev = priv->mdev;
1378 mlx5_core_destroy_cq(mdev, &cq->mcq);
1382 mlx5e_open_cq(struct mlx5e_channel *c,
1383 struct mlx5e_cq_param *param,
1384 struct mlx5e_cq *cq,
1385 mlx5e_cq_comp_t *comp,
1390 err = mlx5e_create_cq(c, param, cq, comp);
1394 err = mlx5e_enable_cq(cq, param, moderation_mode);
1396 goto err_destroy_cq;
1401 mlx5e_destroy_cq(cq);
1407 mlx5e_close_cq(struct mlx5e_cq *cq)
1409 mlx5e_disable_cq(cq);
1410 mlx5e_destroy_cq(cq);
1414 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1415 struct mlx5e_channel_param *cparam)
1417 u8 tx_moderation_mode;
1421 switch (c->priv->params.tx_cq_moderation_mode) {
1423 tx_moderation_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1426 if (MLX5_CAP_GEN(c->priv->mdev, cq_period_start_from_cqe))
1427 tx_moderation_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
1429 tx_moderation_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1432 for (tc = 0; tc < c->num_tc; tc++) {
1433 /* open completion queue */
1434 err = mlx5e_open_cq(c, &cparam->tx_cq, &c->sq[tc].cq,
1435 &mlx5e_tx_cq_comp, tx_moderation_mode);
1437 goto err_close_tx_cqs;
1442 for (tc--; tc >= 0; tc--)
1443 mlx5e_close_cq(&c->sq[tc].cq);
1449 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1453 for (tc = 0; tc < c->num_tc; tc++)
1454 mlx5e_close_cq(&c->sq[tc].cq);
1458 mlx5e_open_sqs(struct mlx5e_channel *c,
1459 struct mlx5e_channel_param *cparam)
1464 for (tc = 0; tc < c->num_tc; tc++) {
1465 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1473 for (tc--; tc >= 0; tc--)
1474 mlx5e_close_sq_wait(&c->sq[tc]);
1480 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
1484 for (tc = 0; tc < c->num_tc; tc++)
1485 mlx5e_close_sq_wait(&c->sq[tc]);
1489 mlx5e_chan_mtx_init(struct mlx5e_channel *c)
1493 mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
1495 for (tc = 0; tc < c->num_tc; tc++) {
1496 struct mlx5e_sq *sq = c->sq + tc;
1498 mtx_init(&sq->lock, "mlx5tx", MTX_NETWORK_LOCK, MTX_DEF);
1499 mtx_init(&sq->comp_lock, "mlx5comp", MTX_NETWORK_LOCK,
1502 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
1504 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1506 /* ensure the TX completion event factor is not zero */
1507 if (sq->cev_factor == 0)
1513 mlx5e_chan_mtx_destroy(struct mlx5e_channel *c)
1517 mtx_destroy(&c->rq.mtx);
1519 for (tc = 0; tc < c->num_tc; tc++) {
1520 mtx_destroy(&c->sq[tc].lock);
1521 mtx_destroy(&c->sq[tc].comp_lock);
1526 mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1527 struct mlx5e_channel_param *cparam,
1528 struct mlx5e_channel *volatile *cp)
1530 struct mlx5e_channel *c;
1531 u8 rx_moderation_mode;
1534 c = malloc(sizeof(*c), M_MLX5EN, M_WAITOK | M_ZERO);
1541 c->pdev = &priv->mdev->pdev->dev;
1543 c->mkey_be = cpu_to_be32(priv->mr.key);
1544 c->num_tc = priv->num_tc;
1547 mlx5e_chan_mtx_init(c);
1549 /* open transmit completion queue */
1550 err = mlx5e_open_tx_cqs(c, cparam);
1554 switch (priv->params.rx_cq_moderation_mode) {
1556 rx_moderation_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1559 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1560 rx_moderation_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
1562 rx_moderation_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1566 /* open receive completion queue */
1567 err = mlx5e_open_cq(c, &cparam->rx_cq, &c->rq.cq,
1568 &mlx5e_rx_cq_comp, rx_moderation_mode);
1570 goto err_close_tx_cqs;
1572 err = mlx5e_open_sqs(c, cparam);
1574 goto err_close_rx_cq;
1576 err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1580 /* store channel pointer */
1583 /* poll receive queue initially */
1584 c->rq.cq.mcq.comp(&c->rq.cq.mcq);
1589 mlx5e_close_sqs_wait(c);
1592 mlx5e_close_cq(&c->rq.cq);
1595 mlx5e_close_tx_cqs(c);
1598 /* destroy mutexes */
1599 mlx5e_chan_mtx_destroy(c);
1605 mlx5e_close_channel(struct mlx5e_channel *volatile *pp)
1607 struct mlx5e_channel *c = *pp;
1609 /* check if channel is already closed */
1612 mlx5e_close_rq(&c->rq);
1616 mlx5e_close_channel_wait(struct mlx5e_channel *volatile *pp)
1618 struct mlx5e_channel *c = *pp;
1620 /* check if channel is already closed */
1623 /* ensure channel pointer is no longer used */
1626 mlx5e_close_rq_wait(&c->rq);
1627 mlx5e_close_sqs_wait(c);
1628 mlx5e_close_cq(&c->rq.cq);
1629 mlx5e_close_tx_cqs(c);
1630 /* destroy mutexes */
1631 mlx5e_chan_mtx_destroy(c);
1636 mlx5e_build_rq_param(struct mlx5e_priv *priv,
1637 struct mlx5e_rq_param *param)
1639 void *rqc = param->rqc;
1640 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1642 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1643 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1644 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1645 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1646 MLX5_SET(wq, wq, pd, priv->pdn);
1648 param->wq.buf_numa_node = 0;
1649 param->wq.db_numa_node = 0;
1650 param->wq.linear = 1;
1654 mlx5e_build_sq_param(struct mlx5e_priv *priv,
1655 struct mlx5e_sq_param *param)
1657 void *sqc = param->sqc;
1658 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1660 MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1661 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1662 MLX5_SET(wq, wq, pd, priv->pdn);
1664 param->wq.buf_numa_node = 0;
1665 param->wq.db_numa_node = 0;
1666 param->wq.linear = 1;
1670 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1671 struct mlx5e_cq_param *param)
1673 void *cqc = param->cqc;
1675 MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1679 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1680 struct mlx5e_cq_param *param)
1682 void *cqc = param->cqc;
1686 * TODO The sysctl to control on/off is a bool value for now, which means
1687 * we only support CSUM, once HASH is implemnted we'll need to address that.
1689 if (priv->params.cqe_zipping_en) {
1690 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1691 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
1694 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1695 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1696 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1698 mlx5e_build_common_cq_param(priv, param);
1702 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1703 struct mlx5e_cq_param *param)
1705 void *cqc = param->cqc;
1707 MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1708 MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
1709 MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
1711 mlx5e_build_common_cq_param(priv, param);
1715 mlx5e_build_channel_param(struct mlx5e_priv *priv,
1716 struct mlx5e_channel_param *cparam)
1718 memset(cparam, 0, sizeof(*cparam));
1720 mlx5e_build_rq_param(priv, &cparam->rq);
1721 mlx5e_build_sq_param(priv, &cparam->sq);
1722 mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1723 mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1727 mlx5e_open_channels(struct mlx5e_priv *priv)
1729 struct mlx5e_channel_param cparam;
1735 priv->channel = malloc(priv->params.num_channels *
1736 sizeof(struct mlx5e_channel *), M_MLX5EN, M_WAITOK | M_ZERO);
1737 if (priv->channel == NULL)
1740 mlx5e_build_channel_param(priv, &cparam);
1741 for (i = 0; i < priv->params.num_channels; i++) {
1742 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1744 goto err_close_channels;
1747 for (j = 0; j < priv->params.num_channels; j++) {
1748 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j]->rq);
1750 goto err_close_channels;
1756 for (i--; i >= 0; i--) {
1757 mlx5e_close_channel(&priv->channel[i]);
1758 mlx5e_close_channel_wait(&priv->channel[i]);
1761 /* remove "volatile" attribute from "channel" pointer */
1762 ptr = __DECONST(void *, priv->channel);
1763 priv->channel = NULL;
1765 free(ptr, M_MLX5EN);
1771 mlx5e_close_channels(struct mlx5e_priv *priv)
1776 if (priv->channel == NULL)
1779 for (i = 0; i < priv->params.num_channels; i++)
1780 mlx5e_close_channel(&priv->channel[i]);
1781 for (i = 0; i < priv->params.num_channels; i++)
1782 mlx5e_close_channel_wait(&priv->channel[i]);
1784 /* remove "volatile" attribute from "channel" pointer */
1785 ptr = __DECONST(void *, priv->channel);
1786 priv->channel = NULL;
1788 free(ptr, M_MLX5EN);
1792 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
1794 return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
1795 priv->params.tx_cq_moderation_usec,
1796 priv->params.tx_cq_moderation_pkts));
1800 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
1802 return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
1803 priv->params.rx_cq_moderation_usec,
1804 priv->params.rx_cq_moderation_pkts));
1808 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1816 err = mlx5e_refresh_rq_params(priv, &c->rq);
1820 for (i = 0; i != c->num_tc; i++) {
1821 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
1830 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
1834 if (priv->channel == NULL)
1837 for (i = 0; i < priv->params.num_channels; i++) {
1840 err = mlx5e_refresh_channel_params_sub(priv, priv->channel[i]);
1848 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
1850 struct mlx5_core_dev *mdev = priv->mdev;
1851 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1852 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1854 memset(in, 0, sizeof(in));
1856 MLX5_SET(tisc, tisc, prio, tc);
1857 MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
1859 return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
1863 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
1865 mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
1869 mlx5e_open_tises(struct mlx5e_priv *priv)
1871 int num_tc = priv->num_tc;
1875 for (tc = 0; tc < num_tc; tc++) {
1876 err = mlx5e_open_tis(priv, tc);
1878 goto err_close_tises;
1884 for (tc--; tc >= 0; tc--)
1885 mlx5e_close_tis(priv, tc);
1891 mlx5e_close_tises(struct mlx5e_priv *priv)
1893 int num_tc = priv->num_tc;
1896 for (tc = 0; tc < num_tc; tc++)
1897 mlx5e_close_tis(priv, tc);
1901 mlx5e_open_rqt(struct mlx5e_priv *priv)
1903 struct mlx5_core_dev *mdev = priv->mdev;
1905 u32 out[MLX5_ST_SZ_DW(create_rqt_out)];
1912 sz = 1 << priv->params.rx_hash_log_tbl_sz;
1914 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
1915 in = mlx5_vzalloc(inlen);
1918 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
1920 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
1921 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
1923 for (i = 0; i < sz; i++) {
1926 ix = rss_get_indirection_to_bucket(i);
1930 /* ensure we don't overflow */
1931 ix %= priv->params.num_channels;
1932 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix]->rq.rqn);
1935 MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
1937 memset(out, 0, sizeof(out));
1938 err = mlx5_cmd_exec_check_status(mdev, in, inlen, out, sizeof(out));
1940 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
1948 mlx5e_close_rqt(struct mlx5e_priv *priv)
1950 u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)];
1951 u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)];
1953 memset(in, 0, sizeof(in));
1955 MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
1956 MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
1958 mlx5_cmd_exec_check_status(priv->mdev, in, sizeof(in), out,
1963 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
1965 void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1968 MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
1970 #define ROUGH_MAX_L2_L3_HDR_SZ 256
1972 #define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
1973 MLX5_HASH_FIELD_SEL_DST_IP)
1975 #define MLX5_HASH_ALL (MLX5_HASH_FIELD_SEL_SRC_IP |\
1976 MLX5_HASH_FIELD_SEL_DST_IP |\
1977 MLX5_HASH_FIELD_SEL_L4_SPORT |\
1978 MLX5_HASH_FIELD_SEL_L4_DPORT)
1980 #define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
1981 MLX5_HASH_FIELD_SEL_DST_IP |\
1982 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
1984 if (priv->params.hw_lro_en) {
1985 MLX5_SET(tirc, tirc, lro_enable_mask,
1986 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
1987 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
1988 MLX5_SET(tirc, tirc, lro_max_msg_sz,
1989 (priv->params.lro_wqe_sz -
1990 ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
1991 /* TODO: add the option to choose timer value dynamically */
1992 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
1993 MLX5_CAP_ETH(priv->mdev,
1994 lro_timer_supported_periods[2]));
1997 /* setup parameters for hashing TIR type, if any */
2000 MLX5_SET(tirc, tirc, disp_type,
2001 MLX5_TIRC_DISP_TYPE_DIRECT);
2002 MLX5_SET(tirc, tirc, inline_rqn,
2003 priv->channel[0]->rq.rqn);
2006 MLX5_SET(tirc, tirc, disp_type,
2007 MLX5_TIRC_DISP_TYPE_INDIRECT);
2008 MLX5_SET(tirc, tirc, indirect_table,
2010 MLX5_SET(tirc, tirc, rx_hash_fn,
2011 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
2012 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
2015 * The FreeBSD RSS implementation does currently not
2016 * support symmetric Toeplitz hashes:
2018 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
2019 rss_getkey((uint8_t *)hkey);
2021 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2022 hkey[0] = cpu_to_be32(0xD181C62C);
2023 hkey[1] = cpu_to_be32(0xF7F4DB5B);
2024 hkey[2] = cpu_to_be32(0x1983A2FC);
2025 hkey[3] = cpu_to_be32(0x943E1ADB);
2026 hkey[4] = cpu_to_be32(0xD9389E6B);
2027 hkey[5] = cpu_to_be32(0xD1039C2C);
2028 hkey[6] = cpu_to_be32(0xA74499AD);
2029 hkey[7] = cpu_to_be32(0x593D56D9);
2030 hkey[8] = cpu_to_be32(0xF3253C06);
2031 hkey[9] = cpu_to_be32(0x2ADC1FFC);
2037 case MLX5E_TT_IPV4_TCP:
2038 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2039 MLX5_L3_PROT_TYPE_IPV4);
2040 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2041 MLX5_L4_PROT_TYPE_TCP);
2043 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2044 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2048 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2052 case MLX5E_TT_IPV6_TCP:
2053 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2054 MLX5_L3_PROT_TYPE_IPV6);
2055 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2056 MLX5_L4_PROT_TYPE_TCP);
2058 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2059 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2063 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2067 case MLX5E_TT_IPV4_UDP:
2068 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2069 MLX5_L3_PROT_TYPE_IPV4);
2070 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2071 MLX5_L4_PROT_TYPE_UDP);
2073 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2074 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2078 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2082 case MLX5E_TT_IPV6_UDP:
2083 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2084 MLX5_L3_PROT_TYPE_IPV6);
2085 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2086 MLX5_L4_PROT_TYPE_UDP);
2088 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2089 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2093 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2097 case MLX5E_TT_IPV4_IPSEC_AH:
2098 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2099 MLX5_L3_PROT_TYPE_IPV4);
2100 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2101 MLX5_HASH_IP_IPSEC_SPI);
2104 case MLX5E_TT_IPV6_IPSEC_AH:
2105 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2106 MLX5_L3_PROT_TYPE_IPV6);
2107 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2108 MLX5_HASH_IP_IPSEC_SPI);
2111 case MLX5E_TT_IPV4_IPSEC_ESP:
2112 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2113 MLX5_L3_PROT_TYPE_IPV4);
2114 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2115 MLX5_HASH_IP_IPSEC_SPI);
2118 case MLX5E_TT_IPV6_IPSEC_ESP:
2119 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2120 MLX5_L3_PROT_TYPE_IPV6);
2121 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2122 MLX5_HASH_IP_IPSEC_SPI);
2126 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2127 MLX5_L3_PROT_TYPE_IPV4);
2128 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2133 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2134 MLX5_L3_PROT_TYPE_IPV6);
2135 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2145 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2147 struct mlx5_core_dev *mdev = priv->mdev;
2153 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2154 in = mlx5_vzalloc(inlen);
2157 tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2159 mlx5e_build_tir_ctx(priv, tirc, tt);
2161 err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2169 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2171 mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2175 mlx5e_open_tirs(struct mlx5e_priv *priv)
2180 for (i = 0; i < MLX5E_NUM_TT; i++) {
2181 err = mlx5e_open_tir(priv, i);
2183 goto err_close_tirs;
2189 for (i--; i >= 0; i--)
2190 mlx5e_close_tir(priv, i);
2196 mlx5e_close_tirs(struct mlx5e_priv *priv)
2200 for (i = 0; i < MLX5E_NUM_TT; i++)
2201 mlx5e_close_tir(priv, i);
2205 * SW MTU does not include headers,
2206 * HW MTU includes all headers and checksums.
2209 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2211 struct mlx5e_priv *priv = ifp->if_softc;
2212 struct mlx5_core_dev *mdev = priv->mdev;
2217 err = mlx5_set_port_mtu(mdev, MLX5E_SW2HW_MTU(sw_mtu));
2219 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n",
2220 __func__, sw_mtu, err);
2223 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2225 ifp->if_mtu = MLX5E_HW2SW_MTU(hw_mtu);
2227 if (ifp->if_mtu != sw_mtu) {
2228 if_printf(ifp, "Port MTU %d is different than "
2229 "ifp mtu %d\n", sw_mtu, (int)ifp->if_mtu);
2232 if_printf(ifp, "Query port MTU, after setting new "
2233 "MTU value, failed\n");
2234 ifp->if_mtu = sw_mtu;
2240 mlx5e_open_locked(struct ifnet *ifp)
2242 struct mlx5e_priv *priv = ifp->if_softc;
2245 /* check if already opened */
2246 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2250 if (rss_getnumbuckets() > priv->params.num_channels) {
2251 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than "
2252 "channels(%u) available\n", rss_getnumbuckets(),
2253 priv->params.num_channels);
2256 err = mlx5e_open_tises(priv);
2258 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n",
2262 err = mlx5_vport_alloc_q_counter(priv->mdev, &priv->counter_set_id);
2264 if_printf(priv->ifp,
2265 "%s: mlx5_vport_alloc_q_counter failed: %d\n",
2267 goto err_close_tises;
2269 err = mlx5e_open_channels(priv);
2271 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n",
2273 goto err_dalloc_q_counter;
2275 err = mlx5e_open_rqt(priv);
2277 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n",
2279 goto err_close_channels;
2281 err = mlx5e_open_tirs(priv);
2283 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n",
2285 goto err_close_rqls;
2287 err = mlx5e_open_flow_table(priv);
2289 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n",
2291 goto err_close_tirs;
2293 err = mlx5e_add_all_vlan_rules(priv);
2295 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
2297 goto err_close_flow_table;
2299 set_bit(MLX5E_STATE_OPENED, &priv->state);
2301 mlx5e_update_carrier(priv);
2302 mlx5e_set_rx_mode_core(priv);
2306 err_close_flow_table:
2307 mlx5e_close_flow_table(priv);
2310 mlx5e_close_tirs(priv);
2313 mlx5e_close_rqt(priv);
2316 mlx5e_close_channels(priv);
2318 err_dalloc_q_counter:
2319 mlx5_vport_dealloc_q_counter(priv->mdev, priv->counter_set_id);
2322 mlx5e_close_tises(priv);
2328 mlx5e_open(void *arg)
2330 struct mlx5e_priv *priv = arg;
2333 if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
2334 if_printf(priv->ifp,
2335 "%s: Setting port status to up failed\n",
2338 mlx5e_open_locked(priv->ifp);
2339 priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
2344 mlx5e_close_locked(struct ifnet *ifp)
2346 struct mlx5e_priv *priv = ifp->if_softc;
2348 /* check if already closed */
2349 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2352 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2354 mlx5e_set_rx_mode_core(priv);
2355 mlx5e_del_all_vlan_rules(priv);
2356 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
2357 mlx5e_close_flow_table(priv);
2358 mlx5e_close_tirs(priv);
2359 mlx5e_close_rqt(priv);
2360 mlx5e_close_channels(priv);
2361 mlx5_vport_dealloc_q_counter(priv->mdev, priv->counter_set_id);
2362 mlx5e_close_tises(priv);
2367 #if (__FreeBSD_version >= 1100000)
2369 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
2371 struct mlx5e_priv *priv = ifp->if_softc;
2374 /* PRIV_LOCK(priv); XXX not allowed */
2376 case IFCOUNTER_IPACKETS:
2377 retval = priv->stats.vport.rx_packets;
2379 case IFCOUNTER_IERRORS:
2380 retval = priv->stats.vport.rx_error_packets;
2382 case IFCOUNTER_IQDROPS:
2383 retval = priv->stats.vport.rx_out_of_buffer;
2385 case IFCOUNTER_OPACKETS:
2386 retval = priv->stats.vport.tx_packets;
2388 case IFCOUNTER_OERRORS:
2389 retval = priv->stats.vport.tx_error_packets;
2391 case IFCOUNTER_IBYTES:
2392 retval = priv->stats.vport.rx_bytes;
2394 case IFCOUNTER_OBYTES:
2395 retval = priv->stats.vport.tx_bytes;
2397 case IFCOUNTER_IMCASTS:
2398 retval = priv->stats.vport.rx_multicast_packets;
2400 case IFCOUNTER_OMCASTS:
2401 retval = priv->stats.vport.tx_multicast_packets;
2403 case IFCOUNTER_OQDROPS:
2404 retval = priv->stats.vport.tx_queue_dropped;
2407 retval = if_get_counter_default(ifp, cnt);
2410 /* PRIV_UNLOCK(priv); XXX not allowed */
2416 mlx5e_set_rx_mode(struct ifnet *ifp)
2418 struct mlx5e_priv *priv = ifp->if_softc;
2420 schedule_work(&priv->set_rx_mode_work);
2424 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2426 struct mlx5e_priv *priv;
2428 struct ifi2creq i2c;
2436 priv = ifp->if_softc;
2438 /* check if detaching */
2439 if (priv == NULL || priv->gone != 0)
2444 ifr = (struct ifreq *)data;
2447 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
2449 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
2450 ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
2453 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2455 mlx5e_close_locked(ifp);
2458 mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
2461 mlx5e_open_locked(ifp);
2464 if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n",
2465 MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
2470 if ((ifp->if_flags & IFF_UP) &&
2471 (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2472 mlx5e_set_rx_mode(ifp);
2476 if (ifp->if_flags & IFF_UP) {
2477 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2478 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2479 mlx5e_open_locked(ifp);
2480 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2481 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
2484 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2485 mlx5_set_port_status(priv->mdev,
2487 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2488 mlx5e_close_locked(ifp);
2489 mlx5e_update_carrier(priv);
2490 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2497 mlx5e_set_rx_mode(ifp);
2502 ifr = (struct ifreq *)data;
2503 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
2506 ifr = (struct ifreq *)data;
2508 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2510 if (mask & IFCAP_TXCSUM) {
2511 ifp->if_capenable ^= IFCAP_TXCSUM;
2512 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2514 if (IFCAP_TSO4 & ifp->if_capenable &&
2515 !(IFCAP_TXCSUM & ifp->if_capenable)) {
2516 ifp->if_capenable &= ~IFCAP_TSO4;
2517 ifp->if_hwassist &= ~CSUM_IP_TSO;
2519 "tso4 disabled due to -txcsum.\n");
2522 if (mask & IFCAP_TXCSUM_IPV6) {
2523 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
2524 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2526 if (IFCAP_TSO6 & ifp->if_capenable &&
2527 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2528 ifp->if_capenable &= ~IFCAP_TSO6;
2529 ifp->if_hwassist &= ~CSUM_IP6_TSO;
2531 "tso6 disabled due to -txcsum6.\n");
2534 if (mask & IFCAP_RXCSUM)
2535 ifp->if_capenable ^= IFCAP_RXCSUM;
2536 if (mask & IFCAP_RXCSUM_IPV6)
2537 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
2538 if (mask & IFCAP_TSO4) {
2539 if (!(IFCAP_TSO4 & ifp->if_capenable) &&
2540 !(IFCAP_TXCSUM & ifp->if_capenable)) {
2541 if_printf(ifp, "enable txcsum first.\n");
2545 ifp->if_capenable ^= IFCAP_TSO4;
2546 ifp->if_hwassist ^= CSUM_IP_TSO;
2548 if (mask & IFCAP_TSO6) {
2549 if (!(IFCAP_TSO6 & ifp->if_capenable) &&
2550 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2551 if_printf(ifp, "enable txcsum6 first.\n");
2555 ifp->if_capenable ^= IFCAP_TSO6;
2556 ifp->if_hwassist ^= CSUM_IP6_TSO;
2558 if (mask & IFCAP_VLAN_HWFILTER) {
2559 if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
2560 mlx5e_disable_vlan_filter(priv);
2562 mlx5e_enable_vlan_filter(priv);
2564 ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
2566 if (mask & IFCAP_VLAN_HWTAGGING)
2567 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2568 if (mask & IFCAP_WOL_MAGIC)
2569 ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2571 VLAN_CAPABILITIES(ifp);
2572 /* turn off LRO means also turn of HW LRO - if it's on */
2573 if (mask & IFCAP_LRO) {
2574 int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2575 bool need_restart = false;
2577 ifp->if_capenable ^= IFCAP_LRO;
2578 if (!(ifp->if_capenable & IFCAP_LRO)) {
2579 if (priv->params.hw_lro_en) {
2580 priv->params.hw_lro_en = false;
2581 need_restart = true;
2582 /* Not sure this is the correct way */
2583 priv->params_ethtool.hw_lro = priv->params.hw_lro_en;
2586 if (was_opened && need_restart) {
2587 mlx5e_close_locked(ifp);
2588 mlx5e_open_locked(ifp);
2596 ifr = (struct ifreq *)data;
2599 * Copy from the user-space address ifr_data to the
2600 * kernel-space address i2c
2602 error = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
2606 if (i2c.len > sizeof(i2c.data)) {
2612 /* Get module_num which is required for the query_eeprom */
2613 error = mlx5_query_module_num(priv->mdev, &module_num);
2615 if_printf(ifp, "Query module num failed, eeprom "
2616 "reading is not supported\n");
2620 /* Check if module is present before doing an access */
2621 if (mlx5_query_module_status(priv->mdev, module_num) !=
2622 MLX5_MODULE_STATUS_PLUGGED) {
2627 * Currently 0XA0 and 0xA2 are the only addresses permitted.
2628 * The internal conversion is as follows:
2630 if (i2c.dev_addr == 0xA0)
2631 read_addr = MLX5E_I2C_ADDR_LOW;
2632 else if (i2c.dev_addr == 0xA2)
2633 read_addr = MLX5E_I2C_ADDR_HIGH;
2635 if_printf(ifp, "Query eeprom failed, "
2636 "Invalid Address: %X\n", i2c.dev_addr);
2640 error = mlx5_query_eeprom(priv->mdev,
2641 read_addr, MLX5E_EEPROM_LOW_PAGE,
2642 (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
2643 (uint32_t *)i2c.data, &size_read);
2645 if_printf(ifp, "Query eeprom failed, eeprom "
2646 "reading is not supported\n");
2651 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
2652 error = mlx5_query_eeprom(priv->mdev,
2653 read_addr, MLX5E_EEPROM_LOW_PAGE,
2654 (uint32_t)(i2c.offset + size_read),
2655 (uint32_t)(i2c.len - size_read), module_num,
2656 (uint32_t *)(i2c.data + size_read), &size_read);
2659 if_printf(ifp, "Query eeprom failed, eeprom "
2660 "reading is not supported\n");
2665 error = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
2671 error = ether_ioctl(ifp, command, data);
2678 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2681 * TODO: uncoment once FW really sets all these bits if
2682 * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
2683 * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
2684 * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
2688 /* TODO: add more must-to-have features */
2694 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
2695 struct mlx5e_priv *priv,
2696 int num_comp_vectors)
2699 * TODO: Consider link speed for setting "log_sq_size",
2700 * "log_rq_size" and "cq_moderation_xxx":
2702 priv->params.log_sq_size =
2703 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
2704 priv->params.log_rq_size =
2705 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
2706 priv->params.rx_cq_moderation_usec =
2707 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
2708 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
2709 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
2710 priv->params.rx_cq_moderation_mode =
2711 MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
2712 priv->params.rx_cq_moderation_pkts =
2713 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
2714 priv->params.tx_cq_moderation_usec =
2715 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
2716 priv->params.tx_cq_moderation_pkts =
2717 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
2718 priv->params.min_rx_wqes =
2719 MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
2720 priv->params.rx_hash_log_tbl_sz =
2721 (order_base_2(num_comp_vectors) >
2722 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
2723 order_base_2(num_comp_vectors) :
2724 MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
2725 priv->params.num_tc = 1;
2726 priv->params.default_vlan_prio = 0;
2727 priv->counter_set_id = -1;
2730 * hw lro is currently defaulted to off. when it won't anymore we
2731 * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
2733 priv->params.hw_lro_en = false;
2734 priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
2736 priv->params.cqe_zipping_en = !!MLX5_CAP_GEN(mdev, cqe_compression);
2739 priv->params.num_channels = num_comp_vectors;
2740 priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
2741 priv->queue_mapping_channel_mask =
2742 roundup_pow_of_two(num_comp_vectors) - 1;
2743 priv->num_tc = priv->params.num_tc;
2744 priv->default_vlan_prio = priv->params.default_vlan_prio;
2746 INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
2747 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
2748 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
2752 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
2753 struct mlx5_core_mr *mr)
2755 struct ifnet *ifp = priv->ifp;
2756 struct mlx5_core_dev *mdev = priv->mdev;
2757 struct mlx5_create_mkey_mbox_in *in;
2760 in = mlx5_vzalloc(sizeof(*in));
2762 if_printf(ifp, "%s: failed to allocate inbox\n", __func__);
2765 in->seg.flags = MLX5_PERM_LOCAL_WRITE |
2766 MLX5_PERM_LOCAL_READ |
2767 MLX5_ACCESS_MODE_PA;
2768 in->seg.flags_pd = cpu_to_be32(pdn | MLX5_MKEY_LEN64);
2769 in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
2771 err = mlx5_core_create_mkey(mdev, mr, in, sizeof(*in), NULL, NULL,
2774 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n",
2782 static const char *mlx5e_vport_stats_desc[] = {
2783 MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
2786 static const char *mlx5e_pport_stats_desc[] = {
2787 MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
2791 mlx5e_priv_mtx_init(struct mlx5e_priv *priv)
2793 mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
2794 sx_init(&priv->state_lock, "mlx5state");
2795 callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
2799 mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv)
2801 mtx_destroy(&priv->async_events_mtx);
2802 sx_destroy(&priv->state_lock);
2806 sysctl_firmware(SYSCTL_HANDLER_ARGS)
2809 * %d.%d%.d the string format.
2810 * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
2811 * We need at most 5 chars to store that.
2812 * It also has: two "." and NULL at the end, which means we need 18
2813 * (5*3 + 3) chars at most.
2816 struct mlx5e_priv *priv = arg1;
2819 snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
2820 fw_rev_sub(priv->mdev));
2821 error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
2826 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
2828 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
2829 OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
2830 sysctl_firmware, "A", "HCA firmware version");
2832 SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
2833 OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
2838 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
2840 #if (__FreeBSD_version < 1100000)
2844 /* Only receiving pauseframes is enabled by default */
2845 priv->params.tx_pauseframe_control = 0;
2846 priv->params.rx_pauseframe_control = 1;
2848 #if (__FreeBSD_version < 1100000)
2849 /* compute path for sysctl */
2850 snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
2851 device_get_unit(priv->mdev->pdev->dev.bsddev));
2853 /* try to fetch tunable, if any */
2854 TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
2856 /* compute path for sysctl */
2857 snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
2858 device_get_unit(priv->mdev->pdev->dev.bsddev));
2860 /* try to fetch tunable, if any */
2861 TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
2864 /* register pausframe SYSCTLs */
2865 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2866 OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
2867 &priv->params.tx_pauseframe_control, 0,
2868 "Set to enable TX pause frames. Clear to disable.");
2870 SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2871 OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
2872 &priv->params.rx_pauseframe_control, 0,
2873 "Set to enable RX pause frames. Clear to disable.");
2876 priv->params.tx_pauseframe_control =
2877 priv->params.tx_pauseframe_control ? 1 : 0;
2878 priv->params.rx_pauseframe_control =
2879 priv->params.rx_pauseframe_control ? 1 : 0;
2881 /* update firmware */
2882 mlx5_set_port_pause(priv->mdev, 1,
2883 priv->params.rx_pauseframe_control,
2884 priv->params.tx_pauseframe_control);
2888 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
2890 static volatile int mlx5_en_unit;
2892 struct mlx5e_priv *priv;
2893 u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
2894 struct sysctl_oid_list *child;
2895 int ncv = mdev->priv.eq_table.num_comp_vectors;
2901 if (mlx5e_check_required_hca_cap(mdev)) {
2902 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
2905 priv = malloc(sizeof(*priv), M_MLX5EN, M_WAITOK | M_ZERO);
2907 mlx5_core_err(mdev, "malloc() failed\n");
2910 mlx5e_priv_mtx_init(priv);
2912 ifp = priv->ifp = if_alloc(IFT_ETHER);
2914 mlx5_core_err(mdev, "if_alloc() failed\n");
2917 ifp->if_softc = priv;
2918 if_initname(ifp, "mce", atomic_fetchadd_int(&mlx5_en_unit, 1));
2919 ifp->if_mtu = ETHERMTU;
2920 ifp->if_init = mlx5e_open;
2921 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2922 ifp->if_ioctl = mlx5e_ioctl;
2923 ifp->if_transmit = mlx5e_xmit;
2924 ifp->if_qflush = if_qflush;
2925 #if (__FreeBSD_version >= 1100000)
2926 ifp->if_get_counter = mlx5e_get_counter;
2928 ifp->if_snd.ifq_maxlen = ifqmaxlen;
2930 * Set driver features
2932 ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
2933 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
2934 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
2935 ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
2936 ifp->if_capabilities |= IFCAP_LRO;
2937 ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
2939 /* set TSO limits so that we don't have to drop TX packets */
2940 ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
2941 ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
2942 ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
2944 ifp->if_capenable = ifp->if_capabilities;
2945 ifp->if_hwassist = 0;
2946 if (ifp->if_capenable & IFCAP_TSO)
2947 ifp->if_hwassist |= CSUM_TSO;
2948 if (ifp->if_capenable & IFCAP_TXCSUM)
2949 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2950 if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
2951 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2953 /* ifnet sysctl tree */
2954 sysctl_ctx_init(&priv->sysctl_ctx);
2955 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
2956 OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
2957 if (priv->sysctl_ifnet == NULL) {
2958 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
2959 goto err_free_sysctl;
2961 snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
2962 priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
2963 OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
2964 if (priv->sysctl_ifnet == NULL) {
2965 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
2966 goto err_free_sysctl;
2969 /* HW sysctl tree */
2970 child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
2971 priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
2972 OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
2973 if (priv->sysctl_hw == NULL) {
2974 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
2975 goto err_free_sysctl;
2977 mlx5e_build_ifp_priv(mdev, priv, ncv);
2978 err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
2980 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n",
2982 goto err_free_sysctl;
2984 err = mlx5_core_alloc_pd(mdev, &priv->pdn);
2986 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n",
2988 goto err_unmap_free_uar;
2990 err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
2992 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n",
2994 goto err_dealloc_pd;
2996 err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
2998 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n",
3000 goto err_dealloc_transport_domain;
3002 mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
3004 /* check if we should generate a random MAC address */
3005 if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
3006 is_zero_ether_addr(dev_addr)) {
3007 random_ether_addr(dev_addr);
3008 if_printf(ifp, "Assigned random MAC address\n");
3011 /* set default MTU */
3012 mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
3015 device_set_desc(mdev->pdev->dev.bsddev, mlx5e_version);
3017 /* Set default media status */
3018 priv->media_status_last = IFM_AVALID;
3019 priv->media_active_last = IFM_ETHER | IFM_AUTO |
3020 IFM_ETH_RXPAUSE | IFM_FDX;
3022 /* setup default pauseframes configuration */
3023 mlx5e_setup_pauseframes(priv);
3025 err = mlx5_query_port_proto_cap(mdev, ð_proto_cap, MLX5_PTYS_EN);
3028 if_printf(ifp, "%s: Query port media capability failed, %d\n",
3032 /* Setup supported medias */
3033 ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
3034 mlx5e_media_change, mlx5e_media_status);
3036 for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
3037 if (mlx5e_mode_table[i].baudrate == 0)
3039 if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
3040 ifmedia_add(&priv->media,
3041 mlx5e_mode_table[i].subtype |
3042 IFM_ETHER, 0, NULL);
3043 ifmedia_add(&priv->media,
3044 mlx5e_mode_table[i].subtype |
3045 IFM_ETHER | IFM_FDX |
3046 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3050 ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
3051 ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3052 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3054 /* Set autoselect by default */
3055 ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3056 IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
3057 ether_ifattach(ifp, dev_addr);
3059 /* Register for VLAN events */
3060 priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
3061 mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
3062 priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
3063 mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
3065 /* Link is down by default */
3066 if_link_state_change(ifp, LINK_STATE_DOWN);
3068 mlx5e_enable_async_events(priv);
3070 mlx5e_add_hw_stats(priv);
3072 mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3073 "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
3074 priv->stats.vport.arg);
3076 mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3077 "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
3078 priv->stats.pport.arg);
3080 mlx5e_create_ethtool(priv);
3082 mtx_lock(&priv->async_events_mtx);
3083 mlx5e_update_stats(priv);
3084 mtx_unlock(&priv->async_events_mtx);
3088 err_dealloc_transport_domain:
3089 mlx5_dealloc_transport_domain(mdev, priv->tdn);
3092 mlx5_core_dealloc_pd(mdev, priv->pdn);
3095 mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3098 sysctl_ctx_free(&priv->sysctl_ctx);
3103 mlx5e_priv_mtx_destroy(priv);
3104 free(priv, M_MLX5EN);
3109 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
3111 struct mlx5e_priv *priv = vpriv;
3112 struct ifnet *ifp = priv->ifp;
3114 /* don't allow more IOCTLs */
3117 /* XXX wait a bit to allow IOCTL handlers to complete */
3120 /* stop watchdog timer */
3121 callout_drain(&priv->watchdog);
3123 if (priv->vlan_attach != NULL)
3124 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
3125 if (priv->vlan_detach != NULL)
3126 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
3128 /* make sure device gets closed */
3130 mlx5e_close_locked(ifp);
3133 /* unregister device */
3134 ifmedia_removeall(&priv->media);
3135 ether_ifdetach(ifp);
3138 /* destroy all remaining sysctl nodes */
3139 if (priv->sysctl_debug)
3140 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
3141 sysctl_ctx_free(&priv->stats.vport.ctx);
3142 sysctl_ctx_free(&priv->stats.pport.ctx);
3143 sysctl_ctx_free(&priv->sysctl_ctx);
3145 mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
3146 mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
3147 mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3148 mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
3149 mlx5e_disable_async_events(priv);
3150 flush_scheduled_work();
3151 mlx5e_priv_mtx_destroy(priv);
3152 free(priv, M_MLX5EN);
3156 mlx5e_get_ifp(void *vpriv)
3158 struct mlx5e_priv *priv = vpriv;
3163 static struct mlx5_interface mlx5e_interface = {
3164 .add = mlx5e_create_ifp,
3165 .remove = mlx5e_destroy_ifp,
3166 .event = mlx5e_async_event,
3167 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3168 .get_dev = mlx5e_get_ifp,
3174 mlx5_register_interface(&mlx5e_interface);
3180 mlx5_unregister_interface(&mlx5e_interface);
3183 module_init_order(mlx5e_init, SI_ORDER_THIRD);
3184 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
3186 #if (__FreeBSD_version >= 1100000)
3187 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
3189 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
3190 MODULE_VERSION(mlx5en, 1);