sys/dev/mlx5/mlx5_en/mlx5_en_main.c

   1 /*-
   2  * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include "en.h"
  29
  30 #include <sys/sockio.h>
  31 #include <machine/atomic.h>
  32
  33 #ifndef ETH_DRIVER_VERSION
  34 #define ETH_DRIVER_VERSION      "3.5.0"
  35 #endif
  36 #define DRIVER_RELDATE  "November 2018"
  37
  38 static const char mlx5e_version[] = "mlx5en: Mellanox Ethernet driver "
  39         ETH_DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
  40
  41 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs);
  42
  43 struct mlx5e_channel_param {
  44         struct mlx5e_rq_param rq;
  45         struct mlx5e_sq_param sq;
  46         struct mlx5e_cq_param rx_cq;
  47         struct mlx5e_cq_param tx_cq;
  48 };
  49
  50 static const struct {
  51         u32     subtype;
  52         u64     baudrate;
  53 }       mlx5e_mode_table[MLX5E_LINK_MODES_NUMBER] = {
  54
  55         [MLX5E_1000BASE_CX_SGMII] = {
  56                 .subtype = IFM_1000_CX_SGMII,
  57                 .baudrate = IF_Mbps(1000ULL),
  58         },
  59         [MLX5E_1000BASE_KX] = {
  60                 .subtype = IFM_1000_KX,
  61                 .baudrate = IF_Mbps(1000ULL),
  62         },
  63         [MLX5E_10GBASE_CX4] = {
  64                 .subtype = IFM_10G_CX4,
  65                 .baudrate = IF_Gbps(10ULL),
  66         },
  67         [MLX5E_10GBASE_KX4] = {
  68                 .subtype = IFM_10G_KX4,
  69                 .baudrate = IF_Gbps(10ULL),
  70         },
  71         [MLX5E_10GBASE_KR] = {
  72                 .subtype = IFM_10G_KR,
  73                 .baudrate = IF_Gbps(10ULL),
  74         },
  75         [MLX5E_20GBASE_KR2] = {
  76                 .subtype = IFM_20G_KR2,
  77                 .baudrate = IF_Gbps(20ULL),
  78         },
  79         [MLX5E_40GBASE_CR4] = {
  80                 .subtype = IFM_40G_CR4,
  81                 .baudrate = IF_Gbps(40ULL),
  82         },
  83         [MLX5E_40GBASE_KR4] = {
  84                 .subtype = IFM_40G_KR4,
  85                 .baudrate = IF_Gbps(40ULL),
  86         },
  87         [MLX5E_56GBASE_R4] = {
  88                 .subtype = IFM_56G_R4,
  89                 .baudrate = IF_Gbps(56ULL),
  90         },
  91         [MLX5E_10GBASE_CR] = {
  92                 .subtype = IFM_10G_CR1,
  93                 .baudrate = IF_Gbps(10ULL),
  94         },
  95         [MLX5E_10GBASE_SR] = {
  96                 .subtype = IFM_10G_SR,
  97                 .baudrate = IF_Gbps(10ULL),
  98         },
  99         [MLX5E_10GBASE_ER] = {
 100                 .subtype = IFM_10G_ER,
 101                 .baudrate = IF_Gbps(10ULL),
 102         },
 103         [MLX5E_40GBASE_SR4] = {
 104                 .subtype = IFM_40G_SR4,
 105                 .baudrate = IF_Gbps(40ULL),
 106         },
 107         [MLX5E_40GBASE_LR4] = {
 108                 .subtype = IFM_40G_LR4,
 109                 .baudrate = IF_Gbps(40ULL),
 110         },
 111         [MLX5E_100GBASE_CR4] = {
 112                 .subtype = IFM_100G_CR4,
 113                 .baudrate = IF_Gbps(100ULL),
 114         },
 115         [MLX5E_100GBASE_SR4] = {
 116                 .subtype = IFM_100G_SR4,
 117                 .baudrate = IF_Gbps(100ULL),
 118         },
 119         [MLX5E_100GBASE_KR4] = {
 120                 .subtype = IFM_100G_KR4,
 121                 .baudrate = IF_Gbps(100ULL),
 122         },
 123         [MLX5E_100GBASE_LR4] = {
 124                 .subtype = IFM_100G_LR4,
 125                 .baudrate = IF_Gbps(100ULL),
 126         },
 127         [MLX5E_100BASE_TX] = {
 128                 .subtype = IFM_100_TX,
 129                 .baudrate = IF_Mbps(100ULL),
 130         },
 131         [MLX5E_1000BASE_T] = {
 132                 .subtype = IFM_1000_T,
 133                 .baudrate = IF_Mbps(1000ULL),
 134         },
 135         [MLX5E_10GBASE_T] = {
 136                 .subtype = IFM_10G_T,
 137                 .baudrate = IF_Gbps(10ULL),
 138         },
 139         [MLX5E_25GBASE_CR] = {
 140                 .subtype = IFM_25G_CR,
 141                 .baudrate = IF_Gbps(25ULL),
 142         },
 143         [MLX5E_25GBASE_KR] = {
 144                 .subtype = IFM_25G_KR,
 145                 .baudrate = IF_Gbps(25ULL),
 146         },
 147         [MLX5E_25GBASE_SR] = {
 148                 .subtype = IFM_25G_SR,
 149                 .baudrate = IF_Gbps(25ULL),
 150         },
 151         [MLX5E_50GBASE_CR2] = {
 152                 .subtype = IFM_50G_CR2,
 153                 .baudrate = IF_Gbps(50ULL),
 154         },
 155         [MLX5E_50GBASE_KR2] = {
 156                 .subtype = IFM_50G_KR2,
 157                 .baudrate = IF_Gbps(50ULL),
 158         },
 159 };
 160
 161 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
 162
 163 static void
 164 mlx5e_update_carrier(struct mlx5e_priv *priv)
 165 {
 166         struct mlx5_core_dev *mdev = priv->mdev;
 167         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 168         u32 eth_proto_oper;
 169         int error;
 170         u8 port_state;
 171         u8 is_er_type;
 172         u8 i;
 173
 174         port_state = mlx5_query_vport_state(mdev,
 175             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 176
 177         if (port_state == VPORT_STATE_UP) {
 178                 priv->media_status_last |= IFM_ACTIVE;
 179         } else {
 180                 priv->media_status_last &= ~IFM_ACTIVE;
 181                 priv->media_active_last = IFM_ETHER;
 182                 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
 183                 return;
 184         }
 185
 186         error = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
 187         if (error) {
 188                 priv->media_active_last = IFM_ETHER;
 189                 priv->ifp->if_baudrate = 1;
 190                 if_printf(priv->ifp, "%s: query port ptys failed: 0x%x\n",
 191                     __func__, error);
 192                 return;
 193         }
 194         eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
 195
 196         for (i = 0; i != MLX5E_LINK_MODES_NUMBER; i++) {
 197                 if (mlx5e_mode_table[i].baudrate == 0)
 198                         continue;
 199                 if (MLX5E_PROT_MASK(i) & eth_proto_oper) {
 200                         u32 subtype = mlx5e_mode_table[i].subtype;
 201
 202                         priv->ifp->if_baudrate =
 203                             mlx5e_mode_table[i].baudrate;
 204
 205                         switch (subtype) {
 206                         case IFM_10G_ER:
 207                                 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
 208                                 if (error != 0) {
 209                                         if_printf(priv->ifp, "%s: query port pddr failed: %d\n",
 210                                             __func__, error);
 211                                 }
 212                                 if (error != 0 || is_er_type == 0)
 213                                         subtype = IFM_10G_LR;
 214                                 break;
 215                         case IFM_40G_LR4:
 216                                 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
 217                                 if (error != 0) {
 218                                         if_printf(priv->ifp, "%s: query port pddr failed: %d\n",
 219                                             __func__, error);
 220                                 }
 221                                 if (error == 0 && is_er_type != 0)
 222                                         subtype = IFM_40G_ER4;
 223                                 break;
 224                         }
 225                         priv->media_active_last = subtype | IFM_ETHER | IFM_FDX;
 226                         break;
 227                 }
 228         }
 229         if_link_state_change(priv->ifp, LINK_STATE_UP);
 230 }
 231
 232 static void
 233 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
 234 {
 235         struct mlx5e_priv *priv = dev->if_softc;
 236
 237         ifmr->ifm_status = priv->media_status_last;
 238         ifmr->ifm_active = priv->media_active_last |
 239             (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
 240             (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
 241
 242 }
 243
 244 static u32
 245 mlx5e_find_link_mode(u32 subtype)
 246 {
 247         u32 i;
 248         u32 link_mode = 0;
 249
 250         switch (subtype) {
 251         case IFM_10G_LR:
 252                 subtype = IFM_10G_ER;
 253                 break;
 254         case IFM_40G_ER4:
 255                 subtype = IFM_40G_LR4;
 256                 break;
 257         }
 258
 259         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
 260                 if (mlx5e_mode_table[i].baudrate == 0)
 261                         continue;
 262                 if (mlx5e_mode_table[i].subtype == subtype)
 263                         link_mode |= MLX5E_PROT_MASK(i);
 264         }
 265
 266         return (link_mode);
 267 }
 268
 269 static int
 270 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv)
 271 {
 272         return (mlx5_set_port_pause_and_pfc(priv->mdev, 1,
 273             priv->params.rx_pauseframe_control,
 274             priv->params.tx_pauseframe_control,
 275             priv->params.rx_priority_flow_control,
 276             priv->params.tx_priority_flow_control));
 277 }
 278
 279 static int
 280 mlx5e_set_port_pfc(struct mlx5e_priv *priv)
 281 {
 282         int error;
 283
 284         if (priv->gone != 0) {
 285                 error = -ENXIO;
 286         } else if (priv->params.rx_pauseframe_control ||
 287             priv->params.tx_pauseframe_control) {
 288                 if_printf(priv->ifp,
 289                     "Global pauseframes must be disabled before enabling PFC.\n");
 290                 error = -EINVAL;
 291         } else {
 292                 error = mlx5e_set_port_pause_and_pfc(priv);
 293         }
 294         return (error);
 295 }
 296
 297 static int
 298 mlx5e_media_change(struct ifnet *dev)
 299 {
 300         struct mlx5e_priv *priv = dev->if_softc;
 301         struct mlx5_core_dev *mdev = priv->mdev;
 302         u32 eth_proto_cap;
 303         u32 link_mode;
 304         int was_opened;
 305         int locked;
 306         int error;
 307
 308         locked = PRIV_LOCKED(priv);
 309         if (!locked)
 310                 PRIV_LOCK(priv);
 311
 312         if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
 313                 error = EINVAL;
 314                 goto done;
 315         }
 316         link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media));
 317
 318         /* query supported capabilities */
 319         error = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
 320         if (error != 0) {
 321                 if_printf(dev, "Query port media capability failed\n");
 322                 goto done;
 323         }
 324         /* check for autoselect */
 325         if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
 326                 link_mode = eth_proto_cap;
 327                 if (link_mode == 0) {
 328                         if_printf(dev, "Port media capability is zero\n");
 329                         error = EINVAL;
 330                         goto done;
 331                 }
 332         } else {
 333                 link_mode = link_mode & eth_proto_cap;
 334                 if (link_mode == 0) {
 335                         if_printf(dev, "Not supported link mode requested\n");
 336                         error = EINVAL;
 337                         goto done;
 338                 }
 339         }
 340         if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
 341                 /* check if PFC is enabled */
 342                 if (priv->params.rx_priority_flow_control ||
 343                     priv->params.tx_priority_flow_control) {
 344                         if_printf(dev, "PFC must be disabled before enabling global pauseframes.\n");
 345                         error = EINVAL;
 346                         goto done;
 347                 }
 348         }
 349         /* update pauseframe control bits */
 350         priv->params.rx_pauseframe_control =
 351             (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
 352         priv->params.tx_pauseframe_control =
 353             (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
 354
 355         /* check if device is opened */
 356         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
 357
 358         /* reconfigure the hardware */
 359         mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
 360         mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN);
 361         error = -mlx5e_set_port_pause_and_pfc(priv);
 362         if (was_opened)
 363                 mlx5_set_port_status(mdev, MLX5_PORT_UP);
 364
 365 done:
 366         if (!locked)
 367                 PRIV_UNLOCK(priv);
 368         return (error);
 369 }
 370
 371 static void
 372 mlx5e_update_carrier_work(struct work_struct *work)
 373 {
 374         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 375             update_carrier_work);
 376
 377         PRIV_LOCK(priv);
 378         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 379                 mlx5e_update_carrier(priv);
 380         PRIV_UNLOCK(priv);
 381 }
 382
 383 /*
 384  * This function reads the physical port counters from the firmware
 385  * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
 386  * macros. The output is converted from big-endian 64-bit values into
 387  * host endian ones and stored in the "priv->stats.pport" structure.
 388  */
 389 static void
 390 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 391 {
 392         struct mlx5_core_dev *mdev = priv->mdev;
 393         struct mlx5e_pport_stats *s = &priv->stats.pport;
 394         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 395         u32 *in;
 396         u32 *out;
 397         const u64 *ptr;
 398         unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 399         unsigned x;
 400         unsigned y;
 401         unsigned z;
 402
 403         /* allocate firmware request structures */
 404         in = mlx5_vzalloc(sz);
 405         out = mlx5_vzalloc(sz);
 406         if (in == NULL || out == NULL)
 407                 goto free_out;
 408
 409         /*
 410          * Get pointer to the 64-bit counter set which is located at a
 411          * fixed offset in the output firmware request structure:
 412          */
 413         ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
 414
 415         MLX5_SET(ppcnt_reg, in, local_port, 1);
 416
 417         /* read IEEE802_3 counter group using predefined counter layout */
 418         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 419         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 420         for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM;
 421              x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
 422                 s->arg[y] = be64toh(ptr[x]);
 423
 424         /* read RFC2819 counter group using predefined counter layout */
 425         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 426         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 427         for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
 428                 s->arg[y] = be64toh(ptr[x]);
 429         for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
 430             MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
 431                 s_debug->arg[y] = be64toh(ptr[x]);
 432
 433         /* read RFC2863 counter group using predefined counter layout */
 434         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 435         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 436         for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
 437                 s_debug->arg[y] = be64toh(ptr[x]);
 438
 439         /* read physical layer stats counter group using predefined counter layout */
 440         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 441         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 442         for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
 443                 s_debug->arg[y] = be64toh(ptr[x]);
 444
 445         /* read Extended Ethernet counter group using predefined counter layout */
 446         MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
 447         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 448         for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++)
 449                 s_debug->arg[y] = be64toh(ptr[x]);
 450
 451         /* read per-priority counters */
 452         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 453
 454         /* iterate all the priorities */
 455         for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) {
 456                 MLX5_SET(ppcnt_reg, in, prio_tc, z);
 457                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 458
 459                 /* read per priority stats counter group using predefined counter layout */
 460                 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM /
 461                     MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++)
 462                         s->arg[y] = be64toh(ptr[x]);
 463         }
 464
 465 free_out:
 466         /* free firmware request structures */
 467         kvfree(in);
 468         kvfree(out);
 469 }
 470
 471 /*
 472  * This function is called regularly to collect all statistics
 473  * counters from the firmware. The values can be viewed through the
 474  * sysctl interface. Execution is serialized using the priv's global
 475  * configuration lock.
 476  */
 477 static void
 478 mlx5e_update_stats_work(struct work_struct *work)
 479 {
 480         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 481             update_stats_work);
 482         struct mlx5_core_dev *mdev = priv->mdev;
 483         struct mlx5e_vport_stats *s = &priv->stats.vport;
 484         struct mlx5e_sq_stats *sq_stats;
 485         struct buf_ring *sq_br;
 486 #if (__FreeBSD_version < 1100000)
 487         struct ifnet *ifp = priv->ifp;
 488 #endif
 489
 490         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 491         u32 *out;
 492         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 493         u64 tso_packets = 0;
 494         u64 tso_bytes = 0;
 495         u64 tx_queue_dropped = 0;
 496         u64 tx_defragged = 0;
 497         u64 tx_offload_none = 0;
 498         u64 lro_packets = 0;
 499         u64 lro_bytes = 0;
 500         u64 sw_lro_queued = 0;
 501         u64 sw_lro_flushed = 0;
 502         u64 rx_csum_none = 0;
 503         u64 rx_wqe_err = 0;
 504         u32 rx_out_of_buffer = 0;
 505         int i;
 506         int j;
 507
 508         PRIV_LOCK(priv);
 509         out = mlx5_vzalloc(outlen);
 510         if (out == NULL)
 511                 goto free_out;
 512         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
 513                 goto free_out;
 514
 515         /* Collect firts the SW counters and then HW for consistency */
 516         for (i = 0; i < priv->params.num_channels; i++) {
 517                 struct mlx5e_channel *pch = priv->channel + i;
 518                 struct mlx5e_rq *rq = &pch->rq;
 519                 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats;
 520
 521                 /* collect stats from LRO */
 522                 rq_stats->sw_lro_queued = rq->lro.lro_queued;
 523                 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
 524                 sw_lro_queued += rq_stats->sw_lro_queued;
 525                 sw_lro_flushed += rq_stats->sw_lro_flushed;
 526                 lro_packets += rq_stats->lro_packets;
 527                 lro_bytes += rq_stats->lro_bytes;
 528                 rx_csum_none += rq_stats->csum_none;
 529                 rx_wqe_err += rq_stats->wqe_err;
 530
 531                 for (j = 0; j < priv->num_tc; j++) {
 532                         sq_stats = &pch->sq[j].stats;
 533                         sq_br = pch->sq[j].br;
 534
 535                         tso_packets += sq_stats->tso_packets;
 536                         tso_bytes += sq_stats->tso_bytes;
 537                         tx_queue_dropped += sq_stats->dropped;
 538                         if (sq_br != NULL)
 539                                 tx_queue_dropped += sq_br->br_drops;
 540                         tx_defragged += sq_stats->defragged;
 541                         tx_offload_none += sq_stats->csum_offload_none;
 542                 }
 543         }
 544
 545         /* update counters */
 546         s->tso_packets = tso_packets;
 547         s->tso_bytes = tso_bytes;
 548         s->tx_queue_dropped = tx_queue_dropped;
 549         s->tx_defragged = tx_defragged;
 550         s->lro_packets = lro_packets;
 551         s->lro_bytes = lro_bytes;
 552         s->sw_lro_queued = sw_lro_queued;
 553         s->sw_lro_flushed = sw_lro_flushed;
 554         s->rx_csum_none = rx_csum_none;
 555         s->rx_wqe_err = rx_wqe_err;
 556
 557         /* HW counters */
 558         memset(in, 0, sizeof(in));
 559
 560         MLX5_SET(query_vport_counter_in, in, opcode,
 561             MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 562         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 563         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 564
 565         memset(out, 0, outlen);
 566
 567         /* get number of out-of-buffer drops first */
 568         if (mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
 569             &rx_out_of_buffer))
 570                 goto free_out;
 571
 572         /* accumulate difference into a 64-bit counter */
 573         s->rx_out_of_buffer += (u64)(u32)(rx_out_of_buffer - s->rx_out_of_buffer_prev);
 574         s->rx_out_of_buffer_prev = rx_out_of_buffer;
 575
 576         /* get port statistics */
 577         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
 578                 goto free_out;
 579
 580 #define MLX5_GET_CTR(out, x) \
 581         MLX5_GET64(query_vport_counter_out, out, x)
 582
 583         s->rx_error_packets =
 584             MLX5_GET_CTR(out, received_errors.packets);
 585         s->rx_error_bytes =
 586             MLX5_GET_CTR(out, received_errors.octets);
 587         s->tx_error_packets =
 588             MLX5_GET_CTR(out, transmit_errors.packets);
 589         s->tx_error_bytes =
 590             MLX5_GET_CTR(out, transmit_errors.octets);
 591
 592         s->rx_unicast_packets =
 593             MLX5_GET_CTR(out, received_eth_unicast.packets);
 594         s->rx_unicast_bytes =
 595             MLX5_GET_CTR(out, received_eth_unicast.octets);
 596         s->tx_unicast_packets =
 597             MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 598         s->tx_unicast_bytes =
 599             MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 600
 601         s->rx_multicast_packets =
 602             MLX5_GET_CTR(out, received_eth_multicast.packets);
 603         s->rx_multicast_bytes =
 604             MLX5_GET_CTR(out, received_eth_multicast.octets);
 605         s->tx_multicast_packets =
 606             MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 607         s->tx_multicast_bytes =
 608             MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 609
 610         s->rx_broadcast_packets =
 611             MLX5_GET_CTR(out, received_eth_broadcast.packets);
 612         s->rx_broadcast_bytes =
 613             MLX5_GET_CTR(out, received_eth_broadcast.octets);
 614         s->tx_broadcast_packets =
 615             MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 616         s->tx_broadcast_bytes =
 617             MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 618
 619         s->rx_packets =
 620             s->rx_unicast_packets +
 621             s->rx_multicast_packets +
 622             s->rx_broadcast_packets -
 623             s->rx_out_of_buffer;
 624         s->rx_bytes =
 625             s->rx_unicast_bytes +
 626             s->rx_multicast_bytes +
 627             s->rx_broadcast_bytes;
 628         s->tx_packets =
 629             s->tx_unicast_packets +
 630             s->tx_multicast_packets +
 631             s->tx_broadcast_packets;
 632         s->tx_bytes =
 633             s->tx_unicast_bytes +
 634             s->tx_multicast_bytes +
 635             s->tx_broadcast_bytes;
 636
 637         /* Update calculated offload counters */
 638         s->tx_csum_offload = s->tx_packets - tx_offload_none;
 639         s->rx_csum_good = s->rx_packets - s->rx_csum_none;
 640
 641         /* Get physical port counters */
 642         mlx5e_update_pport_counters(priv);
 643
 644         s->tx_jumbo_packets =
 645             priv->stats.port_stats_debug.tx_stat_p1519to2047octets +
 646             priv->stats.port_stats_debug.tx_stat_p2048to4095octets +
 647             priv->stats.port_stats_debug.tx_stat_p4096to8191octets +
 648             priv->stats.port_stats_debug.tx_stat_p8192to10239octets;
 649
 650 #if (__FreeBSD_version < 1100000)
 651         /* no get_counters interface in fbsd 10 */
 652         ifp->if_ipackets = s->rx_packets;
 653         ifp->if_ierrors = s->rx_error_packets +
 654             priv->stats.pport.alignment_err +
 655             priv->stats.pport.check_seq_err +
 656             priv->stats.pport.crc_align_errors +
 657             priv->stats.pport.in_range_len_errors +
 658             priv->stats.pport.jabbers +
 659             priv->stats.pport.out_of_range_len +
 660             priv->stats.pport.oversize_pkts +
 661             priv->stats.pport.symbol_err +
 662             priv->stats.pport.too_long_errors +
 663             priv->stats.pport.undersize_pkts +
 664             priv->stats.pport.unsupported_op_rx;
 665         ifp->if_iqdrops = s->rx_out_of_buffer +
 666             priv->stats.pport.drop_events;
 667         ifp->if_opackets = s->tx_packets;
 668         ifp->if_oerrors = s->tx_error_packets;
 669         ifp->if_snd.ifq_drops = s->tx_queue_dropped;
 670         ifp->if_ibytes = s->rx_bytes;
 671         ifp->if_obytes = s->tx_bytes;
 672         ifp->if_collisions =
 673             priv->stats.pport.collisions;
 674 #endif
 675
 676 free_out:
 677         kvfree(out);
 678
 679         /* Update diagnostics, if any */
 680         if (priv->params_ethtool.diag_pci_enable ||
 681             priv->params_ethtool.diag_general_enable) {
 682                 int error = mlx5_core_get_diagnostics_full(mdev,
 683                     priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL,
 684                     priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL);
 685                 if (error != 0)
 686                         if_printf(priv->ifp, "Failed reading diagnostics: %d\n", error);
 687         }
 688         PRIV_UNLOCK(priv);
 689 }
 690
 691 static void
 692 mlx5e_update_stats(void *arg)
 693 {
 694         struct mlx5e_priv *priv = arg;
 695
 696         queue_work(priv->wq, &priv->update_stats_work);
 697
 698         callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
 699 }
 700
 701 static void
 702 mlx5e_async_event_sub(struct mlx5e_priv *priv,
 703     enum mlx5_dev_event event)
 704 {
 705         switch (event) {
 706         case MLX5_DEV_EVENT_PORT_UP:
 707         case MLX5_DEV_EVENT_PORT_DOWN:
 708                 queue_work(priv->wq, &priv->update_carrier_work);
 709                 break;
 710
 711         default:
 712                 break;
 713         }
 714 }
 715
 716 static void
 717 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 718     enum mlx5_dev_event event, unsigned long param)
 719 {
 720         struct mlx5e_priv *priv = vpriv;
 721
 722         mtx_lock(&priv->async_events_mtx);
 723         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 724                 mlx5e_async_event_sub(priv, event);
 725         mtx_unlock(&priv->async_events_mtx);
 726 }
 727
 728 static void
 729 mlx5e_enable_async_events(struct mlx5e_priv *priv)
 730 {
 731         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 732 }
 733
 734 static void
 735 mlx5e_disable_async_events(struct mlx5e_priv *priv)
 736 {
 737         mtx_lock(&priv->async_events_mtx);
 738         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 739         mtx_unlock(&priv->async_events_mtx);
 740 }
 741
 742 static const char *mlx5e_rq_stats_desc[] = {
 743         MLX5E_RQ_STATS(MLX5E_STATS_DESC)
 744 };
 745
 746 static int
 747 mlx5e_create_rq(struct mlx5e_channel *c,
 748     struct mlx5e_rq_param *param,
 749     struct mlx5e_rq *rq)
 750 {
 751         struct mlx5e_priv *priv = c->priv;
 752         struct mlx5_core_dev *mdev = priv->mdev;
 753         char buffer[16];
 754         void *rqc = param->rqc;
 755         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 756         int wq_sz;
 757         int err;
 758         int i;
 759         u32 nsegs, wqe_sz;
 760
 761         err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
 762         if (err != 0)
 763                 goto done;
 764
 765         /* Create DMA descriptor TAG */
 766         if ((err = -bus_dma_tag_create(
 767             bus_get_dma_tag(mdev->pdev->dev.bsddev),
 768             1,                          /* any alignment */
 769             0,                          /* no boundary */
 770             BUS_SPACE_MAXADDR,          /* lowaddr */
 771             BUS_SPACE_MAXADDR,          /* highaddr */
 772             NULL, NULL,                 /* filter, filterarg */
 773             nsegs * MLX5E_MAX_RX_BYTES, /* maxsize */
 774             nsegs,                      /* nsegments */
 775             nsegs * MLX5E_MAX_RX_BYTES, /* maxsegsize */
 776             0,                          /* flags */
 777             NULL, NULL,                 /* lockfunc, lockfuncarg */
 778             &rq->dma_tag)))
 779                 goto done;
 780
 781         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 782             &rq->wq_ctrl);
 783         if (err)
 784                 goto err_free_dma_tag;
 785
 786         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 787
 788         err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs);
 789         if (err != 0)
 790                 goto err_rq_wq_destroy;
 791
 792         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 793
 794         err = -tcp_lro_init_args(&rq->lro, c->ifp, TCP_LRO_ENTRIES, wq_sz);
 795         if (err)
 796                 goto err_rq_wq_destroy;
 797
 798         rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
 799         for (i = 0; i != wq_sz; i++) {
 800                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 801 #if (MLX5E_MAX_RX_SEGS == 1)
 802                 uint32_t byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 803 #else
 804                 int j;
 805 #endif
 806
 807                 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
 808                 if (err != 0) {
 809                         while (i--)
 810                                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 811                         goto err_rq_mbuf_free;
 812                 }
 813
 814                 /* set value for constant fields */
 815 #if (MLX5E_MAX_RX_SEGS == 1)
 816                 wqe->data[0].lkey = c->mkey_be;
 817                 wqe->data[0].byte_count = cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
 818 #else
 819                 for (j = 0; j < rq->nsegs; j++)
 820                         wqe->data[j].lkey = c->mkey_be;
 821 #endif
 822         }
 823
 824         INIT_WORK(&rq->dim.work, mlx5e_dim_work);
 825         if (priv->params.rx_cq_moderation_mode < 2) {
 826                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
 827         } else {
 828                 void *cqc = container_of(param,
 829                     struct mlx5e_channel_param, rq)->rx_cq.cqc;
 830
 831                 switch (MLX5_GET(cqc, cqc, cq_period_mode)) {
 832                 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 833                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 834                         break;
 835                 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 836                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 837                         break;
 838                 default:
 839                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
 840                         break;
 841                 }
 842         }
 843
 844         rq->ifp = c->ifp;
 845         rq->channel = c;
 846         rq->ix = c->ix;
 847
 848         snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
 849         mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
 850             buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
 851             rq->stats.arg);
 852         return (0);
 853
 854 err_rq_mbuf_free:
 855         free(rq->mbuf, M_MLX5EN);
 856         tcp_lro_free(&rq->lro);
 857 err_rq_wq_destroy:
 858         mlx5_wq_destroy(&rq->wq_ctrl);
 859 err_free_dma_tag:
 860         bus_dma_tag_destroy(rq->dma_tag);
 861 done:
 862         return (err);
 863 }
 864
 865 static void
 866 mlx5e_destroy_rq(struct mlx5e_rq *rq)
 867 {
 868         int wq_sz;
 869         int i;
 870
 871         /* destroy all sysctl nodes */
 872         sysctl_ctx_free(&rq->stats.ctx);
 873
 874         /* free leftover LRO packets, if any */
 875         tcp_lro_free(&rq->lro);
 876
 877         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 878         for (i = 0; i != wq_sz; i++) {
 879                 if (rq->mbuf[i].mbuf != NULL) {
 880                         bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map);
 881                         m_freem(rq->mbuf[i].mbuf);
 882                 }
 883                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 884         }
 885         free(rq->mbuf, M_MLX5EN);
 886         mlx5_wq_destroy(&rq->wq_ctrl);
 887 }
 888
 889 static int
 890 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 891 {
 892         struct mlx5e_channel *c = rq->channel;
 893         struct mlx5e_priv *priv = c->priv;
 894         struct mlx5_core_dev *mdev = priv->mdev;
 895
 896         void *in;
 897         void *rqc;
 898         void *wq;
 899         int inlen;
 900         int err;
 901
 902         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 903             sizeof(u64) * rq->wq_ctrl.buf.npages;
 904         in = mlx5_vzalloc(inlen);
 905         if (in == NULL)
 906                 return (-ENOMEM);
 907
 908         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 909         wq = MLX5_ADDR_OF(rqc, rqc, wq);
 910
 911         memcpy(rqc, param->rqc, sizeof(param->rqc));
 912
 913         MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
 914         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
 915         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
 916         if (priv->counter_set_id >= 0)
 917                 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
 918         MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
 919             PAGE_SHIFT);
 920         MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
 921
 922         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 923             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
 924
 925         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 926
 927         kvfree(in);
 928
 929         return (err);
 930 }
 931
 932 static int
 933 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
 934 {
 935         struct mlx5e_channel *c = rq->channel;
 936         struct mlx5e_priv *priv = c->priv;
 937         struct mlx5_core_dev *mdev = priv->mdev;
 938
 939         void *in;
 940         void *rqc;
 941         int inlen;
 942         int err;
 943
 944         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 945         in = mlx5_vzalloc(inlen);
 946         if (in == NULL)
 947                 return (-ENOMEM);
 948
 949         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 950
 951         MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
 952         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 953         MLX5_SET(rqc, rqc, state, next_state);
 954
 955         err = mlx5_core_modify_rq(mdev, in, inlen);
 956
 957         kvfree(in);
 958
 959         return (err);
 960 }
 961
 962 static void
 963 mlx5e_disable_rq(struct mlx5e_rq *rq)
 964 {
 965         struct mlx5e_channel *c = rq->channel;
 966         struct mlx5e_priv *priv = c->priv;
 967         struct mlx5_core_dev *mdev = priv->mdev;
 968
 969         mlx5_core_destroy_rq(mdev, rq->rqn);
 970 }
 971
 972 static int
 973 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 974 {
 975         struct mlx5e_channel *c = rq->channel;
 976         struct mlx5e_priv *priv = c->priv;
 977         struct mlx5_wq_ll *wq = &rq->wq;
 978         int i;
 979
 980         for (i = 0; i < 1000; i++) {
 981                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 982                         return (0);
 983
 984                 msleep(4);
 985         }
 986         return (-ETIMEDOUT);
 987 }
 988
 989 static int
 990 mlx5e_open_rq(struct mlx5e_channel *c,
 991     struct mlx5e_rq_param *param,
 992     struct mlx5e_rq *rq)
 993 {
 994         int err;
 995
 996         err = mlx5e_create_rq(c, param, rq);
 997         if (err)
 998                 return (err);
 999
1000         err = mlx5e_enable_rq(rq, param);
1001         if (err)
1002                 goto err_destroy_rq;
1003
1004         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1005         if (err)
1006                 goto err_disable_rq;
1007
1008         c->rq.enabled = 1;
1009
1010         return (0);
1011
1012 err_disable_rq:
1013         mlx5e_disable_rq(rq);
1014 err_destroy_rq:
1015         mlx5e_destroy_rq(rq);
1016
1017         return (err);
1018 }
1019
1020 static void
1021 mlx5e_close_rq(struct mlx5e_rq *rq)
1022 {
1023         mtx_lock(&rq->mtx);
1024         rq->enabled = 0;
1025         callout_stop(&rq->watchdog);
1026         mtx_unlock(&rq->mtx);
1027
1028         callout_drain(&rq->watchdog);
1029
1030         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
1031 }
1032
1033 static void
1034 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
1035 {
1036
1037         mlx5e_disable_rq(rq);
1038         mlx5e_close_cq(&rq->cq);
1039         cancel_work_sync(&rq->dim.work);
1040         mlx5e_destroy_rq(rq);
1041 }
1042
1043 void
1044 mlx5e_free_sq_db(struct mlx5e_sq *sq)
1045 {
1046         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1047         int x;
1048
1049         for (x = 0; x != wq_sz; x++)
1050                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1051         free(sq->mbuf, M_MLX5EN);
1052 }
1053
1054 int
1055 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
1056 {
1057         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1058         int err;
1059         int x;
1060
1061         sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1062
1063         /* Create DMA descriptor MAPs */
1064         for (x = 0; x != wq_sz; x++) {
1065                 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
1066                 if (err != 0) {
1067                         while (x--)
1068                                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1069                         free(sq->mbuf, M_MLX5EN);
1070                         return (err);
1071                 }
1072         }
1073         return (0);
1074 }
1075
1076 static const char *mlx5e_sq_stats_desc[] = {
1077         MLX5E_SQ_STATS(MLX5E_STATS_DESC)
1078 };
1079
1080 void
1081 mlx5e_update_sq_inline(struct mlx5e_sq *sq)
1082 {
1083         sq->max_inline = sq->priv->params.tx_max_inline;
1084         sq->min_inline_mode = sq->priv->params.tx_min_inline_mode;
1085
1086         /*
1087          * Check if trust state is DSCP or if inline mode is NONE which
1088          * indicates CX-5 or newer hardware.
1089          */
1090         if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP ||
1091             sq->min_inline_mode == MLX5_INLINE_MODE_NONE) {
1092                 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert))
1093                         sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN;
1094                 else
1095                         sq->min_insert_caps = MLX5E_INSERT_NON_VLAN;
1096         } else {
1097                 sq->min_insert_caps = 0;
1098         }
1099 }
1100
1101 static void
1102 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1103 {
1104         int i;
1105
1106         for (i = 0; i != c->num_tc; i++) {
1107                 mtx_lock(&c->sq[i].lock);
1108                 mlx5e_update_sq_inline(&c->sq[i]);
1109                 mtx_unlock(&c->sq[i].lock);
1110         }
1111 }
1112
1113 void
1114 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv)
1115 {
1116         int i;
1117
1118         /* check if channels are closed */
1119         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
1120                 return;
1121
1122         for (i = 0; i < priv->params.num_channels; i++)
1123                 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]);
1124 }
1125
1126 static int
1127 mlx5e_create_sq(struct mlx5e_channel *c,
1128     int tc,
1129     struct mlx5e_sq_param *param,
1130     struct mlx5e_sq *sq)
1131 {
1132         struct mlx5e_priv *priv = c->priv;
1133         struct mlx5_core_dev *mdev = priv->mdev;
1134         char buffer[16];
1135         void *sqc = param->sqc;
1136         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1137         int err;
1138
1139         /* Create DMA descriptor TAG */
1140         if ((err = -bus_dma_tag_create(
1141             bus_get_dma_tag(mdev->pdev->dev.bsddev),
1142             1,                          /* any alignment */
1143             0,                          /* no boundary */
1144             BUS_SPACE_MAXADDR,          /* lowaddr */
1145             BUS_SPACE_MAXADDR,          /* highaddr */
1146             NULL, NULL,                 /* filter, filterarg */
1147             MLX5E_MAX_TX_PAYLOAD_SIZE,  /* maxsize */
1148             MLX5E_MAX_TX_MBUF_FRAGS,    /* nsegments */
1149             MLX5E_MAX_TX_MBUF_SIZE,     /* maxsegsize */
1150             0,                          /* flags */
1151             NULL, NULL,                 /* lockfunc, lockfuncarg */
1152             &sq->dma_tag)))
1153                 goto done;
1154
1155         err = mlx5_alloc_map_uar(mdev, &sq->uar);
1156         if (err)
1157                 goto err_free_dma_tag;
1158
1159         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
1160             &sq->wq_ctrl);
1161         if (err)
1162                 goto err_unmap_free_uar;
1163
1164         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1165         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1166
1167         err = mlx5e_alloc_sq_db(sq);
1168         if (err)
1169                 goto err_sq_wq_destroy;
1170
1171         sq->mkey_be = c->mkey_be;
1172         sq->ifp = priv->ifp;
1173         sq->priv = priv;
1174         sq->tc = tc;
1175
1176         mlx5e_update_sq_inline(sq);
1177
1178         snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1179         mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1180             buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1181             sq->stats.arg);
1182
1183         return (0);
1184
1185 err_sq_wq_destroy:
1186         mlx5_wq_destroy(&sq->wq_ctrl);
1187
1188 err_unmap_free_uar:
1189         mlx5_unmap_free_uar(mdev, &sq->uar);
1190
1191 err_free_dma_tag:
1192         bus_dma_tag_destroy(sq->dma_tag);
1193 done:
1194         return (err);
1195 }
1196
1197 static void
1198 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1199 {
1200         /* destroy all sysctl nodes */
1201         sysctl_ctx_free(&sq->stats.ctx);
1202
1203         mlx5e_free_sq_db(sq);
1204         mlx5_wq_destroy(&sq->wq_ctrl);
1205         mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1206 }
1207
1208 int
1209 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1210     int tis_num)
1211 {
1212         void *in;
1213         void *sqc;
1214         void *wq;
1215         int inlen;
1216         int err;
1217
1218         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1219             sizeof(u64) * sq->wq_ctrl.buf.npages;
1220         in = mlx5_vzalloc(inlen);
1221         if (in == NULL)
1222                 return (-ENOMEM);
1223
1224         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1225         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1226
1227         memcpy(sqc, param->sqc, sizeof(param->sqc));
1228
1229         MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1230         MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1231         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1232         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1233         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1234
1235         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1236         MLX5_SET(wq, wq, uar_page, sq->uar.index);
1237         MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1238             PAGE_SHIFT);
1239         MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1240
1241         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1242             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1243
1244         err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1245
1246         kvfree(in);
1247
1248         return (err);
1249 }
1250
1251 int
1252 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1253 {
1254         void *in;
1255         void *sqc;
1256         int inlen;
1257         int err;
1258
1259         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1260         in = mlx5_vzalloc(inlen);
1261         if (in == NULL)
1262                 return (-ENOMEM);
1263
1264         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1265
1266         MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1267         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1268         MLX5_SET(sqc, sqc, state, next_state);
1269
1270         err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1271
1272         kvfree(in);
1273
1274         return (err);
1275 }
1276
1277 void
1278 mlx5e_disable_sq(struct mlx5e_sq *sq)
1279 {
1280
1281         mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1282 }
1283
1284 static int
1285 mlx5e_open_sq(struct mlx5e_channel *c,
1286     int tc,
1287     struct mlx5e_sq_param *param,
1288     struct mlx5e_sq *sq)
1289 {
1290         int err;
1291
1292         err = mlx5e_create_sq(c, tc, param, sq);
1293         if (err)
1294                 return (err);
1295
1296         err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1297         if (err)
1298                 goto err_destroy_sq;
1299
1300         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1301         if (err)
1302                 goto err_disable_sq;
1303
1304         WRITE_ONCE(sq->running, 1);
1305
1306         return (0);
1307
1308 err_disable_sq:
1309         mlx5e_disable_sq(sq);
1310 err_destroy_sq:
1311         mlx5e_destroy_sq(sq);
1312
1313         return (err);
1314 }
1315
1316 static void
1317 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1318 {
1319         /* fill up remainder with NOPs */
1320         while (sq->cev_counter != 0) {
1321                 while (!mlx5e_sq_has_room_for(sq, 1)) {
1322                         if (can_sleep != 0) {
1323                                 mtx_unlock(&sq->lock);
1324                                 msleep(4);
1325                                 mtx_lock(&sq->lock);
1326                         } else {
1327                                 goto done;
1328                         }
1329                 }
1330                 /* send a single NOP */
1331                 mlx5e_send_nop(sq, 1);
1332                 atomic_thread_fence_rel();
1333         }
1334 done:
1335         /* Check if we need to write the doorbell */
1336         if (likely(sq->doorbell.d64 != 0)) {
1337                 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1338                 sq->doorbell.d64 = 0;
1339         }
1340 }
1341
1342 void
1343 mlx5e_sq_cev_timeout(void *arg)
1344 {
1345         struct mlx5e_sq *sq = arg;
1346
1347         mtx_assert(&sq->lock, MA_OWNED);
1348
1349         /* check next state */
1350         switch (sq->cev_next_state) {
1351         case MLX5E_CEV_STATE_SEND_NOPS:
1352                 /* fill TX ring with NOPs, if any */
1353                 mlx5e_sq_send_nops_locked(sq, 0);
1354
1355                 /* check if completed */
1356                 if (sq->cev_counter == 0) {
1357                         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1358                         return;
1359                 }
1360                 break;
1361         default:
1362                 /* send NOPs on next timeout */
1363                 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1364                 break;
1365         }
1366
1367         /* restart timer */
1368         callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1369 }
1370
1371 void
1372 mlx5e_drain_sq(struct mlx5e_sq *sq)
1373 {
1374         int error;
1375         struct mlx5_core_dev *mdev= sq->priv->mdev;
1376
1377         /*
1378          * Check if already stopped.
1379          *
1380          * NOTE: Serialization of this function is managed by the
1381          * caller ensuring the priv's state lock is locked or in case
1382          * of rate limit support, a single thread manages drain and
1383          * resume of SQs. The "running" variable can therefore safely
1384          * be read without any locks.
1385          */
1386         if (READ_ONCE(sq->running) == 0)
1387                 return;
1388
1389         /* don't put more packets into the SQ */
1390         WRITE_ONCE(sq->running, 0);
1391
1392         /* serialize access to DMA rings */
1393         mtx_lock(&sq->lock);
1394
1395         /* teardown event factor timer, if any */
1396         sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1397         callout_stop(&sq->cev_callout);
1398
1399         /* send dummy NOPs in order to flush the transmit ring */
1400         mlx5e_sq_send_nops_locked(sq, 1);
1401         mtx_unlock(&sq->lock);
1402
1403         /* make sure it is safe to free the callout */
1404         callout_drain(&sq->cev_callout);
1405
1406         /* wait till SQ is empty or link is down */
1407         mtx_lock(&sq->lock);
1408         while (sq->cc != sq->pc &&
1409             (sq->priv->media_status_last & IFM_ACTIVE) != 0 &&
1410             mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1411                 mtx_unlock(&sq->lock);
1412                 msleep(1);
1413                 sq->cq.mcq.comp(&sq->cq.mcq);
1414                 mtx_lock(&sq->lock);
1415         }
1416         mtx_unlock(&sq->lock);
1417
1418         /* error out remaining requests */
1419         error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1420         if (error != 0) {
1421                 if_printf(sq->ifp,
1422                     "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error);
1423         }
1424
1425         /* wait till SQ is empty */
1426         mtx_lock(&sq->lock);
1427         while (sq->cc != sq->pc &&
1428                mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1429                 mtx_unlock(&sq->lock);
1430                 msleep(1);
1431                 sq->cq.mcq.comp(&sq->cq.mcq);
1432                 mtx_lock(&sq->lock);
1433         }
1434         mtx_unlock(&sq->lock);
1435 }
1436
1437 static void
1438 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1439 {
1440
1441         mlx5e_drain_sq(sq);
1442         mlx5e_disable_sq(sq);
1443         mlx5e_destroy_sq(sq);
1444 }
1445
1446 static int
1447 mlx5e_create_cq(struct mlx5e_priv *priv,
1448     struct mlx5e_cq_param *param,
1449     struct mlx5e_cq *cq,
1450     mlx5e_cq_comp_t *comp,
1451     int eq_ix)
1452 {
1453         struct mlx5_core_dev *mdev = priv->mdev;
1454         struct mlx5_core_cq *mcq = &cq->mcq;
1455         int eqn_not_used;
1456         int irqn;
1457         int err;
1458         u32 i;
1459
1460         param->wq.buf_numa_node = 0;
1461         param->wq.db_numa_node = 0;
1462
1463         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1464             &cq->wq_ctrl);
1465         if (err)
1466                 return (err);
1467
1468         mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1469
1470         mcq->cqe_sz = 64;
1471         mcq->set_ci_db = cq->wq_ctrl.db.db;
1472         mcq->arm_db = cq->wq_ctrl.db.db + 1;
1473         *mcq->set_ci_db = 0;
1474         *mcq->arm_db = 0;
1475         mcq->vector = eq_ix;
1476         mcq->comp = comp;
1477         mcq->event = mlx5e_cq_error_event;
1478         mcq->irqn = irqn;
1479         mcq->uar = &priv->cq_uar;
1480
1481         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1482                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1483
1484                 cqe->op_own = 0xf1;
1485         }
1486
1487         cq->priv = priv;
1488
1489         return (0);
1490 }
1491
1492 static void
1493 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1494 {
1495         mlx5_wq_destroy(&cq->wq_ctrl);
1496 }
1497
1498 static int
1499 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1500 {
1501         struct mlx5_core_cq *mcq = &cq->mcq;
1502         void *in;
1503         void *cqc;
1504         int inlen;
1505         int irqn_not_used;
1506         int eqn;
1507         int err;
1508
1509         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1510             sizeof(u64) * cq->wq_ctrl.buf.npages;
1511         in = mlx5_vzalloc(inlen);
1512         if (in == NULL)
1513                 return (-ENOMEM);
1514
1515         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1516
1517         memcpy(cqc, param->cqc, sizeof(param->cqc));
1518
1519         mlx5_fill_page_array(&cq->wq_ctrl.buf,
1520             (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1521
1522         mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
1523
1524         MLX5_SET(cqc, cqc, c_eqn, eqn);
1525         MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1526         MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1527             PAGE_SHIFT);
1528         MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1529
1530         err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
1531
1532         kvfree(in);
1533
1534         if (err)
1535                 return (err);
1536
1537         mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock));
1538
1539         return (0);
1540 }
1541
1542 static void
1543 mlx5e_disable_cq(struct mlx5e_cq *cq)
1544 {
1545
1546         mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
1547 }
1548
1549 int
1550 mlx5e_open_cq(struct mlx5e_priv *priv,
1551     struct mlx5e_cq_param *param,
1552     struct mlx5e_cq *cq,
1553     mlx5e_cq_comp_t *comp,
1554     int eq_ix)
1555 {
1556         int err;
1557
1558         err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
1559         if (err)
1560                 return (err);
1561
1562         err = mlx5e_enable_cq(cq, param, eq_ix);
1563         if (err)
1564                 goto err_destroy_cq;
1565
1566         return (0);
1567
1568 err_destroy_cq:
1569         mlx5e_destroy_cq(cq);
1570
1571         return (err);
1572 }
1573
1574 void
1575 mlx5e_close_cq(struct mlx5e_cq *cq)
1576 {
1577         mlx5e_disable_cq(cq);
1578         mlx5e_destroy_cq(cq);
1579 }
1580
1581 static int
1582 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1583     struct mlx5e_channel_param *cparam)
1584 {
1585         int err;
1586         int tc;
1587
1588         for (tc = 0; tc < c->num_tc; tc++) {
1589                 /* open completion queue */
1590                 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
1591                     &mlx5e_tx_cq_comp, c->ix);
1592                 if (err)
1593                         goto err_close_tx_cqs;
1594         }
1595         return (0);
1596
1597 err_close_tx_cqs:
1598         for (tc--; tc >= 0; tc--)
1599                 mlx5e_close_cq(&c->sq[tc].cq);
1600
1601         return (err);
1602 }
1603
1604 static void
1605 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1606 {
1607         int tc;
1608
1609         for (tc = 0; tc < c->num_tc; tc++)
1610                 mlx5e_close_cq(&c->sq[tc].cq);
1611 }
1612
1613 static int
1614 mlx5e_open_sqs(struct mlx5e_channel *c,
1615     struct mlx5e_channel_param *cparam)
1616 {
1617         int err;
1618         int tc;
1619
1620         for (tc = 0; tc < c->num_tc; tc++) {
1621                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1622                 if (err)
1623                         goto err_close_sqs;
1624         }
1625
1626         return (0);
1627
1628 err_close_sqs:
1629         for (tc--; tc >= 0; tc--)
1630                 mlx5e_close_sq_wait(&c->sq[tc]);
1631
1632         return (err);
1633 }
1634
1635 static void
1636 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
1637 {
1638         int tc;
1639
1640         for (tc = 0; tc < c->num_tc; tc++)
1641                 mlx5e_close_sq_wait(&c->sq[tc]);
1642 }
1643
1644 static void
1645 mlx5e_chan_mtx_init(struct mlx5e_channel *c)
1646 {
1647         int tc;
1648
1649         mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
1650
1651         callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
1652
1653         for (tc = 0; tc < c->num_tc; tc++) {
1654                 struct mlx5e_sq *sq = c->sq + tc;
1655
1656                 mtx_init(&sq->lock, "mlx5tx",
1657                     MTX_NETWORK_LOCK " TX", MTX_DEF);
1658                 mtx_init(&sq->comp_lock, "mlx5comp",
1659                     MTX_NETWORK_LOCK " TX", MTX_DEF);
1660
1661                 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
1662
1663                 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1664
1665                 /* ensure the TX completion event factor is not zero */
1666                 if (sq->cev_factor == 0)
1667                         sq->cev_factor = 1;
1668         }
1669 }
1670
1671 static void
1672 mlx5e_chan_mtx_destroy(struct mlx5e_channel *c)
1673 {
1674         int tc;
1675
1676         mtx_destroy(&c->rq.mtx);
1677
1678         for (tc = 0; tc < c->num_tc; tc++) {
1679                 mtx_destroy(&c->sq[tc].lock);
1680                 mtx_destroy(&c->sq[tc].comp_lock);
1681         }
1682 }
1683
1684 static int
1685 mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1686     struct mlx5e_channel_param *cparam,
1687     struct mlx5e_channel *c)
1688 {
1689         int err;
1690
1691         memset(c, 0, sizeof(*c));
1692
1693         c->priv = priv;
1694         c->ix = ix;
1695         c->ifp = priv->ifp;
1696         c->mkey_be = cpu_to_be32(priv->mr.key);
1697         c->num_tc = priv->num_tc;
1698
1699         /* init mutexes */
1700         mlx5e_chan_mtx_init(c);
1701
1702         /* open transmit completion queue */
1703         err = mlx5e_open_tx_cqs(c, cparam);
1704         if (err)
1705                 goto err_free;
1706
1707         /* open receive completion queue */
1708         err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
1709             &mlx5e_rx_cq_comp, c->ix);
1710         if (err)
1711                 goto err_close_tx_cqs;
1712
1713         err = mlx5e_open_sqs(c, cparam);
1714         if (err)
1715                 goto err_close_rx_cq;
1716
1717         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1718         if (err)
1719                 goto err_close_sqs;
1720
1721         /* poll receive queue initially */
1722         c->rq.cq.mcq.comp(&c->rq.cq.mcq);
1723
1724         return (0);
1725
1726 err_close_sqs:
1727         mlx5e_close_sqs_wait(c);
1728
1729 err_close_rx_cq:
1730         mlx5e_close_cq(&c->rq.cq);
1731
1732 err_close_tx_cqs:
1733         mlx5e_close_tx_cqs(c);
1734
1735 err_free:
1736         /* destroy mutexes */
1737         mlx5e_chan_mtx_destroy(c);
1738         return (err);
1739 }
1740
1741 static void
1742 mlx5e_close_channel(struct mlx5e_channel *c)
1743 {
1744         mlx5e_close_rq(&c->rq);
1745 }
1746
1747 static void
1748 mlx5e_close_channel_wait(struct mlx5e_channel *c)
1749 {
1750         mlx5e_close_rq_wait(&c->rq);
1751         mlx5e_close_sqs_wait(c);
1752         mlx5e_close_tx_cqs(c);
1753         /* destroy mutexes */
1754         mlx5e_chan_mtx_destroy(c);
1755 }
1756
1757 static int
1758 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs)
1759 {
1760         u32 r, n;
1761
1762         r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz :
1763             MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
1764         if (r > MJUM16BYTES)
1765                 return (-ENOMEM);
1766
1767         if (r > MJUM9BYTES)
1768                 r = MJUM16BYTES;
1769         else if (r > MJUMPAGESIZE)
1770                 r = MJUM9BYTES;
1771         else if (r > MCLBYTES)
1772                 r = MJUMPAGESIZE;
1773         else
1774                 r = MCLBYTES;
1775
1776         /*
1777          * n + 1 must be a power of two, because stride size must be.
1778          * Stride size is 16 * (n + 1), as the first segment is
1779          * control.
1780          */
1781         for (n = howmany(r, MLX5E_MAX_RX_BYTES); !powerof2(n + 1); n++)
1782                 ;
1783
1784         *wqe_sz = r;
1785         *nsegs = n;
1786         return (0);
1787 }
1788
1789 static void
1790 mlx5e_build_rq_param(struct mlx5e_priv *priv,
1791     struct mlx5e_rq_param *param)
1792 {
1793         void *rqc = param->rqc;
1794         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1795         u32 wqe_sz, nsegs;
1796
1797         mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
1798         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1799         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1800         MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) +
1801             nsegs * sizeof(struct mlx5_wqe_data_seg)));
1802         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1803         MLX5_SET(wq, wq, pd, priv->pdn);
1804
1805         param->wq.buf_numa_node = 0;
1806         param->wq.db_numa_node = 0;
1807         param->wq.linear = 1;
1808 }
1809
1810 static void
1811 mlx5e_build_sq_param(struct mlx5e_priv *priv,
1812     struct mlx5e_sq_param *param)
1813 {
1814         void *sqc = param->sqc;
1815         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1816
1817         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1818         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1819         MLX5_SET(wq, wq, pd, priv->pdn);
1820
1821         param->wq.buf_numa_node = 0;
1822         param->wq.db_numa_node = 0;
1823         param->wq.linear = 1;
1824 }
1825
1826 static void
1827 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1828     struct mlx5e_cq_param *param)
1829 {
1830         void *cqc = param->cqc;
1831
1832         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1833 }
1834
1835 static void
1836 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr)
1837 {
1838
1839         *ptr = net_dim_get_profile(mode, MLX5E_DIM_DEFAULT_PROFILE);
1840
1841         /* apply LRO restrictions */
1842         if (priv->params.hw_lro_en &&
1843             ptr->pkts > MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO) {
1844                 ptr->pkts = MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO;
1845         }
1846 }
1847
1848 static void
1849 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1850     struct mlx5e_cq_param *param)
1851 {
1852         struct net_dim_cq_moder curr;
1853         void *cqc = param->cqc;
1854
1855
1856         /*
1857          * TODO The sysctl to control on/off is a bool value for now, which means
1858          * we only support CSUM, once HASH is implemnted we'll need to address that.
1859          */
1860         if (priv->params.cqe_zipping_en) {
1861                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1862                 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
1863         }
1864
1865         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1866
1867         switch (priv->params.rx_cq_moderation_mode) {
1868         case 0:
1869                 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1870                 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1871                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1872                 break;
1873         case 1:
1874                 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1875                 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1876                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1877                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1878                 else
1879                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1880                 break;
1881         case 2:
1882                 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr);
1883                 MLX5_SET(cqc, cqc, cq_period, curr.usec);
1884                 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
1885                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1886                 break;
1887         case 3:
1888                 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr);
1889                 MLX5_SET(cqc, cqc, cq_period, curr.usec);
1890                 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
1891                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1892                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1893                 else
1894                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1895                 break;
1896         default:
1897                 break;
1898         }
1899
1900         mlx5e_dim_build_cq_param(priv, param);
1901
1902         mlx5e_build_common_cq_param(priv, param);
1903 }
1904
1905 static void
1906 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1907     struct mlx5e_cq_param *param)
1908 {
1909         void *cqc = param->cqc;
1910
1911         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1912         MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
1913         MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
1914
1915         switch (priv->params.tx_cq_moderation_mode) {
1916         case 0:
1917                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1918                 break;
1919         default:
1920                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1921                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1922                 else
1923                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1924                 break;
1925         }
1926
1927         mlx5e_build_common_cq_param(priv, param);
1928 }
1929
1930 static void
1931 mlx5e_build_channel_param(struct mlx5e_priv *priv,
1932     struct mlx5e_channel_param *cparam)
1933 {
1934         memset(cparam, 0, sizeof(*cparam));
1935
1936         mlx5e_build_rq_param(priv, &cparam->rq);
1937         mlx5e_build_sq_param(priv, &cparam->sq);
1938         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1939         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1940 }
1941
1942 static int
1943 mlx5e_open_channels(struct mlx5e_priv *priv)
1944 {
1945         struct mlx5e_channel_param cparam;
1946         int err;
1947         int i;
1948         int j;
1949
1950         mlx5e_build_channel_param(priv, &cparam);
1951         for (i = 0; i < priv->params.num_channels; i++) {
1952                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1953                 if (err)
1954                         goto err_close_channels;
1955         }
1956
1957         for (j = 0; j < priv->params.num_channels; j++) {
1958                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j].rq);
1959                 if (err)
1960                         goto err_close_channels;
1961         }
1962
1963         return (0);
1964
1965 err_close_channels:
1966         while (i--) {
1967                 mlx5e_close_channel(&priv->channel[i]);
1968                 mlx5e_close_channel_wait(&priv->channel[i]);
1969         }
1970         return (err);
1971 }
1972
1973 static void
1974 mlx5e_close_channels(struct mlx5e_priv *priv)
1975 {
1976         int i;
1977
1978         for (i = 0; i < priv->params.num_channels; i++)
1979                 mlx5e_close_channel(&priv->channel[i]);
1980         for (i = 0; i < priv->params.num_channels; i++)
1981                 mlx5e_close_channel_wait(&priv->channel[i]);
1982 }
1983
1984 static int
1985 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
1986 {
1987
1988         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
1989                 uint8_t cq_mode;
1990
1991                 switch (priv->params.tx_cq_moderation_mode) {
1992                 case 0:
1993                 case 2:
1994                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1995                         break;
1996                 default:
1997                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
1998                         break;
1999                 }
2000
2001                 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq,
2002                     priv->params.tx_cq_moderation_usec,
2003                     priv->params.tx_cq_moderation_pkts,
2004                     cq_mode));
2005         }
2006
2007         return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
2008             priv->params.tx_cq_moderation_usec,
2009             priv->params.tx_cq_moderation_pkts));
2010 }
2011
2012 static int
2013 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
2014 {
2015
2016         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2017                 uint8_t cq_mode;
2018                 uint8_t dim_mode;
2019                 int retval;
2020
2021                 switch (priv->params.rx_cq_moderation_mode) {
2022                 case 0:
2023                 case 2:
2024                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2025                         dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2026                         break;
2027                 default:
2028                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2029                         dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
2030                         break;
2031                 }
2032
2033                 /* tear down dynamic interrupt moderation */
2034                 mtx_lock(&rq->mtx);
2035                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
2036                 mtx_unlock(&rq->mtx);
2037
2038                 /* wait for dynamic interrupt moderation work task, if any */
2039                 cancel_work_sync(&rq->dim.work);
2040
2041                 if (priv->params.rx_cq_moderation_mode >= 2) {
2042                         struct net_dim_cq_moder curr;
2043
2044                         mlx5e_get_default_profile(priv, dim_mode, &curr);
2045
2046                         retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2047                             curr.usec, curr.pkts, cq_mode);
2048
2049                         /* set dynamic interrupt moderation mode and zero defaults */
2050                         mtx_lock(&rq->mtx);
2051                         rq->dim.mode = dim_mode;
2052                         rq->dim.state = 0;
2053                         rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE;
2054                         mtx_unlock(&rq->mtx);
2055                 } else {
2056                         retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2057                             priv->params.rx_cq_moderation_usec,
2058                             priv->params.rx_cq_moderation_pkts,
2059                             cq_mode);
2060                 }
2061                 return (retval);
2062         }
2063
2064         return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
2065             priv->params.rx_cq_moderation_usec,
2066             priv->params.rx_cq_moderation_pkts));
2067 }
2068
2069 static int
2070 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
2071 {
2072         int err;
2073         int i;
2074
2075         err = mlx5e_refresh_rq_params(priv, &c->rq);
2076         if (err)
2077                 goto done;
2078
2079         for (i = 0; i != c->num_tc; i++) {
2080                 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
2081                 if (err)
2082                         goto done;
2083         }
2084 done:
2085         return (err);
2086 }
2087
2088 int
2089 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
2090 {
2091         int i;
2092
2093         /* check if channels are closed */
2094         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2095                 return (EINVAL);
2096
2097         for (i = 0; i < priv->params.num_channels; i++) {
2098                 int err;
2099
2100                 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]);
2101                 if (err)
2102                         return (err);
2103         }
2104         return (0);
2105 }
2106
2107 static int
2108 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
2109 {
2110         struct mlx5_core_dev *mdev = priv->mdev;
2111         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
2112         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2113
2114         memset(in, 0, sizeof(in));
2115
2116         MLX5_SET(tisc, tisc, prio, tc);
2117         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
2118
2119         return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
2120 }
2121
2122 static void
2123 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
2124 {
2125         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2126 }
2127
2128 static int
2129 mlx5e_open_tises(struct mlx5e_priv *priv)
2130 {
2131         int num_tc = priv->num_tc;
2132         int err;
2133         int tc;
2134
2135         for (tc = 0; tc < num_tc; tc++) {
2136                 err = mlx5e_open_tis(priv, tc);
2137                 if (err)
2138                         goto err_close_tises;
2139         }
2140
2141         return (0);
2142
2143 err_close_tises:
2144         for (tc--; tc >= 0; tc--)
2145                 mlx5e_close_tis(priv, tc);
2146
2147         return (err);
2148 }
2149
2150 static void
2151 mlx5e_close_tises(struct mlx5e_priv *priv)
2152 {
2153         int num_tc = priv->num_tc;
2154         int tc;
2155
2156         for (tc = 0; tc < num_tc; tc++)
2157                 mlx5e_close_tis(priv, tc);
2158 }
2159
2160 static int
2161 mlx5e_open_rqt(struct mlx5e_priv *priv)
2162 {
2163         struct mlx5_core_dev *mdev = priv->mdev;
2164         u32 *in;
2165         u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
2166         void *rqtc;
2167         int inlen;
2168         int err;
2169         int sz;
2170         int i;
2171
2172         sz = 1 << priv->params.rx_hash_log_tbl_sz;
2173
2174         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2175         in = mlx5_vzalloc(inlen);
2176         if (in == NULL)
2177                 return (-ENOMEM);
2178         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2179
2180         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2181         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2182
2183         for (i = 0; i < sz; i++) {
2184                 int ix = i;
2185 #ifdef RSS
2186                 ix = rss_get_indirection_to_bucket(ix);
2187 #endif
2188                 /* ensure we don't overflow */
2189                 ix %= priv->params.num_channels;
2190
2191                 /* apply receive side scaling stride, if any */
2192                 ix -= ix % (int)priv->params.channels_rsss;
2193
2194                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn);
2195         }
2196
2197         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
2198
2199         err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
2200         if (!err)
2201                 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
2202
2203         kvfree(in);
2204
2205         return (err);
2206 }
2207
2208 static void
2209 mlx5e_close_rqt(struct mlx5e_priv *priv)
2210 {
2211         u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0};
2212         u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0};
2213
2214         MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
2215         MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
2216
2217         mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out));
2218 }
2219
2220 static void
2221 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
2222 {
2223         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2224         __be32 *hkey;
2225
2226         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2227
2228 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2229
2230 #define MLX5_HASH_IP     (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2231                           MLX5_HASH_FIELD_SEL_DST_IP)
2232
2233 #define MLX5_HASH_ALL    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2234                           MLX5_HASH_FIELD_SEL_DST_IP   |\
2235                           MLX5_HASH_FIELD_SEL_L4_SPORT |\
2236                           MLX5_HASH_FIELD_SEL_L4_DPORT)
2237
2238 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2239                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2240                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2241
2242         if (priv->params.hw_lro_en) {
2243                 MLX5_SET(tirc, tirc, lro_enable_mask,
2244                     MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2245                     MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2246                 MLX5_SET(tirc, tirc, lro_max_msg_sz,
2247                     (priv->params.lro_wqe_sz -
2248                     ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2249                 /* TODO: add the option to choose timer value dynamically */
2250                 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
2251                     MLX5_CAP_ETH(priv->mdev,
2252                     lro_timer_supported_periods[2]));
2253         }
2254
2255         /* setup parameters for hashing TIR type, if any */
2256         switch (tt) {
2257         case MLX5E_TT_ANY:
2258                 MLX5_SET(tirc, tirc, disp_type,
2259                     MLX5_TIRC_DISP_TYPE_DIRECT);
2260                 MLX5_SET(tirc, tirc, inline_rqn,
2261                     priv->channel[0].rq.rqn);
2262                 break;
2263         default:
2264                 MLX5_SET(tirc, tirc, disp_type,
2265                     MLX5_TIRC_DISP_TYPE_INDIRECT);
2266                 MLX5_SET(tirc, tirc, indirect_table,
2267                     priv->rqtn);
2268                 MLX5_SET(tirc, tirc, rx_hash_fn,
2269                     MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
2270                 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
2271 #ifdef RSS
2272                 /*
2273                  * The FreeBSD RSS implementation does currently not
2274                  * support symmetric Toeplitz hashes:
2275                  */
2276                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
2277                 rss_getkey((uint8_t *)hkey);
2278 #else
2279                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2280                 hkey[0] = cpu_to_be32(0xD181C62C);
2281                 hkey[1] = cpu_to_be32(0xF7F4DB5B);
2282                 hkey[2] = cpu_to_be32(0x1983A2FC);
2283                 hkey[3] = cpu_to_be32(0x943E1ADB);
2284                 hkey[4] = cpu_to_be32(0xD9389E6B);
2285                 hkey[5] = cpu_to_be32(0xD1039C2C);
2286                 hkey[6] = cpu_to_be32(0xA74499AD);
2287                 hkey[7] = cpu_to_be32(0x593D56D9);
2288                 hkey[8] = cpu_to_be32(0xF3253C06);
2289                 hkey[9] = cpu_to_be32(0x2ADC1FFC);
2290 #endif
2291                 break;
2292         }
2293
2294         switch (tt) {
2295         case MLX5E_TT_IPV4_TCP:
2296                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2297                     MLX5_L3_PROT_TYPE_IPV4);
2298                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2299                     MLX5_L4_PROT_TYPE_TCP);
2300 #ifdef RSS
2301                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2302                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2303                             MLX5_HASH_IP);
2304                 } else
2305 #endif
2306                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2307                     MLX5_HASH_ALL);
2308                 break;
2309
2310         case MLX5E_TT_IPV6_TCP:
2311                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2312                     MLX5_L3_PROT_TYPE_IPV6);
2313                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2314                     MLX5_L4_PROT_TYPE_TCP);
2315 #ifdef RSS
2316                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2317                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2318                             MLX5_HASH_IP);
2319                 } else
2320 #endif
2321                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2322                     MLX5_HASH_ALL);
2323                 break;
2324
2325         case MLX5E_TT_IPV4_UDP:
2326                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2327                     MLX5_L3_PROT_TYPE_IPV4);
2328                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2329                     MLX5_L4_PROT_TYPE_UDP);
2330 #ifdef RSS
2331                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2332                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2333                             MLX5_HASH_IP);
2334                 } else
2335 #endif
2336                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2337                     MLX5_HASH_ALL);
2338                 break;
2339
2340         case MLX5E_TT_IPV6_UDP:
2341                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2342                     MLX5_L3_PROT_TYPE_IPV6);
2343                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2344                     MLX5_L4_PROT_TYPE_UDP);
2345 #ifdef RSS
2346                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2347                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2348                             MLX5_HASH_IP);
2349                 } else
2350 #endif
2351                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2352                     MLX5_HASH_ALL);
2353                 break;
2354
2355         case MLX5E_TT_IPV4_IPSEC_AH:
2356                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2357                     MLX5_L3_PROT_TYPE_IPV4);
2358                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2359                     MLX5_HASH_IP_IPSEC_SPI);
2360                 break;
2361
2362         case MLX5E_TT_IPV6_IPSEC_AH:
2363                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2364                     MLX5_L3_PROT_TYPE_IPV6);
2365                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2366                     MLX5_HASH_IP_IPSEC_SPI);
2367                 break;
2368
2369         case MLX5E_TT_IPV4_IPSEC_ESP:
2370                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2371                     MLX5_L3_PROT_TYPE_IPV4);
2372                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2373                     MLX5_HASH_IP_IPSEC_SPI);
2374                 break;
2375
2376         case MLX5E_TT_IPV6_IPSEC_ESP:
2377                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2378                     MLX5_L3_PROT_TYPE_IPV6);
2379                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2380                     MLX5_HASH_IP_IPSEC_SPI);
2381                 break;
2382
2383         case MLX5E_TT_IPV4:
2384                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2385                     MLX5_L3_PROT_TYPE_IPV4);
2386                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2387                     MLX5_HASH_IP);
2388                 break;
2389
2390         case MLX5E_TT_IPV6:
2391                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2392                     MLX5_L3_PROT_TYPE_IPV6);
2393                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2394                     MLX5_HASH_IP);
2395                 break;
2396
2397         default:
2398                 break;
2399         }
2400 }
2401
2402 static int
2403 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2404 {
2405         struct mlx5_core_dev *mdev = priv->mdev;
2406         u32 *in;
2407         void *tirc;
2408         int inlen;
2409         int err;
2410
2411         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2412         in = mlx5_vzalloc(inlen);
2413         if (in == NULL)
2414                 return (-ENOMEM);
2415         tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2416
2417         mlx5e_build_tir_ctx(priv, tirc, tt);
2418
2419         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2420
2421         kvfree(in);
2422
2423         return (err);
2424 }
2425
2426 static void
2427 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2428 {
2429         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2430 }
2431
2432 static int
2433 mlx5e_open_tirs(struct mlx5e_priv *priv)
2434 {
2435         int err;
2436         int i;
2437
2438         for (i = 0; i < MLX5E_NUM_TT; i++) {
2439                 err = mlx5e_open_tir(priv, i);
2440                 if (err)
2441                         goto err_close_tirs;
2442         }
2443
2444         return (0);
2445
2446 err_close_tirs:
2447         for (i--; i >= 0; i--)
2448                 mlx5e_close_tir(priv, i);
2449
2450         return (err);
2451 }
2452
2453 static void
2454 mlx5e_close_tirs(struct mlx5e_priv *priv)
2455 {
2456         int i;
2457
2458         for (i = 0; i < MLX5E_NUM_TT; i++)
2459                 mlx5e_close_tir(priv, i);
2460 }
2461
2462 /*
2463  * SW MTU does not include headers,
2464  * HW MTU includes all headers and checksums.
2465  */
2466 static int
2467 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2468 {
2469         struct mlx5e_priv *priv = ifp->if_softc;
2470         struct mlx5_core_dev *mdev = priv->mdev;
2471         int hw_mtu;
2472         int err;
2473
2474         hw_mtu = MLX5E_SW2HW_MTU(sw_mtu);
2475
2476         err = mlx5_set_port_mtu(mdev, hw_mtu);
2477         if (err) {
2478                 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n",
2479                     __func__, sw_mtu, err);
2480                 return (err);
2481         }
2482
2483         /* Update vport context MTU */
2484         err = mlx5_set_vport_mtu(mdev, hw_mtu);
2485         if (err) {
2486                 if_printf(ifp, "%s: Failed updating vport context with MTU size, err=%d\n",
2487                     __func__, err);
2488         }
2489
2490         ifp->if_mtu = sw_mtu;
2491
2492         err = mlx5_query_vport_mtu(mdev, &hw_mtu);
2493         if (err || !hw_mtu) {
2494                 /* fallback to port oper mtu */
2495                 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2496         }
2497         if (err) {
2498                 if_printf(ifp, "Query port MTU, after setting new "
2499                     "MTU value, failed\n");
2500                 return (err);
2501         } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
2502                 err = -E2BIG,
2503                 if_printf(ifp, "Port MTU %d is smaller than "
2504                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2505         } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
2506                 err = -EINVAL;
2507                 if_printf(ifp, "Port MTU %d is bigger than "
2508                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2509         }
2510         priv->params_ethtool.hw_mtu = hw_mtu;
2511
2512         return (err);
2513 }
2514
2515 int
2516 mlx5e_open_locked(struct ifnet *ifp)
2517 {
2518         struct mlx5e_priv *priv = ifp->if_softc;
2519         int err;
2520         u16 set_id;
2521
2522         /* check if already opened */
2523         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2524                 return (0);
2525
2526 #ifdef RSS
2527         if (rss_getnumbuckets() > priv->params.num_channels) {
2528                 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than "
2529                     "channels(%u) available\n", rss_getnumbuckets(),
2530                     priv->params.num_channels);
2531         }
2532 #endif
2533         err = mlx5e_open_tises(priv);
2534         if (err) {
2535                 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n",
2536                     __func__, err);
2537                 return (err);
2538         }
2539         err = mlx5_vport_alloc_q_counter(priv->mdev,
2540             MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
2541         if (err) {
2542                 if_printf(priv->ifp,
2543                     "%s: mlx5_vport_alloc_q_counter failed: %d\n",
2544                     __func__, err);
2545                 goto err_close_tises;
2546         }
2547         /* store counter set ID */
2548         priv->counter_set_id = set_id;
2549
2550         err = mlx5e_open_channels(priv);
2551         if (err) {
2552                 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n",
2553                     __func__, err);
2554                 goto err_dalloc_q_counter;
2555         }
2556         err = mlx5e_open_rqt(priv);
2557         if (err) {
2558                 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n",
2559                     __func__, err);
2560                 goto err_close_channels;
2561         }
2562         err = mlx5e_open_tirs(priv);
2563         if (err) {
2564                 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n",
2565                     __func__, err);
2566                 goto err_close_rqls;
2567         }
2568         err = mlx5e_open_flow_table(priv);
2569         if (err) {
2570                 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n",
2571                     __func__, err);
2572                 goto err_close_tirs;
2573         }
2574         err = mlx5e_add_all_vlan_rules(priv);
2575         if (err) {
2576                 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
2577                     __func__, err);
2578                 goto err_close_flow_table;
2579         }
2580         set_bit(MLX5E_STATE_OPENED, &priv->state);
2581
2582         mlx5e_update_carrier(priv);
2583         mlx5e_set_rx_mode_core(priv);
2584
2585         return (0);
2586
2587 err_close_flow_table:
2588         mlx5e_close_flow_table(priv);
2589
2590 err_close_tirs:
2591         mlx5e_close_tirs(priv);
2592
2593 err_close_rqls:
2594         mlx5e_close_rqt(priv);
2595
2596 err_close_channels:
2597         mlx5e_close_channels(priv);
2598
2599 err_dalloc_q_counter:
2600         mlx5_vport_dealloc_q_counter(priv->mdev,
2601             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2602
2603 err_close_tises:
2604         mlx5e_close_tises(priv);
2605
2606         return (err);
2607 }
2608
2609 static void
2610 mlx5e_open(void *arg)
2611 {
2612         struct mlx5e_priv *priv = arg;
2613
2614         PRIV_LOCK(priv);
2615         if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
2616                 if_printf(priv->ifp,
2617                     "%s: Setting port status to up failed\n",
2618                     __func__);
2619
2620         mlx5e_open_locked(priv->ifp);
2621         priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
2622         PRIV_UNLOCK(priv);
2623 }
2624
2625 int
2626 mlx5e_close_locked(struct ifnet *ifp)
2627 {
2628         struct mlx5e_priv *priv = ifp->if_softc;
2629
2630         /* check if already closed */
2631         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2632                 return (0);
2633
2634         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2635
2636         mlx5e_set_rx_mode_core(priv);
2637         mlx5e_del_all_vlan_rules(priv);
2638         if_link_state_change(priv->ifp, LINK_STATE_DOWN);
2639         mlx5e_close_flow_table(priv);
2640         mlx5e_close_tirs(priv);
2641         mlx5e_close_rqt(priv);
2642         mlx5e_close_channels(priv);
2643         mlx5_vport_dealloc_q_counter(priv->mdev,
2644             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2645         mlx5e_close_tises(priv);
2646
2647         return (0);
2648 }
2649
2650 #if (__FreeBSD_version >= 1100000)
2651 static uint64_t
2652 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
2653 {
2654         struct mlx5e_priv *priv = ifp->if_softc;
2655         u64 retval;
2656
2657         /* PRIV_LOCK(priv); XXX not allowed */
2658         switch (cnt) {
2659         case IFCOUNTER_IPACKETS:
2660                 retval = priv->stats.vport.rx_packets;
2661                 break;
2662         case IFCOUNTER_IERRORS:
2663                 retval = priv->stats.vport.rx_error_packets +
2664                     priv->stats.pport.alignment_err +
2665                     priv->stats.pport.check_seq_err +
2666                     priv->stats.pport.crc_align_errors +
2667                     priv->stats.pport.in_range_len_errors +
2668                     priv->stats.pport.jabbers +
2669                     priv->stats.pport.out_of_range_len +
2670                     priv->stats.pport.oversize_pkts +
2671                     priv->stats.pport.symbol_err +
2672                     priv->stats.pport.too_long_errors +
2673                     priv->stats.pport.undersize_pkts +
2674                     priv->stats.pport.unsupported_op_rx;
2675                 break;
2676         case IFCOUNTER_IQDROPS:
2677                 retval = priv->stats.vport.rx_out_of_buffer +
2678                     priv->stats.pport.drop_events;
2679                 break;
2680         case IFCOUNTER_OPACKETS:
2681                 retval = priv->stats.vport.tx_packets;
2682                 break;
2683         case IFCOUNTER_OERRORS:
2684                 retval = priv->stats.vport.tx_error_packets;
2685                 break;
2686         case IFCOUNTER_IBYTES:
2687                 retval = priv->stats.vport.rx_bytes;
2688                 break;
2689         case IFCOUNTER_OBYTES:
2690                 retval = priv->stats.vport.tx_bytes;
2691                 break;
2692         case IFCOUNTER_IMCASTS:
2693                 retval = priv->stats.vport.rx_multicast_packets;
2694                 break;
2695         case IFCOUNTER_OMCASTS:
2696                 retval = priv->stats.vport.tx_multicast_packets;
2697                 break;
2698         case IFCOUNTER_OQDROPS:
2699                 retval = priv->stats.vport.tx_queue_dropped;
2700                 break;
2701         case IFCOUNTER_COLLISIONS:
2702                 retval = priv->stats.pport.collisions;
2703                 break;
2704         default:
2705                 retval = if_get_counter_default(ifp, cnt);
2706                 break;
2707         }
2708         /* PRIV_UNLOCK(priv); XXX not allowed */
2709         return (retval);
2710 }
2711 #endif
2712
2713 static void
2714 mlx5e_set_rx_mode(struct ifnet *ifp)
2715 {
2716         struct mlx5e_priv *priv = ifp->if_softc;
2717
2718         queue_work(priv->wq, &priv->set_rx_mode_work);
2719 }
2720
2721 static int
2722 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2723 {
2724         struct mlx5e_priv *priv;
2725         struct ifreq *ifr;
2726         struct ifi2creq i2c;
2727         int error = 0;
2728         int mask = 0;
2729         int size_read = 0;
2730         int module_status;
2731         int module_num;
2732         int max_mtu;
2733         uint8_t read_addr;
2734
2735         priv = ifp->if_softc;
2736
2737         /* check if detaching */
2738         if (priv == NULL || priv->gone != 0)
2739                 return (ENXIO);
2740
2741         switch (command) {
2742         case SIOCSIFMTU:
2743                 ifr = (struct ifreq *)data;
2744
2745                 PRIV_LOCK(priv);
2746                 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
2747
2748                 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
2749                     ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
2750                         int was_opened;
2751
2752                         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2753                         if (was_opened)
2754                                 mlx5e_close_locked(ifp);
2755
2756                         /* set new MTU */
2757                         mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
2758
2759                         if (was_opened)
2760                                 mlx5e_open_locked(ifp);
2761                 } else {
2762                         error = EINVAL;
2763                         if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n",
2764                             MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
2765                 }
2766                 PRIV_UNLOCK(priv);
2767                 break;
2768         case SIOCSIFFLAGS:
2769                 if ((ifp->if_flags & IFF_UP) &&
2770                     (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2771                         mlx5e_set_rx_mode(ifp);
2772                         break;
2773                 }
2774                 PRIV_LOCK(priv);
2775                 if (ifp->if_flags & IFF_UP) {
2776                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2777                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2778                                         mlx5e_open_locked(ifp);
2779                                 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2780                                 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
2781                         }
2782                 } else {
2783                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2784                                 mlx5_set_port_status(priv->mdev,
2785                                     MLX5_PORT_DOWN);
2786                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2787                                         mlx5e_close_locked(ifp);
2788                                 mlx5e_update_carrier(priv);
2789                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2790                         }
2791                 }
2792                 PRIV_UNLOCK(priv);
2793                 break;
2794         case SIOCADDMULTI:
2795         case SIOCDELMULTI:
2796                 mlx5e_set_rx_mode(ifp);
2797                 break;
2798         case SIOCSIFMEDIA:
2799         case SIOCGIFMEDIA:
2800         case SIOCGIFXMEDIA:
2801                 ifr = (struct ifreq *)data;
2802                 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
2803                 break;
2804         case SIOCSIFCAP:
2805                 ifr = (struct ifreq *)data;
2806                 PRIV_LOCK(priv);
2807                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2808
2809                 if (mask & IFCAP_TXCSUM) {
2810                         ifp->if_capenable ^= IFCAP_TXCSUM;
2811                         ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2812
2813                         if (IFCAP_TSO4 & ifp->if_capenable &&
2814                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2815                                 ifp->if_capenable &= ~IFCAP_TSO4;
2816                                 ifp->if_hwassist &= ~CSUM_IP_TSO;
2817                                 if_printf(ifp,
2818                                     "tso4 disabled due to -txcsum.\n");
2819                         }
2820                 }
2821                 if (mask & IFCAP_TXCSUM_IPV6) {
2822                         ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
2823                         ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2824
2825                         if (IFCAP_TSO6 & ifp->if_capenable &&
2826                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2827                                 ifp->if_capenable &= ~IFCAP_TSO6;
2828                                 ifp->if_hwassist &= ~CSUM_IP6_TSO;
2829                                 if_printf(ifp,
2830                                     "tso6 disabled due to -txcsum6.\n");
2831                         }
2832                 }
2833                 if (mask & IFCAP_RXCSUM)
2834                         ifp->if_capenable ^= IFCAP_RXCSUM;
2835                 if (mask & IFCAP_RXCSUM_IPV6)
2836                         ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
2837                 if (mask & IFCAP_TSO4) {
2838                         if (!(IFCAP_TSO4 & ifp->if_capenable) &&
2839                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2840                                 if_printf(ifp, "enable txcsum first.\n");
2841                                 error = EAGAIN;
2842                                 goto out;
2843                         }
2844                         ifp->if_capenable ^= IFCAP_TSO4;
2845                         ifp->if_hwassist ^= CSUM_IP_TSO;
2846                 }
2847                 if (mask & IFCAP_TSO6) {
2848                         if (!(IFCAP_TSO6 & ifp->if_capenable) &&
2849                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2850                                 if_printf(ifp, "enable txcsum6 first.\n");
2851                                 error = EAGAIN;
2852                                 goto out;
2853                         }
2854                         ifp->if_capenable ^= IFCAP_TSO6;
2855                         ifp->if_hwassist ^= CSUM_IP6_TSO;
2856                 }
2857                 if (mask & IFCAP_VLAN_HWFILTER) {
2858                         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
2859                                 mlx5e_disable_vlan_filter(priv);
2860                         else
2861                                 mlx5e_enable_vlan_filter(priv);
2862
2863                         ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
2864                 }
2865                 if (mask & IFCAP_VLAN_HWTAGGING)
2866                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2867                 if (mask & IFCAP_WOL_MAGIC)
2868                         ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2869
2870                 VLAN_CAPABILITIES(ifp);
2871                 /* turn off LRO means also turn of HW LRO - if it's on */
2872                 if (mask & IFCAP_LRO) {
2873                         int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2874                         bool need_restart = false;
2875
2876                         ifp->if_capenable ^= IFCAP_LRO;
2877
2878                         /* figure out if updating HW LRO is needed */
2879                         if (!(ifp->if_capenable & IFCAP_LRO)) {
2880                                 if (priv->params.hw_lro_en) {
2881                                         priv->params.hw_lro_en = false;
2882                                         need_restart = true;
2883                                 }
2884                         } else {
2885                                 if (priv->params.hw_lro_en == false &&
2886                                     priv->params_ethtool.hw_lro != 0) {
2887                                         priv->params.hw_lro_en = true;
2888                                         need_restart = true;
2889                                 }
2890                         }
2891                         if (was_opened && need_restart) {
2892                                 mlx5e_close_locked(ifp);
2893                                 mlx5e_open_locked(ifp);
2894                         }
2895                 }
2896 out:
2897                 PRIV_UNLOCK(priv);
2898                 break;
2899
2900         case SIOCGI2C:
2901                 ifr = (struct ifreq *)data;
2902
2903                 /*
2904                  * Copy from the user-space address ifr_data to the
2905                  * kernel-space address i2c
2906                  */
2907                 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
2908                 if (error)
2909                         break;
2910
2911                 if (i2c.len > sizeof(i2c.data)) {
2912                         error = EINVAL;
2913                         break;
2914                 }
2915
2916                 PRIV_LOCK(priv);
2917                 /* Get module_num which is required for the query_eeprom */
2918                 error = mlx5_query_module_num(priv->mdev, &module_num);
2919                 if (error) {
2920                         if_printf(ifp, "Query module num failed, eeprom "
2921                             "reading is not supported\n");
2922                         error = EINVAL;
2923                         goto err_i2c;
2924                 }
2925                 /* Check if module is present before doing an access */
2926                 module_status = mlx5_query_module_status(priv->mdev, module_num);
2927                 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED &&
2928                     module_status != MLX5_MODULE_STATUS_PLUGGED_DISABLED) {
2929                         error = EINVAL;
2930                         goto err_i2c;
2931                 }
2932                 /*
2933                  * Currently 0XA0 and 0xA2 are the only addresses permitted.
2934                  * The internal conversion is as follows:
2935                  */
2936                 if (i2c.dev_addr == 0xA0)
2937                         read_addr = MLX5E_I2C_ADDR_LOW;
2938                 else if (i2c.dev_addr == 0xA2)
2939                         read_addr = MLX5E_I2C_ADDR_HIGH;
2940                 else {
2941                         if_printf(ifp, "Query eeprom failed, "
2942                             "Invalid Address: %X\n", i2c.dev_addr);
2943                         error = EINVAL;
2944                         goto err_i2c;
2945                 }
2946                 error = mlx5_query_eeprom(priv->mdev,
2947                     read_addr, MLX5E_EEPROM_LOW_PAGE,
2948                     (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
2949                     (uint32_t *)i2c.data, &size_read);
2950                 if (error) {
2951                         if_printf(ifp, "Query eeprom failed, eeprom "
2952                             "reading is not supported\n");
2953                         error = EINVAL;
2954                         goto err_i2c;
2955                 }
2956
2957                 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
2958                         error = mlx5_query_eeprom(priv->mdev,
2959                             read_addr, MLX5E_EEPROM_LOW_PAGE,
2960                             (uint32_t)(i2c.offset + size_read),
2961                             (uint32_t)(i2c.len - size_read), module_num,
2962                             (uint32_t *)(i2c.data + size_read), &size_read);
2963                 }
2964                 if (error) {
2965                         if_printf(ifp, "Query eeprom failed, eeprom "
2966                             "reading is not supported\n");
2967                         error = EINVAL;
2968                         goto err_i2c;
2969                 }
2970
2971                 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
2972 err_i2c:
2973                 PRIV_UNLOCK(priv);
2974                 break;
2975
2976         default:
2977                 error = ether_ioctl(ifp, command, data);
2978                 break;
2979         }
2980         return (error);
2981 }
2982
2983 static int
2984 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2985 {
2986         /*
2987          * TODO: uncoment once FW really sets all these bits if
2988          * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
2989          * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
2990          * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
2991          * -ENOTSUPP;
2992          */
2993
2994         /* TODO: add more must-to-have features */
2995
2996         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2997                 return (-ENODEV);
2998
2999         return (0);
3000 }
3001
3002 static u16
3003 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3004 {
3005         uint32_t bf_buf_size = (1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U;
3006
3007         bf_buf_size -= sizeof(struct mlx5e_tx_wqe) - 2;
3008
3009         /* verify against driver hardware limit */
3010         if (bf_buf_size > MLX5E_MAX_TX_INLINE)
3011                 bf_buf_size = MLX5E_MAX_TX_INLINE;
3012
3013         return (bf_buf_size);
3014 }
3015
3016 static int
3017 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
3018     struct mlx5e_priv *priv,
3019     int num_comp_vectors)
3020 {
3021         int err;
3022
3023         /*
3024          * TODO: Consider link speed for setting "log_sq_size",
3025          * "log_rq_size" and "cq_moderation_xxx":
3026          */
3027         priv->params.log_sq_size =
3028             MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3029         priv->params.log_rq_size =
3030             MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3031         priv->params.rx_cq_moderation_usec =
3032             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3033             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
3034             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3035         priv->params.rx_cq_moderation_mode =
3036             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
3037         priv->params.rx_cq_moderation_pkts =
3038             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3039         priv->params.tx_cq_moderation_usec =
3040             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3041         priv->params.tx_cq_moderation_pkts =
3042             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3043         priv->params.min_rx_wqes =
3044             MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
3045         priv->params.rx_hash_log_tbl_sz =
3046             (order_base_2(num_comp_vectors) >
3047             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
3048             order_base_2(num_comp_vectors) :
3049             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
3050         priv->params.num_tc = 1;
3051         priv->params.default_vlan_prio = 0;
3052         priv->counter_set_id = -1;
3053         priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3054
3055         err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3056         if (err)
3057                 return (err);
3058
3059         /*
3060          * hw lro is currently defaulted to off. when it won't anymore we
3061          * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
3062          */
3063         priv->params.hw_lro_en = false;
3064         priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3065
3066         priv->params.cqe_zipping_en = !!MLX5_CAP_GEN(mdev, cqe_compression);
3067
3068         priv->mdev = mdev;
3069         priv->params.num_channels = num_comp_vectors;
3070         priv->params.channels_rsss = 1;
3071         priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
3072         priv->queue_mapping_channel_mask =
3073             roundup_pow_of_two(num_comp_vectors) - 1;
3074         priv->num_tc = priv->params.num_tc;
3075         priv->default_vlan_prio = priv->params.default_vlan_prio;
3076
3077         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3078         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3079         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3080
3081         return (0);
3082 }
3083
3084 static int
3085 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
3086                   struct mlx5_core_mr *mkey)
3087 {
3088         struct ifnet *ifp = priv->ifp;
3089         struct mlx5_core_dev *mdev = priv->mdev;
3090         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3091         void *mkc;
3092         u32 *in;
3093         int err;
3094
3095         in = mlx5_vzalloc(inlen);
3096         if (in == NULL) {
3097                 if_printf(ifp, "%s: failed to allocate inbox\n", __func__);
3098                 return (-ENOMEM);
3099         }
3100
3101         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3102         MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA);
3103         MLX5_SET(mkc, mkc, lw, 1);
3104         MLX5_SET(mkc, mkc, lr, 1);
3105
3106         MLX5_SET(mkc, mkc, pd, pdn);
3107         MLX5_SET(mkc, mkc, length64, 1);
3108         MLX5_SET(mkc, mkc, qpn, 0xffffff);
3109
3110         err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
3111         if (err)
3112                 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n",
3113                     __func__, err);
3114
3115         kvfree(in);
3116         return (err);
3117 }
3118
3119 static const char *mlx5e_vport_stats_desc[] = {
3120         MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
3121 };
3122
3123 static const char *mlx5e_pport_stats_desc[] = {
3124         MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
3125 };
3126
3127 static void
3128 mlx5e_priv_mtx_init(struct mlx5e_priv *priv)
3129 {
3130         mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
3131         sx_init(&priv->state_lock, "mlx5state");
3132         callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
3133         MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
3134 }
3135
3136 static void
3137 mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv)
3138 {
3139         mtx_destroy(&priv->async_events_mtx);
3140         sx_destroy(&priv->state_lock);
3141 }
3142
3143 static int
3144 sysctl_firmware(SYSCTL_HANDLER_ARGS)
3145 {
3146         /*
3147          * %d.%d%.d the string format.
3148          * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
3149          * We need at most 5 chars to store that.
3150          * It also has: two "." and NULL at the end, which means we need 18
3151          * (5*3 + 3) chars at most.
3152          */
3153         char fw[18];
3154         struct mlx5e_priv *priv = arg1;
3155         int error;
3156
3157         snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
3158             fw_rev_sub(priv->mdev));
3159         error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
3160         return (error);
3161 }
3162
3163 static void
3164 mlx5e_disable_tx_dma(struct mlx5e_channel *ch)
3165 {
3166         int i;
3167
3168         for (i = 0; i < ch->num_tc; i++)
3169                 mlx5e_drain_sq(&ch->sq[i]);
3170 }
3171
3172 static void
3173 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq)
3174 {
3175
3176         sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP);
3177         sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8);
3178         mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
3179         sq->doorbell.d64 = 0;
3180 }
3181
3182 void
3183 mlx5e_resume_sq(struct mlx5e_sq *sq)
3184 {
3185         int err;
3186
3187         /* check if already enabled */
3188         if (READ_ONCE(sq->running) != 0)
3189                 return;
3190
3191         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR,
3192             MLX5_SQC_STATE_RST);
3193         if (err != 0) {
3194                 if_printf(sq->ifp,
3195                     "mlx5e_modify_sq() from ERR to RST failed: %d\n", err);
3196         }
3197
3198         sq->cc = 0;
3199         sq->pc = 0;
3200
3201         /* reset doorbell prior to moving from RST to RDY */
3202         mlx5e_reset_sq_doorbell_record(sq);
3203
3204         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST,
3205             MLX5_SQC_STATE_RDY);
3206         if (err != 0) {
3207                 if_printf(sq->ifp,
3208                     "mlx5e_modify_sq() from RST to RDY failed: %d\n", err);
3209         }
3210
3211         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
3212         WRITE_ONCE(sq->running, 1);
3213 }
3214
3215 static void
3216 mlx5e_enable_tx_dma(struct mlx5e_channel *ch)
3217 {
3218         int i;
3219
3220         for (i = 0; i < ch->num_tc; i++)
3221                 mlx5e_resume_sq(&ch->sq[i]);
3222 }
3223
3224 static void
3225 mlx5e_disable_rx_dma(struct mlx5e_channel *ch)
3226 {
3227         struct mlx5e_rq *rq = &ch->rq;
3228         int err;
3229
3230         mtx_lock(&rq->mtx);
3231         rq->enabled = 0;
3232         callout_stop(&rq->watchdog);
3233         mtx_unlock(&rq->mtx);
3234
3235         callout_drain(&rq->watchdog);
3236
3237         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
3238         if (err != 0) {
3239                 if_printf(rq->ifp,
3240                     "mlx5e_modify_rq() from RDY to RST failed: %d\n", err);
3241         }
3242
3243         while (!mlx5_wq_ll_is_empty(&rq->wq)) {
3244                 msleep(1);
3245                 rq->cq.mcq.comp(&rq->cq.mcq);
3246         }
3247
3248         /*
3249          * Transitioning into RST state will allow the FW to track less ERR state queues,
3250          * thus reducing the recv queue flushing time
3251          */
3252         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST);
3253         if (err != 0) {
3254                 if_printf(rq->ifp,
3255                     "mlx5e_modify_rq() from ERR to RST failed: %d\n", err);
3256         }
3257 }
3258
3259 static void
3260 mlx5e_enable_rx_dma(struct mlx5e_channel *ch)
3261 {
3262         struct mlx5e_rq *rq = &ch->rq;
3263         int err;
3264
3265         rq->wq.wqe_ctr = 0;
3266         mlx5_wq_ll_update_db_record(&rq->wq);
3267         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3268         if (err != 0) {
3269                 if_printf(rq->ifp,
3270                     "mlx5e_modify_rq() from RST to RDY failed: %d\n", err);
3271         }
3272
3273         rq->enabled = 1;
3274
3275         rq->cq.mcq.comp(&rq->cq.mcq);
3276 }
3277
3278 void
3279 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value)
3280 {
3281         int i;
3282
3283         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3284                 return;
3285
3286         for (i = 0; i < priv->params.num_channels; i++) {
3287                 if (value)
3288                         mlx5e_disable_tx_dma(&priv->channel[i]);
3289                 else
3290                         mlx5e_enable_tx_dma(&priv->channel[i]);
3291         }
3292 }
3293
3294 void
3295 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value)
3296 {
3297         int i;
3298
3299         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3300                 return;
3301
3302         for (i = 0; i < priv->params.num_channels; i++) {
3303                 if (value)
3304                         mlx5e_disable_rx_dma(&priv->channel[i]);
3305                 else
3306                         mlx5e_enable_rx_dma(&priv->channel[i]);
3307         }
3308 }
3309
3310 static void
3311 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
3312 {
3313         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3314             OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
3315             sysctl_firmware, "A", "HCA firmware version");
3316
3317         SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3318             OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
3319             "Board ID");
3320 }
3321
3322 static int
3323 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3324 {
3325         struct mlx5e_priv *priv = arg1;
3326         uint8_t temp[MLX5E_MAX_PRIORITY];
3327         uint32_t tx_pfc;
3328         int err;
3329         int i;
3330
3331         PRIV_LOCK(priv);
3332
3333         tx_pfc = priv->params.tx_priority_flow_control;
3334
3335         for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3336                 temp[i] = (tx_pfc >> i) & 1;
3337
3338         err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3339         if (err || !req->newptr)
3340                 goto done;
3341         err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3342         if (err)
3343                 goto done;
3344
3345         priv->params.tx_priority_flow_control = 0;
3346
3347         /* range check input value */
3348         for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3349                 if (temp[i] > 1) {
3350                         err = ERANGE;
3351                         goto done;
3352                 }
3353                 priv->params.tx_priority_flow_control |= (temp[i] << i);
3354         }
3355
3356         /* check if update is required */
3357         if (tx_pfc != priv->params.tx_priority_flow_control)
3358                 err = -mlx5e_set_port_pfc(priv);
3359 done:
3360         if (err != 0)
3361                 priv->params.tx_priority_flow_control= tx_pfc;
3362         PRIV_UNLOCK(priv);
3363
3364         return (err);
3365 }
3366
3367 static int
3368 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3369 {
3370         struct mlx5e_priv *priv = arg1;
3371         uint8_t temp[MLX5E_MAX_PRIORITY];
3372         uint32_t rx_pfc;
3373         int err;
3374         int i;
3375
3376         PRIV_LOCK(priv);
3377
3378         rx_pfc = priv->params.rx_priority_flow_control;
3379
3380         for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3381                 temp[i] = (rx_pfc >> i) & 1;
3382
3383         err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3384         if (err || !req->newptr)
3385                 goto done;
3386         err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3387         if (err)
3388                 goto done;
3389
3390         priv->params.rx_priority_flow_control = 0;
3391
3392         /* range check input value */
3393         for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3394                 if (temp[i] > 1) {
3395                         err = ERANGE;
3396                         goto done;
3397                 }
3398                 priv->params.rx_priority_flow_control |= (temp[i] << i);
3399         }
3400
3401         /* check if update is required */
3402         if (rx_pfc != priv->params.rx_priority_flow_control)
3403                 err = -mlx5e_set_port_pfc(priv);
3404 done:
3405         if (err != 0)
3406                 priv->params.rx_priority_flow_control= rx_pfc;
3407         PRIV_UNLOCK(priv);
3408
3409         return (err);
3410 }
3411
3412 static void
3413 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
3414 {
3415 #if (__FreeBSD_version < 1100000)
3416         char path[96];
3417 #endif
3418         int error;
3419
3420         /* enable pauseframes by default */
3421         priv->params.tx_pauseframe_control = 1;
3422         priv->params.rx_pauseframe_control = 1;
3423
3424         /* disable ports flow control, PFC, by default */
3425         priv->params.tx_priority_flow_control = 0;
3426         priv->params.rx_priority_flow_control = 0;
3427
3428 #if (__FreeBSD_version < 1100000)
3429         /* compute path for sysctl */
3430         snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
3431             device_get_unit(priv->mdev->pdev->dev.bsddev));
3432
3433         /* try to fetch tunable, if any */
3434         TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
3435
3436         /* compute path for sysctl */
3437         snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
3438             device_get_unit(priv->mdev->pdev->dev.bsddev));
3439
3440         /* try to fetch tunable, if any */
3441         TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
3442 #endif
3443
3444         /* register pauseframe SYSCTLs */
3445         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3446             OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
3447             &priv->params.tx_pauseframe_control, 0,
3448             "Set to enable TX pause frames. Clear to disable.");
3449
3450         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3451             OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
3452             &priv->params.rx_pauseframe_control, 0,
3453             "Set to enable RX pause frames. Clear to disable.");
3454
3455         /* register priority flow control, PFC, SYSCTLs */
3456         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3457             OID_AUTO, "tx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
3458             CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_tx_priority_flow_control, "CU",
3459             "Set to enable TX ports flow control frames for priorities 0..7. Clear to disable.");
3460
3461         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3462             OID_AUTO, "rx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
3463             CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_rx_priority_flow_control, "CU",
3464             "Set to enable RX ports flow control frames for priorities 0..7. Clear to disable.");
3465
3466         PRIV_LOCK(priv);
3467
3468         /* range check */
3469         priv->params.tx_pauseframe_control =
3470             priv->params.tx_pauseframe_control ? 1 : 0;
3471         priv->params.rx_pauseframe_control =
3472             priv->params.rx_pauseframe_control ? 1 : 0;
3473
3474         /* update firmware */
3475         error = mlx5e_set_port_pause_and_pfc(priv);
3476         if (error == -EINVAL) {
3477                 if_printf(priv->ifp,
3478                     "Global pauseframes must be disabled before enabling PFC.\n");
3479                 priv->params.rx_priority_flow_control = 0;
3480                 priv->params.tx_priority_flow_control = 0;
3481
3482                 /* update firmware */
3483                 (void) mlx5e_set_port_pause_and_pfc(priv);
3484         }
3485         PRIV_UNLOCK(priv);
3486 }
3487
3488 static void *
3489 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
3490 {
3491         struct ifnet *ifp;
3492         struct mlx5e_priv *priv;
3493         u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
3494         struct sysctl_oid_list *child;
3495         int ncv = mdev->priv.eq_table.num_comp_vectors;
3496         char unit[16];
3497         int err;
3498         int i;
3499         u32 eth_proto_cap;
3500
3501         if (mlx5e_check_required_hca_cap(mdev)) {
3502                 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
3503                 return (NULL);
3504         }
3505         /*
3506          * Try to allocate the priv and make room for worst-case
3507          * number of channel structures:
3508          */
3509         priv = malloc(sizeof(*priv) +
3510             (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors),
3511             M_MLX5EN, M_WAITOK | M_ZERO);
3512         mlx5e_priv_mtx_init(priv);
3513
3514         ifp = priv->ifp = if_alloc(IFT_ETHER);
3515         if (ifp == NULL) {
3516                 mlx5_core_err(mdev, "if_alloc() failed\n");
3517                 goto err_free_priv;
3518         }
3519         ifp->if_softc = priv;
3520         if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev));
3521         ifp->if_mtu = ETHERMTU;
3522         ifp->if_init = mlx5e_open;
3523         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
3524         ifp->if_ioctl = mlx5e_ioctl;
3525         ifp->if_transmit = mlx5e_xmit;
3526         ifp->if_qflush = if_qflush;
3527 #if (__FreeBSD_version >= 1100000)
3528         ifp->if_get_counter = mlx5e_get_counter;
3529 #endif
3530         ifp->if_snd.ifq_maxlen = ifqmaxlen;
3531         /*
3532          * Set driver features
3533          */
3534         ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
3535         ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
3536         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
3537         ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
3538         ifp->if_capabilities |= IFCAP_LRO;
3539         ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
3540         ifp->if_capabilities |= IFCAP_HWSTATS;
3541
3542         /* set TSO limits so that we don't have to drop TX packets */
3543         ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
3544         ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
3545         ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
3546
3547         ifp->if_capenable = ifp->if_capabilities;
3548         ifp->if_hwassist = 0;
3549         if (ifp->if_capenable & IFCAP_TSO)
3550                 ifp->if_hwassist |= CSUM_TSO;
3551         if (ifp->if_capenable & IFCAP_TXCSUM)
3552                 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
3553         if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
3554                 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3555
3556         /* ifnet sysctl tree */
3557         sysctl_ctx_init(&priv->sysctl_ctx);
3558         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
3559             OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
3560         if (priv->sysctl_ifnet == NULL) {
3561                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3562                 goto err_free_sysctl;
3563         }
3564         snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
3565         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3566             OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
3567         if (priv->sysctl_ifnet == NULL) {
3568                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3569                 goto err_free_sysctl;
3570         }
3571
3572         /* HW sysctl tree */
3573         child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
3574         priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
3575             OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
3576         if (priv->sysctl_hw == NULL) {
3577                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3578                 goto err_free_sysctl;
3579         }
3580
3581         err = mlx5e_build_ifp_priv(mdev, priv, ncv);
3582         if (err) {
3583                 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err);
3584                 goto err_free_sysctl;
3585         }
3586
3587         snprintf(unit, sizeof(unit), "mce%u_wq",
3588             device_get_unit(mdev->pdev->dev.bsddev));
3589         priv->wq = alloc_workqueue(unit, 0, 1);
3590         if (priv->wq == NULL) {
3591                 if_printf(ifp, "%s: alloc_workqueue failed\n", __func__);
3592                 goto err_free_sysctl;
3593         }
3594
3595         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
3596         if (err) {
3597                 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n",
3598                     __func__, err);
3599                 goto err_free_wq;
3600         }
3601         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
3602         if (err) {
3603                 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n",
3604                     __func__, err);
3605                 goto err_unmap_free_uar;
3606         }
3607         err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
3608         if (err) {
3609                 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n",
3610                     __func__, err);
3611                 goto err_dealloc_pd;
3612         }
3613         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
3614         if (err) {
3615                 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n",
3616                     __func__, err);
3617                 goto err_dealloc_transport_domain;
3618         }
3619         mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
3620
3621         /* check if we should generate a random MAC address */
3622         if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
3623             is_zero_ether_addr(dev_addr)) {
3624                 random_ether_addr(dev_addr);
3625                 if_printf(ifp, "Assigned random MAC address\n");
3626         }
3627
3628         /* set default MTU */
3629         mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
3630
3631         /* Set default media status */
3632         priv->media_status_last = IFM_AVALID;
3633         priv->media_active_last = IFM_ETHER | IFM_AUTO |
3634             IFM_ETH_RXPAUSE | IFM_FDX;
3635
3636         /* setup default pauseframes configuration */
3637         mlx5e_setup_pauseframes(priv);
3638
3639         err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
3640         if (err) {
3641                 eth_proto_cap = 0;
3642                 if_printf(ifp, "%s: Query port media capability failed, %d\n",
3643                     __func__, err);
3644         }
3645
3646         /* Setup supported medias */
3647         ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
3648             mlx5e_media_change, mlx5e_media_status);
3649
3650         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
3651                 if (mlx5e_mode_table[i].baudrate == 0)
3652                         continue;
3653                 if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
3654                         ifmedia_add(&priv->media,
3655                             mlx5e_mode_table[i].subtype |
3656                             IFM_ETHER, 0, NULL);
3657                         ifmedia_add(&priv->media,
3658                             mlx5e_mode_table[i].subtype |
3659                             IFM_ETHER | IFM_FDX |
3660                             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3661                 }
3662         }
3663
3664         /* Additional supported medias */
3665         ifmedia_add(&priv->media, IFM_10G_LR | IFM_ETHER, 0, NULL);
3666         ifmedia_add(&priv->media, IFM_10G_LR |
3667             IFM_ETHER | IFM_FDX |
3668             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3669
3670         ifmedia_add(&priv->media, IFM_40G_ER4 | IFM_ETHER, 0, NULL);
3671         ifmedia_add(&priv->media, IFM_40G_ER4 |
3672             IFM_ETHER | IFM_FDX |
3673             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3674
3675         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
3676         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3677             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3678
3679         /* Set autoselect by default */
3680         ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3681             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
3682         ether_ifattach(ifp, dev_addr);
3683
3684         /* Register for VLAN events */
3685         priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
3686             mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
3687         priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
3688             mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
3689
3690         /* Link is down by default */
3691         if_link_state_change(ifp, LINK_STATE_DOWN);
3692
3693         mlx5e_enable_async_events(priv);
3694
3695         mlx5e_add_hw_stats(priv);
3696
3697         mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3698             "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
3699             priv->stats.vport.arg);
3700
3701         mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3702             "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
3703             priv->stats.pport.arg);
3704
3705         mlx5e_create_ethtool(priv);
3706
3707         mtx_lock(&priv->async_events_mtx);
3708         mlx5e_update_stats(priv);
3709         mtx_unlock(&priv->async_events_mtx);
3710
3711         return (priv);
3712
3713 err_dealloc_transport_domain:
3714         mlx5_dealloc_transport_domain(mdev, priv->tdn);
3715
3716 err_dealloc_pd:
3717         mlx5_core_dealloc_pd(mdev, priv->pdn);
3718
3719 err_unmap_free_uar:
3720         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3721
3722 err_free_wq:
3723         destroy_workqueue(priv->wq);
3724
3725 err_free_sysctl:
3726         sysctl_ctx_free(&priv->sysctl_ctx);
3727         if (priv->sysctl_debug)
3728                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
3729         if_free(ifp);
3730
3731 err_free_priv:
3732         mlx5e_priv_mtx_destroy(priv);
3733         free(priv, M_MLX5EN);
3734         return (NULL);
3735 }
3736
3737 static void
3738 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
3739 {
3740         struct mlx5e_priv *priv = vpriv;
3741         struct ifnet *ifp = priv->ifp;
3742
3743         /* don't allow more IOCTLs */
3744         priv->gone = 1;
3745
3746         /* XXX wait a bit to allow IOCTL handlers to complete */
3747         pause("W", hz);
3748
3749         /* stop watchdog timer */
3750         callout_drain(&priv->watchdog);
3751
3752         if (priv->vlan_attach != NULL)
3753                 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
3754         if (priv->vlan_detach != NULL)
3755                 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
3756
3757         /* make sure device gets closed */
3758         PRIV_LOCK(priv);
3759         mlx5e_close_locked(ifp);
3760         PRIV_UNLOCK(priv);
3761
3762         /* unregister device */
3763         ifmedia_removeall(&priv->media);
3764         ether_ifdetach(ifp);
3765         if_free(ifp);
3766
3767         /* destroy all remaining sysctl nodes */
3768         sysctl_ctx_free(&priv->stats.vport.ctx);
3769         sysctl_ctx_free(&priv->stats.pport.ctx);
3770         if (priv->sysctl_debug)
3771                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
3772         sysctl_ctx_free(&priv->sysctl_ctx);
3773
3774         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
3775         mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
3776         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3777         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
3778         mlx5e_disable_async_events(priv);
3779         destroy_workqueue(priv->wq);
3780         mlx5e_priv_mtx_destroy(priv);
3781         free(priv, M_MLX5EN);
3782 }
3783
3784 static void *
3785 mlx5e_get_ifp(void *vpriv)
3786 {
3787         struct mlx5e_priv *priv = vpriv;
3788
3789         return (priv->ifp);
3790 }
3791
3792 static struct mlx5_interface mlx5e_interface = {
3793         .add = mlx5e_create_ifp,
3794         .remove = mlx5e_destroy_ifp,
3795         .event = mlx5e_async_event,
3796         .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3797         .get_dev = mlx5e_get_ifp,
3798 };
3799
3800 void
3801 mlx5e_init(void)
3802 {
3803         mlx5_register_interface(&mlx5e_interface);
3804 }
3805
3806 void
3807 mlx5e_cleanup(void)
3808 {
3809         mlx5_unregister_interface(&mlx5e_interface);
3810 }
3811
3812 static void
3813 mlx5e_show_version(void __unused *arg)
3814 {
3815
3816         printf("%s", mlx5e_version);
3817 }
3818 SYSINIT(mlx5e_show_version, SI_SUB_DRIVERS, SI_ORDER_ANY, mlx5e_show_version, NULL);
3819
3820 module_init_order(mlx5e_init, SI_ORDER_THIRD);
3821 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
3822
3823 #if (__FreeBSD_version >= 1100000)
3824 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
3825 #endif
3826 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
3827 MODULE_VERSION(mlx5en, 1);