sys/dev/mlx5/mlx5_en/mlx5_en_main.c

   1 /*-
   2  * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include "en.h"
  29
  30 #include <sys/sockio.h>
  31 #include <machine/atomic.h>
  32
  33 #ifndef ETH_DRIVER_VERSION
  34 #define ETH_DRIVER_VERSION      "3.5.0"
  35 #endif
  36 #define DRIVER_RELDATE  "November 2018"
  37
  38 static const char mlx5e_version[] = "mlx5en: Mellanox Ethernet driver "
  39         ETH_DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
  40
  41 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs);
  42
  43 struct mlx5e_channel_param {
  44         struct mlx5e_rq_param rq;
  45         struct mlx5e_sq_param sq;
  46         struct mlx5e_cq_param rx_cq;
  47         struct mlx5e_cq_param tx_cq;
  48 };
  49
  50 static const struct {
  51         u32     subtype;
  52         u64     baudrate;
  53 }       mlx5e_mode_table[MLX5E_LINK_MODES_NUMBER] = {
  54
  55         [MLX5E_1000BASE_CX_SGMII] = {
  56                 .subtype = IFM_1000_CX_SGMII,
  57                 .baudrate = IF_Mbps(1000ULL),
  58         },
  59         [MLX5E_1000BASE_KX] = {
  60                 .subtype = IFM_1000_KX,
  61                 .baudrate = IF_Mbps(1000ULL),
  62         },
  63         [MLX5E_10GBASE_CX4] = {
  64                 .subtype = IFM_10G_CX4,
  65                 .baudrate = IF_Gbps(10ULL),
  66         },
  67         [MLX5E_10GBASE_KX4] = {
  68                 .subtype = IFM_10G_KX4,
  69                 .baudrate = IF_Gbps(10ULL),
  70         },
  71         [MLX5E_10GBASE_KR] = {
  72                 .subtype = IFM_10G_KR,
  73                 .baudrate = IF_Gbps(10ULL),
  74         },
  75         [MLX5E_20GBASE_KR2] = {
  76                 .subtype = IFM_20G_KR2,
  77                 .baudrate = IF_Gbps(20ULL),
  78         },
  79         [MLX5E_40GBASE_CR4] = {
  80                 .subtype = IFM_40G_CR4,
  81                 .baudrate = IF_Gbps(40ULL),
  82         },
  83         [MLX5E_40GBASE_KR4] = {
  84                 .subtype = IFM_40G_KR4,
  85                 .baudrate = IF_Gbps(40ULL),
  86         },
  87         [MLX5E_56GBASE_R4] = {
  88                 .subtype = IFM_56G_R4,
  89                 .baudrate = IF_Gbps(56ULL),
  90         },
  91         [MLX5E_10GBASE_CR] = {
  92                 .subtype = IFM_10G_CR1,
  93                 .baudrate = IF_Gbps(10ULL),
  94         },
  95         [MLX5E_10GBASE_SR] = {
  96                 .subtype = IFM_10G_SR,
  97                 .baudrate = IF_Gbps(10ULL),
  98         },
  99         [MLX5E_10GBASE_ER] = {
 100                 .subtype = IFM_10G_ER,
 101                 .baudrate = IF_Gbps(10ULL),
 102         },
 103         [MLX5E_40GBASE_SR4] = {
 104                 .subtype = IFM_40G_SR4,
 105                 .baudrate = IF_Gbps(40ULL),
 106         },
 107         [MLX5E_40GBASE_LR4] = {
 108                 .subtype = IFM_40G_LR4,
 109                 .baudrate = IF_Gbps(40ULL),
 110         },
 111         [MLX5E_100GBASE_CR4] = {
 112                 .subtype = IFM_100G_CR4,
 113                 .baudrate = IF_Gbps(100ULL),
 114         },
 115         [MLX5E_100GBASE_SR4] = {
 116                 .subtype = IFM_100G_SR4,
 117                 .baudrate = IF_Gbps(100ULL),
 118         },
 119         [MLX5E_100GBASE_KR4] = {
 120                 .subtype = IFM_100G_KR4,
 121                 .baudrate = IF_Gbps(100ULL),
 122         },
 123         [MLX5E_100GBASE_LR4] = {
 124                 .subtype = IFM_100G_LR4,
 125                 .baudrate = IF_Gbps(100ULL),
 126         },
 127         [MLX5E_100BASE_TX] = {
 128                 .subtype = IFM_100_TX,
 129                 .baudrate = IF_Mbps(100ULL),
 130         },
 131         [MLX5E_1000BASE_T] = {
 132                 .subtype = IFM_1000_T,
 133                 .baudrate = IF_Mbps(1000ULL),
 134         },
 135         [MLX5E_10GBASE_T] = {
 136                 .subtype = IFM_10G_T,
 137                 .baudrate = IF_Gbps(10ULL),
 138         },
 139         [MLX5E_25GBASE_CR] = {
 140                 .subtype = IFM_25G_CR,
 141                 .baudrate = IF_Gbps(25ULL),
 142         },
 143         [MLX5E_25GBASE_KR] = {
 144                 .subtype = IFM_25G_KR,
 145                 .baudrate = IF_Gbps(25ULL),
 146         },
 147         [MLX5E_25GBASE_SR] = {
 148                 .subtype = IFM_25G_SR,
 149                 .baudrate = IF_Gbps(25ULL),
 150         },
 151         [MLX5E_50GBASE_CR2] = {
 152                 .subtype = IFM_50G_CR2,
 153                 .baudrate = IF_Gbps(50ULL),
 154         },
 155         [MLX5E_50GBASE_KR2] = {
 156                 .subtype = IFM_50G_KR2,
 157                 .baudrate = IF_Gbps(50ULL),
 158         },
 159 };
 160
 161 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
 162
 163 static void
 164 mlx5e_update_carrier(struct mlx5e_priv *priv)
 165 {
 166         struct mlx5_core_dev *mdev = priv->mdev;
 167         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 168         u32 eth_proto_oper;
 169         int error;
 170         u8 port_state;
 171         u8 is_er_type;
 172         u8 i;
 173
 174         port_state = mlx5_query_vport_state(mdev,
 175             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 176
 177         if (port_state == VPORT_STATE_UP) {
 178                 priv->media_status_last |= IFM_ACTIVE;
 179         } else {
 180                 priv->media_status_last &= ~IFM_ACTIVE;
 181                 priv->media_active_last = IFM_ETHER;
 182                 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
 183                 return;
 184         }
 185
 186         error = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
 187         if (error) {
 188                 priv->media_active_last = IFM_ETHER;
 189                 priv->ifp->if_baudrate = 1;
 190                 if_printf(priv->ifp, "%s: query port ptys failed: 0x%x\n",
 191                     __func__, error);
 192                 return;
 193         }
 194         eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
 195
 196         for (i = 0; i != MLX5E_LINK_MODES_NUMBER; i++) {
 197                 if (mlx5e_mode_table[i].baudrate == 0)
 198                         continue;
 199                 if (MLX5E_PROT_MASK(i) & eth_proto_oper) {
 200                         u32 subtype = mlx5e_mode_table[i].subtype;
 201
 202                         priv->ifp->if_baudrate =
 203                             mlx5e_mode_table[i].baudrate;
 204
 205                         switch (subtype) {
 206                         case IFM_10G_ER:
 207                                 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
 208                                 if (error != 0) {
 209                                         if_printf(priv->ifp, "%s: query port pddr failed: %d\n",
 210                                             __func__, error);
 211                                 }
 212                                 if (error != 0 || is_er_type == 0)
 213                                         subtype = IFM_10G_LR;
 214                                 break;
 215                         case IFM_40G_LR4:
 216                                 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
 217                                 if (error != 0) {
 218                                         if_printf(priv->ifp, "%s: query port pddr failed: %d\n",
 219                                             __func__, error);
 220                                 }
 221                                 if (error == 0 && is_er_type != 0)
 222                                         subtype = IFM_40G_ER4;
 223                                 break;
 224                         }
 225                         priv->media_active_last = subtype | IFM_ETHER | IFM_FDX;
 226                         break;
 227                 }
 228         }
 229         if_link_state_change(priv->ifp, LINK_STATE_UP);
 230 }
 231
 232 static void
 233 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
 234 {
 235         struct mlx5e_priv *priv = dev->if_softc;
 236
 237         ifmr->ifm_status = priv->media_status_last;
 238         ifmr->ifm_active = priv->media_active_last |
 239             (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
 240             (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
 241
 242 }
 243
 244 static u32
 245 mlx5e_find_link_mode(u32 subtype)
 246 {
 247         u32 i;
 248         u32 link_mode = 0;
 249
 250         switch (subtype) {
 251         case IFM_10G_LR:
 252                 subtype = IFM_10G_ER;
 253                 break;
 254         case IFM_40G_ER4:
 255                 subtype = IFM_40G_LR4;
 256                 break;
 257         }
 258
 259         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
 260                 if (mlx5e_mode_table[i].baudrate == 0)
 261                         continue;
 262                 if (mlx5e_mode_table[i].subtype == subtype)
 263                         link_mode |= MLX5E_PROT_MASK(i);
 264         }
 265
 266         return (link_mode);
 267 }
 268
 269 static int
 270 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv)
 271 {
 272         return (mlx5_set_port_pause_and_pfc(priv->mdev, 1,
 273             priv->params.rx_pauseframe_control,
 274             priv->params.tx_pauseframe_control,
 275             priv->params.rx_priority_flow_control,
 276             priv->params.tx_priority_flow_control));
 277 }
 278
 279 static int
 280 mlx5e_set_port_pfc(struct mlx5e_priv *priv)
 281 {
 282         int error;
 283
 284         if (priv->params.rx_pauseframe_control ||
 285             priv->params.tx_pauseframe_control) {
 286                 if_printf(priv->ifp,
 287                     "Global pauseframes must be disabled before enabling PFC.\n");
 288                 error = -EINVAL;
 289         } else {
 290                 error = mlx5e_set_port_pause_and_pfc(priv);
 291         }
 292         return (error);
 293 }
 294
 295 static int
 296 mlx5e_media_change(struct ifnet *dev)
 297 {
 298         struct mlx5e_priv *priv = dev->if_softc;
 299         struct mlx5_core_dev *mdev = priv->mdev;
 300         u32 eth_proto_cap;
 301         u32 link_mode;
 302         int was_opened;
 303         int locked;
 304         int error;
 305
 306         locked = PRIV_LOCKED(priv);
 307         if (!locked)
 308                 PRIV_LOCK(priv);
 309
 310         if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
 311                 error = EINVAL;
 312                 goto done;
 313         }
 314         link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media));
 315
 316         /* query supported capabilities */
 317         error = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
 318         if (error != 0) {
 319                 if_printf(dev, "Query port media capability failed\n");
 320                 goto done;
 321         }
 322         /* check for autoselect */
 323         if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
 324                 link_mode = eth_proto_cap;
 325                 if (link_mode == 0) {
 326                         if_printf(dev, "Port media capability is zero\n");
 327                         error = EINVAL;
 328                         goto done;
 329                 }
 330         } else {
 331                 link_mode = link_mode & eth_proto_cap;
 332                 if (link_mode == 0) {
 333                         if_printf(dev, "Not supported link mode requested\n");
 334                         error = EINVAL;
 335                         goto done;
 336                 }
 337         }
 338         if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
 339                 /* check if PFC is enabled */
 340                 if (priv->params.rx_priority_flow_control ||
 341                     priv->params.tx_priority_flow_control) {
 342                         if_printf(dev, "PFC must be disabled before enabling global pauseframes.\n");
 343                         error = EINVAL;
 344                         goto done;
 345                 }
 346         }
 347         /* update pauseframe control bits */
 348         priv->params.rx_pauseframe_control =
 349             (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
 350         priv->params.tx_pauseframe_control =
 351             (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
 352
 353         /* check if device is opened */
 354         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
 355
 356         /* reconfigure the hardware */
 357         mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
 358         mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN);
 359         error = -mlx5e_set_port_pause_and_pfc(priv);
 360         if (was_opened)
 361                 mlx5_set_port_status(mdev, MLX5_PORT_UP);
 362
 363 done:
 364         if (!locked)
 365                 PRIV_UNLOCK(priv);
 366         return (error);
 367 }
 368
 369 static void
 370 mlx5e_update_carrier_work(struct work_struct *work)
 371 {
 372         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 373             update_carrier_work);
 374
 375         PRIV_LOCK(priv);
 376         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 377                 mlx5e_update_carrier(priv);
 378         PRIV_UNLOCK(priv);
 379 }
 380
 381 /*
 382  * This function reads the physical port counters from the firmware
 383  * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
 384  * macros. The output is converted from big-endian 64-bit values into
 385  * host endian ones and stored in the "priv->stats.pport" structure.
 386  */
 387 static void
 388 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 389 {
 390         struct mlx5_core_dev *mdev = priv->mdev;
 391         struct mlx5e_pport_stats *s = &priv->stats.pport;
 392         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 393         u32 *in;
 394         u32 *out;
 395         const u64 *ptr;
 396         unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 397         unsigned x;
 398         unsigned y;
 399         unsigned z;
 400
 401         /* allocate firmware request structures */
 402         in = mlx5_vzalloc(sz);
 403         out = mlx5_vzalloc(sz);
 404         if (in == NULL || out == NULL)
 405                 goto free_out;
 406
 407         /*
 408          * Get pointer to the 64-bit counter set which is located at a
 409          * fixed offset in the output firmware request structure:
 410          */
 411         ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
 412
 413         MLX5_SET(ppcnt_reg, in, local_port, 1);
 414
 415         /* read IEEE802_3 counter group using predefined counter layout */
 416         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 417         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 418         for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM;
 419              x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
 420                 s->arg[y] = be64toh(ptr[x]);
 421
 422         /* read RFC2819 counter group using predefined counter layout */
 423         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 424         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 425         for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
 426                 s->arg[y] = be64toh(ptr[x]);
 427         for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
 428             MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
 429                 s_debug->arg[y] = be64toh(ptr[x]);
 430
 431         /* read RFC2863 counter group using predefined counter layout */
 432         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 433         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 434         for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
 435                 s_debug->arg[y] = be64toh(ptr[x]);
 436
 437         /* read physical layer stats counter group using predefined counter layout */
 438         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 439         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 440         for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
 441                 s_debug->arg[y] = be64toh(ptr[x]);
 442
 443         /* read per-priority counters */
 444         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 445
 446         /* iterate all the priorities */
 447         for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) {
 448                 MLX5_SET(ppcnt_reg, in, prio_tc, z);
 449                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 450
 451                 /* read per priority stats counter group using predefined counter layout */
 452                 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM /
 453                     MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++)
 454                         s->arg[y] = be64toh(ptr[x]);
 455         }
 456 free_out:
 457         /* free firmware request structures */
 458         kvfree(in);
 459         kvfree(out);
 460 }
 461
 462 /*
 463  * This function is called regularly to collect all statistics
 464  * counters from the firmware. The values can be viewed through the
 465  * sysctl interface. Execution is serialized using the priv's global
 466  * configuration lock.
 467  */
 468 static void
 469 mlx5e_update_stats_work(struct work_struct *work)
 470 {
 471         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 472             update_stats_work);
 473         struct mlx5_core_dev *mdev = priv->mdev;
 474         struct mlx5e_vport_stats *s = &priv->stats.vport;
 475         struct mlx5e_sq_stats *sq_stats;
 476         struct buf_ring *sq_br;
 477 #if (__FreeBSD_version < 1100000)
 478         struct ifnet *ifp = priv->ifp;
 479 #endif
 480
 481         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 482         u32 *out;
 483         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 484         u64 tso_packets = 0;
 485         u64 tso_bytes = 0;
 486         u64 tx_queue_dropped = 0;
 487         u64 tx_defragged = 0;
 488         u64 tx_offload_none = 0;
 489         u64 lro_packets = 0;
 490         u64 lro_bytes = 0;
 491         u64 sw_lro_queued = 0;
 492         u64 sw_lro_flushed = 0;
 493         u64 rx_csum_none = 0;
 494         u64 rx_wqe_err = 0;
 495         u32 rx_out_of_buffer = 0;
 496         int i;
 497         int j;
 498
 499         PRIV_LOCK(priv);
 500         out = mlx5_vzalloc(outlen);
 501         if (out == NULL)
 502                 goto free_out;
 503         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
 504                 goto free_out;
 505
 506         /* Collect firts the SW counters and then HW for consistency */
 507         for (i = 0; i < priv->params.num_channels; i++) {
 508                 struct mlx5e_channel *pch = priv->channel + i;
 509                 struct mlx5e_rq *rq = &pch->rq;
 510                 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats;
 511
 512                 /* collect stats from LRO */
 513                 rq_stats->sw_lro_queued = rq->lro.lro_queued;
 514                 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
 515                 sw_lro_queued += rq_stats->sw_lro_queued;
 516                 sw_lro_flushed += rq_stats->sw_lro_flushed;
 517                 lro_packets += rq_stats->lro_packets;
 518                 lro_bytes += rq_stats->lro_bytes;
 519                 rx_csum_none += rq_stats->csum_none;
 520                 rx_wqe_err += rq_stats->wqe_err;
 521
 522                 for (j = 0; j < priv->num_tc; j++) {
 523                         sq_stats = &pch->sq[j].stats;
 524                         sq_br = pch->sq[j].br;
 525
 526                         tso_packets += sq_stats->tso_packets;
 527                         tso_bytes += sq_stats->tso_bytes;
 528                         tx_queue_dropped += sq_stats->dropped;
 529                         if (sq_br != NULL)
 530                                 tx_queue_dropped += sq_br->br_drops;
 531                         tx_defragged += sq_stats->defragged;
 532                         tx_offload_none += sq_stats->csum_offload_none;
 533                 }
 534         }
 535
 536         s->tx_jumbo_packets =
 537             priv->stats.port_stats_debug.p1519to2047octets +
 538             priv->stats.port_stats_debug.p2048to4095octets +
 539             priv->stats.port_stats_debug.p4096to8191octets +
 540             priv->stats.port_stats_debug.p8192to10239octets;
 541
 542         /* update counters */
 543         s->tso_packets = tso_packets;
 544         s->tso_bytes = tso_bytes;
 545         s->tx_queue_dropped = tx_queue_dropped;
 546         s->tx_defragged = tx_defragged;
 547         s->lro_packets = lro_packets;
 548         s->lro_bytes = lro_bytes;
 549         s->sw_lro_queued = sw_lro_queued;
 550         s->sw_lro_flushed = sw_lro_flushed;
 551         s->rx_csum_none = rx_csum_none;
 552         s->rx_wqe_err = rx_wqe_err;
 553
 554         /* HW counters */
 555         memset(in, 0, sizeof(in));
 556
 557         MLX5_SET(query_vport_counter_in, in, opcode,
 558             MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 559         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 560         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 561
 562         memset(out, 0, outlen);
 563
 564         /* get number of out-of-buffer drops first */
 565         if (mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
 566             &rx_out_of_buffer))
 567                 goto free_out;
 568
 569         /* accumulate difference into a 64-bit counter */
 570         s->rx_out_of_buffer += (u64)(u32)(rx_out_of_buffer - s->rx_out_of_buffer_prev);
 571         s->rx_out_of_buffer_prev = rx_out_of_buffer;
 572
 573         /* get port statistics */
 574         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen))
 575                 goto free_out;
 576
 577 #define MLX5_GET_CTR(out, x) \
 578         MLX5_GET64(query_vport_counter_out, out, x)
 579
 580         s->rx_error_packets =
 581             MLX5_GET_CTR(out, received_errors.packets);
 582         s->rx_error_bytes =
 583             MLX5_GET_CTR(out, received_errors.octets);
 584         s->tx_error_packets =
 585             MLX5_GET_CTR(out, transmit_errors.packets);
 586         s->tx_error_bytes =
 587             MLX5_GET_CTR(out, transmit_errors.octets);
 588
 589         s->rx_unicast_packets =
 590             MLX5_GET_CTR(out, received_eth_unicast.packets);
 591         s->rx_unicast_bytes =
 592             MLX5_GET_CTR(out, received_eth_unicast.octets);
 593         s->tx_unicast_packets =
 594             MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 595         s->tx_unicast_bytes =
 596             MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 597
 598         s->rx_multicast_packets =
 599             MLX5_GET_CTR(out, received_eth_multicast.packets);
 600         s->rx_multicast_bytes =
 601             MLX5_GET_CTR(out, received_eth_multicast.octets);
 602         s->tx_multicast_packets =
 603             MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 604         s->tx_multicast_bytes =
 605             MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 606
 607         s->rx_broadcast_packets =
 608             MLX5_GET_CTR(out, received_eth_broadcast.packets);
 609         s->rx_broadcast_bytes =
 610             MLX5_GET_CTR(out, received_eth_broadcast.octets);
 611         s->tx_broadcast_packets =
 612             MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 613         s->tx_broadcast_bytes =
 614             MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 615
 616         s->rx_packets =
 617             s->rx_unicast_packets +
 618             s->rx_multicast_packets +
 619             s->rx_broadcast_packets -
 620             s->rx_out_of_buffer;
 621         s->rx_bytes =
 622             s->rx_unicast_bytes +
 623             s->rx_multicast_bytes +
 624             s->rx_broadcast_bytes;
 625         s->tx_packets =
 626             s->tx_unicast_packets +
 627             s->tx_multicast_packets +
 628             s->tx_broadcast_packets;
 629         s->tx_bytes =
 630             s->tx_unicast_bytes +
 631             s->tx_multicast_bytes +
 632             s->tx_broadcast_bytes;
 633
 634         /* Update calculated offload counters */
 635         s->tx_csum_offload = s->tx_packets - tx_offload_none;
 636         s->rx_csum_good = s->rx_packets - s->rx_csum_none;
 637
 638         /* Get physical port counters */
 639         mlx5e_update_pport_counters(priv);
 640
 641 #if (__FreeBSD_version < 1100000)
 642         /* no get_counters interface in fbsd 10 */
 643         ifp->if_ipackets = s->rx_packets;
 644         ifp->if_ierrors = s->rx_error_packets +
 645             priv->stats.pport.alignment_err +
 646             priv->stats.pport.check_seq_err +
 647             priv->stats.pport.crc_align_errors +
 648             priv->stats.pport.in_range_len_errors +
 649             priv->stats.pport.jabbers +
 650             priv->stats.pport.out_of_range_len +
 651             priv->stats.pport.oversize_pkts +
 652             priv->stats.pport.symbol_err +
 653             priv->stats.pport.too_long_errors +
 654             priv->stats.pport.undersize_pkts +
 655             priv->stats.pport.unsupported_op_rx;
 656         ifp->if_iqdrops = s->rx_out_of_buffer +
 657             priv->stats.pport.drop_events;
 658         ifp->if_opackets = s->tx_packets;
 659         ifp->if_oerrors = s->tx_error_packets;
 660         ifp->if_snd.ifq_drops = s->tx_queue_dropped;
 661         ifp->if_ibytes = s->rx_bytes;
 662         ifp->if_obytes = s->tx_bytes;
 663         ifp->if_collisions =
 664             priv->stats.pport.collisions;
 665 #endif
 666
 667 free_out:
 668         kvfree(out);
 669
 670         /* Update diagnostics, if any */
 671         if (priv->params_ethtool.diag_pci_enable ||
 672             priv->params_ethtool.diag_general_enable) {
 673                 int error = mlx5_core_get_diagnostics_full(mdev,
 674                     priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL,
 675                     priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL);
 676                 if (error != 0)
 677                         if_printf(priv->ifp, "Failed reading diagnostics: %d\n", error);
 678         }
 679         PRIV_UNLOCK(priv);
 680 }
 681
 682 static void
 683 mlx5e_update_stats(void *arg)
 684 {
 685         struct mlx5e_priv *priv = arg;
 686
 687         queue_work(priv->wq, &priv->update_stats_work);
 688
 689         callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
 690 }
 691
 692 static void
 693 mlx5e_async_event_sub(struct mlx5e_priv *priv,
 694     enum mlx5_dev_event event)
 695 {
 696         switch (event) {
 697         case MLX5_DEV_EVENT_PORT_UP:
 698         case MLX5_DEV_EVENT_PORT_DOWN:
 699                 queue_work(priv->wq, &priv->update_carrier_work);
 700                 break;
 701
 702         default:
 703                 break;
 704         }
 705 }
 706
 707 static void
 708 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 709     enum mlx5_dev_event event, unsigned long param)
 710 {
 711         struct mlx5e_priv *priv = vpriv;
 712
 713         mtx_lock(&priv->async_events_mtx);
 714         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 715                 mlx5e_async_event_sub(priv, event);
 716         mtx_unlock(&priv->async_events_mtx);
 717 }
 718
 719 static void
 720 mlx5e_enable_async_events(struct mlx5e_priv *priv)
 721 {
 722         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 723 }
 724
 725 static void
 726 mlx5e_disable_async_events(struct mlx5e_priv *priv)
 727 {
 728         mtx_lock(&priv->async_events_mtx);
 729         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 730         mtx_unlock(&priv->async_events_mtx);
 731 }
 732
 733 static void mlx5e_calibration_callout(void *arg);
 734 static int mlx5e_calibration_duration = 20;
 735 static int mlx5e_fast_calibration = 1;
 736 static int mlx5e_normal_calibration = 30;
 737
 738 static SYSCTL_NODE(_hw_mlx5, OID_AUTO, calibr, CTLFLAG_RW, 0,
 739     "MLX5 timestamp calibration parameteres");
 740
 741 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, duration, CTLFLAG_RWTUN,
 742     &mlx5e_calibration_duration, 0,
 743     "Duration of initial calibration");
 744 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, fast, CTLFLAG_RWTUN,
 745     &mlx5e_fast_calibration, 0,
 746     "Recalibration interval during initial calibration");
 747 SYSCTL_INT(_hw_mlx5_calibr, OID_AUTO, normal, CTLFLAG_RWTUN,
 748     &mlx5e_normal_calibration, 0,
 749     "Recalibration interval during normal operations");
 750
 751 /*
 752  * Ignites the calibration process.
 753  */
 754 static void
 755 mlx5e_reset_calibration_callout(struct mlx5e_priv *priv)
 756 {
 757
 758         if (priv->clbr_done == 0)
 759                 mlx5e_calibration_callout(priv);
 760         else
 761                 callout_reset_curcpu(&priv->tstmp_clbr, (priv->clbr_done <
 762                     mlx5e_calibration_duration ? mlx5e_fast_calibration :
 763                     mlx5e_normal_calibration) * hz, mlx5e_calibration_callout,
 764                     priv);
 765 }
 766
 767 static uint64_t
 768 mlx5e_timespec2usec(const struct timespec *ts)
 769 {
 770
 771         return ((uint64_t)ts->tv_sec * 1000000000 + ts->tv_nsec);
 772 }
 773
 774 static uint64_t
 775 mlx5e_hw_clock(struct mlx5e_priv *priv)
 776 {
 777         struct mlx5_init_seg *iseg;
 778         uint32_t hw_h, hw_h1, hw_l;
 779
 780         iseg = priv->mdev->iseg;
 781         do {
 782                 hw_h = ioread32be(&iseg->internal_timer_h);
 783                 hw_l = ioread32be(&iseg->internal_timer_l);
 784                 hw_h1 = ioread32be(&iseg->internal_timer_h);
 785         } while (hw_h1 != hw_h);
 786         return (((uint64_t)hw_h << 32) | hw_l);
 787 }
 788
 789 /*
 790  * The calibration callout, it runs either in the context of the
 791  * thread which enables calibration, or in callout.  It takes the
 792  * snapshot of system and adapter clocks, then advances the pointers to
 793  * the calibration point to allow rx path to read the consistent data
 794  * lockless.
 795  */
 796 static void
 797 mlx5e_calibration_callout(void *arg)
 798 {
 799         struct mlx5e_priv *priv;
 800         struct mlx5e_clbr_point *next, *curr;
 801         struct timespec ts;
 802         int clbr_curr_next;
 803
 804         priv = arg;
 805         curr = &priv->clbr_points[priv->clbr_curr];
 806         clbr_curr_next = priv->clbr_curr + 1;
 807         if (clbr_curr_next >= nitems(priv->clbr_points))
 808                 clbr_curr_next = 0;
 809         next = &priv->clbr_points[clbr_curr_next];
 810
 811         next->base_prev = curr->base_curr;
 812         next->clbr_hw_prev = curr->clbr_hw_curr;
 813
 814         next->clbr_hw_curr = mlx5e_hw_clock(priv);
 815         if (((next->clbr_hw_curr - curr->clbr_hw_prev) >> MLX5E_TSTMP_PREC) ==
 816             0) {
 817                 if_printf(priv->ifp, "HW failed tstmp frozen %#jx %#jx,"
 818                     "disabling\n", next->clbr_hw_curr, curr->clbr_hw_prev);
 819                 priv->clbr_done = 0;
 820                 return;
 821         }
 822
 823         nanouptime(&ts);
 824         next->base_curr = mlx5e_timespec2usec(&ts);
 825
 826         curr->clbr_gen = 0;
 827         atomic_thread_fence_rel();
 828         priv->clbr_curr = clbr_curr_next;
 829         atomic_store_rel_int(&next->clbr_gen, ++(priv->clbr_gen));
 830
 831         if (priv->clbr_done < mlx5e_calibration_duration)
 832                 priv->clbr_done++;
 833         mlx5e_reset_calibration_callout(priv);
 834 }
 835
 836 static const char *mlx5e_rq_stats_desc[] = {
 837         MLX5E_RQ_STATS(MLX5E_STATS_DESC)
 838 };
 839
 840 static int
 841 mlx5e_create_rq(struct mlx5e_channel *c,
 842     struct mlx5e_rq_param *param,
 843     struct mlx5e_rq *rq)
 844 {
 845         struct mlx5e_priv *priv = c->priv;
 846         struct mlx5_core_dev *mdev = priv->mdev;
 847         char buffer[16];
 848         void *rqc = param->rqc;
 849         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 850         int wq_sz;
 851         int err;
 852         int i;
 853         u32 nsegs, wqe_sz;
 854
 855         err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
 856         if (err != 0)
 857                 goto done;
 858
 859         /* Create DMA descriptor TAG */
 860         if ((err = -bus_dma_tag_create(
 861             bus_get_dma_tag(mdev->pdev->dev.bsddev),
 862             1,                          /* any alignment */
 863             0,                          /* no boundary */
 864             BUS_SPACE_MAXADDR,          /* lowaddr */
 865             BUS_SPACE_MAXADDR,          /* highaddr */
 866             NULL, NULL,                 /* filter, filterarg */
 867             nsegs * MLX5E_MAX_RX_BYTES, /* maxsize */
 868             nsegs,                      /* nsegments */
 869             nsegs * MLX5E_MAX_RX_BYTES, /* maxsegsize */
 870             0,                          /* flags */
 871             NULL, NULL,                 /* lockfunc, lockfuncarg */
 872             &rq->dma_tag)))
 873                 goto done;
 874
 875         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 876             &rq->wq_ctrl);
 877         if (err)
 878                 goto err_free_dma_tag;
 879
 880         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 881
 882         err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs);
 883         if (err != 0)
 884                 goto err_rq_wq_destroy;
 885
 886         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 887
 888         err = -tcp_lro_init_args(&rq->lro, c->tag.m_snd_tag.ifp, TCP_LRO_ENTRIES, wq_sz);
 889         if (err)
 890                 goto err_rq_wq_destroy;
 891
 892         rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
 893         for (i = 0; i != wq_sz; i++) {
 894                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 895 #if (MLX5E_MAX_RX_SEGS == 1)
 896                 uint32_t byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 897 #else
 898                 int j;
 899 #endif
 900
 901                 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
 902                 if (err != 0) {
 903                         while (i--)
 904                                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 905                         goto err_rq_mbuf_free;
 906                 }
 907
 908                 /* set value for constant fields */
 909 #if (MLX5E_MAX_RX_SEGS == 1)
 910                 wqe->data[0].lkey = c->mkey_be;
 911                 wqe->data[0].byte_count = cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
 912 #else
 913                 for (j = 0; j < rq->nsegs; j++)
 914                         wqe->data[j].lkey = c->mkey_be;
 915 #endif
 916         }
 917
 918         INIT_WORK(&rq->dim.work, mlx5e_dim_work);
 919         if (priv->params.rx_cq_moderation_mode < 2) {
 920                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
 921         } else {
 922                 void *cqc = container_of(param,
 923                     struct mlx5e_channel_param, rq)->rx_cq.cqc;
 924
 925                 switch (MLX5_GET(cqc, cqc, cq_period_mode)) {
 926                 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 927                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 928                         break;
 929                 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 930                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 931                         break;
 932                 default:
 933                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
 934                         break;
 935                 }
 936         }
 937
 938         rq->ifp = c->tag.m_snd_tag.ifp;
 939         rq->channel = c;
 940         rq->ix = c->ix;
 941
 942         snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
 943         mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
 944             buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
 945             rq->stats.arg);
 946         return (0);
 947
 948 err_rq_mbuf_free:
 949         free(rq->mbuf, M_MLX5EN);
 950         tcp_lro_free(&rq->lro);
 951 err_rq_wq_destroy:
 952         mlx5_wq_destroy(&rq->wq_ctrl);
 953 err_free_dma_tag:
 954         bus_dma_tag_destroy(rq->dma_tag);
 955 done:
 956         return (err);
 957 }
 958
 959 static void
 960 mlx5e_destroy_rq(struct mlx5e_rq *rq)
 961 {
 962         int wq_sz;
 963         int i;
 964
 965         /* destroy all sysctl nodes */
 966         sysctl_ctx_free(&rq->stats.ctx);
 967
 968         /* free leftover LRO packets, if any */
 969         tcp_lro_free(&rq->lro);
 970
 971         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 972         for (i = 0; i != wq_sz; i++) {
 973                 if (rq->mbuf[i].mbuf != NULL) {
 974                         bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map);
 975                         m_freem(rq->mbuf[i].mbuf);
 976                 }
 977                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 978         }
 979         free(rq->mbuf, M_MLX5EN);
 980         mlx5_wq_destroy(&rq->wq_ctrl);
 981 }
 982
 983 static int
 984 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 985 {
 986         struct mlx5e_channel *c = rq->channel;
 987         struct mlx5e_priv *priv = c->priv;
 988         struct mlx5_core_dev *mdev = priv->mdev;
 989
 990         void *in;
 991         void *rqc;
 992         void *wq;
 993         int inlen;
 994         int err;
 995
 996         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 997             sizeof(u64) * rq->wq_ctrl.buf.npages;
 998         in = mlx5_vzalloc(inlen);
 999         if (in == NULL)
1000                 return (-ENOMEM);
1001
1002         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1003         wq = MLX5_ADDR_OF(rqc, rqc, wq);
1004
1005         memcpy(rqc, param->rqc, sizeof(param->rqc));
1006
1007         MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
1008         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1009         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1010         if (priv->counter_set_id >= 0)
1011                 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
1012         MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
1013             PAGE_SHIFT);
1014         MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
1015
1016         mlx5_fill_page_array(&rq->wq_ctrl.buf,
1017             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1018
1019         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
1020
1021         kvfree(in);
1022
1023         return (err);
1024 }
1025
1026 static int
1027 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
1028 {
1029         struct mlx5e_channel *c = rq->channel;
1030         struct mlx5e_priv *priv = c->priv;
1031         struct mlx5_core_dev *mdev = priv->mdev;
1032
1033         void *in;
1034         void *rqc;
1035         int inlen;
1036         int err;
1037
1038         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
1039         in = mlx5_vzalloc(inlen);
1040         if (in == NULL)
1041                 return (-ENOMEM);
1042
1043         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
1044
1045         MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
1046         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
1047         MLX5_SET(rqc, rqc, state, next_state);
1048
1049         err = mlx5_core_modify_rq(mdev, in, inlen);
1050
1051         kvfree(in);
1052
1053         return (err);
1054 }
1055
1056 static void
1057 mlx5e_disable_rq(struct mlx5e_rq *rq)
1058 {
1059         struct mlx5e_channel *c = rq->channel;
1060         struct mlx5e_priv *priv = c->priv;
1061         struct mlx5_core_dev *mdev = priv->mdev;
1062
1063         mlx5_core_destroy_rq(mdev, rq->rqn);
1064 }
1065
1066 static int
1067 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
1068 {
1069         struct mlx5e_channel *c = rq->channel;
1070         struct mlx5e_priv *priv = c->priv;
1071         struct mlx5_wq_ll *wq = &rq->wq;
1072         int i;
1073
1074         for (i = 0; i < 1000; i++) {
1075                 if (wq->cur_sz >= priv->params.min_rx_wqes)
1076                         return (0);
1077
1078                 msleep(4);
1079         }
1080         return (-ETIMEDOUT);
1081 }
1082
1083 static int
1084 mlx5e_open_rq(struct mlx5e_channel *c,
1085     struct mlx5e_rq_param *param,
1086     struct mlx5e_rq *rq)
1087 {
1088         int err;
1089
1090         err = mlx5e_create_rq(c, param, rq);
1091         if (err)
1092                 return (err);
1093
1094         err = mlx5e_enable_rq(rq, param);
1095         if (err)
1096                 goto err_destroy_rq;
1097
1098         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
1099         if (err)
1100                 goto err_disable_rq;
1101
1102         c->rq.enabled = 1;
1103
1104         return (0);
1105
1106 err_disable_rq:
1107         mlx5e_disable_rq(rq);
1108 err_destroy_rq:
1109         mlx5e_destroy_rq(rq);
1110
1111         return (err);
1112 }
1113
1114 static void
1115 mlx5e_close_rq(struct mlx5e_rq *rq)
1116 {
1117         mtx_lock(&rq->mtx);
1118         rq->enabled = 0;
1119         callout_stop(&rq->watchdog);
1120         mtx_unlock(&rq->mtx);
1121
1122         callout_drain(&rq->watchdog);
1123
1124         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
1125 }
1126
1127 static void
1128 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
1129 {
1130         struct mlx5_core_dev *mdev = rq->channel->priv->mdev;
1131
1132         /* wait till RQ is empty */
1133         while (!mlx5_wq_ll_is_empty(&rq->wq) &&
1134                (mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR)) {
1135                 msleep(4);
1136                 rq->cq.mcq.comp(&rq->cq.mcq);
1137         }
1138
1139         cancel_work_sync(&rq->dim.work);
1140         mlx5e_disable_rq(rq);
1141         mlx5e_destroy_rq(rq);
1142 }
1143
1144 void
1145 mlx5e_free_sq_db(struct mlx5e_sq *sq)
1146 {
1147         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1148         int x;
1149
1150         for (x = 0; x != wq_sz; x++)
1151                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1152         free(sq->mbuf, M_MLX5EN);
1153 }
1154
1155 int
1156 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
1157 {
1158         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1159         int err;
1160         int x;
1161
1162         sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1163
1164         /* Create DMA descriptor MAPs */
1165         for (x = 0; x != wq_sz; x++) {
1166                 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
1167                 if (err != 0) {
1168                         while (x--)
1169                                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1170                         free(sq->mbuf, M_MLX5EN);
1171                         return (err);
1172                 }
1173         }
1174         return (0);
1175 }
1176
1177 static const char *mlx5e_sq_stats_desc[] = {
1178         MLX5E_SQ_STATS(MLX5E_STATS_DESC)
1179 };
1180
1181 void
1182 mlx5e_update_sq_inline(struct mlx5e_sq *sq)
1183 {
1184         sq->max_inline = sq->priv->params.tx_max_inline;
1185         sq->min_inline_mode = sq->priv->params.tx_min_inline_mode;
1186
1187         /*
1188          * Check if trust state is DSCP or if inline mode is NONE which
1189          * indicates CX-5 or newer hardware.
1190          */
1191         if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP ||
1192             sq->min_inline_mode == MLX5_INLINE_MODE_NONE) {
1193                 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert))
1194                         sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN;
1195                 else
1196                         sq->min_insert_caps = MLX5E_INSERT_NON_VLAN;
1197         } else {
1198                 sq->min_insert_caps = 0;
1199         }
1200 }
1201
1202 static void
1203 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1204 {
1205         int i;
1206
1207         for (i = 0; i != c->num_tc; i++) {
1208                 mtx_lock(&c->sq[i].lock);
1209                 mlx5e_update_sq_inline(&c->sq[i]);
1210                 mtx_unlock(&c->sq[i].lock);
1211         }
1212 }
1213
1214 void
1215 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv)
1216 {
1217         int i;
1218
1219         /* check if channels are closed */
1220         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
1221                 return;
1222
1223         for (i = 0; i < priv->params.num_channels; i++)
1224                 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]);
1225 }
1226
1227 static int
1228 mlx5e_create_sq(struct mlx5e_channel *c,
1229     int tc,
1230     struct mlx5e_sq_param *param,
1231     struct mlx5e_sq *sq)
1232 {
1233         struct mlx5e_priv *priv = c->priv;
1234         struct mlx5_core_dev *mdev = priv->mdev;
1235         char buffer[16];
1236         void *sqc = param->sqc;
1237         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1238         int err;
1239
1240         /* Create DMA descriptor TAG */
1241         if ((err = -bus_dma_tag_create(
1242             bus_get_dma_tag(mdev->pdev->dev.bsddev),
1243             1,                          /* any alignment */
1244             0,                          /* no boundary */
1245             BUS_SPACE_MAXADDR,          /* lowaddr */
1246             BUS_SPACE_MAXADDR,          /* highaddr */
1247             NULL, NULL,                 /* filter, filterarg */
1248             MLX5E_MAX_TX_PAYLOAD_SIZE,  /* maxsize */
1249             MLX5E_MAX_TX_MBUF_FRAGS,    /* nsegments */
1250             MLX5E_MAX_TX_MBUF_SIZE,     /* maxsegsize */
1251             0,                          /* flags */
1252             NULL, NULL,                 /* lockfunc, lockfuncarg */
1253             &sq->dma_tag)))
1254                 goto done;
1255
1256         err = mlx5_alloc_map_uar(mdev, &sq->uar);
1257         if (err)
1258                 goto err_free_dma_tag;
1259
1260         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
1261             &sq->wq_ctrl);
1262         if (err)
1263                 goto err_unmap_free_uar;
1264
1265         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1266         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1267
1268         err = mlx5e_alloc_sq_db(sq);
1269         if (err)
1270                 goto err_sq_wq_destroy;
1271
1272         sq->mkey_be = c->mkey_be;
1273         sq->ifp = priv->ifp;
1274         sq->priv = priv;
1275         sq->tc = tc;
1276
1277         mlx5e_update_sq_inline(sq);
1278
1279         snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1280         mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1281             buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1282             sq->stats.arg);
1283
1284         return (0);
1285
1286 err_sq_wq_destroy:
1287         mlx5_wq_destroy(&sq->wq_ctrl);
1288
1289 err_unmap_free_uar:
1290         mlx5_unmap_free_uar(mdev, &sq->uar);
1291
1292 err_free_dma_tag:
1293         bus_dma_tag_destroy(sq->dma_tag);
1294 done:
1295         return (err);
1296 }
1297
1298 static void
1299 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1300 {
1301         /* destroy all sysctl nodes */
1302         sysctl_ctx_free(&sq->stats.ctx);
1303
1304         mlx5e_free_sq_db(sq);
1305         mlx5_wq_destroy(&sq->wq_ctrl);
1306         mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1307 }
1308
1309 int
1310 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1311     int tis_num)
1312 {
1313         void *in;
1314         void *sqc;
1315         void *wq;
1316         int inlen;
1317         int err;
1318
1319         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1320             sizeof(u64) * sq->wq_ctrl.buf.npages;
1321         in = mlx5_vzalloc(inlen);
1322         if (in == NULL)
1323                 return (-ENOMEM);
1324
1325         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1326         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1327
1328         memcpy(sqc, param->sqc, sizeof(param->sqc));
1329
1330         MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1331         MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1332         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1333         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1334         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1335
1336         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1337         MLX5_SET(wq, wq, uar_page, sq->uar.index);
1338         MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1339             PAGE_SHIFT);
1340         MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1341
1342         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1343             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1344
1345         err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1346
1347         kvfree(in);
1348
1349         return (err);
1350 }
1351
1352 int
1353 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1354 {
1355         void *in;
1356         void *sqc;
1357         int inlen;
1358         int err;
1359
1360         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1361         in = mlx5_vzalloc(inlen);
1362         if (in == NULL)
1363                 return (-ENOMEM);
1364
1365         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1366
1367         MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1368         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1369         MLX5_SET(sqc, sqc, state, next_state);
1370
1371         err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1372
1373         kvfree(in);
1374
1375         return (err);
1376 }
1377
1378 void
1379 mlx5e_disable_sq(struct mlx5e_sq *sq)
1380 {
1381
1382         mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1383 }
1384
1385 static int
1386 mlx5e_open_sq(struct mlx5e_channel *c,
1387     int tc,
1388     struct mlx5e_sq_param *param,
1389     struct mlx5e_sq *sq)
1390 {
1391         int err;
1392
1393         err = mlx5e_create_sq(c, tc, param, sq);
1394         if (err)
1395                 return (err);
1396
1397         err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1398         if (err)
1399                 goto err_destroy_sq;
1400
1401         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1402         if (err)
1403                 goto err_disable_sq;
1404
1405         WRITE_ONCE(sq->running, 1);
1406
1407         return (0);
1408
1409 err_disable_sq:
1410         mlx5e_disable_sq(sq);
1411 err_destroy_sq:
1412         mlx5e_destroy_sq(sq);
1413
1414         return (err);
1415 }
1416
1417 static void
1418 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1419 {
1420         /* fill up remainder with NOPs */
1421         while (sq->cev_counter != 0) {
1422                 while (!mlx5e_sq_has_room_for(sq, 1)) {
1423                         if (can_sleep != 0) {
1424                                 mtx_unlock(&sq->lock);
1425                                 msleep(4);
1426                                 mtx_lock(&sq->lock);
1427                         } else {
1428                                 goto done;
1429                         }
1430                 }
1431                 /* send a single NOP */
1432                 mlx5e_send_nop(sq, 1);
1433                 atomic_thread_fence_rel();
1434         }
1435 done:
1436         /* Check if we need to write the doorbell */
1437         if (likely(sq->doorbell.d64 != 0)) {
1438                 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1439                 sq->doorbell.d64 = 0;
1440         }
1441 }
1442
1443 void
1444 mlx5e_sq_cev_timeout(void *arg)
1445 {
1446         struct mlx5e_sq *sq = arg;
1447
1448         mtx_assert(&sq->lock, MA_OWNED);
1449
1450         /* check next state */
1451         switch (sq->cev_next_state) {
1452         case MLX5E_CEV_STATE_SEND_NOPS:
1453                 /* fill TX ring with NOPs, if any */
1454                 mlx5e_sq_send_nops_locked(sq, 0);
1455
1456                 /* check if completed */
1457                 if (sq->cev_counter == 0) {
1458                         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1459                         return;
1460                 }
1461                 break;
1462         default:
1463                 /* send NOPs on next timeout */
1464                 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1465                 break;
1466         }
1467
1468         /* restart timer */
1469         callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1470 }
1471
1472 void
1473 mlx5e_drain_sq(struct mlx5e_sq *sq)
1474 {
1475         int error;
1476         struct mlx5_core_dev *mdev= sq->priv->mdev;
1477
1478         /*
1479          * Check if already stopped.
1480          *
1481          * NOTE: Serialization of this function is managed by the
1482          * caller ensuring the priv's state lock is locked or in case
1483          * of rate limit support, a single thread manages drain and
1484          * resume of SQs. The "running" variable can therefore safely
1485          * be read without any locks.
1486          */
1487         if (READ_ONCE(sq->running) == 0)
1488                 return;
1489
1490         /* don't put more packets into the SQ */
1491         WRITE_ONCE(sq->running, 0);
1492
1493         /* serialize access to DMA rings */
1494         mtx_lock(&sq->lock);
1495
1496         /* teardown event factor timer, if any */
1497         sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1498         callout_stop(&sq->cev_callout);
1499
1500         /* send dummy NOPs in order to flush the transmit ring */
1501         mlx5e_sq_send_nops_locked(sq, 1);
1502         mtx_unlock(&sq->lock);
1503
1504         /* make sure it is safe to free the callout */
1505         callout_drain(&sq->cev_callout);
1506
1507         /* wait till SQ is empty or link is down */
1508         mtx_lock(&sq->lock);
1509         while (sq->cc != sq->pc &&
1510             (sq->priv->media_status_last & IFM_ACTIVE) != 0 &&
1511             mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1512                 mtx_unlock(&sq->lock);
1513                 msleep(1);
1514                 sq->cq.mcq.comp(&sq->cq.mcq);
1515                 mtx_lock(&sq->lock);
1516         }
1517         mtx_unlock(&sq->lock);
1518
1519         /* error out remaining requests */
1520         error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1521         if (error != 0) {
1522                 if_printf(sq->ifp,
1523                     "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error);
1524         }
1525
1526         /* wait till SQ is empty */
1527         mtx_lock(&sq->lock);
1528         while (sq->cc != sq->pc &&
1529                mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1530                 mtx_unlock(&sq->lock);
1531                 msleep(1);
1532                 sq->cq.mcq.comp(&sq->cq.mcq);
1533                 mtx_lock(&sq->lock);
1534         }
1535         mtx_unlock(&sq->lock);
1536 }
1537
1538 static void
1539 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1540 {
1541
1542         mlx5e_drain_sq(sq);
1543         mlx5e_disable_sq(sq);
1544         mlx5e_destroy_sq(sq);
1545 }
1546
1547 static int
1548 mlx5e_create_cq(struct mlx5e_priv *priv,
1549     struct mlx5e_cq_param *param,
1550     struct mlx5e_cq *cq,
1551     mlx5e_cq_comp_t *comp,
1552     int eq_ix)
1553 {
1554         struct mlx5_core_dev *mdev = priv->mdev;
1555         struct mlx5_core_cq *mcq = &cq->mcq;
1556         int eqn_not_used;
1557         int irqn;
1558         int err;
1559         u32 i;
1560
1561         param->wq.buf_numa_node = 0;
1562         param->wq.db_numa_node = 0;
1563
1564         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1565             &cq->wq_ctrl);
1566         if (err)
1567                 return (err);
1568
1569         mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1570
1571         mcq->cqe_sz = 64;
1572         mcq->set_ci_db = cq->wq_ctrl.db.db;
1573         mcq->arm_db = cq->wq_ctrl.db.db + 1;
1574         *mcq->set_ci_db = 0;
1575         *mcq->arm_db = 0;
1576         mcq->vector = eq_ix;
1577         mcq->comp = comp;
1578         mcq->event = mlx5e_cq_error_event;
1579         mcq->irqn = irqn;
1580         mcq->uar = &priv->cq_uar;
1581
1582         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1583                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1584
1585                 cqe->op_own = 0xf1;
1586         }
1587
1588         cq->priv = priv;
1589
1590         return (0);
1591 }
1592
1593 static void
1594 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1595 {
1596         mlx5_wq_destroy(&cq->wq_ctrl);
1597 }
1598
1599 static int
1600 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1601 {
1602         struct mlx5_core_cq *mcq = &cq->mcq;
1603         void *in;
1604         void *cqc;
1605         int inlen;
1606         int irqn_not_used;
1607         int eqn;
1608         int err;
1609
1610         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1611             sizeof(u64) * cq->wq_ctrl.buf.npages;
1612         in = mlx5_vzalloc(inlen);
1613         if (in == NULL)
1614                 return (-ENOMEM);
1615
1616         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1617
1618         memcpy(cqc, param->cqc, sizeof(param->cqc));
1619
1620         mlx5_fill_page_array(&cq->wq_ctrl.buf,
1621             (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1622
1623         mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
1624
1625         MLX5_SET(cqc, cqc, c_eqn, eqn);
1626         MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1627         MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1628             PAGE_SHIFT);
1629         MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1630
1631         err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
1632
1633         kvfree(in);
1634
1635         if (err)
1636                 return (err);
1637
1638         mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock));
1639
1640         return (0);
1641 }
1642
1643 static void
1644 mlx5e_disable_cq(struct mlx5e_cq *cq)
1645 {
1646
1647         mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
1648 }
1649
1650 int
1651 mlx5e_open_cq(struct mlx5e_priv *priv,
1652     struct mlx5e_cq_param *param,
1653     struct mlx5e_cq *cq,
1654     mlx5e_cq_comp_t *comp,
1655     int eq_ix)
1656 {
1657         int err;
1658
1659         err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
1660         if (err)
1661                 return (err);
1662
1663         err = mlx5e_enable_cq(cq, param, eq_ix);
1664         if (err)
1665                 goto err_destroy_cq;
1666
1667         return (0);
1668
1669 err_destroy_cq:
1670         mlx5e_destroy_cq(cq);
1671
1672         return (err);
1673 }
1674
1675 void
1676 mlx5e_close_cq(struct mlx5e_cq *cq)
1677 {
1678         mlx5e_disable_cq(cq);
1679         mlx5e_destroy_cq(cq);
1680 }
1681
1682 static int
1683 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1684     struct mlx5e_channel_param *cparam)
1685 {
1686         int err;
1687         int tc;
1688
1689         for (tc = 0; tc < c->num_tc; tc++) {
1690                 /* open completion queue */
1691                 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
1692                     &mlx5e_tx_cq_comp, c->ix);
1693                 if (err)
1694                         goto err_close_tx_cqs;
1695         }
1696         return (0);
1697
1698 err_close_tx_cqs:
1699         for (tc--; tc >= 0; tc--)
1700                 mlx5e_close_cq(&c->sq[tc].cq);
1701
1702         return (err);
1703 }
1704
1705 static void
1706 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1707 {
1708         int tc;
1709
1710         for (tc = 0; tc < c->num_tc; tc++)
1711                 mlx5e_close_cq(&c->sq[tc].cq);
1712 }
1713
1714 static int
1715 mlx5e_open_sqs(struct mlx5e_channel *c,
1716     struct mlx5e_channel_param *cparam)
1717 {
1718         int err;
1719         int tc;
1720
1721         for (tc = 0; tc < c->num_tc; tc++) {
1722                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1723                 if (err)
1724                         goto err_close_sqs;
1725         }
1726
1727         return (0);
1728
1729 err_close_sqs:
1730         for (tc--; tc >= 0; tc--)
1731                 mlx5e_close_sq_wait(&c->sq[tc]);
1732
1733         return (err);
1734 }
1735
1736 static void
1737 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
1738 {
1739         int tc;
1740
1741         for (tc = 0; tc < c->num_tc; tc++)
1742                 mlx5e_close_sq_wait(&c->sq[tc]);
1743 }
1744
1745 static void
1746 mlx5e_chan_mtx_init(struct mlx5e_channel *c)
1747 {
1748         int tc;
1749
1750         mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
1751
1752         callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
1753
1754         for (tc = 0; tc < c->num_tc; tc++) {
1755                 struct mlx5e_sq *sq = c->sq + tc;
1756
1757                 mtx_init(&sq->lock, "mlx5tx",
1758                     MTX_NETWORK_LOCK " TX", MTX_DEF);
1759                 mtx_init(&sq->comp_lock, "mlx5comp",
1760                     MTX_NETWORK_LOCK " TX", MTX_DEF);
1761
1762                 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
1763
1764                 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1765
1766                 /* ensure the TX completion event factor is not zero */
1767                 if (sq->cev_factor == 0)
1768                         sq->cev_factor = 1;
1769         }
1770 }
1771
1772 static void
1773 mlx5e_chan_mtx_destroy(struct mlx5e_channel *c)
1774 {
1775         int tc;
1776
1777         mtx_destroy(&c->rq.mtx);
1778
1779         for (tc = 0; tc < c->num_tc; tc++) {
1780                 mtx_destroy(&c->sq[tc].lock);
1781                 mtx_destroy(&c->sq[tc].comp_lock);
1782         }
1783 }
1784
1785 static int
1786 mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1787     struct mlx5e_channel_param *cparam,
1788     struct mlx5e_channel *c)
1789 {
1790         int err;
1791
1792         memset(c, 0, sizeof(*c));
1793
1794         c->priv = priv;
1795         c->ix = ix;
1796         /* setup send tag */
1797         c->tag.m_snd_tag.ifp = priv->ifp;
1798         c->tag.type = IF_SND_TAG_TYPE_UNLIMITED;
1799         c->mkey_be = cpu_to_be32(priv->mr.key);
1800         c->num_tc = priv->num_tc;
1801
1802         /* init mutexes */
1803         mlx5e_chan_mtx_init(c);
1804
1805         /* open transmit completion queue */
1806         err = mlx5e_open_tx_cqs(c, cparam);
1807         if (err)
1808                 goto err_free;
1809
1810         /* open receive completion queue */
1811         err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
1812             &mlx5e_rx_cq_comp, c->ix);
1813         if (err)
1814                 goto err_close_tx_cqs;
1815
1816         err = mlx5e_open_sqs(c, cparam);
1817         if (err)
1818                 goto err_close_rx_cq;
1819
1820         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1821         if (err)
1822                 goto err_close_sqs;
1823
1824         /* poll receive queue initially */
1825         c->rq.cq.mcq.comp(&c->rq.cq.mcq);
1826
1827         return (0);
1828
1829 err_close_sqs:
1830         mlx5e_close_sqs_wait(c);
1831
1832 err_close_rx_cq:
1833         mlx5e_close_cq(&c->rq.cq);
1834
1835 err_close_tx_cqs:
1836         mlx5e_close_tx_cqs(c);
1837
1838 err_free:
1839         /* destroy mutexes */
1840         mlx5e_chan_mtx_destroy(c);
1841         return (err);
1842 }
1843
1844 static void
1845 mlx5e_close_channel(struct mlx5e_channel *c)
1846 {
1847         mlx5e_close_rq(&c->rq);
1848 }
1849
1850 static void
1851 mlx5e_close_channel_wait(struct mlx5e_channel *c)
1852 {
1853         mlx5e_close_rq_wait(&c->rq);
1854         mlx5e_close_sqs_wait(c);
1855         mlx5e_close_cq(&c->rq.cq);
1856         mlx5e_close_tx_cqs(c);
1857         /* destroy mutexes */
1858         mlx5e_chan_mtx_destroy(c);
1859 }
1860
1861 static int
1862 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs)
1863 {
1864         u32 r, n;
1865
1866         r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz :
1867             MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
1868         if (r > MJUM16BYTES)
1869                 return (-ENOMEM);
1870
1871         if (r > MJUM9BYTES)
1872                 r = MJUM16BYTES;
1873         else if (r > MJUMPAGESIZE)
1874                 r = MJUM9BYTES;
1875         else if (r > MCLBYTES)
1876                 r = MJUMPAGESIZE;
1877         else
1878                 r = MCLBYTES;
1879
1880         /*
1881          * n + 1 must be a power of two, because stride size must be.
1882          * Stride size is 16 * (n + 1), as the first segment is
1883          * control.
1884          */
1885         for (n = howmany(r, MLX5E_MAX_RX_BYTES); !powerof2(n + 1); n++)
1886                 ;
1887
1888         *wqe_sz = r;
1889         *nsegs = n;
1890         return (0);
1891 }
1892
1893 static void
1894 mlx5e_build_rq_param(struct mlx5e_priv *priv,
1895     struct mlx5e_rq_param *param)
1896 {
1897         void *rqc = param->rqc;
1898         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1899         u32 wqe_sz, nsegs;
1900
1901         mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
1902         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1903         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1904         MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) +
1905             nsegs * sizeof(struct mlx5_wqe_data_seg)));
1906         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1907         MLX5_SET(wq, wq, pd, priv->pdn);
1908
1909         param->wq.buf_numa_node = 0;
1910         param->wq.db_numa_node = 0;
1911         param->wq.linear = 1;
1912 }
1913
1914 static void
1915 mlx5e_build_sq_param(struct mlx5e_priv *priv,
1916     struct mlx5e_sq_param *param)
1917 {
1918         void *sqc = param->sqc;
1919         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1920
1921         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1922         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1923         MLX5_SET(wq, wq, pd, priv->pdn);
1924
1925         param->wq.buf_numa_node = 0;
1926         param->wq.db_numa_node = 0;
1927         param->wq.linear = 1;
1928 }
1929
1930 static void
1931 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1932     struct mlx5e_cq_param *param)
1933 {
1934         void *cqc = param->cqc;
1935
1936         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1937 }
1938
1939 static void
1940 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr)
1941 {
1942
1943         *ptr = net_dim_get_profile(mode, MLX5E_DIM_DEFAULT_PROFILE);
1944
1945         /* apply LRO restrictions */
1946         if (priv->params.hw_lro_en &&
1947             ptr->pkts > MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO) {
1948                 ptr->pkts = MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO;
1949         }
1950 }
1951
1952 static void
1953 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1954     struct mlx5e_cq_param *param)
1955 {
1956         struct net_dim_cq_moder curr;
1957         void *cqc = param->cqc;
1958
1959
1960         /*
1961          * TODO The sysctl to control on/off is a bool value for now, which means
1962          * we only support CSUM, once HASH is implemnted we'll need to address that.
1963          */
1964         if (priv->params.cqe_zipping_en) {
1965                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1966                 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
1967         }
1968
1969         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1970
1971         switch (priv->params.rx_cq_moderation_mode) {
1972         case 0:
1973                 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1974                 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1975                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1976                 break;
1977         case 1:
1978                 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1979                 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1980                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1981                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1982                 else
1983                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1984                 break;
1985         case 2:
1986                 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr);
1987                 MLX5_SET(cqc, cqc, cq_period, curr.usec);
1988                 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
1989                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1990                 break;
1991         case 3:
1992                 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr);
1993                 MLX5_SET(cqc, cqc, cq_period, curr.usec);
1994                 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
1995                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1996                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1997                 else
1998                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1999                 break;
2000         default:
2001                 break;
2002         }
2003
2004         mlx5e_dim_build_cq_param(priv, param);
2005
2006         mlx5e_build_common_cq_param(priv, param);
2007 }
2008
2009 static void
2010 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
2011     struct mlx5e_cq_param *param)
2012 {
2013         void *cqc = param->cqc;
2014
2015         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
2016         MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
2017         MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
2018
2019         switch (priv->params.tx_cq_moderation_mode) {
2020         case 0:
2021                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2022                 break;
2023         default:
2024                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
2025                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
2026                 else
2027                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
2028                 break;
2029         }
2030
2031         mlx5e_build_common_cq_param(priv, param);
2032 }
2033
2034 static void
2035 mlx5e_build_channel_param(struct mlx5e_priv *priv,
2036     struct mlx5e_channel_param *cparam)
2037 {
2038         memset(cparam, 0, sizeof(*cparam));
2039
2040         mlx5e_build_rq_param(priv, &cparam->rq);
2041         mlx5e_build_sq_param(priv, &cparam->sq);
2042         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
2043         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
2044 }
2045
2046 static int
2047 mlx5e_open_channels(struct mlx5e_priv *priv)
2048 {
2049         struct mlx5e_channel_param cparam;
2050         int err;
2051         int i;
2052         int j;
2053
2054         mlx5e_build_channel_param(priv, &cparam);
2055         for (i = 0; i < priv->params.num_channels; i++) {
2056                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
2057                 if (err)
2058                         goto err_close_channels;
2059         }
2060
2061         for (j = 0; j < priv->params.num_channels; j++) {
2062                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j].rq);
2063                 if (err)
2064                         goto err_close_channels;
2065         }
2066         return (0);
2067
2068 err_close_channels:
2069         while (i--) {
2070                 mlx5e_close_channel(&priv->channel[i]);
2071                 mlx5e_close_channel_wait(&priv->channel[i]);
2072         }
2073         return (err);
2074 }
2075
2076 static void
2077 mlx5e_close_channels(struct mlx5e_priv *priv)
2078 {
2079         int i;
2080
2081         for (i = 0; i < priv->params.num_channels; i++)
2082                 mlx5e_close_channel(&priv->channel[i]);
2083         for (i = 0; i < priv->params.num_channels; i++)
2084                 mlx5e_close_channel_wait(&priv->channel[i]);
2085 }
2086
2087 static int
2088 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
2089 {
2090
2091         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2092                 uint8_t cq_mode;
2093
2094                 switch (priv->params.tx_cq_moderation_mode) {
2095                 case 0:
2096                 case 2:
2097                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2098                         break;
2099                 default:
2100                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2101                         break;
2102                 }
2103
2104                 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq,
2105                     priv->params.tx_cq_moderation_usec,
2106                     priv->params.tx_cq_moderation_pkts,
2107                     cq_mode));
2108         }
2109
2110         return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
2111             priv->params.tx_cq_moderation_usec,
2112             priv->params.tx_cq_moderation_pkts));
2113 }
2114
2115 static int
2116 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
2117 {
2118
2119         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2120                 uint8_t cq_mode;
2121                 uint8_t dim_mode;
2122                 int retval;
2123
2124                 switch (priv->params.rx_cq_moderation_mode) {
2125                 case 0:
2126                 case 2:
2127                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2128                         dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2129                         break;
2130                 default:
2131                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2132                         dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
2133                         break;
2134                 }
2135
2136                 /* tear down dynamic interrupt moderation */
2137                 mtx_lock(&rq->mtx);
2138                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
2139                 mtx_unlock(&rq->mtx);
2140
2141                 /* wait for dynamic interrupt moderation work task, if any */
2142                 cancel_work_sync(&rq->dim.work);
2143
2144                 if (priv->params.rx_cq_moderation_mode >= 2) {
2145                         struct net_dim_cq_moder curr;
2146
2147                         mlx5e_get_default_profile(priv, dim_mode, &curr);
2148
2149                         retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2150                             curr.usec, curr.pkts, cq_mode);
2151
2152                         /* set dynamic interrupt moderation mode and zero defaults */
2153                         mtx_lock(&rq->mtx);
2154                         rq->dim.mode = dim_mode;
2155                         rq->dim.state = 0;
2156                         rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE;
2157                         mtx_unlock(&rq->mtx);
2158                 } else {
2159                         retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2160                             priv->params.rx_cq_moderation_usec,
2161                             priv->params.rx_cq_moderation_pkts,
2162                             cq_mode);
2163                 }
2164                 return (retval);
2165         }
2166
2167         return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
2168             priv->params.rx_cq_moderation_usec,
2169             priv->params.rx_cq_moderation_pkts));
2170 }
2171
2172 static int
2173 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
2174 {
2175         int err;
2176         int i;
2177
2178         err = mlx5e_refresh_rq_params(priv, &c->rq);
2179         if (err)
2180                 goto done;
2181
2182         for (i = 0; i != c->num_tc; i++) {
2183                 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
2184                 if (err)
2185                         goto done;
2186         }
2187 done:
2188         return (err);
2189 }
2190
2191 int
2192 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
2193 {
2194         int i;
2195
2196         /* check if channels are closed */
2197         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2198                 return (EINVAL);
2199
2200         for (i = 0; i < priv->params.num_channels; i++) {
2201                 int err;
2202
2203                 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]);
2204                 if (err)
2205                         return (err);
2206         }
2207         return (0);
2208 }
2209
2210 static int
2211 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
2212 {
2213         struct mlx5_core_dev *mdev = priv->mdev;
2214         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
2215         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2216
2217         memset(in, 0, sizeof(in));
2218
2219         MLX5_SET(tisc, tisc, prio, tc);
2220         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
2221
2222         return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
2223 }
2224
2225 static void
2226 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
2227 {
2228         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2229 }
2230
2231 static int
2232 mlx5e_open_tises(struct mlx5e_priv *priv)
2233 {
2234         int num_tc = priv->num_tc;
2235         int err;
2236         int tc;
2237
2238         for (tc = 0; tc < num_tc; tc++) {
2239                 err = mlx5e_open_tis(priv, tc);
2240                 if (err)
2241                         goto err_close_tises;
2242         }
2243
2244         return (0);
2245
2246 err_close_tises:
2247         for (tc--; tc >= 0; tc--)
2248                 mlx5e_close_tis(priv, tc);
2249
2250         return (err);
2251 }
2252
2253 static void
2254 mlx5e_close_tises(struct mlx5e_priv *priv)
2255 {
2256         int num_tc = priv->num_tc;
2257         int tc;
2258
2259         for (tc = 0; tc < num_tc; tc++)
2260                 mlx5e_close_tis(priv, tc);
2261 }
2262
2263 static int
2264 mlx5e_open_rqt(struct mlx5e_priv *priv)
2265 {
2266         struct mlx5_core_dev *mdev = priv->mdev;
2267         u32 *in;
2268         u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
2269         void *rqtc;
2270         int inlen;
2271         int err;
2272         int sz;
2273         int i;
2274
2275         sz = 1 << priv->params.rx_hash_log_tbl_sz;
2276
2277         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2278         in = mlx5_vzalloc(inlen);
2279         if (in == NULL)
2280                 return (-ENOMEM);
2281         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2282
2283         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2284         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2285
2286         for (i = 0; i < sz; i++) {
2287                 int ix = i;
2288 #ifdef RSS
2289                 ix = rss_get_indirection_to_bucket(ix);
2290 #endif
2291                 /* ensure we don't overflow */
2292                 ix %= priv->params.num_channels;
2293
2294                 /* apply receive side scaling stride, if any */
2295                 ix -= ix % (int)priv->params.channels_rsss;
2296
2297                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn);
2298         }
2299
2300         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
2301
2302         err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
2303         if (!err)
2304                 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
2305
2306         kvfree(in);
2307
2308         return (err);
2309 }
2310
2311 static void
2312 mlx5e_close_rqt(struct mlx5e_priv *priv)
2313 {
2314         u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0};
2315         u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0};
2316
2317         MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
2318         MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
2319
2320         mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out));
2321 }
2322
2323 static void
2324 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
2325 {
2326         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2327         __be32 *hkey;
2328
2329         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2330
2331 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2332
2333 #define MLX5_HASH_IP     (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2334                           MLX5_HASH_FIELD_SEL_DST_IP)
2335
2336 #define MLX5_HASH_ALL    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2337                           MLX5_HASH_FIELD_SEL_DST_IP   |\
2338                           MLX5_HASH_FIELD_SEL_L4_SPORT |\
2339                           MLX5_HASH_FIELD_SEL_L4_DPORT)
2340
2341 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2342                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2343                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2344
2345         if (priv->params.hw_lro_en) {
2346                 MLX5_SET(tirc, tirc, lro_enable_mask,
2347                     MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2348                     MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2349                 MLX5_SET(tirc, tirc, lro_max_msg_sz,
2350                     (priv->params.lro_wqe_sz -
2351                     ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2352                 /* TODO: add the option to choose timer value dynamically */
2353                 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
2354                     MLX5_CAP_ETH(priv->mdev,
2355                     lro_timer_supported_periods[2]));
2356         }
2357
2358         /* setup parameters for hashing TIR type, if any */
2359         switch (tt) {
2360         case MLX5E_TT_ANY:
2361                 MLX5_SET(tirc, tirc, disp_type,
2362                     MLX5_TIRC_DISP_TYPE_DIRECT);
2363                 MLX5_SET(tirc, tirc, inline_rqn,
2364                     priv->channel[0].rq.rqn);
2365                 break;
2366         default:
2367                 MLX5_SET(tirc, tirc, disp_type,
2368                     MLX5_TIRC_DISP_TYPE_INDIRECT);
2369                 MLX5_SET(tirc, tirc, indirect_table,
2370                     priv->rqtn);
2371                 MLX5_SET(tirc, tirc, rx_hash_fn,
2372                     MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
2373                 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
2374 #ifdef RSS
2375                 /*
2376                  * The FreeBSD RSS implementation does currently not
2377                  * support symmetric Toeplitz hashes:
2378                  */
2379                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
2380                 rss_getkey((uint8_t *)hkey);
2381 #else
2382                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2383                 hkey[0] = cpu_to_be32(0xD181C62C);
2384                 hkey[1] = cpu_to_be32(0xF7F4DB5B);
2385                 hkey[2] = cpu_to_be32(0x1983A2FC);
2386                 hkey[3] = cpu_to_be32(0x943E1ADB);
2387                 hkey[4] = cpu_to_be32(0xD9389E6B);
2388                 hkey[5] = cpu_to_be32(0xD1039C2C);
2389                 hkey[6] = cpu_to_be32(0xA74499AD);
2390                 hkey[7] = cpu_to_be32(0x593D56D9);
2391                 hkey[8] = cpu_to_be32(0xF3253C06);
2392                 hkey[9] = cpu_to_be32(0x2ADC1FFC);
2393 #endif
2394                 break;
2395         }
2396
2397         switch (tt) {
2398         case MLX5E_TT_IPV4_TCP:
2399                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2400                     MLX5_L3_PROT_TYPE_IPV4);
2401                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2402                     MLX5_L4_PROT_TYPE_TCP);
2403 #ifdef RSS
2404                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2405                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2406                             MLX5_HASH_IP);
2407                 } else
2408 #endif
2409                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2410                     MLX5_HASH_ALL);
2411                 break;
2412
2413         case MLX5E_TT_IPV6_TCP:
2414                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2415                     MLX5_L3_PROT_TYPE_IPV6);
2416                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2417                     MLX5_L4_PROT_TYPE_TCP);
2418 #ifdef RSS
2419                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2420                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2421                             MLX5_HASH_IP);
2422                 } else
2423 #endif
2424                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2425                     MLX5_HASH_ALL);
2426                 break;
2427
2428         case MLX5E_TT_IPV4_UDP:
2429                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2430                     MLX5_L3_PROT_TYPE_IPV4);
2431                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2432                     MLX5_L4_PROT_TYPE_UDP);
2433 #ifdef RSS
2434                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2435                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2436                             MLX5_HASH_IP);
2437                 } else
2438 #endif
2439                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2440                     MLX5_HASH_ALL);
2441                 break;
2442
2443         case MLX5E_TT_IPV6_UDP:
2444                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2445                     MLX5_L3_PROT_TYPE_IPV6);
2446                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2447                     MLX5_L4_PROT_TYPE_UDP);
2448 #ifdef RSS
2449                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2450                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2451                             MLX5_HASH_IP);
2452                 } else
2453 #endif
2454                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2455                     MLX5_HASH_ALL);
2456                 break;
2457
2458         case MLX5E_TT_IPV4_IPSEC_AH:
2459                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2460                     MLX5_L3_PROT_TYPE_IPV4);
2461                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2462                     MLX5_HASH_IP_IPSEC_SPI);
2463                 break;
2464
2465         case MLX5E_TT_IPV6_IPSEC_AH:
2466                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2467                     MLX5_L3_PROT_TYPE_IPV6);
2468                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2469                     MLX5_HASH_IP_IPSEC_SPI);
2470                 break;
2471
2472         case MLX5E_TT_IPV4_IPSEC_ESP:
2473                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2474                     MLX5_L3_PROT_TYPE_IPV4);
2475                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2476                     MLX5_HASH_IP_IPSEC_SPI);
2477                 break;
2478
2479         case MLX5E_TT_IPV6_IPSEC_ESP:
2480                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2481                     MLX5_L3_PROT_TYPE_IPV6);
2482                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2483                     MLX5_HASH_IP_IPSEC_SPI);
2484                 break;
2485
2486         case MLX5E_TT_IPV4:
2487                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2488                     MLX5_L3_PROT_TYPE_IPV4);
2489                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2490                     MLX5_HASH_IP);
2491                 break;
2492
2493         case MLX5E_TT_IPV6:
2494                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2495                     MLX5_L3_PROT_TYPE_IPV6);
2496                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2497                     MLX5_HASH_IP);
2498                 break;
2499
2500         default:
2501                 break;
2502         }
2503 }
2504
2505 static int
2506 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2507 {
2508         struct mlx5_core_dev *mdev = priv->mdev;
2509         u32 *in;
2510         void *tirc;
2511         int inlen;
2512         int err;
2513
2514         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2515         in = mlx5_vzalloc(inlen);
2516         if (in == NULL)
2517                 return (-ENOMEM);
2518         tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2519
2520         mlx5e_build_tir_ctx(priv, tirc, tt);
2521
2522         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2523
2524         kvfree(in);
2525
2526         return (err);
2527 }
2528
2529 static void
2530 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2531 {
2532         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2533 }
2534
2535 static int
2536 mlx5e_open_tirs(struct mlx5e_priv *priv)
2537 {
2538         int err;
2539         int i;
2540
2541         for (i = 0; i < MLX5E_NUM_TT; i++) {
2542                 err = mlx5e_open_tir(priv, i);
2543                 if (err)
2544                         goto err_close_tirs;
2545         }
2546
2547         return (0);
2548
2549 err_close_tirs:
2550         for (i--; i >= 0; i--)
2551                 mlx5e_close_tir(priv, i);
2552
2553         return (err);
2554 }
2555
2556 static void
2557 mlx5e_close_tirs(struct mlx5e_priv *priv)
2558 {
2559         int i;
2560
2561         for (i = 0; i < MLX5E_NUM_TT; i++)
2562                 mlx5e_close_tir(priv, i);
2563 }
2564
2565 /*
2566  * SW MTU does not include headers,
2567  * HW MTU includes all headers and checksums.
2568  */
2569 static int
2570 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2571 {
2572         struct mlx5e_priv *priv = ifp->if_softc;
2573         struct mlx5_core_dev *mdev = priv->mdev;
2574         int hw_mtu;
2575         int err;
2576
2577         hw_mtu = MLX5E_SW2HW_MTU(sw_mtu);
2578
2579         err = mlx5_set_port_mtu(mdev, hw_mtu);
2580         if (err) {
2581                 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n",
2582                     __func__, sw_mtu, err);
2583                 return (err);
2584         }
2585
2586         /* Update vport context MTU */
2587         err = mlx5_set_vport_mtu(mdev, hw_mtu);
2588         if (err) {
2589                 if_printf(ifp, "%s: Failed updating vport context with MTU size, err=%d\n",
2590                     __func__, err);
2591         }
2592
2593         ifp->if_mtu = sw_mtu;
2594
2595         err = mlx5_query_vport_mtu(mdev, &hw_mtu);
2596         if (err || !hw_mtu) {
2597                 /* fallback to port oper mtu */
2598                 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2599         }
2600         if (err) {
2601                 if_printf(ifp, "Query port MTU, after setting new "
2602                     "MTU value, failed\n");
2603                 return (err);
2604         } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
2605                 err = -E2BIG,
2606                 if_printf(ifp, "Port MTU %d is smaller than "
2607                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2608         } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
2609                 err = -EINVAL;
2610                 if_printf(ifp, "Port MTU %d is bigger than "
2611                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2612         }
2613         priv->params_ethtool.hw_mtu = hw_mtu;
2614
2615         return (err);
2616 }
2617
2618 int
2619 mlx5e_open_locked(struct ifnet *ifp)
2620 {
2621         struct mlx5e_priv *priv = ifp->if_softc;
2622         int err;
2623         u16 set_id;
2624
2625         /* check if already opened */
2626         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2627                 return (0);
2628
2629 #ifdef RSS
2630         if (rss_getnumbuckets() > priv->params.num_channels) {
2631                 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than "
2632                     "channels(%u) available\n", rss_getnumbuckets(),
2633                     priv->params.num_channels);
2634         }
2635 #endif
2636         err = mlx5e_open_tises(priv);
2637         if (err) {
2638                 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n",
2639                     __func__, err);
2640                 return (err);
2641         }
2642         err = mlx5_vport_alloc_q_counter(priv->mdev,
2643             MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
2644         if (err) {
2645                 if_printf(priv->ifp,
2646                     "%s: mlx5_vport_alloc_q_counter failed: %d\n",
2647                     __func__, err);
2648                 goto err_close_tises;
2649         }
2650         /* store counter set ID */
2651         priv->counter_set_id = set_id;
2652
2653         err = mlx5e_open_channels(priv);
2654         if (err) {
2655                 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n",
2656                     __func__, err);
2657                 goto err_dalloc_q_counter;
2658         }
2659         err = mlx5e_open_rqt(priv);
2660         if (err) {
2661                 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n",
2662                     __func__, err);
2663                 goto err_close_channels;
2664         }
2665         err = mlx5e_open_tirs(priv);
2666         if (err) {
2667                 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n",
2668                     __func__, err);
2669                 goto err_close_rqls;
2670         }
2671         err = mlx5e_open_flow_table(priv);
2672         if (err) {
2673                 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n",
2674                     __func__, err);
2675                 goto err_close_tirs;
2676         }
2677         err = mlx5e_add_all_vlan_rules(priv);
2678         if (err) {
2679                 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
2680                     __func__, err);
2681                 goto err_close_flow_table;
2682         }
2683         set_bit(MLX5E_STATE_OPENED, &priv->state);
2684
2685         mlx5e_update_carrier(priv);
2686         mlx5e_set_rx_mode_core(priv);
2687
2688         return (0);
2689
2690 err_close_flow_table:
2691         mlx5e_close_flow_table(priv);
2692
2693 err_close_tirs:
2694         mlx5e_close_tirs(priv);
2695
2696 err_close_rqls:
2697         mlx5e_close_rqt(priv);
2698
2699 err_close_channels:
2700         mlx5e_close_channels(priv);
2701
2702 err_dalloc_q_counter:
2703         mlx5_vport_dealloc_q_counter(priv->mdev,
2704             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2705
2706 err_close_tises:
2707         mlx5e_close_tises(priv);
2708
2709         return (err);
2710 }
2711
2712 static void
2713 mlx5e_open(void *arg)
2714 {
2715         struct mlx5e_priv *priv = arg;
2716
2717         PRIV_LOCK(priv);
2718         if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
2719                 if_printf(priv->ifp,
2720                     "%s: Setting port status to up failed\n",
2721                     __func__);
2722
2723         mlx5e_open_locked(priv->ifp);
2724         priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
2725         PRIV_UNLOCK(priv);
2726 }
2727
2728 int
2729 mlx5e_close_locked(struct ifnet *ifp)
2730 {
2731         struct mlx5e_priv *priv = ifp->if_softc;
2732
2733         /* check if already closed */
2734         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2735                 return (0);
2736
2737         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2738
2739         mlx5e_set_rx_mode_core(priv);
2740         mlx5e_del_all_vlan_rules(priv);
2741         if_link_state_change(priv->ifp, LINK_STATE_DOWN);
2742         mlx5e_close_flow_table(priv);
2743         mlx5e_close_tirs(priv);
2744         mlx5e_close_rqt(priv);
2745         mlx5e_close_channels(priv);
2746         mlx5_vport_dealloc_q_counter(priv->mdev,
2747             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2748         mlx5e_close_tises(priv);
2749
2750         return (0);
2751 }
2752
2753 #if (__FreeBSD_version >= 1100000)
2754 static uint64_t
2755 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
2756 {
2757         struct mlx5e_priv *priv = ifp->if_softc;
2758         u64 retval;
2759
2760         /* PRIV_LOCK(priv); XXX not allowed */
2761         switch (cnt) {
2762         case IFCOUNTER_IPACKETS:
2763                 retval = priv->stats.vport.rx_packets;
2764                 break;
2765         case IFCOUNTER_IERRORS:
2766                 retval = priv->stats.vport.rx_error_packets +
2767                     priv->stats.pport.alignment_err +
2768                     priv->stats.pport.check_seq_err +
2769                     priv->stats.pport.crc_align_errors +
2770                     priv->stats.pport.in_range_len_errors +
2771                     priv->stats.pport.jabbers +
2772                     priv->stats.pport.out_of_range_len +
2773                     priv->stats.pport.oversize_pkts +
2774                     priv->stats.pport.symbol_err +
2775                     priv->stats.pport.too_long_errors +
2776                     priv->stats.pport.undersize_pkts +
2777                     priv->stats.pport.unsupported_op_rx;
2778                 break;
2779         case IFCOUNTER_IQDROPS:
2780                 retval = priv->stats.vport.rx_out_of_buffer +
2781                     priv->stats.pport.drop_events;
2782                 break;
2783         case IFCOUNTER_OPACKETS:
2784                 retval = priv->stats.vport.tx_packets;
2785                 break;
2786         case IFCOUNTER_OERRORS:
2787                 retval = priv->stats.vport.tx_error_packets;
2788                 break;
2789         case IFCOUNTER_IBYTES:
2790                 retval = priv->stats.vport.rx_bytes;
2791                 break;
2792         case IFCOUNTER_OBYTES:
2793                 retval = priv->stats.vport.tx_bytes;
2794                 break;
2795         case IFCOUNTER_IMCASTS:
2796                 retval = priv->stats.vport.rx_multicast_packets;
2797                 break;
2798         case IFCOUNTER_OMCASTS:
2799                 retval = priv->stats.vport.tx_multicast_packets;
2800                 break;
2801         case IFCOUNTER_OQDROPS:
2802                 retval = priv->stats.vport.tx_queue_dropped;
2803                 break;
2804         case IFCOUNTER_COLLISIONS:
2805                 retval = priv->stats.pport.collisions;
2806                 break;
2807         default:
2808                 retval = if_get_counter_default(ifp, cnt);
2809                 break;
2810         }
2811         /* PRIV_UNLOCK(priv); XXX not allowed */
2812         return (retval);
2813 }
2814 #endif
2815
2816 static void
2817 mlx5e_set_rx_mode(struct ifnet *ifp)
2818 {
2819         struct mlx5e_priv *priv = ifp->if_softc;
2820
2821         queue_work(priv->wq, &priv->set_rx_mode_work);
2822 }
2823
2824 static int
2825 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2826 {
2827         struct mlx5e_priv *priv;
2828         struct ifreq *ifr;
2829         struct ifi2creq i2c;
2830         int error = 0;
2831         int mask = 0;
2832         int size_read = 0;
2833         int module_status;
2834         int module_num;
2835         int max_mtu;
2836         uint8_t read_addr;
2837
2838         priv = ifp->if_softc;
2839
2840         /* check if detaching */
2841         if (priv == NULL || priv->gone != 0)
2842                 return (ENXIO);
2843
2844         switch (command) {
2845         case SIOCSIFMTU:
2846                 ifr = (struct ifreq *)data;
2847
2848                 PRIV_LOCK(priv);
2849                 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
2850
2851                 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
2852                     ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
2853                         int was_opened;
2854
2855                         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2856                         if (was_opened)
2857                                 mlx5e_close_locked(ifp);
2858
2859                         /* set new MTU */
2860                         mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
2861
2862                         if (was_opened)
2863                                 mlx5e_open_locked(ifp);
2864                 } else {
2865                         error = EINVAL;
2866                         if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n",
2867                             MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
2868                 }
2869                 PRIV_UNLOCK(priv);
2870                 break;
2871         case SIOCSIFFLAGS:
2872                 if ((ifp->if_flags & IFF_UP) &&
2873                     (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2874                         mlx5e_set_rx_mode(ifp);
2875                         break;
2876                 }
2877                 PRIV_LOCK(priv);
2878                 if (ifp->if_flags & IFF_UP) {
2879                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2880                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2881                                         mlx5e_open_locked(ifp);
2882                                 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2883                                 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
2884                         }
2885                 } else {
2886                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2887                                 mlx5_set_port_status(priv->mdev,
2888                                     MLX5_PORT_DOWN);
2889                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2890                                         mlx5e_close_locked(ifp);
2891                                 mlx5e_update_carrier(priv);
2892                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2893                         }
2894                 }
2895                 PRIV_UNLOCK(priv);
2896                 break;
2897         case SIOCADDMULTI:
2898         case SIOCDELMULTI:
2899                 mlx5e_set_rx_mode(ifp);
2900                 break;
2901         case SIOCSIFMEDIA:
2902         case SIOCGIFMEDIA:
2903         case SIOCGIFXMEDIA:
2904                 ifr = (struct ifreq *)data;
2905                 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
2906                 break;
2907         case SIOCSIFCAP:
2908                 ifr = (struct ifreq *)data;
2909                 PRIV_LOCK(priv);
2910                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2911
2912                 if (mask & IFCAP_TXCSUM) {
2913                         ifp->if_capenable ^= IFCAP_TXCSUM;
2914                         ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2915
2916                         if (IFCAP_TSO4 & ifp->if_capenable &&
2917                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2918                                 ifp->if_capenable &= ~IFCAP_TSO4;
2919                                 ifp->if_hwassist &= ~CSUM_IP_TSO;
2920                                 if_printf(ifp,
2921                                     "tso4 disabled due to -txcsum.\n");
2922                         }
2923                 }
2924                 if (mask & IFCAP_TXCSUM_IPV6) {
2925                         ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
2926                         ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2927
2928                         if (IFCAP_TSO6 & ifp->if_capenable &&
2929                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2930                                 ifp->if_capenable &= ~IFCAP_TSO6;
2931                                 ifp->if_hwassist &= ~CSUM_IP6_TSO;
2932                                 if_printf(ifp,
2933                                     "tso6 disabled due to -txcsum6.\n");
2934                         }
2935                 }
2936                 if (mask & IFCAP_RXCSUM)
2937                         ifp->if_capenable ^= IFCAP_RXCSUM;
2938                 if (mask & IFCAP_RXCSUM_IPV6)
2939                         ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
2940                 if (mask & IFCAP_TSO4) {
2941                         if (!(IFCAP_TSO4 & ifp->if_capenable) &&
2942                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2943                                 if_printf(ifp, "enable txcsum first.\n");
2944                                 error = EAGAIN;
2945                                 goto out;
2946                         }
2947                         ifp->if_capenable ^= IFCAP_TSO4;
2948                         ifp->if_hwassist ^= CSUM_IP_TSO;
2949                 }
2950                 if (mask & IFCAP_TSO6) {
2951                         if (!(IFCAP_TSO6 & ifp->if_capenable) &&
2952                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2953                                 if_printf(ifp, "enable txcsum6 first.\n");
2954                                 error = EAGAIN;
2955                                 goto out;
2956                         }
2957                         ifp->if_capenable ^= IFCAP_TSO6;
2958                         ifp->if_hwassist ^= CSUM_IP6_TSO;
2959                 }
2960                 if (mask & IFCAP_VLAN_HWFILTER) {
2961                         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
2962                                 mlx5e_disable_vlan_filter(priv);
2963                         else
2964                                 mlx5e_enable_vlan_filter(priv);
2965
2966                         ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
2967                 }
2968                 if (mask & IFCAP_VLAN_HWTAGGING)
2969                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2970                 if (mask & IFCAP_WOL_MAGIC)
2971                         ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2972
2973                 VLAN_CAPABILITIES(ifp);
2974                 /* turn off LRO means also turn of HW LRO - if it's on */
2975                 if (mask & IFCAP_LRO) {
2976                         int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2977                         bool need_restart = false;
2978
2979                         ifp->if_capenable ^= IFCAP_LRO;
2980
2981                         /* figure out if updating HW LRO is needed */
2982                         if (!(ifp->if_capenable & IFCAP_LRO)) {
2983                                 if (priv->params.hw_lro_en) {
2984                                         priv->params.hw_lro_en = false;
2985                                         need_restart = true;
2986                                 }
2987                         } else {
2988                                 if (priv->params.hw_lro_en == false &&
2989                                     priv->params_ethtool.hw_lro != 0) {
2990                                         priv->params.hw_lro_en = true;
2991                                         need_restart = true;
2992                                 }
2993                         }
2994                         if (was_opened && need_restart) {
2995                                 mlx5e_close_locked(ifp);
2996                                 mlx5e_open_locked(ifp);
2997                         }
2998                 }
2999                 if (mask & IFCAP_HWRXTSTMP) {
3000                         ifp->if_capenable ^= IFCAP_HWRXTSTMP;
3001                         if (ifp->if_capenable & IFCAP_HWRXTSTMP) {
3002                                 if (priv->clbr_done == 0)
3003                                         mlx5e_reset_calibration_callout(priv);
3004                         } else {
3005                                 callout_drain(&priv->tstmp_clbr);
3006                                 priv->clbr_done = 0;
3007                         }
3008                 }
3009 out:
3010                 PRIV_UNLOCK(priv);
3011                 break;
3012
3013         case SIOCGI2C:
3014                 ifr = (struct ifreq *)data;
3015
3016                 /*
3017                  * Copy from the user-space address ifr_data to the
3018                  * kernel-space address i2c
3019                  */
3020                 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
3021                 if (error)
3022                         break;
3023
3024                 if (i2c.len > sizeof(i2c.data)) {
3025                         error = EINVAL;
3026                         break;
3027                 }
3028
3029                 PRIV_LOCK(priv);
3030                 /* Get module_num which is required for the query_eeprom */
3031                 error = mlx5_query_module_num(priv->mdev, &module_num);
3032                 if (error) {
3033                         if_printf(ifp, "Query module num failed, eeprom "
3034                             "reading is not supported\n");
3035                         error = EINVAL;
3036                         goto err_i2c;
3037                 }
3038                 /* Check if module is present before doing an access */
3039                 module_status = mlx5_query_module_status(priv->mdev, module_num);
3040                 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED &&
3041                     module_status != MLX5_MODULE_STATUS_PLUGGED_DISABLED) {
3042                         error = EINVAL;
3043                         goto err_i2c;
3044                 }
3045                 /*
3046                  * Currently 0XA0 and 0xA2 are the only addresses permitted.
3047                  * The internal conversion is as follows:
3048                  */
3049                 if (i2c.dev_addr == 0xA0)
3050                         read_addr = MLX5E_I2C_ADDR_LOW;
3051                 else if (i2c.dev_addr == 0xA2)
3052                         read_addr = MLX5E_I2C_ADDR_HIGH;
3053                 else {
3054                         if_printf(ifp, "Query eeprom failed, "
3055                             "Invalid Address: %X\n", i2c.dev_addr);
3056                         error = EINVAL;
3057                         goto err_i2c;
3058                 }
3059                 error = mlx5_query_eeprom(priv->mdev,
3060                     read_addr, MLX5E_EEPROM_LOW_PAGE,
3061                     (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
3062                     (uint32_t *)i2c.data, &size_read);
3063                 if (error) {
3064                         if_printf(ifp, "Query eeprom failed, eeprom "
3065                             "reading is not supported\n");
3066                         error = EINVAL;
3067                         goto err_i2c;
3068                 }
3069
3070                 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
3071                         error = mlx5_query_eeprom(priv->mdev,
3072                             read_addr, MLX5E_EEPROM_LOW_PAGE,
3073                             (uint32_t)(i2c.offset + size_read),
3074                             (uint32_t)(i2c.len - size_read), module_num,
3075                             (uint32_t *)(i2c.data + size_read), &size_read);
3076                 }
3077                 if (error) {
3078                         if_printf(ifp, "Query eeprom failed, eeprom "
3079                             "reading is not supported\n");
3080                         error = EINVAL;
3081                         goto err_i2c;
3082                 }
3083
3084                 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
3085 err_i2c:
3086                 PRIV_UNLOCK(priv);
3087                 break;
3088
3089         default:
3090                 error = ether_ioctl(ifp, command, data);
3091                 break;
3092         }
3093         return (error);
3094 }
3095
3096 static int
3097 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
3098 {
3099         /*
3100          * TODO: uncoment once FW really sets all these bits if
3101          * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
3102          * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
3103          * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
3104          * -ENOTSUPP;
3105          */
3106
3107         /* TODO: add more must-to-have features */
3108
3109         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
3110                 return (-ENODEV);
3111
3112         return (0);
3113 }
3114
3115 static u16
3116 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
3117 {
3118         uint32_t bf_buf_size = (1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U;
3119
3120         bf_buf_size -= sizeof(struct mlx5e_tx_wqe) - 2;
3121
3122         /* verify against driver hardware limit */
3123         if (bf_buf_size > MLX5E_MAX_TX_INLINE)
3124                 bf_buf_size = MLX5E_MAX_TX_INLINE;
3125
3126         return (bf_buf_size);
3127 }
3128
3129 static int
3130 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
3131     struct mlx5e_priv *priv,
3132     int num_comp_vectors)
3133 {
3134         int err;
3135
3136         /*
3137          * TODO: Consider link speed for setting "log_sq_size",
3138          * "log_rq_size" and "cq_moderation_xxx":
3139          */
3140         priv->params.log_sq_size =
3141             MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3142         priv->params.log_rq_size =
3143             MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3144         priv->params.rx_cq_moderation_usec =
3145             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3146             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
3147             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3148         priv->params.rx_cq_moderation_mode =
3149             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
3150         priv->params.rx_cq_moderation_pkts =
3151             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3152         priv->params.tx_cq_moderation_usec =
3153             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3154         priv->params.tx_cq_moderation_pkts =
3155             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3156         priv->params.min_rx_wqes =
3157             MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
3158         priv->params.rx_hash_log_tbl_sz =
3159             (order_base_2(num_comp_vectors) >
3160             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
3161             order_base_2(num_comp_vectors) :
3162             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
3163         priv->params.num_tc = 1;
3164         priv->params.default_vlan_prio = 0;
3165         priv->counter_set_id = -1;
3166         priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3167
3168         err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3169         if (err)
3170                 return (err);
3171
3172         /*
3173          * hw lro is currently defaulted to off. when it won't anymore we
3174          * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
3175          */
3176         priv->params.hw_lro_en = false;
3177         priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3178
3179         priv->params.cqe_zipping_en = !!MLX5_CAP_GEN(mdev, cqe_compression);
3180
3181         priv->mdev = mdev;
3182         priv->params.num_channels = num_comp_vectors;
3183         priv->params.channels_rsss = 1;
3184         priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
3185         priv->queue_mapping_channel_mask =
3186             roundup_pow_of_two(num_comp_vectors) - 1;
3187         priv->num_tc = priv->params.num_tc;
3188         priv->default_vlan_prio = priv->params.default_vlan_prio;
3189
3190         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3191         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3192         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3193
3194         return (0);
3195 }
3196
3197 static int
3198 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
3199                   struct mlx5_core_mr *mkey)
3200 {
3201         struct ifnet *ifp = priv->ifp;
3202         struct mlx5_core_dev *mdev = priv->mdev;
3203         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3204         void *mkc;
3205         u32 *in;
3206         int err;
3207
3208         in = mlx5_vzalloc(inlen);
3209         if (in == NULL) {
3210                 if_printf(ifp, "%s: failed to allocate inbox\n", __func__);
3211                 return (-ENOMEM);
3212         }
3213
3214         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3215         MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA);
3216         MLX5_SET(mkc, mkc, lw, 1);
3217         MLX5_SET(mkc, mkc, lr, 1);
3218
3219         MLX5_SET(mkc, mkc, pd, pdn);
3220         MLX5_SET(mkc, mkc, length64, 1);
3221         MLX5_SET(mkc, mkc, qpn, 0xffffff);
3222
3223         err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
3224         if (err)
3225                 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n",
3226                     __func__, err);
3227
3228         kvfree(in);
3229         return (err);
3230 }
3231
3232 static const char *mlx5e_vport_stats_desc[] = {
3233         MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
3234 };
3235
3236 static const char *mlx5e_pport_stats_desc[] = {
3237         MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
3238 };
3239
3240 static void
3241 mlx5e_priv_mtx_init(struct mlx5e_priv *priv)
3242 {
3243         mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
3244         sx_init(&priv->state_lock, "mlx5state");
3245         callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
3246         MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
3247 }
3248
3249 static void
3250 mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv)
3251 {
3252         mtx_destroy(&priv->async_events_mtx);
3253         sx_destroy(&priv->state_lock);
3254 }
3255
3256 static int
3257 sysctl_firmware(SYSCTL_HANDLER_ARGS)
3258 {
3259         /*
3260          * %d.%d%.d the string format.
3261          * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
3262          * We need at most 5 chars to store that.
3263          * It also has: two "." and NULL at the end, which means we need 18
3264          * (5*3 + 3) chars at most.
3265          */
3266         char fw[18];
3267         struct mlx5e_priv *priv = arg1;
3268         int error;
3269
3270         snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
3271             fw_rev_sub(priv->mdev));
3272         error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
3273         return (error);
3274 }
3275
3276 static void
3277 mlx5e_disable_tx_dma(struct mlx5e_channel *ch)
3278 {
3279         int i;
3280
3281         for (i = 0; i < ch->num_tc; i++)
3282                 mlx5e_drain_sq(&ch->sq[i]);
3283 }
3284
3285 static void
3286 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq)
3287 {
3288
3289         sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP);
3290         sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8);
3291         mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
3292         sq->doorbell.d64 = 0;
3293 }
3294
3295 void
3296 mlx5e_resume_sq(struct mlx5e_sq *sq)
3297 {
3298         int err;
3299
3300         /* check if already enabled */
3301         if (READ_ONCE(sq->running) != 0)
3302                 return;
3303
3304         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR,
3305             MLX5_SQC_STATE_RST);
3306         if (err != 0) {
3307                 if_printf(sq->ifp,
3308                     "mlx5e_modify_sq() from ERR to RST failed: %d\n", err);
3309         }
3310
3311         sq->cc = 0;
3312         sq->pc = 0;
3313
3314         /* reset doorbell prior to moving from RST to RDY */
3315         mlx5e_reset_sq_doorbell_record(sq);
3316
3317         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST,
3318             MLX5_SQC_STATE_RDY);
3319         if (err != 0) {
3320                 if_printf(sq->ifp,
3321                     "mlx5e_modify_sq() from RST to RDY failed: %d\n", err);
3322         }
3323
3324         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
3325         WRITE_ONCE(sq->running, 1);
3326 }
3327
3328 static void
3329 mlx5e_enable_tx_dma(struct mlx5e_channel *ch)
3330 {
3331         int i;
3332
3333         for (i = 0; i < ch->num_tc; i++)
3334                 mlx5e_resume_sq(&ch->sq[i]);
3335 }
3336
3337 static void
3338 mlx5e_disable_rx_dma(struct mlx5e_channel *ch)
3339 {
3340         struct mlx5e_rq *rq = &ch->rq;
3341         int err;
3342
3343         mtx_lock(&rq->mtx);
3344         rq->enabled = 0;
3345         callout_stop(&rq->watchdog);
3346         mtx_unlock(&rq->mtx);
3347
3348         callout_drain(&rq->watchdog);
3349
3350         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
3351         if (err != 0) {
3352                 if_printf(rq->ifp,
3353                     "mlx5e_modify_rq() from RDY to RST failed: %d\n", err);
3354         }
3355
3356         while (!mlx5_wq_ll_is_empty(&rq->wq)) {
3357                 msleep(1);
3358                 rq->cq.mcq.comp(&rq->cq.mcq);
3359         }
3360
3361         /*
3362          * Transitioning into RST state will allow the FW to track less ERR state queues,
3363          * thus reducing the recv queue flushing time
3364          */
3365         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST);
3366         if (err != 0) {
3367                 if_printf(rq->ifp,
3368                     "mlx5e_modify_rq() from ERR to RST failed: %d\n", err);
3369         }
3370 }
3371
3372 static void
3373 mlx5e_enable_rx_dma(struct mlx5e_channel *ch)
3374 {
3375         struct mlx5e_rq *rq = &ch->rq;
3376         int err;
3377
3378         rq->wq.wqe_ctr = 0;
3379         mlx5_wq_ll_update_db_record(&rq->wq);
3380         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3381         if (err != 0) {
3382                 if_printf(rq->ifp,
3383                     "mlx5e_modify_rq() from RST to RDY failed: %d\n", err);
3384         }
3385
3386         rq->enabled = 1;
3387
3388         rq->cq.mcq.comp(&rq->cq.mcq);
3389 }
3390
3391 void
3392 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value)
3393 {
3394         int i;
3395
3396         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3397                 return;
3398
3399         for (i = 0; i < priv->params.num_channels; i++) {
3400                 if (value)
3401                         mlx5e_disable_tx_dma(&priv->channel[i]);
3402                 else
3403                         mlx5e_enable_tx_dma(&priv->channel[i]);
3404         }
3405 }
3406
3407 void
3408 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value)
3409 {
3410         int i;
3411
3412         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3413                 return;
3414
3415         for (i = 0; i < priv->params.num_channels; i++) {
3416                 if (value)
3417                         mlx5e_disable_rx_dma(&priv->channel[i]);
3418                 else
3419                         mlx5e_enable_rx_dma(&priv->channel[i]);
3420         }
3421 }
3422
3423 static void
3424 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
3425 {
3426         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3427             OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
3428             sysctl_firmware, "A", "HCA firmware version");
3429
3430         SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3431             OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
3432             "Board ID");
3433 }
3434
3435 static int
3436 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3437 {
3438         struct mlx5e_priv *priv = arg1;
3439         uint32_t tx_pfc;
3440         uint32_t value;
3441         int error;
3442
3443         PRIV_LOCK(priv);
3444
3445         tx_pfc = priv->params.tx_priority_flow_control;
3446
3447         /* get current value */
3448         value = (tx_pfc >> arg2) & 1;
3449
3450         error = sysctl_handle_32(oidp, &value, 0, req);
3451
3452         /* range check value */
3453         if (value != 0)
3454                 priv->params.tx_priority_flow_control |= (1 << arg2);
3455         else
3456                 priv->params.tx_priority_flow_control &= ~(1 << arg2);
3457
3458         /* check if update is required */
3459         if (error == 0 && priv->gone == 0 &&
3460             tx_pfc != priv->params.tx_priority_flow_control) {
3461                 error = -mlx5e_set_port_pfc(priv);
3462                 /* restore previous value */
3463                 if (error != 0)
3464                         priv->params.tx_priority_flow_control= tx_pfc;
3465         }
3466         PRIV_UNLOCK(priv);
3467
3468         return (error);
3469 }
3470
3471 static int
3472 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3473 {
3474         struct mlx5e_priv *priv = arg1;
3475         uint32_t rx_pfc;
3476         uint32_t value;
3477         int error;
3478
3479         PRIV_LOCK(priv);
3480
3481         rx_pfc = priv->params.rx_priority_flow_control;
3482
3483         /* get current value */
3484         value = (rx_pfc >> arg2) & 1;
3485
3486         error = sysctl_handle_32(oidp, &value, 0, req);
3487
3488         /* range check value */
3489         if (value != 0)
3490                 priv->params.rx_priority_flow_control |= (1 << arg2);
3491         else
3492                 priv->params.rx_priority_flow_control &= ~(1 << arg2);
3493
3494         /* check if update is required */
3495         if (error == 0 && priv->gone == 0 &&
3496             rx_pfc != priv->params.rx_priority_flow_control) {
3497                 error = -mlx5e_set_port_pfc(priv);
3498                 /* restore previous value */
3499                 if (error != 0)
3500                         priv->params.rx_priority_flow_control= rx_pfc;
3501         }
3502         PRIV_UNLOCK(priv);
3503
3504         return (error);
3505 }
3506
3507 static void
3508 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
3509 {
3510         unsigned int x;
3511         char path[96];
3512         int error;
3513
3514         /* enable pauseframes by default */
3515         priv->params.tx_pauseframe_control = 1;
3516         priv->params.rx_pauseframe_control = 1;
3517
3518         /* disable ports flow control, PFC, by default */
3519         priv->params.tx_priority_flow_control = 0;
3520         priv->params.rx_priority_flow_control = 0;
3521
3522 #if (__FreeBSD_version < 1100000)
3523         /* compute path for sysctl */
3524         snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
3525             device_get_unit(priv->mdev->pdev->dev.bsddev));
3526
3527         /* try to fetch tunable, if any */
3528         TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
3529
3530         /* compute path for sysctl */
3531         snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
3532             device_get_unit(priv->mdev->pdev->dev.bsddev));
3533
3534         /* try to fetch tunable, if any */
3535         TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
3536
3537         for (x = 0; x != 8; x++) {
3538
3539                 /* compute path for sysctl */
3540                 snprintf(path, sizeof(path), "dev.mce.%d.tx_priority_flow_control_%u",
3541                     device_get_unit(priv->mdev->pdev->dev.bsddev), x);
3542
3543                 /* try to fetch tunable, if any */
3544                 if (TUNABLE_INT_FETCH(path, &value) == 0 && value != 0)
3545                         priv->params.tx_priority_flow_control |= 1 << x;
3546
3547                 /* compute path for sysctl */
3548                 snprintf(path, sizeof(path), "dev.mce.%d.rx_priority_flow_control_%u",
3549                     device_get_unit(priv->mdev->pdev->dev.bsddev), x);
3550
3551                 /* try to fetch tunable, if any */
3552                 if (TUNABLE_INT_FETCH(path, &value) == 0 && value != 0)
3553                         priv->params.rx_priority_flow_control |= 1 << x;
3554         }
3555 #endif
3556
3557         /* register pauseframe SYSCTLs */
3558         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3559             OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
3560             &priv->params.tx_pauseframe_control, 0,
3561             "Set to enable TX pause frames. Clear to disable.");
3562
3563         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3564             OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
3565             &priv->params.rx_pauseframe_control, 0,
3566             "Set to enable RX pause frames. Clear to disable.");
3567
3568         /* register priority_flow control, PFC, SYSCTLs */
3569         for (x = 0; x != 8; x++) {
3570                 snprintf(path, sizeof(path), "tx_priority_flow_control_%u", x);
3571
3572                 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3573                     OID_AUTO, path, CTLTYPE_UINT | CTLFLAG_RWTUN |
3574                     CTLFLAG_MPSAFE, priv, x, &mlx5e_sysctl_tx_priority_flow_control, "IU",
3575                     "Set to enable TX ports flow control frames for given priority. Clear to disable.");
3576
3577                 snprintf(path, sizeof(path), "rx_priority_flow_control_%u", x);
3578
3579                 SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3580                     OID_AUTO, path, CTLTYPE_UINT | CTLFLAG_RWTUN |
3581                     CTLFLAG_MPSAFE, priv, x, &mlx5e_sysctl_rx_priority_flow_control, "IU",
3582                     "Set to enable RX ports flow control frames for given priority. Clear to disable.");
3583         }
3584
3585         PRIV_LOCK(priv);
3586
3587         /* range check */
3588         priv->params.tx_pauseframe_control =
3589             priv->params.tx_pauseframe_control ? 1 : 0;
3590         priv->params.rx_pauseframe_control =
3591             priv->params.rx_pauseframe_control ? 1 : 0;
3592
3593         /* update firmware */
3594         error = mlx5e_set_port_pause_and_pfc(priv);
3595         if (error == -EINVAL) {
3596                 if_printf(priv->ifp,
3597                     "Global pauseframes must be disabled before enabling PFC.\n");
3598                 priv->params.rx_priority_flow_control = 0;
3599                 priv->params.tx_priority_flow_control = 0;
3600
3601                 /* update firmware */
3602                 (void) mlx5e_set_port_pause_and_pfc(priv);
3603         }
3604         PRIV_UNLOCK(priv);
3605 }
3606
3607 static int
3608 mlx5e_ul_snd_tag_alloc(struct ifnet *ifp,
3609     union if_snd_tag_alloc_params *params,
3610     struct m_snd_tag **ppmt)
3611 {
3612         struct mlx5e_priv *priv;
3613         struct mlx5e_channel *pch;
3614
3615         priv = ifp->if_softc;
3616
3617         if (unlikely(priv->gone || params->hdr.flowtype == M_HASHTYPE_NONE)) {
3618                 return (EOPNOTSUPP);
3619         } else {
3620                 /* keep this code synced with mlx5e_select_queue() */
3621                 u32 ch = priv->params.num_channels;
3622 #ifdef RSS
3623                 u32 temp;
3624
3625                 if (rss_hash2bucket(params->hdr.flowid,
3626                     params->hdr.flowtype, &temp) == 0)
3627                         ch = temp % ch;
3628                 else
3629 #endif
3630                         ch = (params->hdr.flowid % 128) % ch;
3631
3632                 /*
3633                  * NOTE: The channels array is only freed at detach
3634                  * and it safe to return a pointer to the send tag
3635                  * inside the channels structure as long as we
3636                  * reference the priv.
3637                  */
3638                 pch = priv->channel + ch;
3639
3640                 /* check if send queue is not running */
3641                 if (unlikely(pch->sq[0].running == 0))
3642                         return (ENXIO);
3643                 mlx5e_ref_channel(priv);
3644                 *ppmt = &pch->tag.m_snd_tag;
3645                 return (0);
3646         }
3647 }
3648
3649 static int
3650 mlx5e_ul_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
3651 {
3652         struct mlx5e_channel *pch =
3653             container_of(pmt, struct mlx5e_channel, tag.m_snd_tag);
3654
3655         params->unlimited.max_rate = -1ULL;
3656         params->unlimited.queue_level = mlx5e_sq_queue_level(&pch->sq[0]);
3657         return (0);
3658 }
3659
3660 static void
3661 mlx5e_ul_snd_tag_free(struct m_snd_tag *pmt)
3662 {
3663         struct mlx5e_channel *pch =
3664             container_of(pmt, struct mlx5e_channel, tag.m_snd_tag);
3665
3666         mlx5e_unref_channel(pch->priv);
3667 }
3668
3669 static int
3670 mlx5e_snd_tag_alloc(struct ifnet *ifp,
3671     union if_snd_tag_alloc_params *params,
3672     struct m_snd_tag **ppmt)
3673 {
3674
3675         switch (params->hdr.type) {
3676 #ifdef RATELIMIT
3677         case IF_SND_TAG_TYPE_RATE_LIMIT:
3678                 return (mlx5e_rl_snd_tag_alloc(ifp, params, ppmt));
3679 #endif
3680         case IF_SND_TAG_TYPE_UNLIMITED:
3681                 return (mlx5e_ul_snd_tag_alloc(ifp, params, ppmt));
3682         default:
3683                 return (EOPNOTSUPP);
3684         }
3685 }
3686
3687 static int
3688 mlx5e_snd_tag_modify(struct m_snd_tag *pmt, union if_snd_tag_modify_params *params)
3689 {
3690         struct mlx5e_snd_tag *tag =
3691             container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
3692
3693         switch (tag->type) {
3694 #ifdef RATELIMIT
3695         case IF_SND_TAG_TYPE_RATE_LIMIT:
3696                 return (mlx5e_rl_snd_tag_modify(pmt, params));
3697 #endif
3698         case IF_SND_TAG_TYPE_UNLIMITED:
3699         default:
3700                 return (EOPNOTSUPP);
3701         }
3702 }
3703
3704 static int
3705 mlx5e_snd_tag_query(struct m_snd_tag *pmt, union if_snd_tag_query_params *params)
3706 {
3707         struct mlx5e_snd_tag *tag =
3708             container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
3709
3710         switch (tag->type) {
3711 #ifdef RATELIMIT
3712         case IF_SND_TAG_TYPE_RATE_LIMIT:
3713                 return (mlx5e_rl_snd_tag_query(pmt, params));
3714 #endif
3715         case IF_SND_TAG_TYPE_UNLIMITED:
3716                 return (mlx5e_ul_snd_tag_query(pmt, params));
3717         default:
3718                 return (EOPNOTSUPP);
3719         }
3720 }
3721
3722 static void
3723 mlx5e_snd_tag_free(struct m_snd_tag *pmt)
3724 {
3725         struct mlx5e_snd_tag *tag =
3726             container_of(pmt, struct mlx5e_snd_tag, m_snd_tag);
3727
3728         switch (tag->type) {
3729 #ifdef RATELIMIT
3730         case IF_SND_TAG_TYPE_RATE_LIMIT:
3731                 mlx5e_rl_snd_tag_free(pmt);
3732                 break;
3733 #endif
3734         case IF_SND_TAG_TYPE_UNLIMITED:
3735                 mlx5e_ul_snd_tag_free(pmt);
3736                 break;
3737         default:
3738                 break;
3739         }
3740 }
3741
3742 static void *
3743 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
3744 {
3745         struct ifnet *ifp;
3746         struct mlx5e_priv *priv;
3747         u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
3748         struct sysctl_oid_list *child;
3749         int ncv = mdev->priv.eq_table.num_comp_vectors;
3750         char unit[16];
3751         struct pfil_head_args pa;
3752         int err;
3753         int i;
3754         u32 eth_proto_cap;
3755
3756         if (mlx5e_check_required_hca_cap(mdev)) {
3757                 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
3758                 return (NULL);
3759         }
3760         /*
3761          * Try to allocate the priv and make room for worst-case
3762          * number of channel structures:
3763          */
3764         priv = malloc(sizeof(*priv) +
3765             (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors),
3766             M_MLX5EN, M_WAITOK | M_ZERO);
3767         mlx5e_priv_mtx_init(priv);
3768
3769         ifp = priv->ifp = if_alloc_dev(IFT_ETHER, mdev->pdev->dev.bsddev);
3770         if (ifp == NULL) {
3771                 mlx5_core_err(mdev, "if_alloc() failed\n");
3772                 goto err_free_priv;
3773         }
3774         ifp->if_softc = priv;
3775         if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev));
3776         ifp->if_mtu = ETHERMTU;
3777         ifp->if_init = mlx5e_open;
3778         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
3779         ifp->if_ioctl = mlx5e_ioctl;
3780         ifp->if_transmit = mlx5e_xmit;
3781         ifp->if_qflush = if_qflush;
3782 #if (__FreeBSD_version >= 1100000)
3783         ifp->if_get_counter = mlx5e_get_counter;
3784 #endif
3785         ifp->if_snd.ifq_maxlen = ifqmaxlen;
3786         /*
3787          * Set driver features
3788          */
3789         ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
3790         ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
3791         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
3792         ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
3793         ifp->if_capabilities |= IFCAP_LRO;
3794         ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
3795         ifp->if_capabilities |= IFCAP_HWSTATS | IFCAP_HWRXTSTMP;
3796         ifp->if_capabilities |= IFCAP_TXRTLMT;
3797         ifp->if_snd_tag_alloc = mlx5e_snd_tag_alloc;
3798         ifp->if_snd_tag_free = mlx5e_snd_tag_free;
3799         ifp->if_snd_tag_modify = mlx5e_snd_tag_modify;
3800         ifp->if_snd_tag_query = mlx5e_snd_tag_query;
3801
3802         /* set TSO limits so that we don't have to drop TX packets */
3803         ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
3804         ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
3805         ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
3806
3807         ifp->if_capenable = ifp->if_capabilities;
3808         ifp->if_hwassist = 0;
3809         if (ifp->if_capenable & IFCAP_TSO)
3810                 ifp->if_hwassist |= CSUM_TSO;
3811         if (ifp->if_capenable & IFCAP_TXCSUM)
3812                 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
3813         if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
3814                 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3815
3816         /* ifnet sysctl tree */
3817         sysctl_ctx_init(&priv->sysctl_ctx);
3818         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
3819             OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
3820         if (priv->sysctl_ifnet == NULL) {
3821                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3822                 goto err_free_sysctl;
3823         }
3824         snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
3825         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3826             OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
3827         if (priv->sysctl_ifnet == NULL) {
3828                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3829                 goto err_free_sysctl;
3830         }
3831
3832         /* HW sysctl tree */
3833         child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
3834         priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
3835             OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
3836         if (priv->sysctl_hw == NULL) {
3837                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3838                 goto err_free_sysctl;
3839         }
3840
3841         err = mlx5e_build_ifp_priv(mdev, priv, ncv);
3842         if (err) {
3843                 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err);
3844                 goto err_free_sysctl;
3845         }
3846
3847         snprintf(unit, sizeof(unit), "mce%u_wq",
3848             device_get_unit(mdev->pdev->dev.bsddev));
3849         priv->wq = alloc_workqueue(unit, 0, 1);
3850         if (priv->wq == NULL) {
3851                 if_printf(ifp, "%s: alloc_workqueue failed\n", __func__);
3852                 goto err_free_sysctl;
3853         }
3854
3855         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
3856         if (err) {
3857                 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n",
3858                     __func__, err);
3859                 goto err_free_wq;
3860         }
3861         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
3862         if (err) {
3863                 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n",
3864                     __func__, err);
3865                 goto err_unmap_free_uar;
3866         }
3867         err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
3868         if (err) {
3869                 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n",
3870                     __func__, err);
3871                 goto err_dealloc_pd;
3872         }
3873         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
3874         if (err) {
3875                 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n",
3876                     __func__, err);
3877                 goto err_dealloc_transport_domain;
3878         }
3879         mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
3880
3881         /* check if we should generate a random MAC address */
3882         if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
3883             is_zero_ether_addr(dev_addr)) {
3884                 random_ether_addr(dev_addr);
3885                 if_printf(ifp, "Assigned random MAC address\n");
3886         }
3887 #ifdef RATELIMIT
3888         err = mlx5e_rl_init(priv);
3889         if (err) {
3890                 if_printf(ifp, "%s: mlx5e_rl_init failed, %d\n",
3891                     __func__, err);
3892                 goto err_create_mkey;
3893         }
3894 #endif
3895
3896         /* set default MTU */
3897         mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
3898
3899         /* Set default media status */
3900         priv->media_status_last = IFM_AVALID;
3901         priv->media_active_last = IFM_ETHER | IFM_AUTO |
3902             IFM_ETH_RXPAUSE | IFM_FDX;
3903
3904         /* setup default pauseframes configuration */
3905         mlx5e_setup_pauseframes(priv);
3906
3907         err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
3908         if (err) {
3909                 eth_proto_cap = 0;
3910                 if_printf(ifp, "%s: Query port media capability failed, %d\n",
3911                     __func__, err);
3912         }
3913
3914         /* Setup supported medias */
3915         ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
3916             mlx5e_media_change, mlx5e_media_status);
3917
3918         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
3919                 if (mlx5e_mode_table[i].baudrate == 0)
3920                         continue;
3921                 if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
3922                         ifmedia_add(&priv->media,
3923                             mlx5e_mode_table[i].subtype |
3924                             IFM_ETHER, 0, NULL);
3925                         ifmedia_add(&priv->media,
3926                             mlx5e_mode_table[i].subtype |
3927                             IFM_ETHER | IFM_FDX |
3928                             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3929                 }
3930         }
3931
3932         /* Additional supported medias */
3933         ifmedia_add(&priv->media, IFM_10G_LR | IFM_ETHER, 0, NULL);
3934         ifmedia_add(&priv->media, IFM_10G_LR |
3935             IFM_ETHER | IFM_FDX |
3936             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3937
3938         ifmedia_add(&priv->media, IFM_40G_ER4 | IFM_ETHER, 0, NULL);
3939         ifmedia_add(&priv->media, IFM_40G_ER4 |
3940             IFM_ETHER | IFM_FDX |
3941             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3942
3943         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
3944         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3945             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3946
3947         /* Set autoselect by default */
3948         ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3949             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
3950         ether_ifattach(ifp, dev_addr);
3951
3952         /* Register for VLAN events */
3953         priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
3954             mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
3955         priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
3956             mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
3957
3958         /* Link is down by default */
3959         if_link_state_change(ifp, LINK_STATE_DOWN);
3960
3961         mlx5e_enable_async_events(priv);
3962
3963         mlx5e_add_hw_stats(priv);
3964
3965         mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3966             "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
3967             priv->stats.vport.arg);
3968
3969         mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3970             "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
3971             priv->stats.pport.arg);
3972
3973         mlx5e_create_ethtool(priv);
3974
3975         mtx_lock(&priv->async_events_mtx);
3976         mlx5e_update_stats(priv);
3977         mtx_unlock(&priv->async_events_mtx);
3978
3979         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3980             OID_AUTO, "rx_clbr_done", CTLFLAG_RD,
3981             &priv->clbr_done, 0,
3982             "RX timestamps calibration state");
3983         callout_init(&priv->tstmp_clbr, CALLOUT_DIRECT);
3984         mlx5e_reset_calibration_callout(priv);
3985
3986         pa.pa_version = PFIL_VERSION;
3987         pa.pa_flags = PFIL_IN;
3988         pa.pa_type = PFIL_TYPE_ETHERNET;
3989         pa.pa_headname = ifp->if_xname;
3990         priv->pfil = pfil_head_register(&pa);
3991
3992         return (priv);
3993
3994 #ifdef RATELIMIT
3995 err_create_mkey:
3996         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
3997 #endif
3998 err_dealloc_transport_domain:
3999         mlx5_dealloc_transport_domain(mdev, priv->tdn);
4000
4001 err_dealloc_pd:
4002         mlx5_core_dealloc_pd(mdev, priv->pdn);
4003
4004 err_unmap_free_uar:
4005         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
4006
4007 err_free_wq:
4008         destroy_workqueue(priv->wq);
4009
4010 err_free_sysctl:
4011         sysctl_ctx_free(&priv->sysctl_ctx);
4012         if (priv->sysctl_debug)
4013                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4014         if_free(ifp);
4015
4016 err_free_priv:
4017         mlx5e_priv_mtx_destroy(priv);
4018         free(priv, M_MLX5EN);
4019         return (NULL);
4020 }
4021
4022 static void
4023 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
4024 {
4025         struct mlx5e_priv *priv = vpriv;
4026         struct ifnet *ifp = priv->ifp;
4027
4028         /* don't allow more IOCTLs */
4029         priv->gone = 1;
4030
4031         /* XXX wait a bit to allow IOCTL handlers to complete */
4032         pause("W", hz);
4033
4034 #ifdef RATELIMIT
4035         /*
4036          * The kernel can have reference(s) via the m_snd_tag's into
4037          * the ratelimit channels, and these must go away before
4038          * detaching:
4039          */
4040         while (READ_ONCE(priv->rl.stats.tx_active_connections) != 0) {
4041                 if_printf(priv->ifp, "Waiting for all ratelimit connections "
4042                     "to terminate\n");
4043                 pause("W", hz);
4044         }
4045 #endif
4046         /* stop watchdog timer */
4047         callout_drain(&priv->watchdog);
4048
4049         callout_drain(&priv->tstmp_clbr);
4050
4051         if (priv->vlan_attach != NULL)
4052                 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
4053         if (priv->vlan_detach != NULL)
4054                 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
4055
4056         /* make sure device gets closed */
4057         PRIV_LOCK(priv);
4058         mlx5e_close_locked(ifp);
4059         PRIV_UNLOCK(priv);
4060
4061         /* wait for all unlimited send tags to go away */
4062         while (priv->channel_refs != 0) {
4063                 if_printf(priv->ifp, "Waiting for all unlimited connections "
4064                     "to terminate\n");
4065                 pause("W", hz);
4066         }
4067
4068         /* deregister pfil */
4069         if (priv->pfil != NULL) {
4070                 pfil_head_unregister(priv->pfil);
4071                 priv->pfil = NULL;
4072         }
4073
4074         /* unregister device */
4075         ifmedia_removeall(&priv->media);
4076         ether_ifdetach(ifp);
4077         if_free(ifp);
4078
4079 #ifdef RATELIMIT
4080         mlx5e_rl_cleanup(priv);
4081 #endif
4082         /* destroy all remaining sysctl nodes */
4083         sysctl_ctx_free(&priv->stats.vport.ctx);
4084         sysctl_ctx_free(&priv->stats.pport.ctx);
4085         sysctl_ctx_free(&priv->sysctl_ctx);
4086         if (priv->sysctl_debug)
4087                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
4088
4089         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
4090         mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
4091         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
4092         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
4093         mlx5e_disable_async_events(priv);
4094         destroy_workqueue(priv->wq);
4095         mlx5e_priv_mtx_destroy(priv);
4096         free(priv, M_MLX5EN);
4097 }
4098
4099 static void *
4100 mlx5e_get_ifp(void *vpriv)
4101 {
4102         struct mlx5e_priv *priv = vpriv;
4103
4104         return (priv->ifp);
4105 }
4106
4107 static struct mlx5_interface mlx5e_interface = {
4108         .add = mlx5e_create_ifp,
4109         .remove = mlx5e_destroy_ifp,
4110         .event = mlx5e_async_event,
4111         .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4112         .get_dev = mlx5e_get_ifp,
4113 };
4114
4115 void
4116 mlx5e_init(void)
4117 {
4118         mlx5_register_interface(&mlx5e_interface);
4119 }
4120
4121 void
4122 mlx5e_cleanup(void)
4123 {
4124         mlx5_unregister_interface(&mlx5e_interface);
4125 }
4126
4127 static void
4128 mlx5e_show_version(void __unused *arg)
4129 {
4130
4131         printf("%s", mlx5e_version);
4132 }
4133 SYSINIT(mlx5e_show_version, SI_SUB_DRIVERS, SI_ORDER_ANY, mlx5e_show_version, NULL);
4134
4135 module_init_order(mlx5e_init, SI_ORDER_THIRD);
4136 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
4137
4138 #if (__FreeBSD_version >= 1100000)
4139 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
4140 #endif
4141 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
4142 MODULE_VERSION(mlx5en, 1);