sys/dev/mlx5/mlx5_en/mlx5_en_main.c

   1 /*-
   2  * Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved.
   3  *
   4  * Redistribution and use in source and binary forms, with or without
   5  * modification, are permitted provided that the following conditions
   6  * are met:
   7  * 1. Redistributions of source code must retain the above copyright
   8  *    notice, this list of conditions and the following disclaimer.
   9  * 2. Redistributions in binary form must reproduce the above copyright
  10  *    notice, this list of conditions and the following disclaimer in the
  11  *    documentation and/or other materials provided with the distribution.
  12  *
  13  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND
  14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  16  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  23  * SUCH DAMAGE.
  24  *
  25  * $FreeBSD$
  26  */
  27
  28 #include "en.h"
  29
  30 #include <sys/sockio.h>
  31 #include <machine/atomic.h>
  32
  33 #ifndef ETH_DRIVER_VERSION
  34 #define ETH_DRIVER_VERSION      "3.5.0"
  35 #endif
  36 #define DRIVER_RELDATE  "November 2018"
  37
  38 static const char mlx5e_version[] = "mlx5en: Mellanox Ethernet driver "
  39         ETH_DRIVER_VERSION " (" DRIVER_RELDATE ")\n";
  40
  41 static int mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs);
  42
  43 struct mlx5e_channel_param {
  44         struct mlx5e_rq_param rq;
  45         struct mlx5e_sq_param sq;
  46         struct mlx5e_cq_param rx_cq;
  47         struct mlx5e_cq_param tx_cq;
  48 };
  49
  50 static const struct {
  51         u32     subtype;
  52         u64     baudrate;
  53 }       mlx5e_mode_table[MLX5E_LINK_MODES_NUMBER] = {
  54
  55         [MLX5E_1000BASE_CX_SGMII] = {
  56                 .subtype = IFM_1000_CX_SGMII,
  57                 .baudrate = IF_Mbps(1000ULL),
  58         },
  59         [MLX5E_1000BASE_KX] = {
  60                 .subtype = IFM_1000_KX,
  61                 .baudrate = IF_Mbps(1000ULL),
  62         },
  63         [MLX5E_10GBASE_CX4] = {
  64                 .subtype = IFM_10G_CX4,
  65                 .baudrate = IF_Gbps(10ULL),
  66         },
  67         [MLX5E_10GBASE_KX4] = {
  68                 .subtype = IFM_10G_KX4,
  69                 .baudrate = IF_Gbps(10ULL),
  70         },
  71         [MLX5E_10GBASE_KR] = {
  72                 .subtype = IFM_10G_KR,
  73                 .baudrate = IF_Gbps(10ULL),
  74         },
  75         [MLX5E_20GBASE_KR2] = {
  76                 .subtype = IFM_20G_KR2,
  77                 .baudrate = IF_Gbps(20ULL),
  78         },
  79         [MLX5E_40GBASE_CR4] = {
  80                 .subtype = IFM_40G_CR4,
  81                 .baudrate = IF_Gbps(40ULL),
  82         },
  83         [MLX5E_40GBASE_KR4] = {
  84                 .subtype = IFM_40G_KR4,
  85                 .baudrate = IF_Gbps(40ULL),
  86         },
  87         [MLX5E_56GBASE_R4] = {
  88                 .subtype = IFM_56G_R4,
  89                 .baudrate = IF_Gbps(56ULL),
  90         },
  91         [MLX5E_10GBASE_CR] = {
  92                 .subtype = IFM_10G_CR1,
  93                 .baudrate = IF_Gbps(10ULL),
  94         },
  95         [MLX5E_10GBASE_SR] = {
  96                 .subtype = IFM_10G_SR,
  97                 .baudrate = IF_Gbps(10ULL),
  98         },
  99         [MLX5E_10GBASE_ER] = {
 100                 .subtype = IFM_10G_ER,
 101                 .baudrate = IF_Gbps(10ULL),
 102         },
 103         [MLX5E_40GBASE_SR4] = {
 104                 .subtype = IFM_40G_SR4,
 105                 .baudrate = IF_Gbps(40ULL),
 106         },
 107         [MLX5E_40GBASE_LR4] = {
 108                 .subtype = IFM_40G_LR4,
 109                 .baudrate = IF_Gbps(40ULL),
 110         },
 111         [MLX5E_100GBASE_CR4] = {
 112                 .subtype = IFM_100G_CR4,
 113                 .baudrate = IF_Gbps(100ULL),
 114         },
 115         [MLX5E_100GBASE_SR4] = {
 116                 .subtype = IFM_100G_SR4,
 117                 .baudrate = IF_Gbps(100ULL),
 118         },
 119         [MLX5E_100GBASE_KR4] = {
 120                 .subtype = IFM_100G_KR4,
 121                 .baudrate = IF_Gbps(100ULL),
 122         },
 123         [MLX5E_100GBASE_LR4] = {
 124                 .subtype = IFM_100G_LR4,
 125                 .baudrate = IF_Gbps(100ULL),
 126         },
 127         [MLX5E_100BASE_TX] = {
 128                 .subtype = IFM_100_TX,
 129                 .baudrate = IF_Mbps(100ULL),
 130         },
 131         [MLX5E_1000BASE_T] = {
 132                 .subtype = IFM_1000_T,
 133                 .baudrate = IF_Mbps(1000ULL),
 134         },
 135         [MLX5E_10GBASE_T] = {
 136                 .subtype = IFM_10G_T,
 137                 .baudrate = IF_Gbps(10ULL),
 138         },
 139         [MLX5E_25GBASE_CR] = {
 140                 .subtype = IFM_25G_CR,
 141                 .baudrate = IF_Gbps(25ULL),
 142         },
 143         [MLX5E_25GBASE_KR] = {
 144                 .subtype = IFM_25G_KR,
 145                 .baudrate = IF_Gbps(25ULL),
 146         },
 147         [MLX5E_25GBASE_SR] = {
 148                 .subtype = IFM_25G_SR,
 149                 .baudrate = IF_Gbps(25ULL),
 150         },
 151         [MLX5E_50GBASE_CR2] = {
 152                 .subtype = IFM_50G_CR2,
 153                 .baudrate = IF_Gbps(50ULL),
 154         },
 155         [MLX5E_50GBASE_KR2] = {
 156                 .subtype = IFM_50G_KR2,
 157                 .baudrate = IF_Gbps(50ULL),
 158         },
 159 };
 160
 161 MALLOC_DEFINE(M_MLX5EN, "MLX5EN", "MLX5 Ethernet");
 162
 163 static void
 164 mlx5e_update_carrier(struct mlx5e_priv *priv)
 165 {
 166         struct mlx5_core_dev *mdev = priv->mdev;
 167         u32 out[MLX5_ST_SZ_DW(ptys_reg)];
 168         u32 eth_proto_oper;
 169         int error;
 170         u8 port_state;
 171         u8 is_er_type;
 172         u8 i;
 173
 174         port_state = mlx5_query_vport_state(mdev,
 175             MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT, 0);
 176
 177         if (port_state == VPORT_STATE_UP) {
 178                 priv->media_status_last |= IFM_ACTIVE;
 179         } else {
 180                 priv->media_status_last &= ~IFM_ACTIVE;
 181                 priv->media_active_last = IFM_ETHER;
 182                 if_link_state_change(priv->ifp, LINK_STATE_DOWN);
 183                 return;
 184         }
 185
 186         error = mlx5_query_port_ptys(mdev, out, sizeof(out), MLX5_PTYS_EN, 1);
 187         if (error) {
 188                 priv->media_active_last = IFM_ETHER;
 189                 priv->ifp->if_baudrate = 1;
 190                 if_printf(priv->ifp, "%s: query port ptys failed: 0x%x\n",
 191                     __func__, error);
 192                 return;
 193         }
 194         eth_proto_oper = MLX5_GET(ptys_reg, out, eth_proto_oper);
 195
 196         for (i = 0; i != MLX5E_LINK_MODES_NUMBER; i++) {
 197                 if (mlx5e_mode_table[i].baudrate == 0)
 198                         continue;
 199                 if (MLX5E_PROT_MASK(i) & eth_proto_oper) {
 200                         u32 subtype = mlx5e_mode_table[i].subtype;
 201
 202                         priv->ifp->if_baudrate =
 203                             mlx5e_mode_table[i].baudrate;
 204
 205                         switch (subtype) {
 206                         case IFM_10G_ER:
 207                                 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
 208                                 if (error != 0) {
 209                                         if_printf(priv->ifp, "%s: query port pddr failed: %d\n",
 210                                             __func__, error);
 211                                 }
 212                                 if (error != 0 || is_er_type == 0)
 213                                         subtype = IFM_10G_LR;
 214                                 break;
 215                         case IFM_40G_LR4:
 216                                 error = mlx5_query_pddr_range_info(mdev, 1, &is_er_type);
 217                                 if (error != 0) {
 218                                         if_printf(priv->ifp, "%s: query port pddr failed: %d\n",
 219                                             __func__, error);
 220                                 }
 221                                 if (error == 0 && is_er_type != 0)
 222                                         subtype = IFM_40G_ER4;
 223                                 break;
 224                         }
 225                         priv->media_active_last = subtype | IFM_ETHER | IFM_FDX;
 226                         break;
 227                 }
 228         }
 229         if_link_state_change(priv->ifp, LINK_STATE_UP);
 230 }
 231
 232 static void
 233 mlx5e_media_status(struct ifnet *dev, struct ifmediareq *ifmr)
 234 {
 235         struct mlx5e_priv *priv = dev->if_softc;
 236
 237         ifmr->ifm_status = priv->media_status_last;
 238         ifmr->ifm_active = priv->media_active_last |
 239             (priv->params.rx_pauseframe_control ? IFM_ETH_RXPAUSE : 0) |
 240             (priv->params.tx_pauseframe_control ? IFM_ETH_TXPAUSE : 0);
 241
 242 }
 243
 244 static u32
 245 mlx5e_find_link_mode(u32 subtype)
 246 {
 247         u32 i;
 248         u32 link_mode = 0;
 249
 250         switch (subtype) {
 251         case IFM_10G_LR:
 252                 subtype = IFM_10G_ER;
 253                 break;
 254         case IFM_40G_ER4:
 255                 subtype = IFM_40G_LR4;
 256                 break;
 257         }
 258
 259         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
 260                 if (mlx5e_mode_table[i].baudrate == 0)
 261                         continue;
 262                 if (mlx5e_mode_table[i].subtype == subtype)
 263                         link_mode |= MLX5E_PROT_MASK(i);
 264         }
 265
 266         return (link_mode);
 267 }
 268
 269 static int
 270 mlx5e_set_port_pause_and_pfc(struct mlx5e_priv *priv)
 271 {
 272         return (mlx5_set_port_pause_and_pfc(priv->mdev, 1,
 273             priv->params.rx_pauseframe_control,
 274             priv->params.tx_pauseframe_control,
 275             priv->params.rx_priority_flow_control,
 276             priv->params.tx_priority_flow_control));
 277 }
 278
 279 static int
 280 mlx5e_set_port_pfc(struct mlx5e_priv *priv)
 281 {
 282         int error;
 283
 284         if (priv->gone != 0) {
 285                 error = -ENXIO;
 286         } else if (priv->params.rx_pauseframe_control ||
 287             priv->params.tx_pauseframe_control) {
 288                 if_printf(priv->ifp,
 289                     "Global pauseframes must be disabled before enabling PFC.\n");
 290                 error = -EINVAL;
 291         } else {
 292                 error = mlx5e_set_port_pause_and_pfc(priv);
 293         }
 294         return (error);
 295 }
 296
 297 static int
 298 mlx5e_media_change(struct ifnet *dev)
 299 {
 300         struct mlx5e_priv *priv = dev->if_softc;
 301         struct mlx5_core_dev *mdev = priv->mdev;
 302         u32 eth_proto_cap;
 303         u32 link_mode;
 304         int was_opened;
 305         int locked;
 306         int error;
 307
 308         locked = PRIV_LOCKED(priv);
 309         if (!locked)
 310                 PRIV_LOCK(priv);
 311
 312         if (IFM_TYPE(priv->media.ifm_media) != IFM_ETHER) {
 313                 error = EINVAL;
 314                 goto done;
 315         }
 316         link_mode = mlx5e_find_link_mode(IFM_SUBTYPE(priv->media.ifm_media));
 317
 318         /* query supported capabilities */
 319         error = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
 320         if (error != 0) {
 321                 if_printf(dev, "Query port media capability failed\n");
 322                 goto done;
 323         }
 324         /* check for autoselect */
 325         if (IFM_SUBTYPE(priv->media.ifm_media) == IFM_AUTO) {
 326                 link_mode = eth_proto_cap;
 327                 if (link_mode == 0) {
 328                         if_printf(dev, "Port media capability is zero\n");
 329                         error = EINVAL;
 330                         goto done;
 331                 }
 332         } else {
 333                 link_mode = link_mode & eth_proto_cap;
 334                 if (link_mode == 0) {
 335                         if_printf(dev, "Not supported link mode requested\n");
 336                         error = EINVAL;
 337                         goto done;
 338                 }
 339         }
 340         if (priv->media.ifm_media & (IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE)) {
 341                 /* check if PFC is enabled */
 342                 if (priv->params.rx_priority_flow_control ||
 343                     priv->params.tx_priority_flow_control) {
 344                         if_printf(dev, "PFC must be disabled before enabling global pauseframes.\n");
 345                         error = EINVAL;
 346                         goto done;
 347                 }
 348         }
 349         /* update pauseframe control bits */
 350         priv->params.rx_pauseframe_control =
 351             (priv->media.ifm_media & IFM_ETH_RXPAUSE) ? 1 : 0;
 352         priv->params.tx_pauseframe_control =
 353             (priv->media.ifm_media & IFM_ETH_TXPAUSE) ? 1 : 0;
 354
 355         /* check if device is opened */
 356         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
 357
 358         /* reconfigure the hardware */
 359         mlx5_set_port_status(mdev, MLX5_PORT_DOWN);
 360         mlx5_set_port_proto(mdev, link_mode, MLX5_PTYS_EN);
 361         error = -mlx5e_set_port_pause_and_pfc(priv);
 362         if (was_opened)
 363                 mlx5_set_port_status(mdev, MLX5_PORT_UP);
 364
 365 done:
 366         if (!locked)
 367                 PRIV_UNLOCK(priv);
 368         return (error);
 369 }
 370
 371 static void
 372 mlx5e_update_carrier_work(struct work_struct *work)
 373 {
 374         struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
 375             update_carrier_work);
 376
 377         PRIV_LOCK(priv);
 378         if (test_bit(MLX5E_STATE_OPENED, &priv->state))
 379                 mlx5e_update_carrier(priv);
 380         PRIV_UNLOCK(priv);
 381 }
 382
 383 /*
 384  * This function reads the physical port counters from the firmware
 385  * using a pre-defined layout defined by various MLX5E_PPORT_XXX()
 386  * macros. The output is converted from big-endian 64-bit values into
 387  * host endian ones and stored in the "priv->stats.pport" structure.
 388  */
 389 static void
 390 mlx5e_update_pport_counters(struct mlx5e_priv *priv)
 391 {
 392         struct mlx5_core_dev *mdev = priv->mdev;
 393         struct mlx5e_pport_stats *s = &priv->stats.pport;
 394         struct mlx5e_port_stats_debug *s_debug = &priv->stats.port_stats_debug;
 395         u32 *in;
 396         u32 *out;
 397         const u64 *ptr;
 398         unsigned sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
 399         unsigned x;
 400         unsigned y;
 401         unsigned z;
 402
 403         /* allocate firmware request structures */
 404         in = mlx5_vzalloc(sz);
 405         out = mlx5_vzalloc(sz);
 406         if (in == NULL || out == NULL)
 407                 goto free_out;
 408
 409         /*
 410          * Get pointer to the 64-bit counter set which is located at a
 411          * fixed offset in the output firmware request structure:
 412          */
 413         ptr = (const uint64_t *)MLX5_ADDR_OF(ppcnt_reg, out, counter_set);
 414
 415         MLX5_SET(ppcnt_reg, in, local_port, 1);
 416
 417         /* read IEEE802_3 counter group using predefined counter layout */
 418         MLX5_SET(ppcnt_reg, in, grp, MLX5_IEEE_802_3_COUNTERS_GROUP);
 419         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 420         for (x = 0, y = MLX5E_PPORT_PER_PRIO_STATS_NUM;
 421              x != MLX5E_PPORT_IEEE802_3_STATS_NUM; x++, y++)
 422                 s->arg[y] = be64toh(ptr[x]);
 423
 424         /* read RFC2819 counter group using predefined counter layout */
 425         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2819_COUNTERS_GROUP);
 426         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 427         for (x = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM; x++, y++)
 428                 s->arg[y] = be64toh(ptr[x]);
 429         for (y = 0; x != MLX5E_PPORT_RFC2819_STATS_NUM +
 430             MLX5E_PPORT_RFC2819_STATS_DEBUG_NUM; x++, y++)
 431                 s_debug->arg[y] = be64toh(ptr[x]);
 432
 433         /* read RFC2863 counter group using predefined counter layout */
 434         MLX5_SET(ppcnt_reg, in, grp, MLX5_RFC_2863_COUNTERS_GROUP);
 435         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 436         for (x = 0; x != MLX5E_PPORT_RFC2863_STATS_DEBUG_NUM; x++, y++)
 437                 s_debug->arg[y] = be64toh(ptr[x]);
 438
 439         /* read physical layer stats counter group using predefined counter layout */
 440         MLX5_SET(ppcnt_reg, in, grp, MLX5_PHYSICAL_LAYER_COUNTERS_GROUP);
 441         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 442         for (x = 0; x != MLX5E_PPORT_PHYSICAL_LAYER_STATS_DEBUG_NUM; x++, y++)
 443                 s_debug->arg[y] = be64toh(ptr[x]);
 444
 445         /* read Extended Ethernet counter group using predefined counter layout */
 446         MLX5_SET(ppcnt_reg, in, grp, MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP);
 447         mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 448         for (x = 0; x != MLX5E_PPORT_ETHERNET_EXTENDED_STATS_DEBUG_NUM; x++, y++)
 449                 s_debug->arg[y] = be64toh(ptr[x]);
 450
 451         /* read per-priority counters */
 452         MLX5_SET(ppcnt_reg, in, grp, MLX5_PER_PRIORITY_COUNTERS_GROUP);
 453
 454         /* iterate all the priorities */
 455         for (y = z = 0; z != MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO; z++) {
 456                 MLX5_SET(ppcnt_reg, in, prio_tc, z);
 457                 mlx5_core_access_reg(mdev, in, sz, out, sz, MLX5_REG_PPCNT, 0, 0);
 458
 459                 /* read per priority stats counter group using predefined counter layout */
 460                 for (x = 0; x != (MLX5E_PPORT_PER_PRIO_STATS_NUM /
 461                     MLX5E_PPORT_PER_PRIO_STATS_NUM_PRIO); x++, y++)
 462                         s->arg[y] = be64toh(ptr[x]);
 463         }
 464
 465 free_out:
 466         /* free firmware request structures */
 467         kvfree(in);
 468         kvfree(out);
 469 }
 470
 471 /*
 472  * This function is called regularly to collect all statistics
 473  * counters from the firmware. The values can be viewed through the
 474  * sysctl interface. Execution is serialized using the priv's global
 475  * configuration lock.
 476  */
 477 static void
 478 mlx5e_update_stats_locked(struct mlx5e_priv *priv)
 479 {
 480         struct mlx5_core_dev *mdev = priv->mdev;
 481         struct mlx5e_vport_stats *s = &priv->stats.vport;
 482         struct mlx5e_sq_stats *sq_stats;
 483         struct buf_ring *sq_br;
 484 #if (__FreeBSD_version < 1100000)
 485         struct ifnet *ifp = priv->ifp;
 486 #endif
 487
 488         u32 in[MLX5_ST_SZ_DW(query_vport_counter_in)];
 489         u32 *out;
 490         int outlen = MLX5_ST_SZ_BYTES(query_vport_counter_out);
 491         u64 tso_packets = 0;
 492         u64 tso_bytes = 0;
 493         u64 tx_queue_dropped = 0;
 494         u64 tx_defragged = 0;
 495         u64 tx_offload_none = 0;
 496         u64 lro_packets = 0;
 497         u64 lro_bytes = 0;
 498         u64 sw_lro_queued = 0;
 499         u64 sw_lro_flushed = 0;
 500         u64 rx_csum_none = 0;
 501         u64 rx_wqe_err = 0;
 502         u64 rx_packets = 0;
 503         u64 rx_bytes = 0;
 504         u32 rx_out_of_buffer = 0;
 505         int i;
 506         int j;
 507
 508         out = mlx5_vzalloc(outlen);
 509         if (out == NULL)
 510                 goto free_out;
 511
 512         /* Collect firts the SW counters and then HW for consistency */
 513         for (i = 0; i < priv->params.num_channels; i++) {
 514                 struct mlx5e_channel *pch = priv->channel + i;
 515                 struct mlx5e_rq *rq = &pch->rq;
 516                 struct mlx5e_rq_stats *rq_stats = &pch->rq.stats;
 517
 518                 /* collect stats from LRO */
 519                 rq_stats->sw_lro_queued = rq->lro.lro_queued;
 520                 rq_stats->sw_lro_flushed = rq->lro.lro_flushed;
 521                 sw_lro_queued += rq_stats->sw_lro_queued;
 522                 sw_lro_flushed += rq_stats->sw_lro_flushed;
 523                 lro_packets += rq_stats->lro_packets;
 524                 lro_bytes += rq_stats->lro_bytes;
 525                 rx_csum_none += rq_stats->csum_none;
 526                 rx_wqe_err += rq_stats->wqe_err;
 527                 rx_packets += rq_stats->packets;
 528                 rx_bytes += rq_stats->bytes;
 529
 530                 for (j = 0; j < priv->num_tc; j++) {
 531                         sq_stats = &pch->sq[j].stats;
 532                         sq_br = pch->sq[j].br;
 533
 534                         tso_packets += sq_stats->tso_packets;
 535                         tso_bytes += sq_stats->tso_bytes;
 536                         tx_queue_dropped += sq_stats->dropped;
 537                         if (sq_br != NULL)
 538                                 tx_queue_dropped += sq_br->br_drops;
 539                         tx_defragged += sq_stats->defragged;
 540                         tx_offload_none += sq_stats->csum_offload_none;
 541                 }
 542         }
 543
 544         /* update counters */
 545         s->tso_packets = tso_packets;
 546         s->tso_bytes = tso_bytes;
 547         s->tx_queue_dropped = tx_queue_dropped;
 548         s->tx_defragged = tx_defragged;
 549         s->lro_packets = lro_packets;
 550         s->lro_bytes = lro_bytes;
 551         s->sw_lro_queued = sw_lro_queued;
 552         s->sw_lro_flushed = sw_lro_flushed;
 553         s->rx_csum_none = rx_csum_none;
 554         s->rx_wqe_err = rx_wqe_err;
 555         s->rx_packets = rx_packets;
 556         s->rx_bytes = rx_bytes;
 557
 558         /* HW counters */
 559         memset(in, 0, sizeof(in));
 560
 561         MLX5_SET(query_vport_counter_in, in, opcode,
 562             MLX5_CMD_OP_QUERY_VPORT_COUNTER);
 563         MLX5_SET(query_vport_counter_in, in, op_mod, 0);
 564         MLX5_SET(query_vport_counter_in, in, other_vport, 0);
 565
 566         memset(out, 0, outlen);
 567
 568         /* get number of out-of-buffer drops first */
 569         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0 &&
 570             mlx5_vport_query_out_of_rx_buffer(mdev, priv->counter_set_id,
 571             &rx_out_of_buffer) == 0) {
 572                 /* accumulate difference into a 64-bit counter */
 573                 s->rx_out_of_buffer += (u64)(u32)(rx_out_of_buffer -
 574                     s->rx_out_of_buffer_prev);
 575                 s->rx_out_of_buffer_prev = rx_out_of_buffer;
 576         }
 577
 578         /* get port statistics */
 579         if (mlx5_cmd_exec(mdev, in, sizeof(in), out, outlen) == 0) {
 580 #define MLX5_GET_CTR(out, x) \
 581         MLX5_GET64(query_vport_counter_out, out, x)
 582
 583                 s->rx_error_packets =
 584                     MLX5_GET_CTR(out, received_errors.packets);
 585                 s->rx_error_bytes =
 586                     MLX5_GET_CTR(out, received_errors.octets);
 587                 s->tx_error_packets =
 588                     MLX5_GET_CTR(out, transmit_errors.packets);
 589                 s->tx_error_bytes =
 590                     MLX5_GET_CTR(out, transmit_errors.octets);
 591
 592                 s->rx_unicast_packets =
 593                     MLX5_GET_CTR(out, received_eth_unicast.packets);
 594                 s->rx_unicast_bytes =
 595                     MLX5_GET_CTR(out, received_eth_unicast.octets);
 596                 s->tx_unicast_packets =
 597                     MLX5_GET_CTR(out, transmitted_eth_unicast.packets);
 598                 s->tx_unicast_bytes =
 599                     MLX5_GET_CTR(out, transmitted_eth_unicast.octets);
 600
 601                 s->rx_multicast_packets =
 602                     MLX5_GET_CTR(out, received_eth_multicast.packets);
 603                 s->rx_multicast_bytes =
 604                     MLX5_GET_CTR(out, received_eth_multicast.octets);
 605                 s->tx_multicast_packets =
 606                     MLX5_GET_CTR(out, transmitted_eth_multicast.packets);
 607                 s->tx_multicast_bytes =
 608                     MLX5_GET_CTR(out, transmitted_eth_multicast.octets);
 609
 610                 s->rx_broadcast_packets =
 611                     MLX5_GET_CTR(out, received_eth_broadcast.packets);
 612                 s->rx_broadcast_bytes =
 613                     MLX5_GET_CTR(out, received_eth_broadcast.octets);
 614                 s->tx_broadcast_packets =
 615                     MLX5_GET_CTR(out, transmitted_eth_broadcast.packets);
 616                 s->tx_broadcast_bytes =
 617                     MLX5_GET_CTR(out, transmitted_eth_broadcast.octets);
 618
 619                 s->tx_packets = s->tx_unicast_packets +
 620                     s->tx_multicast_packets + s->tx_broadcast_packets;
 621                 s->tx_bytes = s->tx_unicast_bytes + s->tx_multicast_bytes +
 622                     s->tx_broadcast_bytes;
 623
 624                 /* Update calculated offload counters */
 625                 s->tx_csum_offload = s->tx_packets - tx_offload_none;
 626                 s->rx_csum_good = s->rx_packets - s->rx_csum_none;
 627         }
 628
 629         /* Get physical port counters */
 630         mlx5e_update_pport_counters(priv);
 631
 632         s->tx_jumbo_packets =
 633             priv->stats.port_stats_debug.tx_stat_p1519to2047octets +
 634             priv->stats.port_stats_debug.tx_stat_p2048to4095octets +
 635             priv->stats.port_stats_debug.tx_stat_p4096to8191octets +
 636             priv->stats.port_stats_debug.tx_stat_p8192to10239octets;
 637
 638 #if (__FreeBSD_version < 1100000)
 639         /* no get_counters interface in fbsd 10 */
 640         ifp->if_ipackets = s->rx_packets;
 641         ifp->if_ierrors = priv->stats.pport.in_range_len_errors +
 642             priv->stats.pport.out_of_range_len +
 643             priv->stats.pport.too_long_errors +
 644             priv->stats.pport.check_seq_err +
 645             priv->stats.pport.alignment_err;
 646         ifp->if_iqdrops = s->rx_out_of_buffer;
 647         ifp->if_opackets = s->tx_packets;
 648         ifp->if_oerrors = priv->stats.port_stats_debug.out_discards;
 649         ifp->if_snd.ifq_drops = s->tx_queue_dropped;
 650         ifp->if_ibytes = s->rx_bytes;
 651         ifp->if_obytes = s->tx_bytes;
 652         ifp->if_collisions =
 653             priv->stats.pport.collisions;
 654 #endif
 655
 656 free_out:
 657         kvfree(out);
 658
 659         /* Update diagnostics, if any */
 660         if (priv->params_ethtool.diag_pci_enable ||
 661             priv->params_ethtool.diag_general_enable) {
 662                 int error = mlx5_core_get_diagnostics_full(mdev,
 663                     priv->params_ethtool.diag_pci_enable ? &priv->params_pci : NULL,
 664                     priv->params_ethtool.diag_general_enable ? &priv->params_general : NULL);
 665                 if (error != 0)
 666                         if_printf(priv->ifp, "Failed reading diagnostics: %d\n", error);
 667         }
 668 }
 669
 670 static void
 671 mlx5e_update_stats_work(struct work_struct *work)
 672 {
 673         struct mlx5e_priv *priv;
 674
 675         priv  = container_of(work, struct mlx5e_priv, update_stats_work);
 676         PRIV_LOCK(priv);
 677         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
 678                 mlx5e_update_stats_locked(priv);
 679         PRIV_UNLOCK(priv);
 680 }
 681
 682 static void
 683 mlx5e_update_stats(void *arg)
 684 {
 685         struct mlx5e_priv *priv = arg;
 686
 687         queue_work(priv->wq, &priv->update_stats_work);
 688
 689         callout_reset(&priv->watchdog, hz, &mlx5e_update_stats, priv);
 690 }
 691
 692 static void
 693 mlx5e_async_event_sub(struct mlx5e_priv *priv,
 694     enum mlx5_dev_event event)
 695 {
 696         switch (event) {
 697         case MLX5_DEV_EVENT_PORT_UP:
 698         case MLX5_DEV_EVENT_PORT_DOWN:
 699                 queue_work(priv->wq, &priv->update_carrier_work);
 700                 break;
 701
 702         default:
 703                 break;
 704         }
 705 }
 706
 707 static void
 708 mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
 709     enum mlx5_dev_event event, unsigned long param)
 710 {
 711         struct mlx5e_priv *priv = vpriv;
 712
 713         mtx_lock(&priv->async_events_mtx);
 714         if (test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state))
 715                 mlx5e_async_event_sub(priv, event);
 716         mtx_unlock(&priv->async_events_mtx);
 717 }
 718
 719 static void
 720 mlx5e_enable_async_events(struct mlx5e_priv *priv)
 721 {
 722         set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 723 }
 724
 725 static void
 726 mlx5e_disable_async_events(struct mlx5e_priv *priv)
 727 {
 728         mtx_lock(&priv->async_events_mtx);
 729         clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLE, &priv->state);
 730         mtx_unlock(&priv->async_events_mtx);
 731 }
 732
 733 static const char *mlx5e_rq_stats_desc[] = {
 734         MLX5E_RQ_STATS(MLX5E_STATS_DESC)
 735 };
 736
 737 static int
 738 mlx5e_create_rq(struct mlx5e_channel *c,
 739     struct mlx5e_rq_param *param,
 740     struct mlx5e_rq *rq)
 741 {
 742         struct mlx5e_priv *priv = c->priv;
 743         struct mlx5_core_dev *mdev = priv->mdev;
 744         char buffer[16];
 745         void *rqc = param->rqc;
 746         void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
 747         int wq_sz;
 748         int err;
 749         int i;
 750         u32 nsegs, wqe_sz;
 751
 752         err = mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
 753         if (err != 0)
 754                 goto done;
 755
 756         /* Create DMA descriptor TAG */
 757         if ((err = -bus_dma_tag_create(
 758             bus_get_dma_tag(mdev->pdev->dev.bsddev),
 759             1,                          /* any alignment */
 760             0,                          /* no boundary */
 761             BUS_SPACE_MAXADDR,          /* lowaddr */
 762             BUS_SPACE_MAXADDR,          /* highaddr */
 763             NULL, NULL,                 /* filter, filterarg */
 764             nsegs * MLX5E_MAX_RX_BYTES, /* maxsize */
 765             nsegs,                      /* nsegments */
 766             nsegs * MLX5E_MAX_RX_BYTES, /* maxsegsize */
 767             0,                          /* flags */
 768             NULL, NULL,                 /* lockfunc, lockfuncarg */
 769             &rq->dma_tag)))
 770                 goto done;
 771
 772         err = mlx5_wq_ll_create(mdev, &param->wq, rqc_wq, &rq->wq,
 773             &rq->wq_ctrl);
 774         if (err)
 775                 goto err_free_dma_tag;
 776
 777         rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
 778
 779         err = mlx5e_get_wqe_sz(priv, &rq->wqe_sz, &rq->nsegs);
 780         if (err != 0)
 781                 goto err_rq_wq_destroy;
 782
 783         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 784
 785         err = -tcp_lro_init_args(&rq->lro, c->ifp, TCP_LRO_ENTRIES, wq_sz);
 786         if (err)
 787                 goto err_rq_wq_destroy;
 788
 789         rq->mbuf = malloc(wq_sz * sizeof(rq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
 790         for (i = 0; i != wq_sz; i++) {
 791                 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
 792 #if (MLX5E_MAX_RX_SEGS == 1)
 793                 uint32_t byte_count = rq->wqe_sz - MLX5E_NET_IP_ALIGN;
 794 #else
 795                 int j;
 796 #endif
 797
 798                 err = -bus_dmamap_create(rq->dma_tag, 0, &rq->mbuf[i].dma_map);
 799                 if (err != 0) {
 800                         while (i--)
 801                                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 802                         goto err_rq_mbuf_free;
 803                 }
 804
 805                 /* set value for constant fields */
 806 #if (MLX5E_MAX_RX_SEGS == 1)
 807                 wqe->data[0].lkey = c->mkey_be;
 808                 wqe->data[0].byte_count = cpu_to_be32(byte_count | MLX5_HW_START_PADDING);
 809 #else
 810                 for (j = 0; j < rq->nsegs; j++)
 811                         wqe->data[j].lkey = c->mkey_be;
 812 #endif
 813         }
 814
 815         INIT_WORK(&rq->dim.work, mlx5e_dim_work);
 816         if (priv->params.rx_cq_moderation_mode < 2) {
 817                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
 818         } else {
 819                 void *cqc = container_of(param,
 820                     struct mlx5e_channel_param, rq)->rx_cq.cqc;
 821
 822                 switch (MLX5_GET(cqc, cqc, cq_period_mode)) {
 823                 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
 824                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
 825                         break;
 826                 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
 827                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
 828                         break;
 829                 default:
 830                         rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
 831                         break;
 832                 }
 833         }
 834
 835         rq->ifp = c->ifp;
 836         rq->channel = c;
 837         rq->ix = c->ix;
 838
 839         snprintf(buffer, sizeof(buffer), "rxstat%d", c->ix);
 840         mlx5e_create_stats(&rq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
 841             buffer, mlx5e_rq_stats_desc, MLX5E_RQ_STATS_NUM,
 842             rq->stats.arg);
 843         return (0);
 844
 845 err_rq_mbuf_free:
 846         free(rq->mbuf, M_MLX5EN);
 847         tcp_lro_free(&rq->lro);
 848 err_rq_wq_destroy:
 849         mlx5_wq_destroy(&rq->wq_ctrl);
 850 err_free_dma_tag:
 851         bus_dma_tag_destroy(rq->dma_tag);
 852 done:
 853         return (err);
 854 }
 855
 856 static void
 857 mlx5e_destroy_rq(struct mlx5e_rq *rq)
 858 {
 859         int wq_sz;
 860         int i;
 861
 862         /* destroy all sysctl nodes */
 863         sysctl_ctx_free(&rq->stats.ctx);
 864
 865         /* free leftover LRO packets, if any */
 866         tcp_lro_free(&rq->lro);
 867
 868         wq_sz = mlx5_wq_ll_get_size(&rq->wq);
 869         for (i = 0; i != wq_sz; i++) {
 870                 if (rq->mbuf[i].mbuf != NULL) {
 871                         bus_dmamap_unload(rq->dma_tag, rq->mbuf[i].dma_map);
 872                         m_freem(rq->mbuf[i].mbuf);
 873                 }
 874                 bus_dmamap_destroy(rq->dma_tag, rq->mbuf[i].dma_map);
 875         }
 876         free(rq->mbuf, M_MLX5EN);
 877         mlx5_wq_destroy(&rq->wq_ctrl);
 878 }
 879
 880 static int
 881 mlx5e_enable_rq(struct mlx5e_rq *rq, struct mlx5e_rq_param *param)
 882 {
 883         struct mlx5e_channel *c = rq->channel;
 884         struct mlx5e_priv *priv = c->priv;
 885         struct mlx5_core_dev *mdev = priv->mdev;
 886
 887         void *in;
 888         void *rqc;
 889         void *wq;
 890         int inlen;
 891         int err;
 892
 893         inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
 894             sizeof(u64) * rq->wq_ctrl.buf.npages;
 895         in = mlx5_vzalloc(inlen);
 896         if (in == NULL)
 897                 return (-ENOMEM);
 898
 899         rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
 900         wq = MLX5_ADDR_OF(rqc, rqc, wq);
 901
 902         memcpy(rqc, param->rqc, sizeof(param->rqc));
 903
 904         MLX5_SET(rqc, rqc, cqn, c->rq.cq.mcq.cqn);
 905         MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
 906         MLX5_SET(rqc, rqc, flush_in_error_en, 1);
 907         if (priv->counter_set_id >= 0)
 908                 MLX5_SET(rqc, rqc, counter_set_id, priv->counter_set_id);
 909         MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
 910             PAGE_SHIFT);
 911         MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
 912
 913         mlx5_fill_page_array(&rq->wq_ctrl.buf,
 914             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
 915
 916         err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
 917
 918         kvfree(in);
 919
 920         return (err);
 921 }
 922
 923 static int
 924 mlx5e_modify_rq(struct mlx5e_rq *rq, int curr_state, int next_state)
 925 {
 926         struct mlx5e_channel *c = rq->channel;
 927         struct mlx5e_priv *priv = c->priv;
 928         struct mlx5_core_dev *mdev = priv->mdev;
 929
 930         void *in;
 931         void *rqc;
 932         int inlen;
 933         int err;
 934
 935         inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
 936         in = mlx5_vzalloc(inlen);
 937         if (in == NULL)
 938                 return (-ENOMEM);
 939
 940         rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
 941
 942         MLX5_SET(modify_rq_in, in, rqn, rq->rqn);
 943         MLX5_SET(modify_rq_in, in, rq_state, curr_state);
 944         MLX5_SET(rqc, rqc, state, next_state);
 945
 946         err = mlx5_core_modify_rq(mdev, in, inlen);
 947
 948         kvfree(in);
 949
 950         return (err);
 951 }
 952
 953 static void
 954 mlx5e_disable_rq(struct mlx5e_rq *rq)
 955 {
 956         struct mlx5e_channel *c = rq->channel;
 957         struct mlx5e_priv *priv = c->priv;
 958         struct mlx5_core_dev *mdev = priv->mdev;
 959
 960         mlx5_core_destroy_rq(mdev, rq->rqn);
 961 }
 962
 963 static int
 964 mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
 965 {
 966         struct mlx5e_channel *c = rq->channel;
 967         struct mlx5e_priv *priv = c->priv;
 968         struct mlx5_wq_ll *wq = &rq->wq;
 969         int i;
 970
 971         for (i = 0; i < 1000; i++) {
 972                 if (wq->cur_sz >= priv->params.min_rx_wqes)
 973                         return (0);
 974
 975                 msleep(4);
 976         }
 977         return (-ETIMEDOUT);
 978 }
 979
 980 static int
 981 mlx5e_open_rq(struct mlx5e_channel *c,
 982     struct mlx5e_rq_param *param,
 983     struct mlx5e_rq *rq)
 984 {
 985         int err;
 986
 987         err = mlx5e_create_rq(c, param, rq);
 988         if (err)
 989                 return (err);
 990
 991         err = mlx5e_enable_rq(rq, param);
 992         if (err)
 993                 goto err_destroy_rq;
 994
 995         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
 996         if (err)
 997                 goto err_disable_rq;
 998
 999         c->rq.enabled = 1;
1000
1001         return (0);
1002
1003 err_disable_rq:
1004         mlx5e_disable_rq(rq);
1005 err_destroy_rq:
1006         mlx5e_destroy_rq(rq);
1007
1008         return (err);
1009 }
1010
1011 static void
1012 mlx5e_close_rq(struct mlx5e_rq *rq)
1013 {
1014         mtx_lock(&rq->mtx);
1015         rq->enabled = 0;
1016         callout_stop(&rq->watchdog);
1017         mtx_unlock(&rq->mtx);
1018
1019         callout_drain(&rq->watchdog);
1020
1021         mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
1022 }
1023
1024 static void
1025 mlx5e_close_rq_wait(struct mlx5e_rq *rq)
1026 {
1027
1028         mlx5e_disable_rq(rq);
1029         mlx5e_close_cq(&rq->cq);
1030         cancel_work_sync(&rq->dim.work);
1031         mlx5e_destroy_rq(rq);
1032 }
1033
1034 void
1035 mlx5e_free_sq_db(struct mlx5e_sq *sq)
1036 {
1037         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1038         int x;
1039
1040         for (x = 0; x != wq_sz; x++) {
1041                 if (sq->mbuf[x].mbuf != NULL) {
1042                         bus_dmamap_unload(sq->dma_tag, sq->mbuf[x].dma_map);
1043                         m_freem(sq->mbuf[x].mbuf);
1044                 }
1045                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1046         }
1047         free(sq->mbuf, M_MLX5EN);
1048 }
1049
1050 int
1051 mlx5e_alloc_sq_db(struct mlx5e_sq *sq)
1052 {
1053         int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
1054         int err;
1055         int x;
1056
1057         sq->mbuf = malloc(wq_sz * sizeof(sq->mbuf[0]), M_MLX5EN, M_WAITOK | M_ZERO);
1058
1059         /* Create DMA descriptor MAPs */
1060         for (x = 0; x != wq_sz; x++) {
1061                 err = -bus_dmamap_create(sq->dma_tag, 0, &sq->mbuf[x].dma_map);
1062                 if (err != 0) {
1063                         while (x--)
1064                                 bus_dmamap_destroy(sq->dma_tag, sq->mbuf[x].dma_map);
1065                         free(sq->mbuf, M_MLX5EN);
1066                         return (err);
1067                 }
1068         }
1069         return (0);
1070 }
1071
1072 static const char *mlx5e_sq_stats_desc[] = {
1073         MLX5E_SQ_STATS(MLX5E_STATS_DESC)
1074 };
1075
1076 void
1077 mlx5e_update_sq_inline(struct mlx5e_sq *sq)
1078 {
1079         sq->max_inline = sq->priv->params.tx_max_inline;
1080         sq->min_inline_mode = sq->priv->params.tx_min_inline_mode;
1081
1082         /*
1083          * Check if trust state is DSCP or if inline mode is NONE which
1084          * indicates CX-5 or newer hardware.
1085          */
1086         if (sq->priv->params_ethtool.trust_state != MLX5_QPTS_TRUST_PCP ||
1087             sq->min_inline_mode == MLX5_INLINE_MODE_NONE) {
1088                 if (MLX5_CAP_ETH(sq->priv->mdev, wqe_vlan_insert))
1089                         sq->min_insert_caps = MLX5E_INSERT_VLAN | MLX5E_INSERT_NON_VLAN;
1090                 else
1091                         sq->min_insert_caps = MLX5E_INSERT_NON_VLAN;
1092         } else {
1093                 sq->min_insert_caps = 0;
1094         }
1095 }
1096
1097 static void
1098 mlx5e_refresh_sq_inline_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
1099 {
1100         int i;
1101
1102         for (i = 0; i != c->num_tc; i++) {
1103                 mtx_lock(&c->sq[i].lock);
1104                 mlx5e_update_sq_inline(&c->sq[i]);
1105                 mtx_unlock(&c->sq[i].lock);
1106         }
1107 }
1108
1109 void
1110 mlx5e_refresh_sq_inline(struct mlx5e_priv *priv)
1111 {
1112         int i;
1113
1114         /* check if channels are closed */
1115         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
1116                 return;
1117
1118         for (i = 0; i < priv->params.num_channels; i++)
1119                 mlx5e_refresh_sq_inline_sub(priv, &priv->channel[i]);
1120 }
1121
1122 static int
1123 mlx5e_create_sq(struct mlx5e_channel *c,
1124     int tc,
1125     struct mlx5e_sq_param *param,
1126     struct mlx5e_sq *sq)
1127 {
1128         struct mlx5e_priv *priv = c->priv;
1129         struct mlx5_core_dev *mdev = priv->mdev;
1130         char buffer[16];
1131         void *sqc = param->sqc;
1132         void *sqc_wq = MLX5_ADDR_OF(sqc, sqc, wq);
1133         int err;
1134
1135         /* Create DMA descriptor TAG */
1136         if ((err = -bus_dma_tag_create(
1137             bus_get_dma_tag(mdev->pdev->dev.bsddev),
1138             1,                          /* any alignment */
1139             0,                          /* no boundary */
1140             BUS_SPACE_MAXADDR,          /* lowaddr */
1141             BUS_SPACE_MAXADDR,          /* highaddr */
1142             NULL, NULL,                 /* filter, filterarg */
1143             MLX5E_MAX_TX_PAYLOAD_SIZE,  /* maxsize */
1144             MLX5E_MAX_TX_MBUF_FRAGS,    /* nsegments */
1145             MLX5E_MAX_TX_MBUF_SIZE,     /* maxsegsize */
1146             0,                          /* flags */
1147             NULL, NULL,                 /* lockfunc, lockfuncarg */
1148             &sq->dma_tag)))
1149                 goto done;
1150
1151         err = mlx5_alloc_map_uar(mdev, &sq->uar);
1152         if (err)
1153                 goto err_free_dma_tag;
1154
1155         err = mlx5_wq_cyc_create(mdev, &param->wq, sqc_wq, &sq->wq,
1156             &sq->wq_ctrl);
1157         if (err)
1158                 goto err_unmap_free_uar;
1159
1160         sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
1161         sq->bf_buf_size = (1 << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2;
1162
1163         err = mlx5e_alloc_sq_db(sq);
1164         if (err)
1165                 goto err_sq_wq_destroy;
1166
1167         sq->mkey_be = c->mkey_be;
1168         sq->ifp = priv->ifp;
1169         sq->priv = priv;
1170         sq->tc = tc;
1171
1172         mlx5e_update_sq_inline(sq);
1173
1174         snprintf(buffer, sizeof(buffer), "txstat%dtc%d", c->ix, tc);
1175         mlx5e_create_stats(&sq->stats.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
1176             buffer, mlx5e_sq_stats_desc, MLX5E_SQ_STATS_NUM,
1177             sq->stats.arg);
1178
1179         return (0);
1180
1181 err_sq_wq_destroy:
1182         mlx5_wq_destroy(&sq->wq_ctrl);
1183
1184 err_unmap_free_uar:
1185         mlx5_unmap_free_uar(mdev, &sq->uar);
1186
1187 err_free_dma_tag:
1188         bus_dma_tag_destroy(sq->dma_tag);
1189 done:
1190         return (err);
1191 }
1192
1193 static void
1194 mlx5e_destroy_sq(struct mlx5e_sq *sq)
1195 {
1196         /* destroy all sysctl nodes */
1197         sysctl_ctx_free(&sq->stats.ctx);
1198
1199         mlx5e_free_sq_db(sq);
1200         mlx5_wq_destroy(&sq->wq_ctrl);
1201         mlx5_unmap_free_uar(sq->priv->mdev, &sq->uar);
1202 }
1203
1204 int
1205 mlx5e_enable_sq(struct mlx5e_sq *sq, struct mlx5e_sq_param *param,
1206     int tis_num)
1207 {
1208         void *in;
1209         void *sqc;
1210         void *wq;
1211         int inlen;
1212         int err;
1213
1214         inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1215             sizeof(u64) * sq->wq_ctrl.buf.npages;
1216         in = mlx5_vzalloc(inlen);
1217         if (in == NULL)
1218                 return (-ENOMEM);
1219
1220         sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1221         wq = MLX5_ADDR_OF(sqc, sqc, wq);
1222
1223         memcpy(sqc, param->sqc, sizeof(param->sqc));
1224
1225         MLX5_SET(sqc, sqc, tis_num_0, tis_num);
1226         MLX5_SET(sqc, sqc, cqn, sq->cq.mcq.cqn);
1227         MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1228         MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1229         MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1230
1231         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1232         MLX5_SET(wq, wq, uar_page, sq->uar.index);
1233         MLX5_SET(wq, wq, log_wq_pg_sz, sq->wq_ctrl.buf.page_shift -
1234             PAGE_SHIFT);
1235         MLX5_SET64(wq, wq, dbr_addr, sq->wq_ctrl.db.dma);
1236
1237         mlx5_fill_page_array(&sq->wq_ctrl.buf,
1238             (__be64 *) MLX5_ADDR_OF(wq, wq, pas));
1239
1240         err = mlx5_core_create_sq(sq->priv->mdev, in, inlen, &sq->sqn);
1241
1242         kvfree(in);
1243
1244         return (err);
1245 }
1246
1247 int
1248 mlx5e_modify_sq(struct mlx5e_sq *sq, int curr_state, int next_state)
1249 {
1250         void *in;
1251         void *sqc;
1252         int inlen;
1253         int err;
1254
1255         inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1256         in = mlx5_vzalloc(inlen);
1257         if (in == NULL)
1258                 return (-ENOMEM);
1259
1260         sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1261
1262         MLX5_SET(modify_sq_in, in, sqn, sq->sqn);
1263         MLX5_SET(modify_sq_in, in, sq_state, curr_state);
1264         MLX5_SET(sqc, sqc, state, next_state);
1265
1266         err = mlx5_core_modify_sq(sq->priv->mdev, in, inlen);
1267
1268         kvfree(in);
1269
1270         return (err);
1271 }
1272
1273 void
1274 mlx5e_disable_sq(struct mlx5e_sq *sq)
1275 {
1276
1277         mlx5_core_destroy_sq(sq->priv->mdev, sq->sqn);
1278 }
1279
1280 static int
1281 mlx5e_open_sq(struct mlx5e_channel *c,
1282     int tc,
1283     struct mlx5e_sq_param *param,
1284     struct mlx5e_sq *sq)
1285 {
1286         int err;
1287
1288         err = mlx5e_create_sq(c, tc, param, sq);
1289         if (err)
1290                 return (err);
1291
1292         err = mlx5e_enable_sq(sq, param, c->priv->tisn[tc]);
1293         if (err)
1294                 goto err_destroy_sq;
1295
1296         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST, MLX5_SQC_STATE_RDY);
1297         if (err)
1298                 goto err_disable_sq;
1299
1300         WRITE_ONCE(sq->running, 1);
1301
1302         return (0);
1303
1304 err_disable_sq:
1305         mlx5e_disable_sq(sq);
1306 err_destroy_sq:
1307         mlx5e_destroy_sq(sq);
1308
1309         return (err);
1310 }
1311
1312 static void
1313 mlx5e_sq_send_nops_locked(struct mlx5e_sq *sq, int can_sleep)
1314 {
1315         /* fill up remainder with NOPs */
1316         while (sq->cev_counter != 0) {
1317                 while (!mlx5e_sq_has_room_for(sq, 1)) {
1318                         if (can_sleep != 0) {
1319                                 mtx_unlock(&sq->lock);
1320                                 msleep(4);
1321                                 mtx_lock(&sq->lock);
1322                         } else {
1323                                 goto done;
1324                         }
1325                 }
1326                 /* send a single NOP */
1327                 mlx5e_send_nop(sq, 1);
1328                 atomic_thread_fence_rel();
1329         }
1330 done:
1331         /* Check if we need to write the doorbell */
1332         if (likely(sq->doorbell.d64 != 0)) {
1333                 mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
1334                 sq->doorbell.d64 = 0;
1335         }
1336 }
1337
1338 void
1339 mlx5e_sq_cev_timeout(void *arg)
1340 {
1341         struct mlx5e_sq *sq = arg;
1342
1343         mtx_assert(&sq->lock, MA_OWNED);
1344
1345         /* check next state */
1346         switch (sq->cev_next_state) {
1347         case MLX5E_CEV_STATE_SEND_NOPS:
1348                 /* fill TX ring with NOPs, if any */
1349                 mlx5e_sq_send_nops_locked(sq, 0);
1350
1351                 /* check if completed */
1352                 if (sq->cev_counter == 0) {
1353                         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
1354                         return;
1355                 }
1356                 break;
1357         default:
1358                 /* send NOPs on next timeout */
1359                 sq->cev_next_state = MLX5E_CEV_STATE_SEND_NOPS;
1360                 break;
1361         }
1362
1363         /* restart timer */
1364         callout_reset_curcpu(&sq->cev_callout, hz, mlx5e_sq_cev_timeout, sq);
1365 }
1366
1367 void
1368 mlx5e_drain_sq(struct mlx5e_sq *sq)
1369 {
1370         int error;
1371         struct mlx5_core_dev *mdev= sq->priv->mdev;
1372
1373         /*
1374          * Check if already stopped.
1375          *
1376          * NOTE: Serialization of this function is managed by the
1377          * caller ensuring the priv's state lock is locked or in case
1378          * of rate limit support, a single thread manages drain and
1379          * resume of SQs. The "running" variable can therefore safely
1380          * be read without any locks.
1381          */
1382         if (READ_ONCE(sq->running) == 0)
1383                 return;
1384
1385         /* don't put more packets into the SQ */
1386         WRITE_ONCE(sq->running, 0);
1387
1388         /* serialize access to DMA rings */
1389         mtx_lock(&sq->lock);
1390
1391         /* teardown event factor timer, if any */
1392         sq->cev_next_state = MLX5E_CEV_STATE_HOLD_NOPS;
1393         callout_stop(&sq->cev_callout);
1394
1395         /* send dummy NOPs in order to flush the transmit ring */
1396         mlx5e_sq_send_nops_locked(sq, 1);
1397         mtx_unlock(&sq->lock);
1398
1399         /* make sure it is safe to free the callout */
1400         callout_drain(&sq->cev_callout);
1401
1402         /* wait till SQ is empty or link is down */
1403         mtx_lock(&sq->lock);
1404         while (sq->cc != sq->pc &&
1405             (sq->priv->media_status_last & IFM_ACTIVE) != 0 &&
1406             mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1407                 mtx_unlock(&sq->lock);
1408                 msleep(1);
1409                 sq->cq.mcq.comp(&sq->cq.mcq);
1410                 mtx_lock(&sq->lock);
1411         }
1412         mtx_unlock(&sq->lock);
1413
1414         /* error out remaining requests */
1415         error = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RDY, MLX5_SQC_STATE_ERR);
1416         if (error != 0) {
1417                 if_printf(sq->ifp,
1418                     "mlx5e_modify_sq() from RDY to ERR failed: %d\n", error);
1419         }
1420
1421         /* wait till SQ is empty */
1422         mtx_lock(&sq->lock);
1423         while (sq->cc != sq->pc &&
1424                mdev->state != MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1425                 mtx_unlock(&sq->lock);
1426                 msleep(1);
1427                 sq->cq.mcq.comp(&sq->cq.mcq);
1428                 mtx_lock(&sq->lock);
1429         }
1430         mtx_unlock(&sq->lock);
1431 }
1432
1433 static void
1434 mlx5e_close_sq_wait(struct mlx5e_sq *sq)
1435 {
1436
1437         mlx5e_drain_sq(sq);
1438         mlx5e_disable_sq(sq);
1439         mlx5e_destroy_sq(sq);
1440 }
1441
1442 static int
1443 mlx5e_create_cq(struct mlx5e_priv *priv,
1444     struct mlx5e_cq_param *param,
1445     struct mlx5e_cq *cq,
1446     mlx5e_cq_comp_t *comp,
1447     int eq_ix)
1448 {
1449         struct mlx5_core_dev *mdev = priv->mdev;
1450         struct mlx5_core_cq *mcq = &cq->mcq;
1451         int eqn_not_used;
1452         int irqn;
1453         int err;
1454         u32 i;
1455
1456         param->wq.buf_numa_node = 0;
1457         param->wq.db_numa_node = 0;
1458
1459         err = mlx5_cqwq_create(mdev, &param->wq, param->cqc, &cq->wq,
1460             &cq->wq_ctrl);
1461         if (err)
1462                 return (err);
1463
1464         mlx5_vector2eqn(mdev, eq_ix, &eqn_not_used, &irqn);
1465
1466         mcq->cqe_sz = 64;
1467         mcq->set_ci_db = cq->wq_ctrl.db.db;
1468         mcq->arm_db = cq->wq_ctrl.db.db + 1;
1469         *mcq->set_ci_db = 0;
1470         *mcq->arm_db = 0;
1471         mcq->vector = eq_ix;
1472         mcq->comp = comp;
1473         mcq->event = mlx5e_cq_error_event;
1474         mcq->irqn = irqn;
1475         mcq->uar = &priv->cq_uar;
1476
1477         for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1478                 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1479
1480                 cqe->op_own = 0xf1;
1481         }
1482
1483         cq->priv = priv;
1484
1485         return (0);
1486 }
1487
1488 static void
1489 mlx5e_destroy_cq(struct mlx5e_cq *cq)
1490 {
1491         mlx5_wq_destroy(&cq->wq_ctrl);
1492 }
1493
1494 static int
1495 mlx5e_enable_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param, int eq_ix)
1496 {
1497         struct mlx5_core_cq *mcq = &cq->mcq;
1498         void *in;
1499         void *cqc;
1500         int inlen;
1501         int irqn_not_used;
1502         int eqn;
1503         int err;
1504
1505         inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1506             sizeof(u64) * cq->wq_ctrl.buf.npages;
1507         in = mlx5_vzalloc(inlen);
1508         if (in == NULL)
1509                 return (-ENOMEM);
1510
1511         cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1512
1513         memcpy(cqc, param->cqc, sizeof(param->cqc));
1514
1515         mlx5_fill_page_array(&cq->wq_ctrl.buf,
1516             (__be64 *) MLX5_ADDR_OF(create_cq_in, in, pas));
1517
1518         mlx5_vector2eqn(cq->priv->mdev, eq_ix, &eqn, &irqn_not_used);
1519
1520         MLX5_SET(cqc, cqc, c_eqn, eqn);
1521         MLX5_SET(cqc, cqc, uar_page, mcq->uar->index);
1522         MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.buf.page_shift -
1523             PAGE_SHIFT);
1524         MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1525
1526         err = mlx5_core_create_cq(cq->priv->mdev, mcq, in, inlen);
1527
1528         kvfree(in);
1529
1530         if (err)
1531                 return (err);
1532
1533         mlx5e_cq_arm(cq, MLX5_GET_DOORBELL_LOCK(&cq->priv->doorbell_lock));
1534
1535         return (0);
1536 }
1537
1538 static void
1539 mlx5e_disable_cq(struct mlx5e_cq *cq)
1540 {
1541
1542         mlx5_core_destroy_cq(cq->priv->mdev, &cq->mcq);
1543 }
1544
1545 int
1546 mlx5e_open_cq(struct mlx5e_priv *priv,
1547     struct mlx5e_cq_param *param,
1548     struct mlx5e_cq *cq,
1549     mlx5e_cq_comp_t *comp,
1550     int eq_ix)
1551 {
1552         int err;
1553
1554         err = mlx5e_create_cq(priv, param, cq, comp, eq_ix);
1555         if (err)
1556                 return (err);
1557
1558         err = mlx5e_enable_cq(cq, param, eq_ix);
1559         if (err)
1560                 goto err_destroy_cq;
1561
1562         return (0);
1563
1564 err_destroy_cq:
1565         mlx5e_destroy_cq(cq);
1566
1567         return (err);
1568 }
1569
1570 void
1571 mlx5e_close_cq(struct mlx5e_cq *cq)
1572 {
1573         mlx5e_disable_cq(cq);
1574         mlx5e_destroy_cq(cq);
1575 }
1576
1577 static int
1578 mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1579     struct mlx5e_channel_param *cparam)
1580 {
1581         int err;
1582         int tc;
1583
1584         for (tc = 0; tc < c->num_tc; tc++) {
1585                 /* open completion queue */
1586                 err = mlx5e_open_cq(c->priv, &cparam->tx_cq, &c->sq[tc].cq,
1587                     &mlx5e_tx_cq_comp, c->ix);
1588                 if (err)
1589                         goto err_close_tx_cqs;
1590         }
1591         return (0);
1592
1593 err_close_tx_cqs:
1594         for (tc--; tc >= 0; tc--)
1595                 mlx5e_close_cq(&c->sq[tc].cq);
1596
1597         return (err);
1598 }
1599
1600 static void
1601 mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1602 {
1603         int tc;
1604
1605         for (tc = 0; tc < c->num_tc; tc++)
1606                 mlx5e_close_cq(&c->sq[tc].cq);
1607 }
1608
1609 static int
1610 mlx5e_open_sqs(struct mlx5e_channel *c,
1611     struct mlx5e_channel_param *cparam)
1612 {
1613         int err;
1614         int tc;
1615
1616         for (tc = 0; tc < c->num_tc; tc++) {
1617                 err = mlx5e_open_sq(c, tc, &cparam->sq, &c->sq[tc]);
1618                 if (err)
1619                         goto err_close_sqs;
1620         }
1621
1622         return (0);
1623
1624 err_close_sqs:
1625         for (tc--; tc >= 0; tc--)
1626                 mlx5e_close_sq_wait(&c->sq[tc]);
1627
1628         return (err);
1629 }
1630
1631 static void
1632 mlx5e_close_sqs_wait(struct mlx5e_channel *c)
1633 {
1634         int tc;
1635
1636         for (tc = 0; tc < c->num_tc; tc++)
1637                 mlx5e_close_sq_wait(&c->sq[tc]);
1638 }
1639
1640 static void
1641 mlx5e_chan_mtx_init(struct mlx5e_channel *c)
1642 {
1643         int tc;
1644
1645         mtx_init(&c->rq.mtx, "mlx5rx", MTX_NETWORK_LOCK, MTX_DEF);
1646
1647         callout_init_mtx(&c->rq.watchdog, &c->rq.mtx, 0);
1648
1649         for (tc = 0; tc < c->num_tc; tc++) {
1650                 struct mlx5e_sq *sq = c->sq + tc;
1651
1652                 mtx_init(&sq->lock, "mlx5tx",
1653                     MTX_NETWORK_LOCK " TX", MTX_DEF);
1654                 mtx_init(&sq->comp_lock, "mlx5comp",
1655                     MTX_NETWORK_LOCK " TX", MTX_DEF);
1656
1657                 callout_init_mtx(&sq->cev_callout, &sq->lock, 0);
1658
1659                 sq->cev_factor = c->priv->params_ethtool.tx_completion_fact;
1660
1661                 /* ensure the TX completion event factor is not zero */
1662                 if (sq->cev_factor == 0)
1663                         sq->cev_factor = 1;
1664         }
1665 }
1666
1667 static void
1668 mlx5e_chan_mtx_destroy(struct mlx5e_channel *c)
1669 {
1670         int tc;
1671
1672         mtx_destroy(&c->rq.mtx);
1673
1674         for (tc = 0; tc < c->num_tc; tc++) {
1675                 mtx_destroy(&c->sq[tc].lock);
1676                 mtx_destroy(&c->sq[tc].comp_lock);
1677         }
1678 }
1679
1680 static int
1681 mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1682     struct mlx5e_channel_param *cparam,
1683     struct mlx5e_channel *c)
1684 {
1685         int err;
1686
1687         memset(c, 0, sizeof(*c));
1688
1689         c->priv = priv;
1690         c->ix = ix;
1691         c->ifp = priv->ifp;
1692         c->mkey_be = cpu_to_be32(priv->mr.key);
1693         c->num_tc = priv->num_tc;
1694
1695         /* init mutexes */
1696         mlx5e_chan_mtx_init(c);
1697
1698         /* open transmit completion queue */
1699         err = mlx5e_open_tx_cqs(c, cparam);
1700         if (err)
1701                 goto err_free;
1702
1703         /* open receive completion queue */
1704         err = mlx5e_open_cq(c->priv, &cparam->rx_cq, &c->rq.cq,
1705             &mlx5e_rx_cq_comp, c->ix);
1706         if (err)
1707                 goto err_close_tx_cqs;
1708
1709         err = mlx5e_open_sqs(c, cparam);
1710         if (err)
1711                 goto err_close_rx_cq;
1712
1713         err = mlx5e_open_rq(c, &cparam->rq, &c->rq);
1714         if (err)
1715                 goto err_close_sqs;
1716
1717         /* poll receive queue initially */
1718         c->rq.cq.mcq.comp(&c->rq.cq.mcq);
1719
1720         return (0);
1721
1722 err_close_sqs:
1723         mlx5e_close_sqs_wait(c);
1724
1725 err_close_rx_cq:
1726         mlx5e_close_cq(&c->rq.cq);
1727
1728 err_close_tx_cqs:
1729         mlx5e_close_tx_cqs(c);
1730
1731 err_free:
1732         /* destroy mutexes */
1733         mlx5e_chan_mtx_destroy(c);
1734         return (err);
1735 }
1736
1737 static void
1738 mlx5e_close_channel(struct mlx5e_channel *c)
1739 {
1740         mlx5e_close_rq(&c->rq);
1741 }
1742
1743 static void
1744 mlx5e_close_channel_wait(struct mlx5e_channel *c)
1745 {
1746         mlx5e_close_rq_wait(&c->rq);
1747         mlx5e_close_sqs_wait(c);
1748         mlx5e_close_tx_cqs(c);
1749         /* destroy mutexes */
1750         mlx5e_chan_mtx_destroy(c);
1751 }
1752
1753 static int
1754 mlx5e_get_wqe_sz(struct mlx5e_priv *priv, u32 *wqe_sz, u32 *nsegs)
1755 {
1756         u32 r, n;
1757
1758         r = priv->params.hw_lro_en ? priv->params.lro_wqe_sz :
1759             MLX5E_SW2MB_MTU(priv->ifp->if_mtu);
1760         if (r > MJUM16BYTES)
1761                 return (-ENOMEM);
1762
1763         if (r > MJUM9BYTES)
1764                 r = MJUM16BYTES;
1765         else if (r > MJUMPAGESIZE)
1766                 r = MJUM9BYTES;
1767         else if (r > MCLBYTES)
1768                 r = MJUMPAGESIZE;
1769         else
1770                 r = MCLBYTES;
1771
1772         /*
1773          * n + 1 must be a power of two, because stride size must be.
1774          * Stride size is 16 * (n + 1), as the first segment is
1775          * control.
1776          */
1777         for (n = howmany(r, MLX5E_MAX_RX_BYTES); !powerof2(n + 1); n++)
1778                 ;
1779
1780         *wqe_sz = r;
1781         *nsegs = n;
1782         return (0);
1783 }
1784
1785 static void
1786 mlx5e_build_rq_param(struct mlx5e_priv *priv,
1787     struct mlx5e_rq_param *param)
1788 {
1789         void *rqc = param->rqc;
1790         void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1791         u32 wqe_sz, nsegs;
1792
1793         mlx5e_get_wqe_sz(priv, &wqe_sz, &nsegs);
1794         MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1795         MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1796         MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe) +
1797             nsegs * sizeof(struct mlx5_wqe_data_seg)));
1798         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_rq_size);
1799         MLX5_SET(wq, wq, pd, priv->pdn);
1800
1801         param->wq.buf_numa_node = 0;
1802         param->wq.db_numa_node = 0;
1803         param->wq.linear = 1;
1804 }
1805
1806 static void
1807 mlx5e_build_sq_param(struct mlx5e_priv *priv,
1808     struct mlx5e_sq_param *param)
1809 {
1810         void *sqc = param->sqc;
1811         void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1812
1813         MLX5_SET(wq, wq, log_wq_sz, priv->params.log_sq_size);
1814         MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1815         MLX5_SET(wq, wq, pd, priv->pdn);
1816
1817         param->wq.buf_numa_node = 0;
1818         param->wq.db_numa_node = 0;
1819         param->wq.linear = 1;
1820 }
1821
1822 static void
1823 mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1824     struct mlx5e_cq_param *param)
1825 {
1826         void *cqc = param->cqc;
1827
1828         MLX5_SET(cqc, cqc, uar_page, priv->cq_uar.index);
1829 }
1830
1831 static void
1832 mlx5e_get_default_profile(struct mlx5e_priv *priv, int mode, struct net_dim_cq_moder *ptr)
1833 {
1834
1835         *ptr = net_dim_get_profile(mode, MLX5E_DIM_DEFAULT_PROFILE);
1836
1837         /* apply LRO restrictions */
1838         if (priv->params.hw_lro_en &&
1839             ptr->pkts > MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO) {
1840                 ptr->pkts = MLX5E_DIM_MAX_RX_CQ_MODERATION_PKTS_WITH_LRO;
1841         }
1842 }
1843
1844 static void
1845 mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1846     struct mlx5e_cq_param *param)
1847 {
1848         struct net_dim_cq_moder curr;
1849         void *cqc = param->cqc;
1850
1851         /*
1852          * We use MLX5_CQE_FORMAT_HASH because the RX hash mini CQE
1853          * format is more beneficial for FreeBSD use case.
1854          *
1855          * Adding support for MLX5_CQE_FORMAT_CSUM will require changes
1856          * in mlx5e_decompress_cqe.
1857          */
1858         if (priv->params.cqe_zipping_en) {
1859                 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_HASH);
1860                 MLX5_SET(cqc, cqc, cqe_compression_en, 1);
1861         }
1862
1863         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_rq_size);
1864
1865         switch (priv->params.rx_cq_moderation_mode) {
1866         case 0:
1867                 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1868                 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1869                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1870                 break;
1871         case 1:
1872                 MLX5_SET(cqc, cqc, cq_period, priv->params.rx_cq_moderation_usec);
1873                 MLX5_SET(cqc, cqc, cq_max_count, priv->params.rx_cq_moderation_pkts);
1874                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1875                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1876                 else
1877                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1878                 break;
1879         case 2:
1880                 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE, &curr);
1881                 MLX5_SET(cqc, cqc, cq_period, curr.usec);
1882                 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
1883                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1884                 break;
1885         case 3:
1886                 mlx5e_get_default_profile(priv, NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE, &curr);
1887                 MLX5_SET(cqc, cqc, cq_period, curr.usec);
1888                 MLX5_SET(cqc, cqc, cq_max_count, curr.pkts);
1889                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1890                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1891                 else
1892                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1893                 break;
1894         default:
1895                 break;
1896         }
1897
1898         mlx5e_dim_build_cq_param(priv, param);
1899
1900         mlx5e_build_common_cq_param(priv, param);
1901 }
1902
1903 static void
1904 mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1905     struct mlx5e_cq_param *param)
1906 {
1907         void *cqc = param->cqc;
1908
1909         MLX5_SET(cqc, cqc, log_cq_size, priv->params.log_sq_size);
1910         MLX5_SET(cqc, cqc, cq_period, priv->params.tx_cq_moderation_usec);
1911         MLX5_SET(cqc, cqc, cq_max_count, priv->params.tx_cq_moderation_pkts);
1912
1913         switch (priv->params.tx_cq_moderation_mode) {
1914         case 0:
1915                 MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1916                 break;
1917         default:
1918                 if (MLX5_CAP_GEN(priv->mdev, cq_period_start_from_cqe))
1919                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
1920                 else
1921                         MLX5_SET(cqc, cqc, cq_period_mode, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
1922                 break;
1923         }
1924
1925         mlx5e_build_common_cq_param(priv, param);
1926 }
1927
1928 static void
1929 mlx5e_build_channel_param(struct mlx5e_priv *priv,
1930     struct mlx5e_channel_param *cparam)
1931 {
1932         memset(cparam, 0, sizeof(*cparam));
1933
1934         mlx5e_build_rq_param(priv, &cparam->rq);
1935         mlx5e_build_sq_param(priv, &cparam->sq);
1936         mlx5e_build_rx_cq_param(priv, &cparam->rx_cq);
1937         mlx5e_build_tx_cq_param(priv, &cparam->tx_cq);
1938 }
1939
1940 static int
1941 mlx5e_open_channels(struct mlx5e_priv *priv)
1942 {
1943         struct mlx5e_channel_param cparam;
1944         int err;
1945         int i;
1946         int j;
1947
1948         mlx5e_build_channel_param(priv, &cparam);
1949         for (i = 0; i < priv->params.num_channels; i++) {
1950                 err = mlx5e_open_channel(priv, i, &cparam, &priv->channel[i]);
1951                 if (err)
1952                         goto err_close_channels;
1953         }
1954
1955         for (j = 0; j < priv->params.num_channels; j++) {
1956                 err = mlx5e_wait_for_min_rx_wqes(&priv->channel[j].rq);
1957                 if (err)
1958                         goto err_close_channels;
1959         }
1960
1961         return (0);
1962
1963 err_close_channels:
1964         while (i--) {
1965                 mlx5e_close_channel(&priv->channel[i]);
1966                 mlx5e_close_channel_wait(&priv->channel[i]);
1967         }
1968         return (err);
1969 }
1970
1971 static void
1972 mlx5e_close_channels(struct mlx5e_priv *priv)
1973 {
1974         int i;
1975
1976         for (i = 0; i < priv->params.num_channels; i++)
1977                 mlx5e_close_channel(&priv->channel[i]);
1978         for (i = 0; i < priv->params.num_channels; i++)
1979                 mlx5e_close_channel_wait(&priv->channel[i]);
1980 }
1981
1982 static int
1983 mlx5e_refresh_sq_params(struct mlx5e_priv *priv, struct mlx5e_sq *sq)
1984 {
1985
1986         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
1987                 uint8_t cq_mode;
1988
1989                 switch (priv->params.tx_cq_moderation_mode) {
1990                 case 0:
1991                 case 2:
1992                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
1993                         break;
1994                 default:
1995                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
1996                         break;
1997                 }
1998
1999                 return (mlx5_core_modify_cq_moderation_mode(priv->mdev, &sq->cq.mcq,
2000                     priv->params.tx_cq_moderation_usec,
2001                     priv->params.tx_cq_moderation_pkts,
2002                     cq_mode));
2003         }
2004
2005         return (mlx5_core_modify_cq_moderation(priv->mdev, &sq->cq.mcq,
2006             priv->params.tx_cq_moderation_usec,
2007             priv->params.tx_cq_moderation_pkts));
2008 }
2009
2010 static int
2011 mlx5e_refresh_rq_params(struct mlx5e_priv *priv, struct mlx5e_rq *rq)
2012 {
2013
2014         if (MLX5_CAP_GEN(priv->mdev, cq_period_mode_modify)) {
2015                 uint8_t cq_mode;
2016                 uint8_t dim_mode;
2017                 int retval;
2018
2019                 switch (priv->params.rx_cq_moderation_mode) {
2020                 case 0:
2021                 case 2:
2022                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
2023                         dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
2024                         break;
2025                 default:
2026                         cq_mode = MLX5_CQ_PERIOD_MODE_START_FROM_CQE;
2027                         dim_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
2028                         break;
2029                 }
2030
2031                 /* tear down dynamic interrupt moderation */
2032                 mtx_lock(&rq->mtx);
2033                 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_DISABLED;
2034                 mtx_unlock(&rq->mtx);
2035
2036                 /* wait for dynamic interrupt moderation work task, if any */
2037                 cancel_work_sync(&rq->dim.work);
2038
2039                 if (priv->params.rx_cq_moderation_mode >= 2) {
2040                         struct net_dim_cq_moder curr;
2041
2042                         mlx5e_get_default_profile(priv, dim_mode, &curr);
2043
2044                         retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2045                             curr.usec, curr.pkts, cq_mode);
2046
2047                         /* set dynamic interrupt moderation mode and zero defaults */
2048                         mtx_lock(&rq->mtx);
2049                         rq->dim.mode = dim_mode;
2050                         rq->dim.state = 0;
2051                         rq->dim.profile_ix = MLX5E_DIM_DEFAULT_PROFILE;
2052                         mtx_unlock(&rq->mtx);
2053                 } else {
2054                         retval = mlx5_core_modify_cq_moderation_mode(priv->mdev, &rq->cq.mcq,
2055                             priv->params.rx_cq_moderation_usec,
2056                             priv->params.rx_cq_moderation_pkts,
2057                             cq_mode);
2058                 }
2059                 return (retval);
2060         }
2061
2062         return (mlx5_core_modify_cq_moderation(priv->mdev, &rq->cq.mcq,
2063             priv->params.rx_cq_moderation_usec,
2064             priv->params.rx_cq_moderation_pkts));
2065 }
2066
2067 static int
2068 mlx5e_refresh_channel_params_sub(struct mlx5e_priv *priv, struct mlx5e_channel *c)
2069 {
2070         int err;
2071         int i;
2072
2073         err = mlx5e_refresh_rq_params(priv, &c->rq);
2074         if (err)
2075                 goto done;
2076
2077         for (i = 0; i != c->num_tc; i++) {
2078                 err = mlx5e_refresh_sq_params(priv, &c->sq[i]);
2079                 if (err)
2080                         goto done;
2081         }
2082 done:
2083         return (err);
2084 }
2085
2086 int
2087 mlx5e_refresh_channel_params(struct mlx5e_priv *priv)
2088 {
2089         int i;
2090
2091         /* check if channels are closed */
2092         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2093                 return (EINVAL);
2094
2095         for (i = 0; i < priv->params.num_channels; i++) {
2096                 int err;
2097
2098                 err = mlx5e_refresh_channel_params_sub(priv, &priv->channel[i]);
2099                 if (err)
2100                         return (err);
2101         }
2102         return (0);
2103 }
2104
2105 static int
2106 mlx5e_open_tis(struct mlx5e_priv *priv, int tc)
2107 {
2108         struct mlx5_core_dev *mdev = priv->mdev;
2109         u32 in[MLX5_ST_SZ_DW(create_tis_in)];
2110         void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2111
2112         memset(in, 0, sizeof(in));
2113
2114         MLX5_SET(tisc, tisc, prio, tc);
2115         MLX5_SET(tisc, tisc, transport_domain, priv->tdn);
2116
2117         return (mlx5_core_create_tis(mdev, in, sizeof(in), &priv->tisn[tc]));
2118 }
2119
2120 static void
2121 mlx5e_close_tis(struct mlx5e_priv *priv, int tc)
2122 {
2123         mlx5_core_destroy_tis(priv->mdev, priv->tisn[tc]);
2124 }
2125
2126 static int
2127 mlx5e_open_tises(struct mlx5e_priv *priv)
2128 {
2129         int num_tc = priv->num_tc;
2130         int err;
2131         int tc;
2132
2133         for (tc = 0; tc < num_tc; tc++) {
2134                 err = mlx5e_open_tis(priv, tc);
2135                 if (err)
2136                         goto err_close_tises;
2137         }
2138
2139         return (0);
2140
2141 err_close_tises:
2142         for (tc--; tc >= 0; tc--)
2143                 mlx5e_close_tis(priv, tc);
2144
2145         return (err);
2146 }
2147
2148 static void
2149 mlx5e_close_tises(struct mlx5e_priv *priv)
2150 {
2151         int num_tc = priv->num_tc;
2152         int tc;
2153
2154         for (tc = 0; tc < num_tc; tc++)
2155                 mlx5e_close_tis(priv, tc);
2156 }
2157
2158 static int
2159 mlx5e_open_rqt(struct mlx5e_priv *priv)
2160 {
2161         struct mlx5_core_dev *mdev = priv->mdev;
2162         u32 *in;
2163         u32 out[MLX5_ST_SZ_DW(create_rqt_out)] = {0};
2164         void *rqtc;
2165         int inlen;
2166         int err;
2167         int sz;
2168         int i;
2169
2170         sz = 1 << priv->params.rx_hash_log_tbl_sz;
2171
2172         inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2173         in = mlx5_vzalloc(inlen);
2174         if (in == NULL)
2175                 return (-ENOMEM);
2176         rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2177
2178         MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2179         MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2180
2181         for (i = 0; i < sz; i++) {
2182                 int ix = i;
2183 #ifdef RSS
2184                 ix = rss_get_indirection_to_bucket(ix);
2185 #endif
2186                 /* ensure we don't overflow */
2187                 ix %= priv->params.num_channels;
2188
2189                 /* apply receive side scaling stride, if any */
2190                 ix -= ix % (int)priv->params.channels_rsss;
2191
2192                 MLX5_SET(rqtc, rqtc, rq_num[i], priv->channel[ix].rq.rqn);
2193         }
2194
2195         MLX5_SET(create_rqt_in, in, opcode, MLX5_CMD_OP_CREATE_RQT);
2196
2197         err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
2198         if (!err)
2199                 priv->rqtn = MLX5_GET(create_rqt_out, out, rqtn);
2200
2201         kvfree(in);
2202
2203         return (err);
2204 }
2205
2206 static void
2207 mlx5e_close_rqt(struct mlx5e_priv *priv)
2208 {
2209         u32 in[MLX5_ST_SZ_DW(destroy_rqt_in)] = {0};
2210         u32 out[MLX5_ST_SZ_DW(destroy_rqt_out)] = {0};
2211
2212         MLX5_SET(destroy_rqt_in, in, opcode, MLX5_CMD_OP_DESTROY_RQT);
2213         MLX5_SET(destroy_rqt_in, in, rqtn, priv->rqtn);
2214
2215         mlx5_cmd_exec(priv->mdev, in, sizeof(in), out, sizeof(out));
2216 }
2217
2218 static void
2219 mlx5e_build_tir_ctx(struct mlx5e_priv *priv, u32 * tirc, int tt)
2220 {
2221         void *hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2222         __be32 *hkey;
2223
2224         MLX5_SET(tirc, tirc, transport_domain, priv->tdn);
2225
2226 #define ROUGH_MAX_L2_L3_HDR_SZ 256
2227
2228 #define MLX5_HASH_IP     (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2229                           MLX5_HASH_FIELD_SEL_DST_IP)
2230
2231 #define MLX5_HASH_ALL    (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2232                           MLX5_HASH_FIELD_SEL_DST_IP   |\
2233                           MLX5_HASH_FIELD_SEL_L4_SPORT |\
2234                           MLX5_HASH_FIELD_SEL_L4_DPORT)
2235
2236 #define MLX5_HASH_IP_IPSEC_SPI  (MLX5_HASH_FIELD_SEL_SRC_IP   |\
2237                                  MLX5_HASH_FIELD_SEL_DST_IP   |\
2238                                  MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2239
2240         if (priv->params.hw_lro_en) {
2241                 MLX5_SET(tirc, tirc, lro_enable_mask,
2242                     MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2243                     MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2244                 MLX5_SET(tirc, tirc, lro_max_msg_sz,
2245                     (priv->params.lro_wqe_sz -
2246                     ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2247                 /* TODO: add the option to choose timer value dynamically */
2248                 MLX5_SET(tirc, tirc, lro_timeout_period_usecs,
2249                     MLX5_CAP_ETH(priv->mdev,
2250                     lro_timer_supported_periods[2]));
2251         }
2252
2253         /* setup parameters for hashing TIR type, if any */
2254         switch (tt) {
2255         case MLX5E_TT_ANY:
2256                 MLX5_SET(tirc, tirc, disp_type,
2257                     MLX5_TIRC_DISP_TYPE_DIRECT);
2258                 MLX5_SET(tirc, tirc, inline_rqn,
2259                     priv->channel[0].rq.rqn);
2260                 break;
2261         default:
2262                 MLX5_SET(tirc, tirc, disp_type,
2263                     MLX5_TIRC_DISP_TYPE_INDIRECT);
2264                 MLX5_SET(tirc, tirc, indirect_table,
2265                     priv->rqtn);
2266                 MLX5_SET(tirc, tirc, rx_hash_fn,
2267                     MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ);
2268                 hkey = (__be32 *) MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
2269 #ifdef RSS
2270                 /*
2271                  * The FreeBSD RSS implementation does currently not
2272                  * support symmetric Toeplitz hashes:
2273                  */
2274                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 0);
2275                 rss_getkey((uint8_t *)hkey);
2276 #else
2277                 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2278                 hkey[0] = cpu_to_be32(0xD181C62C);
2279                 hkey[1] = cpu_to_be32(0xF7F4DB5B);
2280                 hkey[2] = cpu_to_be32(0x1983A2FC);
2281                 hkey[3] = cpu_to_be32(0x943E1ADB);
2282                 hkey[4] = cpu_to_be32(0xD9389E6B);
2283                 hkey[5] = cpu_to_be32(0xD1039C2C);
2284                 hkey[6] = cpu_to_be32(0xA74499AD);
2285                 hkey[7] = cpu_to_be32(0x593D56D9);
2286                 hkey[8] = cpu_to_be32(0xF3253C06);
2287                 hkey[9] = cpu_to_be32(0x2ADC1FFC);
2288 #endif
2289                 break;
2290         }
2291
2292         switch (tt) {
2293         case MLX5E_TT_IPV4_TCP:
2294                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2295                     MLX5_L3_PROT_TYPE_IPV4);
2296                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2297                     MLX5_L4_PROT_TYPE_TCP);
2298 #ifdef RSS
2299                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV4)) {
2300                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2301                             MLX5_HASH_IP);
2302                 } else
2303 #endif
2304                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2305                     MLX5_HASH_ALL);
2306                 break;
2307
2308         case MLX5E_TT_IPV6_TCP:
2309                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2310                     MLX5_L3_PROT_TYPE_IPV6);
2311                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2312                     MLX5_L4_PROT_TYPE_TCP);
2313 #ifdef RSS
2314                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_TCP_IPV6)) {
2315                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2316                             MLX5_HASH_IP);
2317                 } else
2318 #endif
2319                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2320                     MLX5_HASH_ALL);
2321                 break;
2322
2323         case MLX5E_TT_IPV4_UDP:
2324                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2325                     MLX5_L3_PROT_TYPE_IPV4);
2326                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2327                     MLX5_L4_PROT_TYPE_UDP);
2328 #ifdef RSS
2329                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV4)) {
2330                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2331                             MLX5_HASH_IP);
2332                 } else
2333 #endif
2334                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2335                     MLX5_HASH_ALL);
2336                 break;
2337
2338         case MLX5E_TT_IPV6_UDP:
2339                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2340                     MLX5_L3_PROT_TYPE_IPV6);
2341                 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2342                     MLX5_L4_PROT_TYPE_UDP);
2343 #ifdef RSS
2344                 if (!(rss_gethashconfig() & RSS_HASHTYPE_RSS_UDP_IPV6)) {
2345                         MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2346                             MLX5_HASH_IP);
2347                 } else
2348 #endif
2349                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2350                     MLX5_HASH_ALL);
2351                 break;
2352
2353         case MLX5E_TT_IPV4_IPSEC_AH:
2354                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2355                     MLX5_L3_PROT_TYPE_IPV4);
2356                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2357                     MLX5_HASH_IP_IPSEC_SPI);
2358                 break;
2359
2360         case MLX5E_TT_IPV6_IPSEC_AH:
2361                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2362                     MLX5_L3_PROT_TYPE_IPV6);
2363                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2364                     MLX5_HASH_IP_IPSEC_SPI);
2365                 break;
2366
2367         case MLX5E_TT_IPV4_IPSEC_ESP:
2368                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2369                     MLX5_L3_PROT_TYPE_IPV4);
2370                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2371                     MLX5_HASH_IP_IPSEC_SPI);
2372                 break;
2373
2374         case MLX5E_TT_IPV6_IPSEC_ESP:
2375                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2376                     MLX5_L3_PROT_TYPE_IPV6);
2377                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2378                     MLX5_HASH_IP_IPSEC_SPI);
2379                 break;
2380
2381         case MLX5E_TT_IPV4:
2382                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2383                     MLX5_L3_PROT_TYPE_IPV4);
2384                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2385                     MLX5_HASH_IP);
2386                 break;
2387
2388         case MLX5E_TT_IPV6:
2389                 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2390                     MLX5_L3_PROT_TYPE_IPV6);
2391                 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2392                     MLX5_HASH_IP);
2393                 break;
2394
2395         default:
2396                 break;
2397         }
2398 }
2399
2400 static int
2401 mlx5e_open_tir(struct mlx5e_priv *priv, int tt)
2402 {
2403         struct mlx5_core_dev *mdev = priv->mdev;
2404         u32 *in;
2405         void *tirc;
2406         int inlen;
2407         int err;
2408
2409         inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2410         in = mlx5_vzalloc(inlen);
2411         if (in == NULL)
2412                 return (-ENOMEM);
2413         tirc = MLX5_ADDR_OF(create_tir_in, in, tir_context);
2414
2415         mlx5e_build_tir_ctx(priv, tirc, tt);
2416
2417         err = mlx5_core_create_tir(mdev, in, inlen, &priv->tirn[tt]);
2418
2419         kvfree(in);
2420
2421         return (err);
2422 }
2423
2424 static void
2425 mlx5e_close_tir(struct mlx5e_priv *priv, int tt)
2426 {
2427         mlx5_core_destroy_tir(priv->mdev, priv->tirn[tt]);
2428 }
2429
2430 static int
2431 mlx5e_open_tirs(struct mlx5e_priv *priv)
2432 {
2433         int err;
2434         int i;
2435
2436         for (i = 0; i < MLX5E_NUM_TT; i++) {
2437                 err = mlx5e_open_tir(priv, i);
2438                 if (err)
2439                         goto err_close_tirs;
2440         }
2441
2442         return (0);
2443
2444 err_close_tirs:
2445         for (i--; i >= 0; i--)
2446                 mlx5e_close_tir(priv, i);
2447
2448         return (err);
2449 }
2450
2451 static void
2452 mlx5e_close_tirs(struct mlx5e_priv *priv)
2453 {
2454         int i;
2455
2456         for (i = 0; i < MLX5E_NUM_TT; i++)
2457                 mlx5e_close_tir(priv, i);
2458 }
2459
2460 /*
2461  * SW MTU does not include headers,
2462  * HW MTU includes all headers and checksums.
2463  */
2464 static int
2465 mlx5e_set_dev_port_mtu(struct ifnet *ifp, int sw_mtu)
2466 {
2467         struct mlx5e_priv *priv = ifp->if_softc;
2468         struct mlx5_core_dev *mdev = priv->mdev;
2469         int hw_mtu;
2470         int err;
2471
2472         hw_mtu = MLX5E_SW2HW_MTU(sw_mtu);
2473
2474         err = mlx5_set_port_mtu(mdev, hw_mtu);
2475         if (err) {
2476                 if_printf(ifp, "%s: mlx5_set_port_mtu failed setting %d, err=%d\n",
2477                     __func__, sw_mtu, err);
2478                 return (err);
2479         }
2480
2481         /* Update vport context MTU */
2482         err = mlx5_set_vport_mtu(mdev, hw_mtu);
2483         if (err) {
2484                 if_printf(ifp, "%s: Failed updating vport context with MTU size, err=%d\n",
2485                     __func__, err);
2486         }
2487
2488         ifp->if_mtu = sw_mtu;
2489
2490         err = mlx5_query_vport_mtu(mdev, &hw_mtu);
2491         if (err || !hw_mtu) {
2492                 /* fallback to port oper mtu */
2493                 err = mlx5_query_port_oper_mtu(mdev, &hw_mtu);
2494         }
2495         if (err) {
2496                 if_printf(ifp, "Query port MTU, after setting new "
2497                     "MTU value, failed\n");
2498                 return (err);
2499         } else if (MLX5E_HW2SW_MTU(hw_mtu) < sw_mtu) {
2500                 err = -E2BIG,
2501                 if_printf(ifp, "Port MTU %d is smaller than "
2502                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2503         } else if (MLX5E_HW2SW_MTU(hw_mtu) > sw_mtu) {
2504                 err = -EINVAL;
2505                 if_printf(ifp, "Port MTU %d is bigger than "
2506                     "ifp mtu %d\n", hw_mtu, sw_mtu);
2507         }
2508         priv->params_ethtool.hw_mtu = hw_mtu;
2509
2510         return (err);
2511 }
2512
2513 int
2514 mlx5e_open_locked(struct ifnet *ifp)
2515 {
2516         struct mlx5e_priv *priv = ifp->if_softc;
2517         int err;
2518         u16 set_id;
2519
2520         /* check if already opened */
2521         if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2522                 return (0);
2523
2524 #ifdef RSS
2525         if (rss_getnumbuckets() > priv->params.num_channels) {
2526                 if_printf(ifp, "NOTE: There are more RSS buckets(%u) than "
2527                     "channels(%u) available\n", rss_getnumbuckets(),
2528                     priv->params.num_channels);
2529         }
2530 #endif
2531         err = mlx5e_open_tises(priv);
2532         if (err) {
2533                 if_printf(ifp, "%s: mlx5e_open_tises failed, %d\n",
2534                     __func__, err);
2535                 return (err);
2536         }
2537         err = mlx5_vport_alloc_q_counter(priv->mdev,
2538             MLX5_INTERFACE_PROTOCOL_ETH, &set_id);
2539         if (err) {
2540                 if_printf(priv->ifp,
2541                     "%s: mlx5_vport_alloc_q_counter failed: %d\n",
2542                     __func__, err);
2543                 goto err_close_tises;
2544         }
2545         /* store counter set ID */
2546         priv->counter_set_id = set_id;
2547
2548         err = mlx5e_open_channels(priv);
2549         if (err) {
2550                 if_printf(ifp, "%s: mlx5e_open_channels failed, %d\n",
2551                     __func__, err);
2552                 goto err_dalloc_q_counter;
2553         }
2554         err = mlx5e_open_rqt(priv);
2555         if (err) {
2556                 if_printf(ifp, "%s: mlx5e_open_rqt failed, %d\n",
2557                     __func__, err);
2558                 goto err_close_channels;
2559         }
2560         err = mlx5e_open_tirs(priv);
2561         if (err) {
2562                 if_printf(ifp, "%s: mlx5e_open_tir failed, %d\n",
2563                     __func__, err);
2564                 goto err_close_rqls;
2565         }
2566         err = mlx5e_open_flow_table(priv);
2567         if (err) {
2568                 if_printf(ifp, "%s: mlx5e_open_flow_table failed, %d\n",
2569                     __func__, err);
2570                 goto err_close_tirs;
2571         }
2572         err = mlx5e_add_all_vlan_rules(priv);
2573         if (err) {
2574                 if_printf(ifp, "%s: mlx5e_add_all_vlan_rules failed, %d\n",
2575                     __func__, err);
2576                 goto err_close_flow_table;
2577         }
2578         set_bit(MLX5E_STATE_OPENED, &priv->state);
2579
2580         mlx5e_update_carrier(priv);
2581         mlx5e_set_rx_mode_core(priv);
2582
2583         return (0);
2584
2585 err_close_flow_table:
2586         mlx5e_close_flow_table(priv);
2587
2588 err_close_tirs:
2589         mlx5e_close_tirs(priv);
2590
2591 err_close_rqls:
2592         mlx5e_close_rqt(priv);
2593
2594 err_close_channels:
2595         mlx5e_close_channels(priv);
2596
2597 err_dalloc_q_counter:
2598         mlx5_vport_dealloc_q_counter(priv->mdev,
2599             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2600
2601 err_close_tises:
2602         mlx5e_close_tises(priv);
2603
2604         return (err);
2605 }
2606
2607 static void
2608 mlx5e_open(void *arg)
2609 {
2610         struct mlx5e_priv *priv = arg;
2611
2612         PRIV_LOCK(priv);
2613         if (mlx5_set_port_status(priv->mdev, MLX5_PORT_UP))
2614                 if_printf(priv->ifp,
2615                     "%s: Setting port status to up failed\n",
2616                     __func__);
2617
2618         mlx5e_open_locked(priv->ifp);
2619         priv->ifp->if_drv_flags |= IFF_DRV_RUNNING;
2620         PRIV_UNLOCK(priv);
2621 }
2622
2623 int
2624 mlx5e_close_locked(struct ifnet *ifp)
2625 {
2626         struct mlx5e_priv *priv = ifp->if_softc;
2627
2628         /* check if already closed */
2629         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2630                 return (0);
2631
2632         clear_bit(MLX5E_STATE_OPENED, &priv->state);
2633
2634         mlx5e_set_rx_mode_core(priv);
2635         mlx5e_del_all_vlan_rules(priv);
2636         if_link_state_change(priv->ifp, LINK_STATE_DOWN);
2637         mlx5e_close_flow_table(priv);
2638         mlx5e_close_tirs(priv);
2639         mlx5e_close_rqt(priv);
2640         mlx5e_close_channels(priv);
2641         mlx5_vport_dealloc_q_counter(priv->mdev,
2642             MLX5_INTERFACE_PROTOCOL_ETH, priv->counter_set_id);
2643         mlx5e_close_tises(priv);
2644
2645         return (0);
2646 }
2647
2648 #if (__FreeBSD_version >= 1100000)
2649 static uint64_t
2650 mlx5e_get_counter(struct ifnet *ifp, ift_counter cnt)
2651 {
2652         struct mlx5e_priv *priv = ifp->if_softc;
2653         u64 retval;
2654
2655         /* PRIV_LOCK(priv); XXX not allowed */
2656         switch (cnt) {
2657         case IFCOUNTER_IPACKETS:
2658                 retval = priv->stats.vport.rx_packets;
2659                 break;
2660         case IFCOUNTER_IERRORS:
2661                 retval = priv->stats.pport.in_range_len_errors +
2662                     priv->stats.pport.out_of_range_len +
2663                     priv->stats.pport.too_long_errors +
2664                     priv->stats.pport.check_seq_err +
2665                     priv->stats.pport.alignment_err;
2666                 break;
2667         case IFCOUNTER_IQDROPS:
2668                 retval = priv->stats.vport.rx_out_of_buffer;
2669                 break;
2670         case IFCOUNTER_OPACKETS:
2671                 retval = priv->stats.vport.tx_packets;
2672                 break;
2673         case IFCOUNTER_OERRORS:
2674                 retval = priv->stats.port_stats_debug.out_discards;
2675                 break;
2676         case IFCOUNTER_IBYTES:
2677                 retval = priv->stats.vport.rx_bytes;
2678                 break;
2679         case IFCOUNTER_OBYTES:
2680                 retval = priv->stats.vport.tx_bytes;
2681                 break;
2682         case IFCOUNTER_IMCASTS:
2683                 retval = priv->stats.vport.rx_multicast_packets;
2684                 break;
2685         case IFCOUNTER_OMCASTS:
2686                 retval = priv->stats.vport.tx_multicast_packets;
2687                 break;
2688         case IFCOUNTER_OQDROPS:
2689                 retval = priv->stats.vport.tx_queue_dropped;
2690                 break;
2691         case IFCOUNTER_COLLISIONS:
2692                 retval = priv->stats.pport.collisions;
2693                 break;
2694         default:
2695                 retval = if_get_counter_default(ifp, cnt);
2696                 break;
2697         }
2698         /* PRIV_UNLOCK(priv); XXX not allowed */
2699         return (retval);
2700 }
2701 #endif
2702
2703 static void
2704 mlx5e_set_rx_mode(struct ifnet *ifp)
2705 {
2706         struct mlx5e_priv *priv = ifp->if_softc;
2707
2708         queue_work(priv->wq, &priv->set_rx_mode_work);
2709 }
2710
2711 static int
2712 mlx5e_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
2713 {
2714         struct mlx5e_priv *priv;
2715         struct ifreq *ifr;
2716         struct ifi2creq i2c;
2717         int error = 0;
2718         int mask = 0;
2719         int size_read = 0;
2720         int module_status;
2721         int module_num;
2722         int max_mtu;
2723         uint8_t read_addr;
2724
2725         priv = ifp->if_softc;
2726
2727         /* check if detaching */
2728         if (priv == NULL || priv->gone != 0)
2729                 return (ENXIO);
2730
2731         switch (command) {
2732         case SIOCSIFMTU:
2733                 ifr = (struct ifreq *)data;
2734
2735                 PRIV_LOCK(priv);
2736                 mlx5_query_port_max_mtu(priv->mdev, &max_mtu);
2737
2738                 if (ifr->ifr_mtu >= MLX5E_MTU_MIN &&
2739                     ifr->ifr_mtu <= MIN(MLX5E_MTU_MAX, max_mtu)) {
2740                         int was_opened;
2741
2742                         was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2743                         if (was_opened)
2744                                 mlx5e_close_locked(ifp);
2745
2746                         /* set new MTU */
2747                         mlx5e_set_dev_port_mtu(ifp, ifr->ifr_mtu);
2748
2749                         if (was_opened)
2750                                 mlx5e_open_locked(ifp);
2751                 } else {
2752                         error = EINVAL;
2753                         if_printf(ifp, "Invalid MTU value. Min val: %d, Max val: %d\n",
2754                             MLX5E_MTU_MIN, MIN(MLX5E_MTU_MAX, max_mtu));
2755                 }
2756                 PRIV_UNLOCK(priv);
2757                 break;
2758         case SIOCSIFFLAGS:
2759                 if ((ifp->if_flags & IFF_UP) &&
2760                     (ifp->if_drv_flags & IFF_DRV_RUNNING)) {
2761                         mlx5e_set_rx_mode(ifp);
2762                         break;
2763                 }
2764                 PRIV_LOCK(priv);
2765                 if (ifp->if_flags & IFF_UP) {
2766                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
2767                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
2768                                         mlx5e_open_locked(ifp);
2769                                 ifp->if_drv_flags |= IFF_DRV_RUNNING;
2770                                 mlx5_set_port_status(priv->mdev, MLX5_PORT_UP);
2771                         }
2772                 } else {
2773                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2774                                 mlx5_set_port_status(priv->mdev,
2775                                     MLX5_PORT_DOWN);
2776                                 if (test_bit(MLX5E_STATE_OPENED, &priv->state) != 0)
2777                                         mlx5e_close_locked(ifp);
2778                                 mlx5e_update_carrier(priv);
2779                                 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2780                         }
2781                 }
2782                 PRIV_UNLOCK(priv);
2783                 break;
2784         case SIOCADDMULTI:
2785         case SIOCDELMULTI:
2786                 mlx5e_set_rx_mode(ifp);
2787                 break;
2788         case SIOCSIFMEDIA:
2789         case SIOCGIFMEDIA:
2790         case SIOCGIFXMEDIA:
2791                 ifr = (struct ifreq *)data;
2792                 error = ifmedia_ioctl(ifp, ifr, &priv->media, command);
2793                 break;
2794         case SIOCSIFCAP:
2795                 ifr = (struct ifreq *)data;
2796                 PRIV_LOCK(priv);
2797                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2798
2799                 if (mask & IFCAP_TXCSUM) {
2800                         ifp->if_capenable ^= IFCAP_TXCSUM;
2801                         ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
2802
2803                         if (IFCAP_TSO4 & ifp->if_capenable &&
2804                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2805                                 ifp->if_capenable &= ~IFCAP_TSO4;
2806                                 ifp->if_hwassist &= ~CSUM_IP_TSO;
2807                                 if_printf(ifp,
2808                                     "tso4 disabled due to -txcsum.\n");
2809                         }
2810                 }
2811                 if (mask & IFCAP_TXCSUM_IPV6) {
2812                         ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
2813                         ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
2814
2815                         if (IFCAP_TSO6 & ifp->if_capenable &&
2816                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2817                                 ifp->if_capenable &= ~IFCAP_TSO6;
2818                                 ifp->if_hwassist &= ~CSUM_IP6_TSO;
2819                                 if_printf(ifp,
2820                                     "tso6 disabled due to -txcsum6.\n");
2821                         }
2822                 }
2823                 if (mask & IFCAP_RXCSUM)
2824                         ifp->if_capenable ^= IFCAP_RXCSUM;
2825                 if (mask & IFCAP_RXCSUM_IPV6)
2826                         ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
2827                 if (mask & IFCAP_TSO4) {
2828                         if (!(IFCAP_TSO4 & ifp->if_capenable) &&
2829                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
2830                                 if_printf(ifp, "enable txcsum first.\n");
2831                                 error = EAGAIN;
2832                                 goto out;
2833                         }
2834                         ifp->if_capenable ^= IFCAP_TSO4;
2835                         ifp->if_hwassist ^= CSUM_IP_TSO;
2836                 }
2837                 if (mask & IFCAP_TSO6) {
2838                         if (!(IFCAP_TSO6 & ifp->if_capenable) &&
2839                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
2840                                 if_printf(ifp, "enable txcsum6 first.\n");
2841                                 error = EAGAIN;
2842                                 goto out;
2843                         }
2844                         ifp->if_capenable ^= IFCAP_TSO6;
2845                         ifp->if_hwassist ^= CSUM_IP6_TSO;
2846                 }
2847                 if (mask & IFCAP_VLAN_HWFILTER) {
2848                         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER)
2849                                 mlx5e_disable_vlan_filter(priv);
2850                         else
2851                                 mlx5e_enable_vlan_filter(priv);
2852
2853                         ifp->if_capenable ^= IFCAP_VLAN_HWFILTER;
2854                 }
2855                 if (mask & IFCAP_VLAN_HWTAGGING)
2856                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2857                 if (mask & IFCAP_WOL_MAGIC)
2858                         ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2859
2860                 VLAN_CAPABILITIES(ifp);
2861                 /* turn off LRO means also turn of HW LRO - if it's on */
2862                 if (mask & IFCAP_LRO) {
2863                         int was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
2864                         bool need_restart = false;
2865
2866                         ifp->if_capenable ^= IFCAP_LRO;
2867
2868                         /* figure out if updating HW LRO is needed */
2869                         if (!(ifp->if_capenable & IFCAP_LRO)) {
2870                                 if (priv->params.hw_lro_en) {
2871                                         priv->params.hw_lro_en = false;
2872                                         need_restart = true;
2873                                 }
2874                         } else {
2875                                 if (priv->params.hw_lro_en == false &&
2876                                     priv->params_ethtool.hw_lro != 0) {
2877                                         priv->params.hw_lro_en = true;
2878                                         need_restart = true;
2879                                 }
2880                         }
2881                         if (was_opened && need_restart) {
2882                                 mlx5e_close_locked(ifp);
2883                                 mlx5e_open_locked(ifp);
2884                         }
2885                 }
2886 out:
2887                 PRIV_UNLOCK(priv);
2888                 break;
2889
2890         case SIOCGI2C:
2891                 ifr = (struct ifreq *)data;
2892
2893                 /*
2894                  * Copy from the user-space address ifr_data to the
2895                  * kernel-space address i2c
2896                  */
2897                 error = copyin(ifr_data_get_ptr(ifr), &i2c, sizeof(i2c));
2898                 if (error)
2899                         break;
2900
2901                 if (i2c.len > sizeof(i2c.data)) {
2902                         error = EINVAL;
2903                         break;
2904                 }
2905
2906                 PRIV_LOCK(priv);
2907                 /* Get module_num which is required for the query_eeprom */
2908                 error = mlx5_query_module_num(priv->mdev, &module_num);
2909                 if (error) {
2910                         if_printf(ifp, "Query module num failed, eeprom "
2911                             "reading is not supported\n");
2912                         error = EINVAL;
2913                         goto err_i2c;
2914                 }
2915                 /* Check if module is present before doing an access */
2916                 module_status = mlx5_query_module_status(priv->mdev, module_num);
2917                 if (module_status != MLX5_MODULE_STATUS_PLUGGED_ENABLED &&
2918                     module_status != MLX5_MODULE_STATUS_PLUGGED_DISABLED) {
2919                         error = EINVAL;
2920                         goto err_i2c;
2921                 }
2922                 /*
2923                  * Currently 0XA0 and 0xA2 are the only addresses permitted.
2924                  * The internal conversion is as follows:
2925                  */
2926                 if (i2c.dev_addr == 0xA0)
2927                         read_addr = MLX5E_I2C_ADDR_LOW;
2928                 else if (i2c.dev_addr == 0xA2)
2929                         read_addr = MLX5E_I2C_ADDR_HIGH;
2930                 else {
2931                         if_printf(ifp, "Query eeprom failed, "
2932                             "Invalid Address: %X\n", i2c.dev_addr);
2933                         error = EINVAL;
2934                         goto err_i2c;
2935                 }
2936                 error = mlx5_query_eeprom(priv->mdev,
2937                     read_addr, MLX5E_EEPROM_LOW_PAGE,
2938                     (uint32_t)i2c.offset, (uint32_t)i2c.len, module_num,
2939                     (uint32_t *)i2c.data, &size_read);
2940                 if (error) {
2941                         if_printf(ifp, "Query eeprom failed, eeprom "
2942                             "reading is not supported\n");
2943                         error = EINVAL;
2944                         goto err_i2c;
2945                 }
2946
2947                 if (i2c.len > MLX5_EEPROM_MAX_BYTES) {
2948                         error = mlx5_query_eeprom(priv->mdev,
2949                             read_addr, MLX5E_EEPROM_LOW_PAGE,
2950                             (uint32_t)(i2c.offset + size_read),
2951                             (uint32_t)(i2c.len - size_read), module_num,
2952                             (uint32_t *)(i2c.data + size_read), &size_read);
2953                 }
2954                 if (error) {
2955                         if_printf(ifp, "Query eeprom failed, eeprom "
2956                             "reading is not supported\n");
2957                         error = EINVAL;
2958                         goto err_i2c;
2959                 }
2960
2961                 error = copyout(&i2c, ifr_data_get_ptr(ifr), sizeof(i2c));
2962 err_i2c:
2963                 PRIV_UNLOCK(priv);
2964                 break;
2965
2966         default:
2967                 error = ether_ioctl(ifp, command, data);
2968                 break;
2969         }
2970         return (error);
2971 }
2972
2973 static int
2974 mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
2975 {
2976         /*
2977          * TODO: uncoment once FW really sets all these bits if
2978          * (!mdev->caps.eth.rss_ind_tbl_cap || !mdev->caps.eth.csum_cap ||
2979          * !mdev->caps.eth.max_lso_cap || !mdev->caps.eth.vlan_cap ||
2980          * !(mdev->caps.gen.flags & MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD)) return
2981          * -ENOTSUPP;
2982          */
2983
2984         /* TODO: add more must-to-have features */
2985
2986         if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
2987                 return (-ENODEV);
2988
2989         return (0);
2990 }
2991
2992 static u16
2993 mlx5e_get_max_inline_cap(struct mlx5_core_dev *mdev)
2994 {
2995         uint32_t bf_buf_size = (1U << MLX5_CAP_GEN(mdev, log_bf_reg_size)) / 2U;
2996
2997         bf_buf_size -= sizeof(struct mlx5e_tx_wqe) - 2;
2998
2999         /* verify against driver hardware limit */
3000         if (bf_buf_size > MLX5E_MAX_TX_INLINE)
3001                 bf_buf_size = MLX5E_MAX_TX_INLINE;
3002
3003         return (bf_buf_size);
3004 }
3005
3006 static int
3007 mlx5e_build_ifp_priv(struct mlx5_core_dev *mdev,
3008     struct mlx5e_priv *priv,
3009     int num_comp_vectors)
3010 {
3011         int err;
3012
3013         /*
3014          * TODO: Consider link speed for setting "log_sq_size",
3015          * "log_rq_size" and "cq_moderation_xxx":
3016          */
3017         priv->params.log_sq_size =
3018             MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
3019         priv->params.log_rq_size =
3020             MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
3021         priv->params.rx_cq_moderation_usec =
3022             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
3023             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE :
3024             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
3025         priv->params.rx_cq_moderation_mode =
3026             MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ? 1 : 0;
3027         priv->params.rx_cq_moderation_pkts =
3028             MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
3029         priv->params.tx_cq_moderation_usec =
3030             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
3031         priv->params.tx_cq_moderation_pkts =
3032             MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
3033         priv->params.min_rx_wqes =
3034             MLX5E_PARAMS_DEFAULT_MIN_RX_WQES;
3035         priv->params.rx_hash_log_tbl_sz =
3036             (order_base_2(num_comp_vectors) >
3037             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ) ?
3038             order_base_2(num_comp_vectors) :
3039             MLX5E_PARAMS_DEFAULT_RX_HASH_LOG_TBL_SZ;
3040         priv->params.num_tc = 1;
3041         priv->params.default_vlan_prio = 0;
3042         priv->counter_set_id = -1;
3043         priv->params.tx_max_inline = mlx5e_get_max_inline_cap(mdev);
3044
3045         err = mlx5_query_min_inline(mdev, &priv->params.tx_min_inline_mode);
3046         if (err)
3047                 return (err);
3048
3049         /*
3050          * hw lro is currently defaulted to off. when it won't anymore we
3051          * will consider the HW capability: "!!MLX5_CAP_ETH(mdev, lro_cap)"
3052          */
3053         priv->params.hw_lro_en = false;
3054         priv->params.lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
3055
3056         /*
3057          * CQE zipping is currently defaulted to off. when it won't
3058          * anymore we will consider the HW capability:
3059          * "!!MLX5_CAP_GEN(mdev, cqe_compression)"
3060          */
3061         priv->params.cqe_zipping_en = false;
3062
3063         priv->mdev = mdev;
3064         priv->params.num_channels = num_comp_vectors;
3065         priv->params.channels_rsss = 1;
3066         priv->order_base_2_num_channels = order_base_2(num_comp_vectors);
3067         priv->queue_mapping_channel_mask =
3068             roundup_pow_of_two(num_comp_vectors) - 1;
3069         priv->num_tc = priv->params.num_tc;
3070         priv->default_vlan_prio = priv->params.default_vlan_prio;
3071
3072         INIT_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
3073         INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
3074         INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
3075
3076         return (0);
3077 }
3078
3079 static int
3080 mlx5e_create_mkey(struct mlx5e_priv *priv, u32 pdn,
3081                   struct mlx5_core_mr *mkey)
3082 {
3083         struct ifnet *ifp = priv->ifp;
3084         struct mlx5_core_dev *mdev = priv->mdev;
3085         int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
3086         void *mkc;
3087         u32 *in;
3088         int err;
3089
3090         in = mlx5_vzalloc(inlen);
3091         if (in == NULL) {
3092                 if_printf(ifp, "%s: failed to allocate inbox\n", __func__);
3093                 return (-ENOMEM);
3094         }
3095
3096         mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
3097         MLX5_SET(mkc, mkc, access_mode, MLX5_ACCESS_MODE_PA);
3098         MLX5_SET(mkc, mkc, lw, 1);
3099         MLX5_SET(mkc, mkc, lr, 1);
3100
3101         MLX5_SET(mkc, mkc, pd, pdn);
3102         MLX5_SET(mkc, mkc, length64, 1);
3103         MLX5_SET(mkc, mkc, qpn, 0xffffff);
3104
3105         err = mlx5_core_create_mkey(mdev, mkey, in, inlen);
3106         if (err)
3107                 if_printf(ifp, "%s: mlx5_core_create_mkey failed, %d\n",
3108                     __func__, err);
3109
3110         kvfree(in);
3111         return (err);
3112 }
3113
3114 static const char *mlx5e_vport_stats_desc[] = {
3115         MLX5E_VPORT_STATS(MLX5E_STATS_DESC)
3116 };
3117
3118 static const char *mlx5e_pport_stats_desc[] = {
3119         MLX5E_PPORT_STATS(MLX5E_STATS_DESC)
3120 };
3121
3122 static void
3123 mlx5e_priv_mtx_init(struct mlx5e_priv *priv)
3124 {
3125         mtx_init(&priv->async_events_mtx, "mlx5async", MTX_NETWORK_LOCK, MTX_DEF);
3126         sx_init(&priv->state_lock, "mlx5state");
3127         callout_init_mtx(&priv->watchdog, &priv->async_events_mtx, 0);
3128         MLX5_INIT_DOORBELL_LOCK(&priv->doorbell_lock);
3129 }
3130
3131 static void
3132 mlx5e_priv_mtx_destroy(struct mlx5e_priv *priv)
3133 {
3134         mtx_destroy(&priv->async_events_mtx);
3135         sx_destroy(&priv->state_lock);
3136 }
3137
3138 static int
3139 sysctl_firmware(SYSCTL_HANDLER_ARGS)
3140 {
3141         /*
3142          * %d.%d%.d the string format.
3143          * fw_rev_{maj,min,sub} return u16, 2^16 = 65536.
3144          * We need at most 5 chars to store that.
3145          * It also has: two "." and NULL at the end, which means we need 18
3146          * (5*3 + 3) chars at most.
3147          */
3148         char fw[18];
3149         struct mlx5e_priv *priv = arg1;
3150         int error;
3151
3152         snprintf(fw, sizeof(fw), "%d.%d.%d", fw_rev_maj(priv->mdev), fw_rev_min(priv->mdev),
3153             fw_rev_sub(priv->mdev));
3154         error = sysctl_handle_string(oidp, fw, sizeof(fw), req);
3155         return (error);
3156 }
3157
3158 static void
3159 mlx5e_disable_tx_dma(struct mlx5e_channel *ch)
3160 {
3161         int i;
3162
3163         for (i = 0; i < ch->num_tc; i++)
3164                 mlx5e_drain_sq(&ch->sq[i]);
3165 }
3166
3167 static void
3168 mlx5e_reset_sq_doorbell_record(struct mlx5e_sq *sq)
3169 {
3170
3171         sq->doorbell.d32[0] = cpu_to_be32(MLX5_OPCODE_NOP);
3172         sq->doorbell.d32[1] = cpu_to_be32(sq->sqn << 8);
3173         mlx5e_tx_notify_hw(sq, sq->doorbell.d32, 0);
3174         sq->doorbell.d64 = 0;
3175 }
3176
3177 void
3178 mlx5e_resume_sq(struct mlx5e_sq *sq)
3179 {
3180         int err;
3181
3182         /* check if already enabled */
3183         if (READ_ONCE(sq->running) != 0)
3184                 return;
3185
3186         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_ERR,
3187             MLX5_SQC_STATE_RST);
3188         if (err != 0) {
3189                 if_printf(sq->ifp,
3190                     "mlx5e_modify_sq() from ERR to RST failed: %d\n", err);
3191         }
3192
3193         sq->cc = 0;
3194         sq->pc = 0;
3195
3196         /* reset doorbell prior to moving from RST to RDY */
3197         mlx5e_reset_sq_doorbell_record(sq);
3198
3199         err = mlx5e_modify_sq(sq, MLX5_SQC_STATE_RST,
3200             MLX5_SQC_STATE_RDY);
3201         if (err != 0) {
3202                 if_printf(sq->ifp,
3203                     "mlx5e_modify_sq() from RST to RDY failed: %d\n", err);
3204         }
3205
3206         sq->cev_next_state = MLX5E_CEV_STATE_INITIAL;
3207         WRITE_ONCE(sq->running, 1);
3208 }
3209
3210 static void
3211 mlx5e_enable_tx_dma(struct mlx5e_channel *ch)
3212 {
3213         int i;
3214
3215         for (i = 0; i < ch->num_tc; i++)
3216                 mlx5e_resume_sq(&ch->sq[i]);
3217 }
3218
3219 static void
3220 mlx5e_disable_rx_dma(struct mlx5e_channel *ch)
3221 {
3222         struct mlx5e_rq *rq = &ch->rq;
3223         int err;
3224
3225         mtx_lock(&rq->mtx);
3226         rq->enabled = 0;
3227         callout_stop(&rq->watchdog);
3228         mtx_unlock(&rq->mtx);
3229
3230         callout_drain(&rq->watchdog);
3231
3232         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RDY, MLX5_RQC_STATE_ERR);
3233         if (err != 0) {
3234                 if_printf(rq->ifp,
3235                     "mlx5e_modify_rq() from RDY to RST failed: %d\n", err);
3236         }
3237
3238         while (!mlx5_wq_ll_is_empty(&rq->wq)) {
3239                 msleep(1);
3240                 rq->cq.mcq.comp(&rq->cq.mcq);
3241         }
3242
3243         /*
3244          * Transitioning into RST state will allow the FW to track less ERR state queues,
3245          * thus reducing the recv queue flushing time
3246          */
3247         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_ERR, MLX5_RQC_STATE_RST);
3248         if (err != 0) {
3249                 if_printf(rq->ifp,
3250                     "mlx5e_modify_rq() from ERR to RST failed: %d\n", err);
3251         }
3252 }
3253
3254 static void
3255 mlx5e_enable_rx_dma(struct mlx5e_channel *ch)
3256 {
3257         struct mlx5e_rq *rq = &ch->rq;
3258         int err;
3259
3260         rq->wq.wqe_ctr = 0;
3261         mlx5_wq_ll_update_db_record(&rq->wq);
3262         err = mlx5e_modify_rq(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
3263         if (err != 0) {
3264                 if_printf(rq->ifp,
3265                     "mlx5e_modify_rq() from RST to RDY failed: %d\n", err);
3266         }
3267
3268         rq->enabled = 1;
3269
3270         rq->cq.mcq.comp(&rq->cq.mcq);
3271 }
3272
3273 void
3274 mlx5e_modify_tx_dma(struct mlx5e_priv *priv, uint8_t value)
3275 {
3276         int i;
3277
3278         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3279                 return;
3280
3281         for (i = 0; i < priv->params.num_channels; i++) {
3282                 if (value)
3283                         mlx5e_disable_tx_dma(&priv->channel[i]);
3284                 else
3285                         mlx5e_enable_tx_dma(&priv->channel[i]);
3286         }
3287 }
3288
3289 void
3290 mlx5e_modify_rx_dma(struct mlx5e_priv *priv, uint8_t value)
3291 {
3292         int i;
3293
3294         if (test_bit(MLX5E_STATE_OPENED, &priv->state) == 0)
3295                 return;
3296
3297         for (i = 0; i < priv->params.num_channels; i++) {
3298                 if (value)
3299                         mlx5e_disable_rx_dma(&priv->channel[i]);
3300                 else
3301                         mlx5e_enable_rx_dma(&priv->channel[i]);
3302         }
3303 }
3304
3305 static void
3306 mlx5e_add_hw_stats(struct mlx5e_priv *priv)
3307 {
3308         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3309             OID_AUTO, "fw_version", CTLTYPE_STRING | CTLFLAG_RD, priv, 0,
3310             sysctl_firmware, "A", "HCA firmware version");
3311
3312         SYSCTL_ADD_STRING(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_hw),
3313             OID_AUTO, "board_id", CTLFLAG_RD, priv->mdev->board_id, 0,
3314             "Board ID");
3315 }
3316
3317 static int
3318 mlx5e_sysctl_tx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3319 {
3320         struct mlx5e_priv *priv = arg1;
3321         uint8_t temp[MLX5E_MAX_PRIORITY];
3322         uint32_t tx_pfc;
3323         int err;
3324         int i;
3325
3326         PRIV_LOCK(priv);
3327
3328         tx_pfc = priv->params.tx_priority_flow_control;
3329
3330         for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3331                 temp[i] = (tx_pfc >> i) & 1;
3332
3333         err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3334         if (err || !req->newptr)
3335                 goto done;
3336         err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3337         if (err)
3338                 goto done;
3339
3340         priv->params.tx_priority_flow_control = 0;
3341
3342         /* range check input value */
3343         for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3344                 if (temp[i] > 1) {
3345                         err = ERANGE;
3346                         goto done;
3347                 }
3348                 priv->params.tx_priority_flow_control |= (temp[i] << i);
3349         }
3350
3351         /* check if update is required */
3352         if (tx_pfc != priv->params.tx_priority_flow_control)
3353                 err = -mlx5e_set_port_pfc(priv);
3354 done:
3355         if (err != 0)
3356                 priv->params.tx_priority_flow_control= tx_pfc;
3357         PRIV_UNLOCK(priv);
3358
3359         return (err);
3360 }
3361
3362 static int
3363 mlx5e_sysctl_rx_priority_flow_control(SYSCTL_HANDLER_ARGS)
3364 {
3365         struct mlx5e_priv *priv = arg1;
3366         uint8_t temp[MLX5E_MAX_PRIORITY];
3367         uint32_t rx_pfc;
3368         int err;
3369         int i;
3370
3371         PRIV_LOCK(priv);
3372
3373         rx_pfc = priv->params.rx_priority_flow_control;
3374
3375         for (i = 0; i != MLX5E_MAX_PRIORITY; i++)
3376                 temp[i] = (rx_pfc >> i) & 1;
3377
3378         err = SYSCTL_OUT(req, temp, MLX5E_MAX_PRIORITY);
3379         if (err || !req->newptr)
3380                 goto done;
3381         err = SYSCTL_IN(req, temp, MLX5E_MAX_PRIORITY);
3382         if (err)
3383                 goto done;
3384
3385         priv->params.rx_priority_flow_control = 0;
3386
3387         /* range check input value */
3388         for (i = 0; i != MLX5E_MAX_PRIORITY; i++) {
3389                 if (temp[i] > 1) {
3390                         err = ERANGE;
3391                         goto done;
3392                 }
3393                 priv->params.rx_priority_flow_control |= (temp[i] << i);
3394         }
3395
3396         /* check if update is required */
3397         if (rx_pfc != priv->params.rx_priority_flow_control)
3398                 err = -mlx5e_set_port_pfc(priv);
3399 done:
3400         if (err != 0)
3401                 priv->params.rx_priority_flow_control= rx_pfc;
3402         PRIV_UNLOCK(priv);
3403
3404         return (err);
3405 }
3406
3407 static void
3408 mlx5e_setup_pauseframes(struct mlx5e_priv *priv)
3409 {
3410 #if (__FreeBSD_version < 1100000)
3411         char path[96];
3412 #endif
3413         int error;
3414
3415         /* enable pauseframes by default */
3416         priv->params.tx_pauseframe_control = 1;
3417         priv->params.rx_pauseframe_control = 1;
3418
3419         /* disable ports flow control, PFC, by default */
3420         priv->params.tx_priority_flow_control = 0;
3421         priv->params.rx_priority_flow_control = 0;
3422
3423 #if (__FreeBSD_version < 1100000)
3424         /* compute path for sysctl */
3425         snprintf(path, sizeof(path), "dev.mce.%d.tx_pauseframe_control",
3426             device_get_unit(priv->mdev->pdev->dev.bsddev));
3427
3428         /* try to fetch tunable, if any */
3429         TUNABLE_INT_FETCH(path, &priv->params.tx_pauseframe_control);
3430
3431         /* compute path for sysctl */
3432         snprintf(path, sizeof(path), "dev.mce.%d.rx_pauseframe_control",
3433             device_get_unit(priv->mdev->pdev->dev.bsddev));
3434
3435         /* try to fetch tunable, if any */
3436         TUNABLE_INT_FETCH(path, &priv->params.rx_pauseframe_control);
3437 #endif
3438
3439         /* register pauseframe SYSCTLs */
3440         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3441             OID_AUTO, "tx_pauseframe_control", CTLFLAG_RDTUN,
3442             &priv->params.tx_pauseframe_control, 0,
3443             "Set to enable TX pause frames. Clear to disable.");
3444
3445         SYSCTL_ADD_INT(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3446             OID_AUTO, "rx_pauseframe_control", CTLFLAG_RDTUN,
3447             &priv->params.rx_pauseframe_control, 0,
3448             "Set to enable RX pause frames. Clear to disable.");
3449
3450         /* register priority flow control, PFC, SYSCTLs */
3451         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3452             OID_AUTO, "tx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
3453             CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_tx_priority_flow_control, "CU",
3454             "Set to enable TX ports flow control frames for priorities 0..7. Clear to disable.");
3455
3456         SYSCTL_ADD_PROC(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3457             OID_AUTO, "rx_priority_flow_control", CTLTYPE_U8 | CTLFLAG_RWTUN |
3458             CTLFLAG_MPSAFE, priv, 0, &mlx5e_sysctl_rx_priority_flow_control, "CU",
3459             "Set to enable RX ports flow control frames for priorities 0..7. Clear to disable.");
3460
3461         PRIV_LOCK(priv);
3462
3463         /* range check */
3464         priv->params.tx_pauseframe_control =
3465             priv->params.tx_pauseframe_control ? 1 : 0;
3466         priv->params.rx_pauseframe_control =
3467             priv->params.rx_pauseframe_control ? 1 : 0;
3468
3469         /* update firmware */
3470         error = mlx5e_set_port_pause_and_pfc(priv);
3471         if (error == -EINVAL) {
3472                 if_printf(priv->ifp,
3473                     "Global pauseframes must be disabled before enabling PFC.\n");
3474                 priv->params.rx_priority_flow_control = 0;
3475                 priv->params.tx_priority_flow_control = 0;
3476
3477                 /* update firmware */
3478                 (void) mlx5e_set_port_pause_and_pfc(priv);
3479         }
3480         PRIV_UNLOCK(priv);
3481 }
3482
3483 static void *
3484 mlx5e_create_ifp(struct mlx5_core_dev *mdev)
3485 {
3486         struct ifnet *ifp;
3487         struct mlx5e_priv *priv;
3488         u8 dev_addr[ETHER_ADDR_LEN] __aligned(4);
3489         struct sysctl_oid_list *child;
3490         int ncv = mdev->priv.eq_table.num_comp_vectors;
3491         char unit[16];
3492         int err;
3493         int i;
3494         u32 eth_proto_cap;
3495
3496         if (mlx5e_check_required_hca_cap(mdev)) {
3497                 mlx5_core_dbg(mdev, "mlx5e_check_required_hca_cap() failed\n");
3498                 return (NULL);
3499         }
3500         /*
3501          * Try to allocate the priv and make room for worst-case
3502          * number of channel structures:
3503          */
3504         priv = malloc(sizeof(*priv) +
3505             (sizeof(priv->channel[0]) * mdev->priv.eq_table.num_comp_vectors),
3506             M_MLX5EN, M_WAITOK | M_ZERO);
3507         mlx5e_priv_mtx_init(priv);
3508
3509         ifp = priv->ifp = if_alloc(IFT_ETHER);
3510         if (ifp == NULL) {
3511                 mlx5_core_err(mdev, "if_alloc() failed\n");
3512                 goto err_free_priv;
3513         }
3514         ifp->if_softc = priv;
3515         if_initname(ifp, "mce", device_get_unit(mdev->pdev->dev.bsddev));
3516         ifp->if_mtu = ETHERMTU;
3517         ifp->if_init = mlx5e_open;
3518         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
3519         ifp->if_ioctl = mlx5e_ioctl;
3520         ifp->if_transmit = mlx5e_xmit;
3521         ifp->if_qflush = if_qflush;
3522 #if (__FreeBSD_version >= 1100000)
3523         ifp->if_get_counter = mlx5e_get_counter;
3524 #endif
3525         ifp->if_snd.ifq_maxlen = ifqmaxlen;
3526         /*
3527          * Set driver features
3528          */
3529         ifp->if_capabilities |= IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6;
3530         ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
3531         ifp->if_capabilities |= IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWFILTER;
3532         ifp->if_capabilities |= IFCAP_LINKSTATE | IFCAP_JUMBO_MTU;
3533         ifp->if_capabilities |= IFCAP_LRO;
3534         ifp->if_capabilities |= IFCAP_TSO | IFCAP_VLAN_HWTSO;
3535         ifp->if_capabilities |= IFCAP_HWSTATS;
3536
3537         /* set TSO limits so that we don't have to drop TX packets */
3538         ifp->if_hw_tsomax = MLX5E_MAX_TX_PAYLOAD_SIZE - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
3539         ifp->if_hw_tsomaxsegcount = MLX5E_MAX_TX_MBUF_FRAGS - 1 /* hdr */;
3540         ifp->if_hw_tsomaxsegsize = MLX5E_MAX_TX_MBUF_SIZE;
3541
3542         ifp->if_capenable = ifp->if_capabilities;
3543         ifp->if_hwassist = 0;
3544         if (ifp->if_capenable & IFCAP_TSO)
3545                 ifp->if_hwassist |= CSUM_TSO;
3546         if (ifp->if_capenable & IFCAP_TXCSUM)
3547                 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP);
3548         if (ifp->if_capenable & IFCAP_TXCSUM_IPV6)
3549                 ifp->if_hwassist |= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
3550
3551         /* ifnet sysctl tree */
3552         sysctl_ctx_init(&priv->sysctl_ctx);
3553         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_STATIC_CHILDREN(_dev),
3554             OID_AUTO, ifp->if_dname, CTLFLAG_RD, 0, "MLX5 ethernet - interface name");
3555         if (priv->sysctl_ifnet == NULL) {
3556                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3557                 goto err_free_sysctl;
3558         }
3559         snprintf(unit, sizeof(unit), "%d", ifp->if_dunit);
3560         priv->sysctl_ifnet = SYSCTL_ADD_NODE(&priv->sysctl_ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3561             OID_AUTO, unit, CTLFLAG_RD, 0, "MLX5 ethernet - interface unit");
3562         if (priv->sysctl_ifnet == NULL) {
3563                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3564                 goto err_free_sysctl;
3565         }
3566
3567         /* HW sysctl tree */
3568         child = SYSCTL_CHILDREN(device_get_sysctl_tree(mdev->pdev->dev.bsddev));
3569         priv->sysctl_hw = SYSCTL_ADD_NODE(&priv->sysctl_ctx, child,
3570             OID_AUTO, "hw", CTLFLAG_RD, 0, "MLX5 ethernet dev hw");
3571         if (priv->sysctl_hw == NULL) {
3572                 mlx5_core_err(mdev, "SYSCTL_ADD_NODE() failed\n");
3573                 goto err_free_sysctl;
3574         }
3575
3576         err = mlx5e_build_ifp_priv(mdev, priv, ncv);
3577         if (err) {
3578                 mlx5_core_err(mdev, "mlx5e_build_ifp_priv() failed (%d)\n", err);
3579                 goto err_free_sysctl;
3580         }
3581
3582         snprintf(unit, sizeof(unit), "mce%u_wq",
3583             device_get_unit(mdev->pdev->dev.bsddev));
3584         priv->wq = alloc_workqueue(unit, 0, 1);
3585         if (priv->wq == NULL) {
3586                 if_printf(ifp, "%s: alloc_workqueue failed\n", __func__);
3587                 goto err_free_sysctl;
3588         }
3589
3590         err = mlx5_alloc_map_uar(mdev, &priv->cq_uar);
3591         if (err) {
3592                 if_printf(ifp, "%s: mlx5_alloc_map_uar failed, %d\n",
3593                     __func__, err);
3594                 goto err_free_wq;
3595         }
3596         err = mlx5_core_alloc_pd(mdev, &priv->pdn);
3597         if (err) {
3598                 if_printf(ifp, "%s: mlx5_core_alloc_pd failed, %d\n",
3599                     __func__, err);
3600                 goto err_unmap_free_uar;
3601         }
3602         err = mlx5_alloc_transport_domain(mdev, &priv->tdn);
3603         if (err) {
3604                 if_printf(ifp, "%s: mlx5_alloc_transport_domain failed, %d\n",
3605                     __func__, err);
3606                 goto err_dealloc_pd;
3607         }
3608         err = mlx5e_create_mkey(priv, priv->pdn, &priv->mr);
3609         if (err) {
3610                 if_printf(ifp, "%s: mlx5e_create_mkey failed, %d\n",
3611                     __func__, err);
3612                 goto err_dealloc_transport_domain;
3613         }
3614         mlx5_query_nic_vport_mac_address(priv->mdev, 0, dev_addr);
3615
3616         /* check if we should generate a random MAC address */
3617         if (MLX5_CAP_GEN(priv->mdev, vport_group_manager) == 0 &&
3618             is_zero_ether_addr(dev_addr)) {
3619                 random_ether_addr(dev_addr);
3620                 if_printf(ifp, "Assigned random MAC address\n");
3621         }
3622
3623         /* set default MTU */
3624         mlx5e_set_dev_port_mtu(ifp, ifp->if_mtu);
3625
3626         /* Set default media status */
3627         priv->media_status_last = IFM_AVALID;
3628         priv->media_active_last = IFM_ETHER | IFM_AUTO |
3629             IFM_ETH_RXPAUSE | IFM_FDX;
3630
3631         /* setup default pauseframes configuration */
3632         mlx5e_setup_pauseframes(priv);
3633
3634         err = mlx5_query_port_proto_cap(mdev, &eth_proto_cap, MLX5_PTYS_EN);
3635         if (err) {
3636                 eth_proto_cap = 0;
3637                 if_printf(ifp, "%s: Query port media capability failed, %d\n",
3638                     __func__, err);
3639         }
3640
3641         /* Setup supported medias */
3642         ifmedia_init(&priv->media, IFM_IMASK | IFM_ETH_FMASK,
3643             mlx5e_media_change, mlx5e_media_status);
3644
3645         for (i = 0; i < MLX5E_LINK_MODES_NUMBER; ++i) {
3646                 if (mlx5e_mode_table[i].baudrate == 0)
3647                         continue;
3648                 if (MLX5E_PROT_MASK(i) & eth_proto_cap) {
3649                         ifmedia_add(&priv->media,
3650                             mlx5e_mode_table[i].subtype |
3651                             IFM_ETHER, 0, NULL);
3652                         ifmedia_add(&priv->media,
3653                             mlx5e_mode_table[i].subtype |
3654                             IFM_ETHER | IFM_FDX |
3655                             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3656                 }
3657         }
3658
3659         /* Additional supported medias */
3660         ifmedia_add(&priv->media, IFM_10G_LR | IFM_ETHER, 0, NULL);
3661         ifmedia_add(&priv->media, IFM_10G_LR |
3662             IFM_ETHER | IFM_FDX |
3663             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3664
3665         ifmedia_add(&priv->media, IFM_40G_ER4 | IFM_ETHER, 0, NULL);
3666         ifmedia_add(&priv->media, IFM_40G_ER4 |
3667             IFM_ETHER | IFM_FDX |
3668             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3669
3670         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO, 0, NULL);
3671         ifmedia_add(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3672             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE, 0, NULL);
3673
3674         /* Set autoselect by default */
3675         ifmedia_set(&priv->media, IFM_ETHER | IFM_AUTO | IFM_FDX |
3676             IFM_ETH_RXPAUSE | IFM_ETH_TXPAUSE);
3677         ether_ifattach(ifp, dev_addr);
3678
3679         /* Register for VLAN events */
3680         priv->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
3681             mlx5e_vlan_rx_add_vid, priv, EVENTHANDLER_PRI_FIRST);
3682         priv->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
3683             mlx5e_vlan_rx_kill_vid, priv, EVENTHANDLER_PRI_FIRST);
3684
3685         /* Link is down by default */
3686         if_link_state_change(ifp, LINK_STATE_DOWN);
3687
3688         mlx5e_enable_async_events(priv);
3689
3690         mlx5e_add_hw_stats(priv);
3691
3692         mlx5e_create_stats(&priv->stats.vport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3693             "vstats", mlx5e_vport_stats_desc, MLX5E_VPORT_STATS_NUM,
3694             priv->stats.vport.arg);
3695
3696         mlx5e_create_stats(&priv->stats.pport.ctx, SYSCTL_CHILDREN(priv->sysctl_ifnet),
3697             "pstats", mlx5e_pport_stats_desc, MLX5E_PPORT_STATS_NUM,
3698             priv->stats.pport.arg);
3699
3700         mlx5e_create_ethtool(priv);
3701
3702         mtx_lock(&priv->async_events_mtx);
3703         mlx5e_update_stats(priv);
3704         mtx_unlock(&priv->async_events_mtx);
3705
3706         return (priv);
3707
3708 err_dealloc_transport_domain:
3709         mlx5_dealloc_transport_domain(mdev, priv->tdn);
3710
3711 err_dealloc_pd:
3712         mlx5_core_dealloc_pd(mdev, priv->pdn);
3713
3714 err_unmap_free_uar:
3715         mlx5_unmap_free_uar(mdev, &priv->cq_uar);
3716
3717 err_free_wq:
3718         destroy_workqueue(priv->wq);
3719
3720 err_free_sysctl:
3721         sysctl_ctx_free(&priv->sysctl_ctx);
3722         if (priv->sysctl_debug)
3723                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
3724         if_free(ifp);
3725
3726 err_free_priv:
3727         mlx5e_priv_mtx_destroy(priv);
3728         free(priv, M_MLX5EN);
3729         return (NULL);
3730 }
3731
3732 static void
3733 mlx5e_destroy_ifp(struct mlx5_core_dev *mdev, void *vpriv)
3734 {
3735         struct mlx5e_priv *priv = vpriv;
3736         struct ifnet *ifp = priv->ifp;
3737
3738         /* don't allow more IOCTLs */
3739         priv->gone = 1;
3740
3741         /* XXX wait a bit to allow IOCTL handlers to complete */
3742         pause("W", hz);
3743
3744         /* stop watchdog timer */
3745         callout_drain(&priv->watchdog);
3746
3747         if (priv->vlan_attach != NULL)
3748                 EVENTHANDLER_DEREGISTER(vlan_config, priv->vlan_attach);
3749         if (priv->vlan_detach != NULL)
3750                 EVENTHANDLER_DEREGISTER(vlan_unconfig, priv->vlan_detach);
3751
3752         /* make sure device gets closed */
3753         PRIV_LOCK(priv);
3754         mlx5e_close_locked(ifp);
3755         PRIV_UNLOCK(priv);
3756
3757         /* unregister device */
3758         ifmedia_removeall(&priv->media);
3759         ether_ifdetach(ifp);
3760         if_free(ifp);
3761
3762         /* destroy all remaining sysctl nodes */
3763         sysctl_ctx_free(&priv->stats.vport.ctx);
3764         sysctl_ctx_free(&priv->stats.pport.ctx);
3765         if (priv->sysctl_debug)
3766                 sysctl_ctx_free(&priv->stats.port_stats_debug.ctx);
3767         sysctl_ctx_free(&priv->sysctl_ctx);
3768
3769         mlx5_core_destroy_mkey(priv->mdev, &priv->mr);
3770         mlx5_dealloc_transport_domain(priv->mdev, priv->tdn);
3771         mlx5_core_dealloc_pd(priv->mdev, priv->pdn);
3772         mlx5_unmap_free_uar(priv->mdev, &priv->cq_uar);
3773         mlx5e_disable_async_events(priv);
3774         destroy_workqueue(priv->wq);
3775         mlx5e_priv_mtx_destroy(priv);
3776         free(priv, M_MLX5EN);
3777 }
3778
3779 static void *
3780 mlx5e_get_ifp(void *vpriv)
3781 {
3782         struct mlx5e_priv *priv = vpriv;
3783
3784         return (priv->ifp);
3785 }
3786
3787 static struct mlx5_interface mlx5e_interface = {
3788         .add = mlx5e_create_ifp,
3789         .remove = mlx5e_destroy_ifp,
3790         .event = mlx5e_async_event,
3791         .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
3792         .get_dev = mlx5e_get_ifp,
3793 };
3794
3795 void
3796 mlx5e_init(void)
3797 {
3798         mlx5_register_interface(&mlx5e_interface);
3799 }
3800
3801 void
3802 mlx5e_cleanup(void)
3803 {
3804         mlx5_unregister_interface(&mlx5e_interface);
3805 }
3806
3807 static void
3808 mlx5e_show_version(void __unused *arg)
3809 {
3810
3811         printf("%s", mlx5e_version);
3812 }
3813 SYSINIT(mlx5e_show_version, SI_SUB_DRIVERS, SI_ORDER_ANY, mlx5e_show_version, NULL);
3814
3815 module_init_order(mlx5e_init, SI_ORDER_THIRD);
3816 module_exit_order(mlx5e_cleanup, SI_ORDER_THIRD);
3817
3818 #if (__FreeBSD_version >= 1100000)
3819 MODULE_DEPEND(mlx5en, linuxkpi, 1, 1, 1);
3820 #endif
3821 MODULE_DEPEND(mlx5en, mlx5, 1, 1, 1);
3822 MODULE_VERSION(mlx5en, 1);